ANALOG DEVICES AD7641

18-Bit, 2 MSPS SAR ADC AD7641 FEATURES FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND DVDD DGND Throughput 2 MSPS (wideband warp and warp mode) AGND 1.5 MSPS (normal mode) OVDD AD7641 AVDD OGND INL: ±2 LSB typical, ±3 LSB max; ±8 ppm of full scale REF 18-bit resolution with no missing codes REF AMP SERIAL PORT Dynamic range: 95.5 dB 18 IN+ SWITCHED D[17:0] CAP DAC SNR: 93.5 dB typical @ 20 kHz (VREF = 2.5 V) IN– MODE0 PARALLEL THD: −112 dB typical @ 20 kHz (VREF = 2.5 V) INTERFACE MODE1 2.048 V internal reference: typ drift 10 ppm/°C; TEMP output PDREF BUSY CLOCK Differential input range: ±VREF (VREF up to 2.5 V) PDBUF RD CONTROL LOGIC AND No pipeline delay (SAR architecture) PD CS CALIBRATION CIRCUITRY RESET D0/OB/2C Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface WARP NORMAL CNVST SPI®/QSPI™/MICROWIRE™/DSP compatible Figure 1. Single 2.5 V supply operation Power dissipation Table 1. PulSAR® Selection 75 mW typical @ 2 MSPS with internal REF 100 to 500 to 650 to 2 μW in power-down mode Type/kSPS 250 570 1000 >1000 Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ Pseudo AD7651, AD7650, AD7653, Differential AD7660, AD7652, AD7667 Speed upgrade of the AD7674, AD7678, AD7679 AD7661 AD7664, AD7666 APPLICATIONS True Bipolar AD7610, AD7665 AD7612, Medical instruments AD7663 AD7671 High speed data acquisition/high dynamic data acquisition True AD7675 AD7676 AD7677 AD7621, Differential AD7622, Digital signal processing AD7623 Spectrum analysis 18-Bit AD7631, AD7679 AD7634, AD7641, Instrumentation Multichannel/ AD7678 AD7674 AD7643 Communications Simultaneous AD7654 AD7655 ATE PRODUCT HIGHLIGHTS GENERAL DESCRIPTION 1. Fast Throughput. The AD7641 is an 18-bit, 2 MSPS, charge redistribution SAR, The AD7641 is a 2 MSPS, charge redistribution, fully differential, analog-to-digital converter (ADC) that 18-bit SAR ADC. operates from a single 2.5 V power supply. The part contains a 2. Superior Linearity. high speed, 18-bit sampling ADC, an internal conversion clock, The AD7641 has no missing 18-bit code. an internal reference (and buffer), error correction circuits, and 3. Internal Reference. both serial and parallel system interface ports. It features two The AD7641 has a 2.048 V internal reference with a typical very high sampling rate modes (wideband warp and warp) and drift of ±10 ppm/°C and an on-chip TEMP sensor. a fast mode (normal) for asynchronous rate applications. The AD7641 is hardware factory calibrated and tested to ensure ac 4. Single-Supply Operation. parameters, such as signal-to-noise ratio (SNR), in addition to The AD7641 operates from a 2.5 V single supply. the more traditional dc parameters of gain, offset, and linearity. 5. Serial or Parallel Interface. The AD7641 is available in Pb-free only packages with Versatile parallel (16- or 8-bit bus) or 2-wire serial interface operation specified from −40°C to +85°C. arrangement compatible with 2.5 V, 3.3 V, or 5 V logic. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04761-001 AD7641 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs ............................................................................. 17 Applications....................................................................................... 1 Multiplexed Inputs ..................................................................... 17 General Description ......................................................................... 1 Driver Amplifier Choice ........................................................... 17 Functional Block Diagram .............................................................. 1 Voltage Reference Input ............................................................ 18 Product Highlights ........................................................................... 1 Power Supply............................................................................... 20 Revision History ............................................................................... 2 Conversion Control ................................................................... 20 Specifications..................................................................................... 3 Interfaces.......................................................................................... 21 Timing Specifications....................................................................... 5 Digital Interface.......................................................................... 21 Absolute Maximum Ratings............................................................ 7 Parallel Interface......................................................................... 21 ESD Caution.................................................................................. 7 Serial interface ............................................................................ 22 Pin Configuration and Function Descriptions............................. 8 Master Serial Interface............................................................... 22 Terminology .................................................................................... 11 Slave Serial Interface .................................................................. 24 Typical Performance Characteristics ........................................... 12 Microprocessor Interfacing....................................................... 26 Appplications Information............................................................ 15 Application Hints ........................................................................... 27 Circuit Information.................................................................... 15 Layout .......................................................................................... 27 Converter Operation.................................................................. 15 Evaluating the AD7641 Performance ...................................... 27 Modes of Operation ................................................................... 15 Outline Dimensions....................................................................... 28 Transfer Functions...................................................................... 16 Ordering Guide .......................................................................... 28 Typical Connection Diagram........................................................ 17 REVISION HISTORY 1/06—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7641 SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUT Voltage Range V − V −V +V V IN+ IN− REF REF 1 Operating Input Voltage V , V to AGND −0.1 AVDD V IN+ IN− Analog Input CMRR f = 100 kHz 58 dB IN Input Current 2 MSPS throughput 18 μA 2 Input Impedance THROUGHPUT SPEED Complete Cycle Wideband warp, warp modes 500 ns Throughput Rate Wideband warp, warp modes 0.001 2 MSPS Time Between Conversions Wideband warp, warp modes 1 ms Complete Cycle Normal mode 667 ns Throughput Rate Normal mode 0 1.5 MSPS DC ACCURACY 3 4 Integral Linearity Error T to T = −40°C to +70°C −3 ±2 +3 LSB MIN MAX 4 Integral Linearity Error T to T = −40°C to +85°C −3.5 ±2 +3.5 LSB MIN MAX No Missing Codes 18 Bits Differential Linearity Error −1 +2 LSB Transition Noise VREF = 2.5 V 1.6 LSB Transition Noise V = 2.048 V 2.0 LSB REF 5 Zero Error, T to T −15 +15 LSB MIN MAX Zero Error Temperature Drift ±0.5 ppm/°C 5 Gain Error, TMIN to TMAX −0.25 +0.25 % of FSR Gain Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 2.5 V ± 5% ±16 LSB AC ACCURACY 6 Dynamic Range VREF = 2.5 V 95.5 dB Signal-to-Noise f = 20 kHz, V = 2.5 V 93.5 dB IN REF f = 20 kHz, V = 2.048 V 92 dB IN REF f = 100 kHz, V = 2.5 V 93 dB IN REF Spurious-Free Dynamic Range fIN = 20 kHz, VREF = 2.5 V 112 dB fIN = 20 kHz, VREF = 2.048 V 113 dB fIN = 100 kHz, VREF = 2.5 V 101 dB Total Harmonic Distortion f = 20 kHz, V = 2.5 V −115 dB IN REF f = 20 kHz, V = 2.048 V −116 dB IN REF f = 100 kHz, V = 2.5 V −101 dB IN REF Signal-to-(Noise + Distortion) fIN = 20 kHz, , VREF = 2.5 V 93.5 dB fIN = 20 kHz, VREF = 2.048 V 92 dB f = 100 kHz, , V = 2.5 V 92.5 dB IN REF −3 dB Input Bandwidth 50 MHz SAMPLING DYNAMICS Aperture Delay 1 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 115 ns INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 2.038 2.048 2.058 V Temperature Drift −40°C to +85°C ±10 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V Rev. 0 | Page 3 of 28 AD7641 Parameter Conditions Min Typ Max Unit Turn-On Settling Time CREF = 10 μF 5 ms REFBUFIN Output Voltage REFBUFIN @ 25°C 1.19 V REFBUFIN Output Resistance 6.33 kΩ EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 1.8 2.048 AVDD + 0.1 V Current Drain 2 MSPS throughput 180 μA REFERENCE BUFFER PDREF = high, PDBUF = low REFBUFIN Input Voltage Range REF = 2.048 V typ 1.05 1.2 1.30 V REFBUFIN Input Current REFBUFIN = 1.2 V 1 nA TEMPERATURE PIN Voltage Output @ 25°C 278 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.7 kΩ DIGITAL INPUTS Logic Levels V −0.3 +0.6 V IL V 1.7 5.25 V IH IIL −1 +1 μA IIH −1 +1 μA DIGITAL OUTPUTS 7 Data Format 8 Pipeline Delay VOL ISINK = 500 μA 0.4 V V I = −500 μA OVDD − 0.3 V OH SOURCE POWER SUPPLIES Specified Performance AVDD 2.37 2.5 2.63 V DVDD 2.37 2.5 2.63 V 9 OVDD 2.30 3.6 V 10 Operating Current 2 MSPS throughput 11 AVDD With internal reference 23 mA DVDD 2.5 mA 12 OVDD 0.5 mA 11 Power Dissipation 10 With Internal Reference 2 MSPS throughput 75 92 mW 10 Without Internal Reference 2 MSPS throughput 68 85 mW 12 In Power-Down Mode PD = high 2 μW 13 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 When using an external reference. With the internal reference, the input range is −0.1 V to VREF. 2 See Analog Inputs section. 3 Linearity is tested using endnotes, not best fit. 4 LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 15.63 μV. 5 See Voltage Reference Input section. These specifications do not include the error contribution from the external reference. 6 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 7 Parallel or serial 18-bit. 8 Conversion results are available immediately after completed conversion. 9 See the Absolute Maximum Ratings section. 10 In warp mode. Tested in parallel reading mode. 11 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high. 12 With all digital inputs forced to OVDD. 13 Consult sales for extended temperature range. Rev. 0 | Page 4 of 28 AD7641 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (Refer to Figure 29 and Figure 30) 1 Convert Pulse Width t1 15 70 ns 2 3 Time Between Conversions (Warp Mode /Normal Mode) t2 500/667 ns CNVST t 23 ns Low to BUSY High Delay 3 BUSY High All Modes (Except Master Serial Read After Convert) t4 385/520 ns Aperture Delay t5 1 ns End of Conversion to BUSY Low Delay t 10 ns 6 Conversion Time (Warp Mode/Normal Mode) t7 385/520 ns Acquisition Time (Warp Mode/Normal Mode) t 115 ns 8 RESET Pulse Width t 15 ns 9 4 RESET Low to BUSY High Delay t38 10 ns 4 t 600 ns BUSY High Time from RESET Low 39 PARALLEL INTERFACE MODES (Refer to Figure 31 to Figure 34 ) CNVST t10 385/520 ns Low to Data Valid Delay (Warp Mode/Normal Mode) Data Valid to BUSY Low Delay t 2 ns 11 Bus Access Request to Data Valid t 20 ns 12 Bus Relinquish Time t13 2 15 ns 5 MASTER SERIAL INTERFACE MODES (Refer to Figure 35 and Figure 36) t 10 ns CS 14 Low to SYNC Valid Delay 5 CS t 10 ns Low to Internal SCLK Valid Delay 15 CS t 10 ns 16 Low to SDOUT Delay CNVST t 14/137 ns Low to SYNC Delay (Warp Mode/Normal Mode) 17 SYNC Asserted to SCLK First Edge Delay t 0.5 ns 18 6 Internal SCLK Period t19 8 14 ns 6 t 2 ns Internal SCLK High 20 6 t 3 ns Internal SCLK Low 21 6 SDOUT Valid Setup Time t22 1 ns 6 SDOUT Valid Hold Time t23 0 ns 6 SCLK Last Edge to SYNC Delay t24 0 ns CS t 10 ns High to SYNC HI-Z 25 CS t 10 ns High to Internal SCLK HI-Z 26 CS t27 10 ns High to SDOUT HI-Z 6 BUSY High in Master Serial Read After Convert t28 See Table 4 ns CNVST t29 383/500 ns Low to SYNC Asserted Delay (All Modes) SYNC Deasserted to BUSY Low Delay t30 13 ns SLAVE SERIAL INTERFACE MODES (Refer to Figure 38 and Figure 39) External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t 1 8 ns 32 SDIN Setup Time t33 5 ns SDIN Hold Time t 5 ns 34 External SCLK Period t35 12.5 ns External SCLK High t36 5 ns External SCLK Low t 5 ns 37 1 See the Conversion Control section. 2 All timings for wideband warp mode are the same as warp mode. 3 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 4 See the Digital Interface section and the RESET section. 5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications. Rev. 0 | Page 5 of 28 AD7641 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t18 0.5 3 3 3 ns Internal SCLK Period Minimum t19 8 16 32 64 ns Internal SCLK Period Maximum t 14 26 52 103 ns 19 Internal SCLK High Minimum t 2 6 15 31 ns 20 Internal SCLK Low Minimum t 3 7 16 32 ns 21 SDOUT Valid Setup Time Minimum t22 1 5 5 5 ns SDOUT Valid Hold Time Minimum t23 0 0.5 10 28 ns SCLK Last Edge to SYNC Delay Minimum t24 0 0.5 9 26 ns BUSY High Width Maximum t 0.630 0.870 1.350 2.28 μs 24 500µAI OL TO OUTPUT 1.4V PIN C L 50pF 2V 0.8V 500µAI OH t t DELAY DELAY NOTE 2V 2V IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND 0.8V 0.8V SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 2. Load Circuit for Digital Interface Timing, Figure 3. Voltage Reference Levels for Timing SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. 0 | Page 6 of 28 04761-002 04761-003 AD7641 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Analog Inputs/Outputs rating only; functional operation of the device at these or any 1 IN+ , IN−, REF, REFBUFIN, TEMP, AVDD + 0.3 V to other conditions above those indicated in the operational INGND, REFGND to AGND AGND − 0.3 V section of this specification is not implied. Exposure to absolute Ground Voltage Differences maximum rating conditions for extended periods may affect AGND, DGND, OGND ±0.3 V device reliability. Supply Voltages AVDD, DVDD −0.3 V to +2.7 V OVDD −0.3 V to +3.8 V 1 See Analog Inputs section. AVDD to DVDD ±2.8 V 2 See Voltage Reference Input section. AVDD, DVDD to OVDD −3.8 V to +2.8 V 3 Specification is for the device in free air: Digital Inputs −0.3 V to +5.5 V 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W. 4 Specification is for the device in free air: 2 PDREF, PDBUF ±20 mA 48-Lead LFCSP; θJA = 26°C/W. 3 Internal Power Dissipation 700 mW 4 Internal Power Dissipation 2.5 W Junction Temperature 125°C Storage Temperature Range –65°C to +125°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 28 AD7641 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 AGND 36 AGND PIN 1 AVDD 2 IDENTIFIER 35 CNVST 3 MODE0 34 PD MODE1 4 33 RESET D0/OB/2C 5 32 CS AD7641 WARP 6 31 RD TOP VIEW NORMAL 7 30 DGND (Not to Scale) D1/A0 8 29 BUSY 9 D2/A1 28 D17 10 D3 27 D16 11 D4/DIVSCLK[0] 26 D15 12 D5/DIVSCLK[1] 25 D14 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin 1 No. Mnemonic Type Description 1, 36, AGND P Analog Power Ground Pin. 41, 42 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3, 4 MODE[0:1] DI Data Output Interface Mode Selection. Interface MODE# MODE1 MODE0 Description 0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 8-bit (byte) interface 3 1 1 Serial interface 5 D0/OB/2C DI/O When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight 2C binary/twos complement. When OB/ is high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI Conversion Mode Selection. When WARP = high and NORMAL = high, this selects wideband warp mode with slightly improved linearity and THD. When WARP = high and NORMAL = low, this selects warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and a minimum conversion rate must be applied to guarantee full specified accuracy. 7 NORMAL DI Conversion Mode Selection. When NORMAL = low and WARP = low, this input selects normal mode where full accuracy is maintained independent of the minimum conversion rate. 8 D1/A0 DI/O When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output as shown in Table 7. 9 D2/A1 DI/O When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus. When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7. 10 D3 D0 When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. 11, 12 D[4:5] DI/O When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus. or DIVSCLK[0:1] When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. Rev. 0 | Page 8 of 28 D6/EXT/INT PDBUF D7/INVSYNC PDREF D8/INVSCLK REFBUFIN D9/RDC/SDIN TEMP OGND AVDD OVDD IN+ DVDD AGND DGND AGND D10/SDOUT NC D11/SCLK IN– D12/SYNC REFGND REF D13/RDERROR 04761-004 AD7641 Pin 1 No. Mnemonic Type Description 13 D6 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus. or EXT/INT When MODE[1:0] = 3, (serial mode), serial clock source select. This input is used to select the internally generated (master) or external (slave) serial data clock. When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output. When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated by CS, connected to the SCLK input. 14 D7 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus. or INVSYNC When MODE[1:0] = 3, (serial mode), invert sync select. In serial master mode (EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D8 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus. or INVSCLK When MODE[1:0] = 3, (serial mode), invert SCLK select. In all serial modes, this input is used to invert the SCLK signal. 16 D9 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus. or RDC When MODE[1:0] = 3, (serial mode), read during convert. When using serial master mode (EXT/INT = low), RDC is used to select the read mode. When RDC = high, the previous conversion result is output on SDOUT during conversion and the period of SCLK changes (see the Master Serial Interface section). When RDC = low (read after convert), the current result can be output on SDOUT only when the conversion is complete. or SDIN When MODE[1:0] = 3, (serial mode), serial data in. When using serial slave mode, (EXT/INT = high), SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the initiation of the read sequence. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (2.5 V or 3 V). 19 DVDD P Digital Power. Nominally at 2.5 V. 20 DGND P Digital Power Ground. 21 D10 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus. or SDOUT When MODE[1:0] = 3, (serial mode), serial data output. In serial mode, this pin is used as the serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7641 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In master mode, EXT/INT = low. SDOUT is valid on both edges of SCLK. In slave mode, EXT/INT = high: When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge. 22 D11 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus. or SCLK When MODE[1:0] = 3, (serial mode), serial clock. In all serial modes, this pin is used as the serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. 23 D12 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus. or SYNC When MODE[1:0] = 3, (serial mode), frame synchronization. In serial master mode (EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid. 24 D13 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus. or RDERROR When MODE[1:0] = 3, (serial mode), read error. In serial slave mode (EXT/INT = high), this output is used as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. Rev. 0 | Page 9 of 28 AD7641 Pin 1 No. Mnemonic Type Description 25 to D[14:17] DO Bit 14 to Bit 17 of the parallel port data output bus. These pins are always outputs, regardless of 28 the interface mode. 29 BUSY DO Busy Output. Transitions high when a conversion is started and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data-ready clock signal. 30 DGND P Digital Power Ground. 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode. 33 RESET DI Reset Input. When high, resets the AD7641. Current conversion, if any, is aborted. Falling edge of RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If not used, this pin can be tied to DGND. 34 PD DI Power-Down Input. When high, power downs the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 37 REF AI/O Reference Output/Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal reference and buffer. Refer to the Voltage Reference Input section. 38 REFGND AI Reference Input Analog Ground. 39 IN− AI Differential Negative Analog Input. 40 NC No Connect. 43 IN+ AI Differential Positive Analog Input. 45 TEMP AO Temperature Sensor Analog Output. 46 REFBUFIN AI/O Internal Reference Output/Reference Buffer Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical) band gap output on this pin, which needs external decoupling. The internal fixed gain reference buffer uses this to produce 2.048 V on the REF pin. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section. 47 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down and an external reference must been used. 48 PDBUF DI Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. Table 7. Data Bus Interface Definition MODE MODE1 MODE0 2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description D0/OB/ 0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-Bit Parallel 1 0 1 2C A0 = 0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-Bit High Word OB/ 1 0 1 2C A0 = 1 R[0] R[1] All Zeros 16-Bit Low Word OB/ 2 1 0 2C A0 = 0 A1 = 0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit High Byte OB/ 2 1 0 A0 = 0 A1 = 1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit Mid Byte OB/2C 2 1 0 2C A0 = 1 A1 = 0 All Hi-Z R[0:1] All Zeros 8-Bit Low Byte OB/ 2 1 0 2C A0 = 1 A1 = 1 All Hi-Z All Zeros R[0:1] 8-Bit Low Byte OB/ 3 1 1 2C All Hi-Z Serial Interface Serial Interface OB/ Rev. 0 | Page 10 of 28 AD7641 TERMINOLOGY Integral Nonlinearity Error (INL) Total Harmonic Distortion (THD) Linearity error refers to the deviation of each individual code THD is the ratio of the rms sum of the first five harmonic from a line drawn from negative full scale through positive full components to the rms value of a full-scale input signal and is scale. The point used as negative full scale occurs ½ LSB before expressed in decibels. the first code transition. Positive full scale is defined as a level Signal to (Noise + Distortion) Ratio (SINAD) 1½ LSB beyond the last code transition. The deviation is SINAD is the ratio of the rms value of the actual input signal to measured from the middle of each code to the true straight line. the rms sum of all other spectral components below the Nyquist Differential Nonlinearity Error (DNL) frequency, including harmonics but excluding dc. The value for In an ideal ADC, code transitions are 1 LSB apart. Differential SINAD is expressed in decibels. nonlinearity is the maximum deviation from this ideal value. It Spurious-Free Dynamic Range (SFDR) is often specified in terms of resolution for which no missing The difference, in decibels (dB), between the rms amplitude of codes are guaranteed. the input signal and the peak spurious signal. Gain Error Effective Number of Bits (ENOB) The first transition (from 000…00 to 000…01) should occur for an analog voltage ½ LSB above the nominal negative full scale ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by (−2.0479922 V for the ±2.048 V range). The last transition (from 111…10 to 111…11) should occur for an analog voltage ENOB = [(SINADdB − 1.76)/6.02] 1½ LSB below the nominal full scale (+2.0479766 V for the ±2.048 V range). The gain error is the deviation of the Aperture Delay difference between the actual level of the last transition and the Aperture delay is a measure of the acquisition performance and actual level of the first transition from the difference between is measured from the falling edge of the CNVST input to when the ideal levels. the input signal is held for a conversion. Zero Error Transient Response The zero error is the difference between the ideal midscale The time required for the AD7641 to achieve its rated accuracy input voltage (0 V) and the actual voltage producing the after a full-scale step function is applied to its input. midscale output code. Reference Voltage Temperature Coefficient Dynamic Range It is derived from the typical shift of output voltage at 25°C on a It is the ratio of the rms value of the full scale to the rms noise sample of parts maximum and minimum reference output measured with the inputs shorted together. The value for voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is dynamic range is expressed in decibels. expressed in ppm/°C using Signal-to-Noise Ratio (SNR) V() Max −V (Min) 6 REF REF TCV() ppm/°C = ×10 REF SNR is the ratio of the rms value of the actual input signal to the V() 25°C×() T −T REF MAX MIN rms sum of all other spectral components below the Nyquist where: frequency, excluding harmonics and dc. The value for SNR is V (Max) = Maximum V at T , T(25°C), or T expressed in decibels. REF REF MIN MAX VREF (Min) = Minimum VREF at TMIN, T(25°C), or TMAX VREF (25°C) = VREF at 25°C TMAX = +85°C TMIN = –40°C Rev. 0 | Page 11 of 28 AD7641 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 2.0 2.5 1.5 2.0 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.5 –1.0 –2.0 –1.5 –2.5 –3.0 –2.0 0 65536 131072 196608 262144 0 65536 131072 196608 262144 CODE CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 40000 30000 σ = 1.55 σ = 2.02 34844 35000 24731 25000 31003 23436 22225 30000 18995 24739 20000 25000 20000 15000 12922 16207 10846 15000 10000 10938 8219 10000 4688 4730 5248 5000 2105 5000 1171 683 2124 912 11 589 00 2 272 232 39 0 0 11 52 117 51 10 1 0 0 CODE IN HEX CODE IN HEX Figure 6. Histogram of 261,120 Conversions of a DC Input at Figure 9. Histogram of 261,120 Conversions of a DC Input at the Code Center (External Reference) the Code Center (Internal Reference) 2.0530 20 18 2.0525 16 –FS 14 2.0520 12 10 2.0515 8 6 2.0510 4 2 2.0505 0 –2 2.0500 –4 ZERO-ERROR –6 2.0495 –8 –10 2.0490 –12 –14 2.0485 +FS –16 –18 2.0480 –20 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Typical Reference Voltage Output vs. Temperature (3 Units) Figure 10. Zero Error, Positive and Negative Full Scale vs. Temperature Rev. 0 | Page 12 of 28 V (V) COUNTS REF INL (LSB) 1FFEF 1FFF0 1FFF1 1FFF2 1FFF3 1FFF4 1FFF5 1FFF6 1FFF7 1FFF8 1FFF9 1FFFA 1FFFB 1FFFC 1FFFD 1FFFE 1FFFF 20000 04761-005 04761-006 04761-007 COUNTS ZERO-ERROR, FULL-SCALE ERROR (LSB) DNL (LSB) 1FED9 1FEDA 1FEDB 1FEDC 1FEDD 1FEDE 1FEDF 1FEE0 1FEE1 1FEE2 1FEE3 1FEE4 1FEE5 1FEE6 1FEE7 1FEE8 1FEE9 1FEEA 1FEEB 04761-010 04761-008 04761-009 AD7641 0 0 f = 2MSPS f = 2MSPS S S = 20.1kHz f = 100.8kHz f IN IN –20 –20 SNR = 93.6dB SNR = 93dB THD = –116dB THD = –101dB –40 –40 SFDR = 101dB SFDR = 112dB SINAD = 93.5dB SINAD = 92.5dB –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 01 100 200 300 400 500 600 700 800 900000 01 100 200 300 400 500 600 700 800 900000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 14. FFT 100 kHz Figure 11. FFT 20 kHz 95 19 95 16.0 93 15.6 SNR ENOB SINAD SNR 94 18 91 15.2 89 14.8 93 17 87 14.4 85 14.0 92 16 83 13.6 SINAD ENOB 81 13.2 91 15 79 12.8 77 12.4 90 14 75 12.0 –55 –35 –15 5 25 45 65 85 105 125 1 10 100 1000 TEMPERATURE (°C) FREQUENCY (kHz) Figure 15. SNR, SINAD, and ENOB vs. Temperature Figure 12. SNR, SINAD, and ENOB vs. Frequency –90 120 –70 120 SFDR –95 SFDR 115 110 –80 –100 110 100 –90 90 –105 105 THIRD –110 100 80 HARMONIC –100 THD –115 95 70 –110 60 –120 90 THD –125 85 50 –120 THIRD SECOND HARMONIC –130 80 40 HARMONIC –130 –135 75 30 SECOND HARMONIC –140 70 –140 20 –55 –35 –15 5 25 45 65 85 105 125 1 10 100 1000 TEMPERATURE (°C) FREQUENCY (kHz) Figure 16. THD, Harmonics, and SFDR vs. Temperature Figure 13. THD, Harmonics, and SFDR vs. Frequency Rev. 0 | Page 13 of 28 THD, HARMONICS (dB) SNR, SINAD (dB) AMPLITUDE (dB of Full Scale) 04761-011 ENOB (Bits) 04761-012 SFDR (dB) 04761-013 THD, HARMONICS (dB) SNR, SINAD (dB) AMPLITUDE (dB of Full Scale) 04761-014 SFDR (dB) ENOB (Bits) 04761-016 04761-015 AD7641 96.0 100000 AVDD 10000 95.5 1000 95.0 DVDD SNR 100 94.5 OVDD = 2.5V, ALL MODES SINAD 10 94.0 1 OVDD = 3.3V, ALL MODES 93.5 0.1 PDREF = PDBUF = HIGH 93.0 0.01 –60 –50 –40 –30 –20 –10 0 10 100 1k 10k 100k 1M 10M INPUT LEVEL (dB) SAMPLING RATE (SPS) Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 19. Operating Current vs. Sample Rate 16 20 14 18 OVDD = 2.5V @ 85°C 12 16 OVDD = 2.5V @ 25°C 10 14 DVDD 8 12 OVDD, 3.3V 6 10 OVDD, 2.5V OVDD = 3.3V @ 25°C 4 8 OVDD = 3.3V @ 85°C 2 6 AVDD 0 4 –55 –35 –15 5 25 45 65 85 105 125 4 50 100 150 200 TEMPERATURE (°C) C (pF) L Figure 18. Power-Down Operating Currents vs. Temperature Figure 20. Typical Delay vs. Load Capacitance CL Rev. 0 | Page 14 of 28 DVDD, OVDD (µA) SNR, SINAD REFERRED TO FULL SCALE (dB) 04761-018 04761-017 OPERATING CURRENTS (µA) t DELAY (ns) 12 04761-020 04761-019 AD7641 APPPLICATIONS INFORMATION IN+ AGND SWITCHES CONTROL LSB SW+ MSB 131,072C 65,536C 4C 2C C C BUSY REF CONTROL COMP LOGIC REFGND OUTPUT CODE 131,072C 65,536C 4C 2C C C SW– MSB LSB CNVST AGND IN– Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION comparator to become unbalanced. By switching each element The AD7641 is a very fast, low power, single-supply, precise of the capacitor array between REFGND and REF, the comparator 18-bit ADC using successive approximation architecture. The input varies by binary weighted voltage steps (V /2, V /4 REF REF AD7641 features different modes to optimize performances throughVREF/131072). The control logic toggles these switches, according to the applications. In warp mode, the AD7641 is starting with the MSB first, to bring the comparator back into a capable of converting 2,000,000 samples per second (2 MSPS). balanced condition. After the completion of this process, the The AD7641 provides the user with an on-chip track-and-hold, control logic generates the ADC output code and brings BUSY successive approximation ADC that does not exhibit any output low. pipeline or latency, making it ideal for multiple multiplexed MODES OF OPERATION channel applications. The AD7641 features three modes of operations: wideband The AD7641 can operate from a single 2.5 V supply and warp, warp, and normal. Each of these modes is more suitable interface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed for specific applications. in a 48-lead LQFP package or a tiny 48-lead LFCSP package, NORMAL which combines space savings with flexibility and allows the The wideband warp (WARP = high, = high) and AD7641 to be configured as either a serial or a parallel NORMAL warp (WARP = high, = low) modes allow the fastest interface. The AD7641 is pin-to-pin-compatible and is a conversion rate of up to 2 MSPS. However, in these modes, the speed upgrade of the AD7674, AD7678, and AD7679. full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two CONVERTER OPERATION consecutive conversions is longer than 1 ms (for instance after The AD7641 is a successive approximation ADC based on a power-up), the first conversion result should be ignored. These charge redistribution DAC. Figure 21 shows the simplified modes make the AD7641 ideal for applications where both high schematic of the ADC. The capacitive DAC consists of two accuracy and fast sample rates are required. Wideband warp identical arrays of 16 binary weighted capacitors that are mode offers slightly improved linearity and THD over warp mode. connected to the two comparator inputs. Normal mode (NORMAL = low, WARP = low) is the fastest During the acquisition phase, terminals of the array tied to the mode (1.5 MSPS) without any limitation on time between comparator’s input are connected to AGND via SW+ and SW−. conversions. This mode makes the AD7641 ideal for All independent switches are connected to the analog inputs. asynchronous applications, such as data acquisition systems, Therefore, the capacitor arrays are used as sampling capacitors where both high accuracy and fast sample rates are required. and acquire the analog signal on the IN+ and IN− inputs. A conversion phase is initiated once the acquisition phase is complete CNVST and the input goes low. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured at the end of the acquisition phase is applied to the comparator inputs, causing the Rev. 0 | Page 15 of 28 04761-021 AD7641 TRANSFER FUNCTIONS Using the OB/2C digital input, except in 18-bit interface mode, Table 8. Output Codes and Ideal Input Voltages the AD7641 offers two output codings: straight binary and twos Digital Output Code (Hex) complement. The LSB size with V = 2.048 V is 2 × V / REF REF Analog Input Straight Twos Description V = 2.048 V Binary Complement 262,144, which is 15.623 μV. Refer to Figure 22 and Table 8 for REF 1 1 the ideal transfer characteristic. FSR −1 LSB +2.0479844 V 0x3FFFF 0x1FFFF FSR − 2 LSB +2.0479688 V 0x3FFFE 0x1FFFE Midscale + 1 LSB +15.625 μV 0x20001 0x00001 111...111 Midscale 0 V 0x20000 0x00000 111...110 111...101 Midscale − 1 LSB −15.625 μV 0x1FFFF 0x3FFFF −FSR + 1 LSB −2.0479844 V 0x30001 0x20001 2 2 −FSR −2.048 V 0x30000 0x20000 1 This is also the code for overrange analog input (VIN+ − VIN− above +V − V ). REF REFGND 2 This is also the code for underrange analog input (VIN+ − VIN− below −V + V ). REF REFGND 000...010 000...001 000...000 –FSR + 1 LSB +FSR – 1 LSB –FSR –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 22. ADC Ideal Transfer Function DIGITAL SUPPLY (2.5V) NOTE 5 DIGITAL 10Ω INTERFACE ANALOG SUPPLY SUPPLY (2.5V) (2.5V OR 3.3V) 100nF 10µF 10µF 100nF 100nF 10µF AVDD AGND DGND DVDD OVDD OGND SERIAL PORT REF NOTE 3 SCLK C REF REFBUFIN 10µF 100nF SDOUT REFGND NOTE 4 BUSY NOTE 2 NOTE 7 MICROCONVERTER/ 50Ω MICROPROCESSOR/ 15Ω D CNVST DSP U1 IN+ 50pF ANALOG INPUT + AD7641 D0/OB/2C C 2.7nF C MODE0 NOTE 1 MODE1 OVDD WARP NORMAL NOTE 2 CS 15Ω CLOCK U2 IN– ANALOG RD INPUT – NOTE 3 C C 2.7nF 50pF PDREF PD PDBUF RESET NOTE 1 10kΩ NOTE 6 1. SEE ANALOG INPUTS SECTION. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4. A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTION, SEE POWER-UP SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 23. Typical Connection Diagram Rev. 0 | Page 16 of 28 ADC CODE (Straight Binary) 04761-022 04761-023 AD7641 TYPICAL CONNECTION DIAGRAM switches. CIN is typically 12 pF and is mainly the ADC sampling Figure 23 shows a typical connection diagram for the AD7641. capacitor. During the conversion phase, when the switches are Different circuitry shown in this diagram is optional and is opened, the input impedance is limited to CPIN. RIN and CIN discussed in the following sections. make a 1-pole, low-pass filter that has a typical −3 dB cutoff ANALOG INPUTS frequency of 50 MHz, thereby reducing an undesirable aliasing effect and limiting the noise coming from the inputs. Figure 24 shows an equivalent circuit of the input structure of the AD7641. Because the input impedance of the AD7641 is very high, the AD7641 can be directly driven by a low impedance source The two diodes, D1 and D2, provide ESD protection for the without gain error. To further improve the noise filtering achieved analog inputs IN+ and IN−. Care must be taken to ensure that by the AD7641 analog input circuit, an external 1-pole RC filter the analog input signal never exceeds the supply rails by more between the amplifier’s outputs and the ADC analog inputs can than 0.3 V, because this causes the diodes to become forward- be used, as shown in Figure 23. However, large source impedances biased and start conducting current. These diodes can handle a significantly affect the ac performance, especially the total forward-biased current of 100 mA maximum. For instance, harmonic distortion (THD). The maximum source impedance these conditions could eventually occur when the input buffer’s depends on the amount of THD that can be tolerated. The THD U1 or U2 supplies are different from AVDD. In such a case, an degrades as a function of the source impedance and the maximum input buffer with a short-circuit current limitation can be used input frequency. to protect the part. AVDD MULTIPLEXED INPUTS When using the full 2 MSPS throughput in multiplexed D 1 R C IN IN IN+ OR IN– applications for a full-scale step, the RC filter, as shown in C PIN D 2 Figure 23, does not settle in the required acquisition time, t8. AGND These values are chosen to optimize the best SNR perform-ance of the AD7641. To use the full 2 MSPS throughput in Figure 24. AD7641 Simplified Analog Input multiplexed applicaitons, the RC should be adjusted to satisfy t 8 (which is ~ 8.5 × RC time constant). However, lowering R and C The analog input of the AD7641 is a true differential structure. increases the RC filter bandwidth and allows more noise into the By using this differential input, small signals common to both AD7641, which degrades SNR. To preserve the SNR performance inputs are rejected, as shown in Figure 25, representing the in these applications using the RC filter shown in Figure 23, typical CMRR over frequency with internal and external references. the AD7641 should be run with t8 > 350 ns; or approximately 65 1/(t7 + t8) ~ 1.35 MSPS in wideband and warp modes. DRIVER AMPLIFIER CHOICE 60 Although the AD7641 is easy to drive, the driver amplifier EXT REF needs to meet the following requirements: INT REF 55 • For multichannel, multiplexed applications, the driver amplifier and the AD7641 analog input circuit must be able to settle for a full-scale step of the capacitor array at an 50 18-bit level (0.0004%). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 18-bit level 45 and should be verified prior to driver selection. The 1 10 100 1000 10000 AD8021 op amp, which combines ultralow noise and high FREQUENCY (kHz) gain bandwidth, meets this settling time requirement even Figure 25. Analog Input CMRR vs. Frequency when used with gains up to 13. During the acquisition phase for ac signals, the impedance of the analog inputs, IN+ and IN−, can be modeled as a parallel combination of capacitor C and the network formed by the PIN series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 175 Ω and is a lumped component comprised of some serial resistors and the on resistance of the Rev. 0 | Page 17 of 28 CMRR (dB) 04761-024 04761-025 AD7641 Single-to-Differential Driver • The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition For applications using unipolar analog signals, a single-ended- noise performance of the AD7641. The noise coming from to-differential driver, as shown in Figure 26, allows for a the driver is filtered by the AD7641 analog input circuit differential input into the part. This configuration, when 1-pole, low-pass filter made by RIN and CIN or by the provided an input signal of 0 to VREF, produces a differential external filter, if one is used. The SNR degradation due ±V with midscale at V /2. The 1-pole filter using R = 10 Ω REF REF to the amplifier is and C = 1 nF provides a corner frequency of 16 MHz. ⎛ ⎞ If the application can tolerate more noise, the AD8139 ⎜ ⎟ 30 ⎜ ⎟ differential driver can be used. SNR = 20log LOSS ⎜ ⎟ πf πf 2 2 −3dB −3dB ⎜ ⎟ 900+ () Ne + () Ne ⎜ N+ N− ⎟ 2 2 ⎝ ⎠ U1 AD8021 ANALOG INPUT (UNIPOLAR 0V TO 2.048V) 10pF where: f–3dB is the input bandwidth of the AD7641 (50 MHz) or 590Ω 15Ω IN+ the cutoff frequency of the input RC filter shown in Figure 23 590Ω 2.7nF (3.9 MHz), if one is used. AD7641 15Ω N is the noise factor of the amplifier (1 in buffer U2 IN– 5kΩ REF AD8021 configuration). 2.7nF 5kΩ 10pF 100nF e and e are the equivalent input voltage noise densities N+ N− 10µF of the op amps connected to IN+ and IN−, in nV/√Hz. This approximation can be used when the resistances used Figure 26. Single-Ended-to-Differential Driver Circuit (Internal Reference Buffer Used) around the amplifier are small. If larger resistances are used, their noise contributions should also be root-sum VOLTAGE REFERENCE INPUT squared. The AD7641 allows the choice of either a very low temperature For instance, when using op amps with an equivalent input drift internal voltage reference or an external reference. noise density of 2.1 nV/√Hz, such as the AD8021, with a noise gain of 1 when configured as a buffer, degrades the Unlike many ADCs with internal references, the internal reference of the AD7641 provides excellent performance and SNR by only 0.25 dB when using the RC filter in Figure 23, can be used in almost all applications. and by 2.5 dB without it. Internal Reference (PDBUF = Low, PDREF = Low) • The driver needs to have a THD performance suitable to that of the AD7641. Figure 13 gives the THD vs. frequency To use the internal reference, the PDREF and PDBUF inputs that the driver should exceed. must both be low. This produces a 1.2 V band gap output on REFBUFIN, which is amplified by the internal buffer and The AD8021 meets these requirements and is appropriate for results in a 2.048 V reference on the REF pin. almost all applications. The AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an The internal reference is temperature compensated to 2.048 V ± NPO ceramic or mica type. Moreover, the use of a noninverting 10 mV. The reference is trimmed to provide a typical drift of 1 gain arrangement is recommended and helps to obtain the 10 ppm/°C. This typical drift characteristic is shown in Figure 7. best signal-to-noise ratio. The output resistance of REFBUFIN is 6.33 kΩ (minimum) The AD8022 can also be used when a dual version is needed when the internal reference is enabled. It is necessary to and a gain of 1 is present. The AD829 is an alternative in decouple this with a ceramic capacitor greater than 100 nF. applications where high frequency (above 100 kHz) performance is Therefore, the capacitor provides an RC filter for noise reduction. not required. In applications with a gain of 1, an 82 pF Because the output impedance of REFBUFIN is typically compensation capacitor is required. The AD8610 is an option 6.33 kΩ, relative humidity (among other industrial contaminates) when low bias current is needed in low frequency applications. can directly affect the drift characteristics of the reference. Typically, a guard ring is used to reduce the effects of drift under such circumstances. Rev. 0 | Page 18 of 28 04761-027 AD7641 However, because the AD7641 has a fine lead pitch, guarding For applications that use multiple AD7641 devices, it is more this node is not practical. Therefore, in these industrial and effective to use an external reference with the internal reference other types of applications, it is recommended to use a conformal buffer to buffer the reference voltage. However, because the coating, such as Dow Corning® 1-2577 or HumiSeal® 1B73. reference buffers are not unity gain, ratiometric, simultaneously sampled designs should use an external reference and external External 1.2 V Reference and Internal Buffer (PDBUF = buffer, such as the AD8031/AD8032; therefore, preserving the Low, PDREF = High) same reference level for all converters. To use an external reference along with the internal buffer, PDREF should be high and PDBUF should be low. This powers The voltage reference temperature coefficient (TC) directly down the internal reference and allows the 1.2 V reference to impacts full scale; therefore, in applications where full-scale be applied to REFBUFIN, producing 2.048 V (typically) on accuracy matters, care must be taken with the TC. For instance, the REF pin. a ±4 ppm/°C TC of the reference changes full scale by ±1 LSB/°C. External 2.5 V Reference (PDBUF = High, PDREF = High) Note that VREF can be increased to AVDD + 0.1 V. Because the To use an external 2.5 V reference directly on the REF pin, input range is defined in terms of VREF, this would essentially PDREF and PDBUF should both be high. increase the range to 0 V to 2.8 V with an AVDD = 2.7 V. For improved drift performance, an external reference, such as Temperature Sensor the AD780 or ADR431, can be used. The advantages of directly The TEMP pin measures the temperature of the AD7641. To using the external voltage reference are: improve the calibration accuracy over the temperature range, • The SNR and dynamic range improvement (about 1.7 dB) the output of the TEMP pin is applied to one of the inputs of resulting from the use of a reference voltage very close to the analog switch (such as, ADG779), and the ADC itself is the supply (2.5 V) instead of a typical 2.048 V reference used to measure its own temperature. This configuration is when the internal reference is used. This is calculated by shown in Figure 27. 2.048 ⎛ ⎞ TEMP ADG779 SNR= 20log ⎜ ⎟ ⎝ 2.50⎠ TEMPERATURE ANALOG INPUT IN+ SENSOR • The power savings when the internal reference is powered (UNIPOLAR) AD7641 C down (PDREF high). AD8021 C PDREF and PDBUF power down the internal reference and Figure 27. Use of the Temperature Sensor the internal reference buffer, respectively. The input current of PDREF and PDBUF should never exceed 20 mA. This can occur when the driving voltage is above AVDD (for instance, at power-up). In this case, a 125 Ω series resistor is recommended. Reference Decoupling Whether using an internal or external reference, the AD7641 voltage reference input (REF) has a dynamic input impedance; therefore, it should be driven by a low impedance source with efficient decoupling between the REF and REFGND inputs. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and REFGND with minimum parasitic inductance. A 10 μF (X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum capacitor) is appropriate when using either the internal reference or one of the recommended reference voltages. The placement of the reference decoupling is also important to the performance of the AD7641. The decoupling capacitor should be mounted on the same side as the ADC right at the REF pin with a thick PCB trace. The REFGND should also connect to the reference decoupling capacitor with the shortest distance. Rev. 0 | Page 19 of 28 04761-028 AD7641 POWER SUPPLY It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital The AD7641 uses three sets of power supply pins: an analog supply currents even further, drive the digital inputs close to 2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a the power rails (that is, OVDD and OGND). digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.3 V CONVERSION CONTROL and 5.25 V. To reduce the number of supplies needed, the digital CNVST The AD7641 is controlled by the input. A falling edge core (DVDD) can be supplied through a simple RC filter from CNVST on is all that is necessary to initiate a conversion. Figure 23. the analog supply, as shown in Detailed timing diagrams of the conversion process are shown Power Sequencing in Figure 29. Once initiated, it cannot be restarted or aborted, The AD7641 is independent of power supply sequencing and even by the power-down input, PD, until the conversion is thus free from supply induced voltage latch-up. In addition, it is complete. The CNVST signal operates independently of CS and very insensitive to power supply variations over a wide RD signals. frequency range, as shown in Figure 28. t 2 t 65.0 1 62.5 CNVST 60.0 57.5 BUSY EXT REF t 4 t 55.0 3 t 6 t 5 52.5 INT REF MODE ACQUIRE CONVERT ACQUIRE CONVERT 50.0 t t 7 8 Figure 29. Basic Conversion Timing 47.5 45.0 For optimal performance, the rising edge of CNVST should not 1 10 100 1000 10000 occur after the maximum CNVST low time, t , or until the end 1 FREQUENCY (MHz) of conversion. Figure 28. PSRR vs. Frequency Although is a digital signal, it should be designed with Power-Up CNVST special care with fast, clean edges and levels with minimum At power-up, or returning to operational mode from the power- overshoot and undershoot or ringing. down mode (PD = high), the AD7641 engages an initialization process. During this time, the first 128 conversions should be The CNVST trace should be shielded with ground and a low ignored or the RESET input could be pulsed to engage a faster value serial resistor (for example, 50 Ω) termination should be initialization process. Refer to the Digital Interface section for added close to the output of the component that drives this line. RESET and timing details. In addition, a 50 pF capacitor is recommended to further reduce the effects of overshoot and undershoot as shown in Figure 23. A simple power-on reset circuit, as shown in Figure 23, can be used to minimize the digital interface. As OVDD powers up, the For applications where SNR is critical, the CNVST signal should capacitor is shorted and brings RESET high; it is then charged have very low jitter. This can be achieved by using a dedicated returning RESET to low. However, this circuit only works when generation, or by clocking with a oscillator for CNVST CNVST powering up the AD7641 because the power-down mode high frequency, low jitter clock, as shown in Figure 23. (PD = high) does not power down any of the supplies and as a result, RESET is low. Rev. 0 | Page 20 of 28 PSRR (dB) 04761-029 04761-030 AD7641 INTERFACES DIGITAL INTERFACE PARALLEL INTERFACE The AD7641 has a versatile digital interface that can be set up The AD7641 is configured to use the parallel interface for an as either a serial or a parallel interface with the host system. The 18-bit, 16-bit, or 8-bit bus width according to Table 7. serial interface is multiplexed on the parallel data bus. The AD7641 Master Parallel Interface digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic Data can be continuously read by tying CS and RD low, thus with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic requiring minimal microprocessor connections. However, in high output voltage. In most applications, the OVDD supply pin this mode, the data bus is always driven and cannot be used in of the AD7641 is connected to the host system interface 2.5 V shared bus applications, unless the device is held in RESET. 2C or 3.3 V digital supply. By using the D0/OB/ input pin, either Figure 31 details the timing for this mode. twos complement or straight binary coding can be used. CS = RD = 0 CS RD The two signals and control the interface. When at least t 1 CNVST one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7641 in t 10 multicircuit applications and is held low in a single AD7641 BUSY design. RD is generally used to enable the conversion result on t 4 t 3 t the data bus. 11 DATA PREVIOUS CONVERSION DATA NEW DATA BUS RESET Figure 31. Master Parallel Data Timing for Reading (Continuous Read) The RESET input is used to reset the AD7641 and generate a fast initialization. A rising edge on RESET aborts the current Slave Parallel Interface conversion (if any) and tristates the data bus. The falling edge of In slave parallel reading mode, the data can be read either after RESET clears the data bus and engages the initialization process each conversion, which is during the next acquisition phase, or indicated by pulsing BUSY high. Conversions can take place during the following conversion, as shown in Figure 32 and after the falling edge of BUSY. Refer to Figure 30 for the RESET Figure 33, respectively. When the data is read during the timing details. conversion, it is recommended that it is read-only during the t first half of the conversion phase. This avoids any potential 9 RESET feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. CNVST CS DATA BUSY RD t t t 38 39 8 Figure 30. RESET Timing BUSY DATA CURRENT BUS CONVERSION t t 12 13 Figure 32. Slave Parallel Data Timing for Reading (Read After Convert) Rev. 0 | Page 21 of 28 04761-031 04761-033 04761-032 AD7641 CS = 0 SERIAL INTERFACE CNVST, t 1 RD The AD7641 is configured to use the serial interface when MODE[1:0] = 3. The AD7641 outputs 18 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 18 clock pulses provided on the SCLK pin. The output data is valid on BUSY t 4 both the rising and falling edge of the data clock. t 3 MASTER SERIAL INTERFACE Internal Clock DATA PREVIOUS BUS CONVERSION The AD7641 is configured to generate and provide the serial t t 12 13 data clock SCLK when the EXT/ pin is held low. The INT Figure 33. Slave Parallel Data Timing for Reading (Read During Convert) AD7641 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the 16-Bit and 8-Bit Interface (Master or Slave) SYNC signal can be inverted. Depending on the read during In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2) convert input, RDC/SDIN, the data can be read after each interfaces, the A0/A1 pins allow a glueless interface to a 16- or conversion or during the following conversion. Figure 35 and 8-bit bus, as shown in Figure 34. By connecting A0/A1 to an Figure 36 show detailed timing diagrams of these two modes. address line(s), the data can be read in two words for a 16-bit interface, or three bytes for an 8-bit interface. This interface can Usually, because the AD7641 is used with a fast throughput, the be used in both master and slave parallel reading modes. Refer master read during conversion mode is the most recommended to Table 7 for the full details of the interface. serial mode. In this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between CS, RD digital activity and critical conversion decisions. In this mode, the SCLK period changes because the LSBs require more time to settle and the SCLK is derived from the SAR conversion cycle. A1 In read after conversion mode, it should be noted that unlike A0 other modes, the BUSY signal returns low after the 18 data bits are pulsed out and not at the end of the conversion phase, HI-Z HI-Z HIGH LOW D[17:2] WORD WORD resulting in a longer BUSY width. As a result, the maximum throughput cannot be achieved in this mode. HI-Z HI-Z HIGH MID LOW D[17:10] BYTE BYTE BYTE In addition, in read after convert mode, the SCLK frequency t t t t 12 12 12 13 can be slowed down to accommodate different hosts using the Figure 34. 8-Bit and 16-Bit Parallel Interface DIVSCLK[1:0] inputs. Refer to Table 4 for the SCLK timing details when using these inputs. Rev. 0 | Page 22 of 28 04761-035 045761-034 AD7641 INVSCLK = INVSYNC = 0 DIVSCLK[1:0] = 0 EXT/INT = 0 RDC/SDIN = 0 CS, RD t 3 CNVST t BUSY 28 t 30 t 29 t 25 SYNC t t 18 14 t 19 t t t 24 20 21 t 26 12 3 16 17 18 SCLK t 15 t 27 SDOUT D17 D16 D2 D1 D0 X t 16 t 23 t 22 Figure 35. Master Serial Data Timing for Reading (Read After Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 19 14 t t 20 21 t 24 t 26 t 15 SCLK 12 3 16 17 18 t 18 t 27 SDOUT X D17 D16 D2 D1 D0 t t 16 23 t 22 Figure 36. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 23 of 28 04761-036 04761-037 AD7641 SLAVE SERIAL INTERFACE External Clock An example of the concatenation of two devices is shown in Figure 37. Simultaneous sampling is possible by using a The AD7641 is configured to accept an externally supplied CNVST common signal. It should be noted that the RDC/SDIN serial data clock on the SCLK pin when the EXT/ pin is INT input is latched on the edge of SCLK opposite to the one used to held high. In this mode, several methods can be used to read shift out the data on SDOUT. Therefore, the MSB of the the data. The external serial clock is gated by CS. When CS and upstream converter just follows the LSB of the downstream are both low, the data can be read after each conversion or RD converter on the next SCLK cycle. during the following conversion. The external clock can be either a continuous or a discontinuous clock. A discontinuous BUSY OUT clock can be either normally high or normally low when inactive. Figure 38 and Figure 39 show the detailed timing BUSY BUSY diagrams of these methods. AD7641 AD7641 #2 #1 (UPSTREAM) (DOWNSTREAM) While the AD7641 is performing a bit decision, it is important DATA RDC/SDIN SDOUT RDC/SDIN SDOUT OUT that voltage transients be avoided on digital input/output pins CNVST CNVST or degradation of the conversion result could occur. This is CS particularly important during the second half of the conversion CS phase because the AD7641 provides error correction circuitry SCLK SCLK that can correct for an improper bit decision made during SCLK IN the first half of the conversion phase. For this reason, it is CS IN recommended that when an external clock is being provided, CNVST IN a discontinuous clock is toggled only when BUSY is low or, Figure 37.Two AD7641 Devices in a Daisy-Chain Configuration more importantly, that it does not transition during the latter External Clock Data Read During Previous Conversion half of BUSY high. Figure 39 shows the detailed timing diagrams of this method. External Discontinuous Clock Data Read After Conversion During a conversion, while CS and RD are both low, the result Though the maximum throughput cannot be achieved using of the previous conversion can be read. The data is shifted out, this mode, it is the most recommended of the serial slave MSB first, with 16 clock pulses and is valid on both the rising modes. Figure 38 shows the detailed timing diagrams of this and falling edge of the clock. The 18 bits have to be read before method. After a conversion is complete, indicated by BUSY the current conversion is complete; otherwise, RDERROR is returning low, the conversion result can be read while both CS pulsed high and can be used to interrupt the host interface to and are low. Data is shifted out MSB first with 18 clock RD prevent incomplete data reading. There is no daisy-chain pulses and is valid on the rising and falling edges of the clock. feature in this mode, and the RDC/SDIN input should always be tied either high or low. Among the advantages of this method is the fact that conversion performance is not degraded because there are no voltage To reduce performance degradation due to digital activity, a fast transients on the digital interface during the conversion process. discontinuous clock (at least 60 MHz when normal mode is Another advantage is the ability to read the data at any speed up used, or 80 MHz when warp mode is used) is recommended to to 80 MHz, which accommodates both the slow digital host ensure that all the bits are read during the first half of the SAR interface and the fast serial reading. conversion phase. Finally, in this mode only, the AD7641 provides a daisy-chain It is also possible to begin to read data after conversion and feature using the RDC/SDIN pin for cascading multiple converters continue to read the last bits after a new conversion is initiated. together. This feature is useful for reducing component count However, this is not recommended when using the fastest and wiring connections when desired, as, for instance, in throughput of any mode because the acquisition time, t8, is isolated multiconverter applications. only 115 ns. If the maximum throughput is not used, thus allowing more acquisition time, then the use of a slower clock speed can be used to read the data. Rev. 0 | Page 24 of 28 04761-038 AD7641 RD = 0 EXT/INT = 1 INVSCLK = 0 CS BUSY t 35 t t 36 37 SCLK 12 3 16 17 18 19 20 t 31 t 32 X D17 D16 D15 D1 X17 X16 SDOUT D0 t 16 t 34 SDIN X17 X16 X15 X1 X0 Y17 Y16 t 33 Figure 38. Slave Serial Data Timing for Reading (Read After Convert) t 31 RD = 0 EXT/INT = 1 INVSCLK = 0 CS t 3 CNVST t 35 BUSY t t 36 37 SCLK 16 2 3 4 17 18 1 t 32 SDOUT X D17 D16 D15 D2 D1 D0 t 16 Figure 39. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 25 of 28 04761-039 04761-040 AD7641 SPI Interface (ADSP-219x) MICROPROCESSOR INTERFACING Figure 40 shows an interface diagram between the AD7641 and The AD7641 is ideally suited for traditional dc measurement an SPI-equipped DSP, the ADSP-219x. To accommodate the applications supporting a microprocessor, and ac signal processing slower speed of the DSP, the AD7641 acts as a slave device and applications interfacing to a digital signal processor. The data must be read after conversion. This mode also allows the AD7641 is designed to interface with a parallel 8-bit or 16-bit daisy-chain feature. The convert command can be initiated in wide interface or with a general-purpose serial port or I/O ports response to an internal timer interrupt. The 18-bit output data on a microcontroller. A variety of external buffers can be used are read with three SPI byte access. The reading process can be with the AD7641 to prevent digital noise from coupling into the initiated in response to the end-of-conversion signal (BUSY ADC. The SPI Interface (ADSP-219x) section illustrates the use going low) using an interrupt line of the DSP. The serial of the AD7641 with the ADSP-219x SPI-equipped DSP. peripheral interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock phase bit (CPHA) = 1, and the SPI interrupt enable (TIMOD) = 00 by writing to the SPI control register (SPICLTx). It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mb/s, allowing it to read an ADC result in less than 1 μs. When a higher sampling rate is desired, it is recommended to use one of the parallel interface modes. DVDD 1 AD7641 ADSP-219x MODE0 MODE1 BUSY PFx EXT/INT CS SPIxSEL (PFx) SDOUT MISOx RD SCLK SCKx INVSCLK CNVST PFx OR TFSx 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 40. Interfacing the AD7641 to ADSP-219x Rev. 0 | Page 26 of 28 04761-041 AD7641 APPLICATION HINTS LAYOUT The DVDD supply of the AD7641 can be either a separate supply or come from the analog supply, AVDD, or from the While the AD7641 has very good immunity to noise on the digital interface supply, OVDD. When the system digital supply power supplies, exercise care with the grounding layout. To is noisy, or fast switching digital signals are present, and no facilitate the use of ground planes that can be easily separated, separate supply is available, it is recommended to connect the design the printed circuit board that houses the AD7641 so that DVDD digital supply to the analog supply AVDD through an the analog and digital sections are separated and confined to RC filter, and to connect the system supply to the interface certain areas of the board. Digital and analog ground planes digital supply OVDD and the remaining digital circuitry. Refer should be joined in only one place, preferably underneath the to Figure 23 for an example of this configuration. When DVDD AD7641, or as close as possible to the AD7641. If the AD7641 is is powered from the system supply, it is useful to insert a bead in a system where multiple devices require analog-to-digital to further reduce high frequency spikes. ground connections, the connections should still be made at one point only, a star ground point, established as close as The AD7641 has four different ground pins: REFGND, AGND, possible to the AD7641. DGND, and OGND. REFGND senses the reference voltage and, because it carries pulsed currents, should have a low impedance To prevent coupling noise onto the die, to avoid radiating noise, return to the reference. AGND is the ground to which most and to reduce feedthrough: internal ADC analog signals are referenced; it must be connected • Do not run digital lines under the device. with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the • Run the analog ground plane under the AD7641. configuration. OGND is connected to the digital system ground. CNVST • Shield fast switching signals, like or clocks, with The layout of the decoupling of the reference voltage is digital ground to avoid radiating noise to other sections of important. To minimize parasitic inductances, place the the board, and never run them near analog signal paths. decoupling capacitor close to the ADC and connect it with short, thick traces. • Avoid crossover of digital and analog signals. EVALUATING THE AD7641 PERFORMANCE • Run traces on different but close layers of the board, at right A recommended layout for the AD7641 is outlined in the angles to each other, to reduce the effect of feedthrough documentation of the EVAL-AD7641-CB evaluation board for through the board. the AD7641. The evaluation board package includes a fully The power supply lines to the AD7641 should use as large a assembled and tested evaluation board, documentation, and trace as possible to provide low impedance paths and reduce the software for controlling the board from a PC via the EVAL- effect of glitches on the power supply lines. Good decoupling is CONTROL BRD3. also important to lower the impedance of the supplies presented to the AD7641, and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, and OVDD. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. Rev. 0 | Page 27 of 28 PAD AD7641 OUTLINE DIMENSIONS 0.75 1.60 9.00 0.60 MAX BSC SQ 0.45 48 37 36 1 PIN 1 7.00 TOP VIEW BSC SQ 1.45 0.20 (PINS DOWN) 1.40 0.09 1.35 7° 3.5° 25 12 0.15 0° 13 24 SEATING 0.05 0.08 MAX 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 41. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 0.40 25 12 24 13 0.30 0.25 MIN 5.50 REF 0.80 MAX PADDLE CONNECTED TO AGND. 1.00 THIS CONNECTION IS NOT 12° MAX 0.65 TYP 0.85 REQUIRED TO MEET THE 0.05 MAX ELECTRICAL PERFORMANCES. 0.80 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 42. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7641BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7641BCPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7641BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 1 AD7641BSTZRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 2 EVAL-AD7641CB Evaluation Board 3 EVAL-CONTROLBRD3 Controller Board 1 Z = Pb-free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04761-0-1/06(0) Rev. 0 | Page 28 of 28