ANALOG DEVICES AD7634

18-Bit, 670 kSPS, Differential ® Programmable Input PulSAR ADC AD7634 FEATURES FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND Multiple pins/software-programmable input ranges 5 V (10 V p-p), +10 V (20 V p-p), ±5 V (20 V p-p), OVDD AGND AD7634 ±10 V (40 V p-p) REF OGND AVDD AMP SERIAL DATA Pins or serial SPI®-compatible input ranges/mode selection REF PDREF PORT Throughput SERIAL PDBUF CONFIGURATION 670 kSPS (warp mode) PORT 18 IN+ SWITCHED D[17:0] CAP DAC 570 kSPS (normal mode) IN– BUSY 450 kSPS (impulse mode) RD INL: ±1.5 LSB typical, ±2.5 LSB maximum (±9.5 ppm of FSR) PARALLEL CS CLOCK INTERFACE CNVST 18-bit resolution with no missing codes D0/OB/2C PD CONTROL LOGIC AND Dynamic range: 102.5 dB D1/A0 CALIBRATION CIRCUITRY RESET SNR: 101 dB @ 2 kHz D2/A1 THD: −112 dB @ 2kHz iCMOS® process technology WARP IMPULSE BIPOLAR TEN MODE0 MODE1 5 V internal reference: typical drift 3 ppm/°C; TEMP output Figure 1. No pipeline delay (SAR architecture) Table 1. 48-Lead PulSAR Selection Parallel (18-/16-/8-bit bus) and serial 5 V/3.3 V interface 100 to 500 to 570 to SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Res 250 570 1000 >1000 Power dissipation Input Type (Bits) (kSPS) (kSPS) (kSPS) (kSPS) 180 mW @ 670 kSPS, warp mode Bipolar 14 AD7951 28 mW @ 100 kSPS, impulse mode Differential 14 AD7952 10 mW @ 1 kSPS, impulse mode Bipolar Pb-free, 48-lead LQFP and 48-Lead LFCSP (7 mm × 7 mm) Unipolar 16 AD7651 AD7650 AD7653 AD7660 AD7652 AD7667 APPLICATIONS AD7661 AD7664 CT scanners AD7666 High dynamic data acquisition Bipolar 16 AD7610 AD7665 AD7612 AD7663 AD7671 Σ-Δ replacement Spectrum analysis Differential 16 AD7675 AD7676 AD7677 AD7621 Unipolar AD7622 Medical instruments AD7623 Instrumentation 16 Simultaneous/ AD7654 Process controls Multichannel AD7655 Unipolar GENERAL DESCRIPTION Differential 18 AD7678 AD7679 AD7674 AD7641 The AD7634 is an 18-bit charge redistribution successive Unipolar AD7643 approximation register (SAR), architecture analog-to- Differential 18 AD7631 AD7634 digital converter (ADC) fabricated on Analog Devices, Inc.’s Bipolar iCMOS high voltage process. The device is configured through hardware or via a dedicated write-only serial configuration port for input range and operating mode. The AD7634 contains a high speed 18-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. A falling edge on CNVST samples the fully differential analog inputs on IN+ and IN−. The AD7634 features four different analog input ranges and three different sampling modes. Operation is specified from −40°C to +85°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 06406-001 AD7634 TABLE OF CONTENTS Features .............................................................................................. 1  Driver Amplifier Choice ........................................................... 21  Applications....................................................................................... 1  Voltage Reference Input/Output .............................................. 22  General Description ......................................................................... 1  Power Supplies............................................................................ 22  Functional Block Diagram .............................................................. 1  Conversion Control ................................................................... 23  Revision History ............................................................................... 2  Interfaces.......................................................................................... 24  Specifications..................................................................................... 3  Digital Interface.......................................................................... 24  Timing Specifications .................................................................. 5  Parallel Interface......................................................................... 24  Absolute Maximum Ratings............................................................ 7  Serial Interface ............................................................................ 25  ESD Caution.................................................................................. 7  Master Serial Interface............................................................... 25  Pin Configuration and Function Descriptions............................. 8  Slave Serial Interface .................................................................. 27  Typical Performance Characteristics ........................................... 12  Hardware Configuration ........................................................... 29  Terminology .................................................................................... 16  Software Configuration ............................................................. 29  Theory of Operation ...................................................................... 17  Microprocessor Interfacing....................................................... 30  Overview...................................................................................... 17  Application Information................................................................ 31  Converter Operation.................................................................. 17  Layout Guidelines....................................................................... 31  Modes of Operation ................................................................... 17  Evaluating Performance ............................................................ 31  Transfer Functions...................................................................... 18  Outline Dimensions....................................................................... 32  Typical Connection Diagram ................................................... 19  Ordering Guide .......................................................................... 32  Analog Inputs.............................................................................. 20  REVISION HISTORY 3/11—Rev. 0 to Rev. A Changes to Resolution Parameter, Table 2 .................................... 3 Changes to Figure 4 and Table 6..................................................... 8 Added Exposed Pad Notation to Outline Dimensions ............. 32 1/07—Revision 0: Initial Version Rev. A | Page 2 of 32 AD7634 SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 18 Bits ANALOG INPUTS Differential Voltage Range, VIN (VIN+) − (VIN−) 0 V to 5 V V = 10 V p-p −V +V V IN REF REF 0 V to 10 V VIN = 20 V p-p −2 VREF +2 VREF V ±5 V V = 20 V p-p −2 V +2 V V IN REF REF ±10 V V = 40 V p-p −4 V +4 V V IN REF REF Operating Voltage Range VIN+, VIN− to AGND 0 V to 5 V −0.1 +5.1 V 0 V to 10 V −0.1 +10.1 V ±5 V −5.1 +5.1 V ±10 V −10.1 +10.1 V Common-Mode Voltage Range VIN+, VIN− 5 V VREF/2 − 0.1 VREF/2 VREF/2 + 0.1 V 10 V V − 0.2 V V + 0.2 V REF REF REF Bipolar Ranges −0.1 0 +0.1 V Analog Input CMRR f = 100 kHz 75 dB IN 1 Input Current VIN = ±5 V, ±10 V @ 670 kSPS 220 μA Input Impedance See
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*OQVUT section THROUGHPUT SPEED Complete Cycle In warp mode 1.49 μs Throughput Rate In warp mode 1 670 kSPS Time Between Conversions In warp mode 1 ms Complete Cycle In normal mode 1.75 μs Throughput Rate In normal mode 0 570 kSPS Complete Cycle In impulse mode 2.22 μs Throughput Rate In impulse mode 0 450 kSPS DC ACCURACY 2 3 Integral Linearity Error 600 kSPS throughput −2.5 ±1.5 +2.5 LSB Integral Linearity Error 670 kSPS throughput ±1.5 LSB No Missing Codes 18 Bits 2 Differential Linearity Error −1 + 2.5 LSB Transition Noise 0.75 LSB Unipolar Zero Error −0.06 + 0.06 %FS Bipolar Zero Error −0.03 + 0.03 %FS Zero Error Temperature Drift ±0.5 ppm/°C Bipolar Full-Scale Error −0.09 +0.09 %FS Unipolar Full-Scale Error −0.07 +0.07 %FS Full-Scale Error Temperature Drift ±0.5 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% 3 LSB AC ACCURACY 4 Dynamic Range VIN = 0 to 5 V, fIN = 2 kHz, −60 dB 100 101.8 dB VIN = all other input ranges, fIN = 2 kHz, −60 dB 100 102.5 dB Signal-to-Noise Ratio (SNR) V = 0 to 5 V, f = 2 kHz 98.5 100.5 dB IN IN VIN = all other input ranges, fIN = 2 kHz 98.5 101 dB Signal-to-(Noise + Distortion), SINAD f = 2 kHz 100 dB IN Total Harmonic Distortion f = 2 kHz 112 dB IN Spurious-Free Dynamic Range fIN = 2 kHz 113 dB −3 dB Input Bandwidth V = 0 V to 5 V 45 MHz IN SAMPLING DYNAMICS Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 500 ns Rev. A | Page 3 of 32 AD7634 Parameter Conditions/Comments Min Typ Max Unit INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 4.965 5.000 5.035 V Temperature Drift −40°C to +85°C ±3 ppm/°C Line Regulation AVDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time C = 22 μF 10 ms REF REFERENCE BUFFER PDREF = high REFBUFIN Input Voltage Range 2.4 2.5 2.6 V EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 4.75 5 AVDD + 0.1 V Current Drain 670 kSPS throughput 250 μA TEMPERATURE PIN Voltage Output @ 25°C 311 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.33 kΩ DIGITAL INPUTS Logic Levels V −0.3 +0.6 V IL VIH 2.1 OVDD + 0.3 V I −1 +1 μA IL I −1 +1 μA IH DIGITAL OUTPUTS Data Format Parallel or serial 18-bit 5 Pipeline Delay V I = 500 μA 0.4 V OL SINK VOH ISOURCE = –500 μA OVDD − 0.6 V POWER SUPPLIES Specified Performance 6 AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V VCC 7 15 15.75 V VEE −15.75 −15 0 V 7 , 8 Operating Current @ 670 kSPS throughput AVDD With Internal Reference 18.2 mA With Internal Reference Disabled 16.5 mA DVDD 7.1 mA OVDD 0.3 mA VCC VCC = 15 V, with internal reference buffer 2.9 mA VCC = 15 V 2 mA VEE VEE = −15 V 2 mA Power Dissipation @ 670 kSPS throughput With Internal Reference PDREF = PDBUF = low 195 225 mW With Internal Reference Disabled PDREF = PDBUF = high 175 205 mW 9 In Power-Down Mode PD = high 10 μW 10 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 With VIN = unipolar 5 V or unipolar 10 V ranges, the input current is typically 70 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section. 2 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference. 3 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference. 4 All specifications in decibels are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Conversion results are available immediately after completed conversion. 6 4.75 V or V – 0.1 V, whichever is larger. REF 7 Tested in parallel reading mode. 8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low. 9 With all digital inputs forced to OVDD. 10 Consult sales for extended temperature range. Rev. A | Page 4 of 32 AD7634 TIMING SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (See Figure 35 and Figure 36) Convert Pulse Width t1 10 ns Time Between Conversions t2 1 Warp Mode/Normal Mode/Impulse Mode 1.49/1.75/2.22 μs CNVST Low to BUSY High Delay t 35 ns 3 BUSY High All Modes (Except Master Serial Read After Convert) t 4 1.18/1.43/1.68 Warp Mode/Normal Mode/Impulse Mode μs Aperture Delay t5 2 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time t 7 Warp Mode/Normal Mode/Impulse Mode 1.18/1.43/1.68 μs Acquisition Time, All modes t 310 ns 8 RESET Pulse Width t9 10 ns PARALLEL INTERFACE MODES (See Figure 37 and Figure 39) CNVST Low to Data Valid Delay t10 1.15/1.40/1.65 Warp Mode/Normal Mode/Impulse Mode μs Data Valid to BUSY Low Delay t11 20 ns Bus Access Request to Data Valid t 40 ns 12 Bus Relinquish Time t 2 15 ns 13 2 MASTER SERIAL INTERFACE MODES (See Figure 41 and Figure 42) CS Low to SYNC Valid Delay t 10 ns 14 2 CS Low to Internal SDCLK Valid Delay t 10 ns 15 t 10 ns CS Low to SDOUT Delay 16 CNVST Low to SYNC Delay, Read During Convert t17 50/290/530 Warp Mode/Normal Mode/Impulse Mode ns SYNC Asserted to SDCLK First Edge Delay t18 3 ns 3 Internal SDCLK Period t 30 45 ns 19 3 Internal SDCLK High t 15 ns 20 3 Internal SDCLK Low t21 10 ns 3 SDOUT Valid Setup Time t22 4 ns 3 SDOUT Valid Hold Time t23 5 ns 3 SDCLK Last Edge to SYNC Delay t 5 ns 24 CS High to SYNC High-Z t 10 ns 25 CS High to Internal SDCLK High-Z t 10 ns 26 CS High to SDOUT High-Z t27 10 ns 3 BUSY High in Master Serial Read After Convert t28 See Table 4 CNVST Low to SYNC Delay Read After Convert Warp Mode/Normal Mode/Impulse Mode t 1.1/1.3/1.5 μs 29 SYNC Deasserted to BUSY Low Delay t 25 ns 30 Rev. A | Page 5 of 32 AD7634 Parameter Symbol Min Typ Max Unit 2 SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES (See Figure 44, Figure 45, and Figure 47) External SDCLK, SCCLK Setup Time t31 5 ns External SDCLK Active Edge to SDOUT Delay t 2 18 ns 32 SDIN/SCIN Setup Time t 5 ns 33 SDIN/SCIN Hold Time t 5 ns 34 External SDCLK/SCCLK Period t35 25 ns External SDCLK/SCCLK High t36 10 ns External SDCLK/SCCLK Low t37 10 ns 1 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load C of 10 pF; otherwise, the load is 60 pF maximum. L 3 In serial master read during convert mode. See Table 4 for serial master read after convert mode. Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns Internal SDCLK Period Minimum t19 30 60 120 240 ns Internal SDCLK Period Maximum t19 45 90 180 360 ns Internal SDCLK High Minimum t 15 30 60 120 ns 20 Internal SDCLK Low Minimum t 10 25 55 115 ns 21 SDOUT Valid Setup Time Minimum t 4 20 20 20 ns 22 SDOUT Valid Hold Time Minimum t23 5 8 35 90 ns SDCLK Last Edge to SYNC Delay Minimum t24 5 7 35 90 ns BUSY High Width Maximum t28 Warp Mode 1.98 2.78 4.34 7.46 μs Normal Mode 2.23 3.03 4.59 7.71 μs Impulse Mode 2.48 3.28 4.84 7.96 μs 1.6mA I OL TO OUTPUT 1.4V PIN C L 60pF 2V 500µA I 0.8V OH t t DELAY DELAY NOTES 1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK, 2V 2V AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD 0.8V 0.8V C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 2. Load Circuit for Digital Interface Timing, Figure 3. Voltage Reference Levels for Timing SDOUT, SYNC, and SDCLK Outputs, C = 10 pF L Rev. A | Page 6 of 32 06406-002 06406-003 AD7634 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Analog Inputs/Outputs rating only; functional operation of the device at these or any 1 1 IN+ , IN− to AGND VEE − 0.3 V to VCC + 0.3 V other conditions above those indicated in the operational REF, REFBUFIN, TEMP, AVDD + 0.3 V to section of this specification is not implied. Exposure to absolute REFGND to AGND AGND − 0.3 V maximum rating conditions for extended periods may affect Ground Voltage Differences device reliability. AGND, DGND, OGND ±0.3 V ESD CAUTION Supply Voltages AVDD, DVDD, OVDD −0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD ±7 V VCC to AGND, DGND –0.3 V to +16.5 V VEE to GND +0.3 V to −16.5 V Digital Inputs −0.3 V to OVDD + 0 .3 V PDREF, PDBUF ±20 mA 2 Internal Power Dissipation 700 mW 3 Internal Power Dissipation 2.5 W Junction Temperature 125°C Storage Temperature Range −65°C to +125°C 1 See the Analog Inputs section. 2 Specification is for the device in free air: 48-lead LFQP; θJA = 91°C/W, θ = 30°C/W. JC 3 Specification is for the device in free air: 48-lead LFCSP; θJA = 26°C/W. Rev. A | Page 7 of 32 AD7634 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 BIPOLAR PIN 1 AVDD 2 35 CNVST 3 34 MODE0 PD MODE1 4 33 RESET 5 32 D0/OB/2C CS AD7634 6 31 WARP RD TOP VIEW IMPULSE 7 30 TEN (Not to Scale) 8 29 D1/A0 BUSY 9 28 D2/A1 D17/SCCS 10 27 D16/SCCLK D3 11 26 D15/SCIN D4/DIVSCLK[0] 12 25 D14/HW/SW D5/DIVSCLK[1] 13 14 15 16 17 18 19 20 21 22 23 24 NOTES 1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED PAD SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. Figure 4. Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be refer- enced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. 3, 4 MODE[0:1] DI Data Input/Output Interface Mode Selection. Interface Mode MODE1 MODE0 Description 0 Low Low 18-bit interface 1 Low High 16-bit interface 2 High Low 8-bit (byte) interface 3 High High Serial interface 2 5 D0/OB/2C DI/O In 18-bit parallel mode, this output is used as Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight binary or twos complement. When OB/2C = high, the digital output is straight binary When OB/2C = low, the MSB is inverted resulting in a twos complement output from its internal shift register. 2 6 WARP DI Conversion Mode Selection. See the Modes of Operation section for a more detailed description. Used in conjunction with the IMPULSE input per the following: Conversion Mode WARP IMPULSE Normal Low Low Impulse Low High Warp High Low Normal High High 2 7 IMPULSE DI Conversion Mode Selection. See the WARP pin description in this table. See the Modes of Operation section for a more detailed description. Rev. A | Page 8 of 32 D6/EXT/INT PDBUF D7/INVSYNC PDREF D8/INVSCLK REFBUFIN D9/RDC/SDIN TEMP OGND AVDD OVDD IN+ DVDD AGND DGND VEE D10/SDOUT VCC D11/SDCLK IN– D12/SYNC REFGND REF D13/RDERROR 06406-004 AD7634 1 Pin No. Mnemonic Type Description 8 D1/A0 DI/O When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output as shown in Table 7. 9 D2/A1 DI/O When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus. When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7. 10 D3 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. 11, 12 D[4:5] or DI/O When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus. DIVSCLK[0:1] When MODE[1:0] = 3, serial data clock division selection. When using serial master read after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. 13 D6 or DO/I When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus. When MODE[1:0] = 3, Serial Data Clock Source Select. In serial mode, this input is used to select EXT/INT the internally generated (master) or external (slave) serial data clock for the AD7634 output data. When EXT/INT = low (master mode), the internal serial data clock is selected on SDCLK output. When EXT/INT = high (slave mode), the output data is synchronized to an external clock signal (gated by CS) connected to the SDCLK input. 14 D7 or When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus. DI/O INVSYNC When MODE[1:0] = 3, Serial Data Invert Sync Select. In serial master mode (MODE[1:0] = 3, EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D8 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus. INVSCLK When MODE[1:0] = 3, Invert SDCLK/SCCLK Select. This input is used to invert both SDCLK and SCCLK. When INVSCLK = low, the rising edge of SDCLK/SCCLK are used. When INVSCLK = high, the falling edge of SDCLK/SCCLK are used. 16 D9 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 9 of the parallel port data output bus. When MODE[1:0] = 3, Serial Data Read During Convert. In serial master mode (MODE[1:0] = 3, RDC or EXT/INT = low), RDC is used to select the read mode. See the Master Serial Interface section. When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable in this mode. When RDC = high, the previous conversion result is read during the current conversion. SDIN When MODE[1:0] = 3, Serial Data In. In serial slave mode (MODE[1:0] = 3, EXT/INT = high), SDIN can be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence. 17 OGND P Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be connected to the system digital ground ideally at the same potential as AGND and DGND. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors. 19 DVDD P Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied from AVDD. 20 DGND P Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital ground ideally at the same potential as AGND and OGND. 21 D10 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus. SDOUT When MODE[1:0] = 3, Serial Data Output. In all serial modes, this pin is used as the serial data output synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7634 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. When EXT/INT = low (master mode), SDOUT is valid on both edges of SDCLK. When EXT/INT = high (slave mode): When INVSCLK = low, SDOUT is updated on SDCLK rising edge. When INVSCLK = high, SDOUT is updated on SDCLK falling edge. Rev. A | Page 9 of 32 AD7634 1 Pin No. Mnemonic Type Description 22 D11 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus. SDCLK When MODE[1:0] = 3, Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. 23 D12 or DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus. SYNC When MODE[1:0] = 3, Serial Data Frame Synchronization. In serial master mode (MODE[1:0] = 3, EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT output is valid. 24 D13 or DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus. RDERROR When MODE[1:0] = 3, Serial Data Read Error. In serial slave mode (MODE[1:0] = 3, EXT/INT = high), this output is used as an incomplete data read error flag. If a data read is started and not completed when the current conversion is completed, the current data is lost and RDERROR is pulsed high. 25 D14 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 14 of the parallel port data output bus. HW/SW When MODE[1:0] = 3, Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7634 by hardware or software. See the Hardware Configuration section and Software Configuration section. When HW/SW = low, the AD7634 is configured through software using the serial configuration register. When HW/SW = high, the AD7634 is configured through dedicated hardware input pins. 26 D15 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 15 of the parallel port data output bus. SCIN When MODE[1:0] = 3, Serial Configuration Data Input. In serial software configuration mode (HW/SW = low), this input is used to serially write in, MSB first, the configuration data into the serial configuration register. The data on this input is latched with SCCLK. See the Software Configuration section. 27 D16 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 16 of the parallel port data output bus. SCCLK When MODE[1:0] = 3, Serial Configuration Clock. In serial software configuration mode (HW/SW = low), this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state of the INVSCLK pin. See the Software Configuration section. 28 D17 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 17 of the parallel port data output bus. SCCS When MODE[1:0] = 3, Serial Configuration Chip Select. In serial software configuration mode (HW/SW = low), this input enables the serial configuration port. See the Software Configuration section. 29 BUSY DO Busy Output. Transitions high when a conversion is started and remains high until the conversion is completed and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data-ready clock signal. Note that in master read after convert mode (MODE[1:0] = 3, EXT/INT = low, RDC = low), the busy time changes according to Table 4. 2 30 TEN DI Input Range Select. Used in conjunction with BIPOLAR per the following: Input Range BIPOLAR TEN 0 V to 5 V Low Low 0 V to 10 V Low High ±5 V High Low ±10 V High High 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode (not used for serial configurable port). 33 RESET DI Reset Input. When high, reset the AD7634. Current conversion, if any, is aborted. The falling edge of RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See the Digital Interface section. If not used, this pin can be tied to OGND. 2 34 PD DI Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. The digital interface remains active during power down. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. Rev. A | Page 10 of 32 AD7634 1 Pin No. Mnemonic Type Description 2 36 BIPOLAR DI Input Range Select. See description for Pin 30. 37 REF AO/I Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, produc- ing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF capacitor is required with or without the internal reference and buffer. See the Voltage Reference Input/Output section. 38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane. 39 IN− AI Analog Input. Referenced to IN+. In the 0 V to 5 V input range, IN− is between 0 V and V V centered about V /2. In the 0 V to 10 V REF REF range, IN− is between 0 V and 2 V V centered about V . REF REF In the ±5 V and ±10 V ranges, IN− is true bipolar up to ±2 V V (±5 V range) or ±4 V V (±10 V range) REF REF and centered about 0 V. In all ranges, IN− must be driven 180° out of phase with IN+. 40 VCC P High Voltage Positive Supply. Normally 7 V to 15 V. 41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges). 43 IN+ AI Analog Input. Referenced to IN−. V centered about V /2. In the 0 V to 10 V In the 0 V to 5 V input range, IN+ is between 0 V and VREF REF range, IN+ is between 0 V and 2 VREF V centered about VREF. In the ±5 V and ±10 V ranges, IN+ is true bipolar up to ±2 VREF V (±5 V range) or ±4 VREF V (±10 V range) and centered about 0 V. In all ranges, IN+ must be driven 180° out of phase with IN− 45 TEMP AO Temperature Sensor Analog Output. When the internal reference is enabled (PDREF = PDBUF = low), this pin outputs a voltage proportional to the temperature of the AD7634. See the Voltage Reference Input/Output section. 46 REFBUFIN AI Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference Input/Output section. 47 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down, and an external reference must be used. 48 PDBUF DI Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. 3 49 EPAD NC Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be soldered to VEE. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power, NC = no internal connection. 2 SW In serial configuration mode (MODE[1:0] = 3, HW/ = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the )BSEXBSF
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$POGJHVSBUJPO section. 3 LFCSP_VQ package only. Table 7. Data Bus Interface Definition MODE MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description 0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-bit parallel 1 0 1 OB/2C A0 = 0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-bit high word 1 0 1 OB/2C A0 = 1 R[0] R[1] All zeros 16-bit low word 2 1 0 OB/2C A0 = 0 A1 = 0 All High-Z R[10:11] R[12:15] R[16:17] 8-bit high byte 2 1 0 OB/2C A0 = 0 A1 = 1 All High-Z R[2:3] R[4:7] R[8:9] 8-bit midbyte 2 1 0 OB/2C A0 = 1 A1 = 0 All High-Z R[0:1] All zeros 8-bit low byte 2 1 0 OB/2C A0 = 1 A1 = 1 All High-Z All zeros R[0:1] 8-bit low byte 3 1 1 OB/2C All High-Z Serial interface Serial interface Rev. A | Page 11 of 32 AD7634 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C. 2.5 2.5 POSITIVE INL = 1.40LSB POSITIVE DNL = 1.28LSB NEGATIVE INL = –1.10LSB NEGATIVE DNL = –0.63LSB 2.0 2.0 1.5 1.5 1.0 0.5 1.0 0 0.5 –0.5 –1.0 0 –1.5 –0.5 –2.0 –1.0 –2.5 0 65536 131072 196608 262144 0 65536 131072 196608 262144 CODE CODE Figure 8. Differential Nonlinearity vs. Code, Bipolar 10 V Range Figure 5. Integral Nonlinearity vs. Code, Bipolar 10 V Range 180 120 NEGATIVE INL NEGATIVE DNL 160 POSITIVE INL POSITIVE DNL 100 140 80 120 100 60 80 60 40 40 20 20 0 0 –2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 –2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 DNL DISTRIBUTION (LSB) INL DISTRIBUTION (LSB) Figure 6. Integral Nonlinearity Distribution, Unipolar 10 V Range Figure 9. Differential Nonlinearity Distribution, Bipolar 5 V Range (288 Devices) (288 Devices) 60000 70000 56811 σ = 0.80 54874 σ = 0.75 59925 60000 50000 50000 40000 40000 34164 30000 32769 30000 20000 20000 11838 10000 6901 10000 2172 1997 349 294 00 25 20 00 005 00 0 0 1FFFC 1FFFE 20000 20002 20004 20006 1FFFE 20000 20002 20004 20006 20008 CODE IN HEX CODE IN HEX Figure 7. Histogram of 261,120 Conversions of a DC Input Figure 10. Histogram of 261,120 Conversions of a DC Input at the Code Center, Bipolar 5 V Range at the Code Transition, Bipolar 5 V Range Rev. A | Page 12 of 32 COUNTS INL (LSB) NUMBER OF UNITS 06406-006 06406-007 06406-005 DNL (LSB) COUNTS NUMBER OF UNITS 06406-009 06406-010 06406-008 AD7634 0 103.0 f = 670kSPS S SNR f = 20.1kHz SINAD –20 IN SNR = 98.3dB 102.5 THD = –116.8dB ±10V –40 ±5V SFDR = 121dB SINAD = 97.8dB –60 102.0 –80 0V TO 10V 101.5 –100 –120 101.0 0V TO 5V –140 100.5 –160 –180 100.0 –60 –50 –40 –30 –20 –10 0 0 50 100 150 200 250 300 FREQUENCY (kHz) INPUT LEVEL (dB) Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 11. FFT 20 kHz, Bipolar 5 V Range, Internal Reference –70 140 100 18.0 SFDR 98 17.5 –80 120 SNR 96 17.0 –90 100 94 16.5 ENOB SINAD 92 16.0 –100 80 SECOND 90 15.5 THD HARMONIC –110 60 88 15.0 86 14.5 –120 40 84 14.0 –130 20 82 13.5 THIRD HARMONIC –140 0 80 13.0 1 10 100 1000 1 10 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 15. THD, Harmonics, and SFDR vs. Frequency, Unipolar 5 V Range Figure 12. SNR, SINAD, and ENOB vs. Frequency, Unipolar 5 V Range 103 103 0V TO 10V 102 102 ±10V 0V TO 10V ±10V 101 101 100 100 0V TO 5V ±5V 0V TO 5V ±5V 99 99 98 98 97 97 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. SINAD vs. Temperature Figure 13. SNR vs. Temperature Rev. A | Page 13 of 32 SNR, SINAD (dB) AMPLITUDE (dB OF FULL SCALE) SNR (dB) 06406-013 06406-011 ENOB (Bits) 06406-012 THD, HARMONICS (dB) SINAD (dB) SNR, SINAD REFERRED TO FULL SCALE (dB) 06406-014 06406-016 SFDR (dB) 06406-015 AD7634 –100 128 0V TO 5V –104 124 –108 120 0V TO 10V ±5V –112 116 ±10V ±5V ±10V –116 112 0V TO 5V 108 –120 0V TO 10V –124 104 100 –128 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 20. SFDR vs. Temperature (Excludes Harmonics) Figure 17. THD vs. Temperature 5.0080 20 16 5.0060 ZERO/OFFSET ERROR 12 5.0040 8 5.0020 4 POSITIVE FULL-SCALE ERROR 5.0000 0 –4 4.9980 –8 4.9960 NEGATIVE –12 FULL-SCALE ERROR 4.9940 –16 4.9920 –20 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Zero/Offset Error, Positive and Negative Full-Scale Error vs. Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices) Temperature, All Normalized to 25°C 60 100000 AVDD, WARP/NORMAL 10000 50 DVDD, ALL MODES 1000 40 100 30 AVDD, IMPULSE 10 VCC +15V 1 VEE –15V 20 ALL MODES 0.1 OVDD, ALL MODES 10 0.01 PDREF = PDBUF = HIGH 0 0.001 01 234 56 78 10 100 1000 10000 100000 1000000 REFERENCE DRIFT (ppm/°C) SAMPLING RATE (SPS) Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices) Figure 22. Operating Currents vs. Sample Rate Rev. A | Page 14 of 32 ZERO/OFFSET ERROR, FULL-SCALE ERROR (LSB) NUMBER OF UNITS THD (dB) 06406-049 06406-017 06406-018 OPERATING CURRENTS (µA) V (V) REF SFDR (dB) 06406-020 06406-022 06406-021 AD7634 50 700 PD = PDBUF = PDREF = HIGH OVDD = 2.7V @ 85°C 45 600 OVDD = 2.7V @ 25°C 40 500 35 30 400 VEE, –15V 25 OVDD = 5V @ 85°C VCC, +15V 300 DVDD 20 OVDD OVDD = 5V @ 25°C AVDD 15 200 10 100 5 0 0 0 50 100 150 200 –55 –35 –15 5 25 45 65 85 105 TEMPERATURE (°C) C (pF) L Figure 23. Power-Down Operating Currents vs. Temperature Figure 24. Typical Delay vs. Load Capacitance C L Rev. A | Page 15 of 32 POWER-DOWN OPERATING CURRENTS (nA) 06406-023 t DELAY (ns) 12 06406-024 AD7634 TERMINOLOGY Least Significant Bit (LSB) Total Harmonic Distortion (THD) The least significant bit, or LSB, is the smallest increment that THD is the ratio of the rms sum of the first five harmonic can be represented by a converter. For a fully differential input components to the rms value of a full-scale input signal and ADC with N bits of resolution, the LSB expressed in volts is is expressed in decibels. V Signal-to-(Noise + Distortion) Ratio (SINAD) INp-p LSB (V ) = N 2 SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist Integral Nonlinearity Error (INL) frequency, including harmonics but excluding dc. The value for Linearity error refers to the deviation of each individual code SINAD is expressed in decibels. from a line drawn from negative full scale through positive full- Spurious-Free Dynamic Range (SFDR) scale. The point used as negative full scale occurs a ½ LSB before the first code transition. Positive full scale is defined as a level The difference, in decibels (dB), between the rms amplitude of 1½ LSBs beyond the last code transition. The deviation is meas- the input signal and the peak spurious signal. ured from the middle of each code to the true straight line. Effective Number of Bits (ENOB) Differential Nonlinearity Error (DNL) ENOB is a measurement of the resolution with a sine wave In an ideal ADC, code transitions are 1 LSB apart. Differential input. It is related to SINAD and is expressed in bits by nonlinearity is the maximum deviation from this ideal value. It ENOB = [(SINAD dB − 1.76)/6.02] is often specified in terms of resolution for which no missing Aperture Delay codes are guaranteed. Aperture delay is a measure of the acquisition performance Bipolar Zero Error measured from the falling edge of the CNVST input to when The difference between the ideal midscale input voltage (0 V) the input signal is held for a conversion. and the actual voltage producing the midscale output code. Transient Response Unipolar Offset Error The time required for the AD7634 to achieve its rated accuracy The first transition should occur at a level ½ LSB above analog after a full-scale step function is applied to its input. ground. The unipolar offset error is the deviation of the actual transition from that point. Reference Voltage Temperature Coefficient Full-Scale Error Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at The last transition (from 111…10 to 111…11 in straight binary the maximum and minimum reference output voltage (VREF) format) should occur for an analog voltage 1½ LSB below the measured at T , T(25°C), and T . It is expressed in ppm/°C as MIN MAX nominal full-scale. The full-scale error is the deviation in LSB (or % of full-scale range) of the actual level of the last transition V (Max)–V (Min) REF REF 6 TCV ( ppm/°C) = ×10 REF from the ideal level and includes the effect of the offset error. V (25°C) × (T –T ) REF MAX MIN Closely related is the gain error (also in LSB or % of full-scale where: range), which does not include the effects of the offset error. V (Max) = maximum V at T , T(25°C), or T . REF REF MIN MAX Dynamic Range VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX. Dynamic range is the ratio of the rms value of the full scale to VREF (25°C) = VREF at 25°C. the rms noise measured for an input typically at −60 dB. The TMAX = +85°C. value for dynamic range is expressed in decibels. TMIN = –40°C. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Rev. A | Page 16 of 32 AD7634 THEORY OF OPERATION IN+ AGND SWITCHES CONTROL SW+ LSB MSB 131,072C 65,536C 4C 2C C C BUSY REF CONTROL COMP LOGIC REFGND OUTPUT CODE 131,072C 65,536C 4C 2C C C SW– MSB LSB CNVST AGND IN– Figure 25. ADC Simplified Schematic OVERVIEW CONVERTER OPERATION The AD7634 is a very fast, low power, precise, 18-bit ADC using The AD7634 is a successive approximation ADC based on a successive approximation capacitive digital-to-analog (CDAC) charge redistribution DAC. Figure 25 shows the simplified architecture. schematic of the ADC. The CDAC consists of two identical arrays of 18 binary weighted capacitors, which are connected The AD7634 can be configured at any time for one of four input to the two comparator inputs. ranges and conversion mode with inputs in parallel and serial hardware modes or by a dedicated write-only, SPI-compatible During the acquisition phase, terminals of the array tied to the interface via a configuration register in serial software mode. comparator’s input are connected to AGND via SW+ and SW−. The AD7634 uses Analog Devices’ patented iCMOS high volt- All independent switches are connected to the analog inputs. Thus, age process to accommodate 0 V to +5 V (10 V p-p), 0 V to the capacitor arrays are used as sampling capacitors and acquire +10 V (20 V p-p), ±5 V (20 V p-p), and ±10 V (40 V p-p) input the analog signal on IN+ and IN− inputs. A conversion phase is ranges on the fully differential IN+ and IN− inputs without the initiated once the acquisition phase is completed and the CNVST use of conventional thin films. Only one acquisition cycle, t8, is input goes low. When the conversion phase begins, SW+ and SW− required for the inputs to latch to the correct configuration. Reset- are opened first. The two capacitor arrays are then disconnected ting or power cycling is not required for reconfiguring the ADC. from the inputs and connected to the REFGND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured The AD7634 features different modes to optimize performance at the end of the acquisition phase is applied to the comparator according to the applications. It is capable of converting 670,000 inputs, causing the comparator to become unbalanced. By switch- samples per second (670 kSPS) in warp mode, 570 kSPS in normal ing each element of the capacitor array between REFGND and mode, and 450 kSPS in impulse mode. REF, the comparator input varies by binary weighted voltage The AD7634 provides the user with an on-chip, track-and-hold, steps (VREF/2, VREF/4 through VREF/ 262,144). The control logic successive approximation ADC that does not exhibit any pipe- toggles these switches, starting with the MSB first, to bring the line or latency, making it ideal for multiple, multiplexed channel comparator back into a balanced condition. applications. After the completion of this process, the control logic generates For unipolar input ranges, the AD7634 typically requires three the ADC output code and brings the BUSY output low. supplies: VCC, AVDD (which can supply DVDD), and OVDD MODES OF OPERATION (which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic). For bipolar input ranges, the AD7634 requires the use of the The AD7634 features three modes of operation: warp, normal, additional VEE supply. and impulse. Each of these modes is more suitable to specific applications. The mode is configured with the input pins, WARP The device is housed in a Pb-free, 48-lead LQFP or a 48-lead and IMPULSE, or via the configuration register. See Table 6 for tiny LFCSP (7 mm × 7 mm) that combine space savings with the pin details; see the Hardware Configuration section and the flexibility. In addition, the AD7634 can be configured as either Software Configuration section for programming the mode a parallel or serial SPI-compatible interface. selection with either pins or configuration register. Note that when using the configuration register, the WARP and IMPULSE inputs are don’t cares and should be tied to either high or low. Rev. A | Page 17 of 32 06406-025 AD7634 Warp Mode TRANSFER FUNCTIONS Setting WARP = high and IMPULSE = low allows the fastest Except in 18-bit parallel interface mode, using the D0/OB/2C conversion rate of up to 670 kSPS. However, in this mode, the digital input or via the configuration register, the AD7634 offers full-specified accuracy is guaranteed only when the time between two output codings: straight binary and twos complement. See conversions does not exceed 1 ms. If the time between two Figure 26 and Table 8 for the ideal transfer characteristic and consecutive conversions is longer than 1 ms (after power-up), digital output codes for the different analog input ranges, V . IN the first conversion result should be ignored because in warp mode, 2C Note that when using the configuration register, the D0/OB/ the ADC performs a background calibration during the SAR input is a don’t care and should be tied to either high or low. conversion process. This calibration can drift if the time between conversions exceeds 1 ms thus causing the first conversion to appear offset. This mode makes the AD7634 ideal for applications 111...111 111...110 where both high accuracy and fast sample rate are required. 111...101 Normal Mode Setting WARP = IMPULSE = low or WARP = IMPULSE = high allows the fastest mode (570 kSPS) without any limitation on time between conversions. This mode makes the AD7634 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. 000...010 000...001 Impulse Mode 000...000 –FSR + 1 LSB +FSR –1LSB Setting WARP = low and IMPULSE = high uses the lowest power –FSR –FSR + 0.5 LSB +FSR – 1.5 LSB dissipation mode and allows power savings between conver- ANALOG INPUT sions. The maximum throughput in this mode is 450 kSPS, and Figure 26. ADC Ideal Transfer Function in this mode, the ADC powers down circuits after conversion, making the AD7634 ideal for battery-powered applications. Table 8. Output Codes and Ideal Input Voltages VREF = 5 V Digital Output Code VIN = 0 V to +5 V VIN = 0 V to +10 V VIN = ±5 V VIN = ±10 V (20 V p-p) Description (10 V p-p) (20 V p-p) (40 V p-p) Straight Binary Twos Complement 1 1 FSR − 1 LSB +4.999962 V +9.999924 V +9.999924 V +19.999847 V 0x3FFFF 0x1FFFF FSR − 2 LSB +4.999924 V +9.999847 V +9.999847 V +19.999695 V 0x3FFFE 0x1FFFE Midscale + 1 LSB +38.15 μV −76.29 μV −76.29 μV +152.59 μV 0x20001 0x00001 Midscale 0 V 0 V 0 V 0 V 0x20000 0x00000 Midscale − 1 LSB −38.15 μV −76.29 μV −76.29 μV −152.59 μV 0x1FFFF 0x3FFFF −FSR + 1 LSB −4.999962 V −9.999924 V −9.999924 V −19.999847 V 0x00001 0x20001 2 2 −FSR −5 V −10 V −10 V −20 V 0x00000 0x20000 1 This is also the code for overrange analog input. 2 This is also the code for underrange analog input. Rev. A | Page 18 of 32 ADC CODE (Straight Binary) 06406-026 AD7634 TYPICAL CONNECTION DIAGRAM Figure 27 shows a typical connection diagram for the AD7634 using the internal reference, serial data interface, and serial configuration port. Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections. DIGITAL SUPPLY (5V) NOTE 5 DIGITAL 10Ω INTERFACE ANALOG SUPPLY SUPPLY (5V) (2.5V, 3.3V, OR 5V) 10µF 100nF 10µF 100nF 100nF 10µF AVDD AGND DGND DVDD OVDD OGND ® +7V TO +15.75V MicroConverter / SUPPLY MICROPROCESSOR/ VCC BUSY 100nF 10µF DSP SDCLK SERIAL PORT 1 SDOUT 100nF 10µF SCCLK –7V TO –15.75V VEE SERIAL SUPPLY PORT 2 SCIN NOTE 6 REF NOTE 3 SCCS C REF REFBUFIN NOTE 7 22µF NOTE 4 33Ω 100nF D CNVST REFGND AD7634 D0/OB/2C NOTE 2 ANALOG MODE[1:0] OVDD INPUT+ 15Ω IN+ U1 HW/SW BIPOLAR C 2.7nF C TEN CLOCK WARP IMPULSE IN– NOTE 3 NOTE 2 ANALOG PDREF PDBUF INPUT– 15Ω PD RD CS RESET U1 C 2.7nF C AGND DGND NOTE 1 NOTE 8 NOTES 1. ANALOG INPUTS ARE DIFFERENTIAL (ANTIPHASE). SEE ANALOG INPUTS SECTION. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION. 4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M). SEE VOLTAGE REFERENCE INPUT/OUTPUT SECTION. 5. OPTIONAL, SEE POWER SUPPLIES SECTION. 6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) + 2V] AND VEE = [VIN(MIN) – 2V] FOR BIPOLAR INPUT RANGES. FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLIES SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. 8. A SEPARATE ANALOG AND DIGITAL GROUND PLANE IS RECOMMENDED, CONNECTED TOGETHER DIRECTLY UNDER THE ADC. SEE LAYOUT GUIDELINES SECTION. Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port Rev. A | Page 19 of 32 06406-027 AD7634 120 ANALOG INPUTS 0V TO 10V Input Range Selection 100 ±5V In parallel mode and serial hardware mode, the input range is selected by using the BIPOLAR (bipolar) and TEN (10 V range) 0V TO 5V 80 inputs. See Table 6 for pin details; see the Hardware Configuration ±10V section and the Software Configuration section for program- 60 ming the mode selection with either pins or configuration register. Note that when using the configuration register, the 40 BIPOLAR and TEN inputs are don’t cares and should be tied to either high or low. 20 Input Structure 0 Figure 28 shows an equivalent circuit for the input structure of 1 10 100 1000 10000 FREQUENCY (kHz) the AD7634. 0V TO 5V Figure 29. Analog Input CMRR vs. Frequency RANGE ONLY AVDD VCC During the acquisition phase for ac signals, the impedance of the analog inputs, IN+ and IN−, can be modeled as a parallel D1 D3 C R IN IN combination of Capacitor C and the network formed by PIN IN+ OR IN– the series connection of R and C . C is primarily the pin IN IN PIN C D2 D4 PIN capacitance. R is typically 70 Ω and is a lumped component IN VEE comprised of serial resistors and the on resistance of the switches. AGND CIN is primarily the ADC sampling capacitor and depending on Figure 28. AD7634 Simplified Analog Input the input range selected is typically 48 pF in the 0 V to 5 V range, The four diodes, D1 to D4, provide ESD protection for the analog typically 24 pF in the 0 V to 10 V and ±5 V ranges, and typically inputs, IN+ and IN−. Care must be taken to ensure that the analog 12 pF in the ±10 V range. During the conversion phase, when the input signal never exceeds the supply rails by more than 0.3 V, switches are opened, the input impedance is limited to C . PIN because this causes the diodes to become forward-biased and Because the input impedance of the AD7634 is very high, it to start conducting current. These diodes can handle a forward- can be directly driven by a low impedance source without gain biased current of 120 mA maximum. For instance, these conditions error. To further improve the noise filtering achieved by the could eventually occur when the input buffer’s U1 supplies are AD7634 analog input circuit, an external, one-pole RC filter different from AVDD, VCC, and VEE. In such a case, an input between the amplifier’s outputs and the ADC analog inputs can buffer with a short-circuit current limitation can be used to protect be used, as shown in Figure 27. However, large source imped- the part although most op amps’ short-circuit current is <100 mA. ances significantly affect the ac performance, especially the Note that D3 and D4 are only used in the 0 V to 5 V range to THD. The maximum source impedance depends on the amount allow for additional protection in applications that are switching of THD that can be tolerated. The THD degrades as a function of from the higher voltage ranges. the source impedance and the maximum input frequency, as This analog input structure of the AD7634 is a true differential shown in Figure 30. structure allowing the sampling of the differential signal between –70 IN+ and IN−. By using this differential input, small signals common to both inputs are rejected as shown in Figure 29, which represents the typical CMRR over frequency. 200Ω –90 100Ω 33Ω –110 15Ω –130 25 50 75 100 0 FREQUENCY (kHz) Figure 30. THD vs. Analog Input Frequency and Source Resistance Rev. A | Page 20 of 32 06406-028 CMRR (dB) THD (dB) 06406-050 06406-029 AD7634 capacitor is required. The AD8610 is an option when low bias DRIVER AMPLIFIER CHOICE current is needed in low frequency applications. Although the AD7634 is easy to drive, the driver amplifier must Because the AD7634 uses a large geometry, high voltage input meet the following requirements: switch, the best linearity performance is obtained when using • For multichannel, multiplexed applications, the driver ampli- the amplifier at its maximum full power bandwidth. Gaining fier and the AD7634 analog input circuit must be able to the amplifier to make use of the more dynamic range of the settle for a full-scale step of the capacitor array at a 18-bit ADC results in increased linearity errors. For applications level (0.0004%). For the amplifier, settling at 0.1% to 0.01% requiring more resolution, the use of an additional amplifier is more commonly specified. This differs significantly from with gain should precede a unity follower driving the AD7634. the settling time at a 18-bit level and should be verified See Table 9 for a list of recommended op amps. prior to driver selection. The AD8021 op amp combines ultra- low noise and high gain bandwidth and meets this settling Table 9. Recommended Driver Amplifiers time requirement even when used with gains of up to 13. Amplifier Typical Application AD829 ±15 V supplies, very low noise, low frequency • The noise generated by the driver amplifier needs to be AD8021 ±12 V supplies, very low noise, high frequency kept as low as possible to preserve the SNR and transition AD8022 ±12 V supplies, very low noise, high noise performance of the AD7634. The noise coming from frequency, dual the driver is filtered by the external 1-pole low-pass filter, ADA4922-1 ±12 V supplies, low noise, high frequency, as shown in Figure 27. The SNR degradation due to the single-ended-to-differential driver amplifier is AD8610/ ±13 V supplies, low bias current, low ⎛ ⎞ AD8620 frequency, single/dual ⎜ ⎟ V ⎜ NADC ⎟ SNR = 20log Single-to-Differential Driver LOSS ⎜ ⎟ π π 2 2 2 ⎜ ⎟ V + f (Ne ) + f (Ne ) For single-ended sources, a single-to-differential driver, such ⎜ NADC −3dB N + −3dB N − ⎟ 2 2 ⎝ ⎠ as the ADA4922-1, can be used because the AD7634 needs to where: be driven differentially. The 1-pole filter using R = 15 Ω and VNADC is the noise of the ADC, which is: C = 2.7 nF provides a corner frequency of 3.9 MHz. 2V 15Ω VCC INp-p OUT+ IN+ 2 2 2.7nF R R G F V = NADC SNR AD7634 ANALOG IN INPUT 20 10 15Ω OUT– U2 IN– ADA4922-1 REF VEE 2.7nF f–3dB is the cutoff frequency of the input filter (3.9 MHz). REF R1 N is the noise factor of the amplifier (+1 in buffer 10µF R2 100nF configuration). e and e are the equivalent input voltage noise densities N+ N− Figure 31. Single-to-Differential Driver Using the ADA4922-1 of the op amps connected to IN+ and IN−, in nV/√Hz. For unipolar 5 V and 10 V input ranges, the internal (or This approximation can be utilized when the resistances external) reference source can be used to level shift U2 for used around the amplifiers are small. If larger resistances are the correct input span. If using an external reference, the used, their noise contributions should also be root-sum values for R1/R2 can be lowered to reduce resistive Johnson squared. noise (1.29E − 10 × √R). For the bipolar ±5 V and ±10 V input • The driver needs to have a THD performance suitable to ranges, the reference connection is not required because the that of the AD7634. Figure 15 shows the THD vs. frequency common-mode voltage is 0 V. See Table 10 for R1/R2 for the that the driver should exceed. different input ranges. The AD8021 meets these requirements and is appropriate for Table 10. R1/R2 Configuration almost all applications. The AD8021 needs a 10 pF external Input Range R1 R2 Common-Mode Voltage compensation capacitor that should have good linearity as an 5 V 2.5 kΩ 2.5 kΩ 2.5 V NPO ceramic or mica type. Moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the 10 V 2.5 kΩ Open 5 V best signal-to-noise ratio. ±5 V, ±10 V 100 Ω 0 V The AD8022 can also be used when a dual version is needed and a gain of 1 is present. The AD829 is an alternative in appli- cations where high frequency (above 100 kHz) performance is not required. In applications with a gain of 1, an 82 pF compensation Rev. A | Page 21 of 32 06406-052 AD7634 the reference decoupling capacitor with the shortest distance This circuit can also be made discretely, and thus more flexible, and to the analog ground plane with several vias. using any of the recommended low noise amplifiers in Table 9. Again, to preserve the SNR of the converter, the resistors, R For applications that use multiple AD7634 or other PulSAR F and R , should be kept low. G devices, it is more effective to use the internal reference buffer to buffer the external 2.5 V reference voltage. VOLTAGE REFERENCE INPUT/OUTPUT The voltage reference temperature coefficient (TC) directly The AD7634 allows the choice of either a very low temperature impacts full scale; therefore, in applications where full-scale drift internal voltage reference, an external reference, or an accuracy matters, care must be taken with the TC. For instance, external buffered reference. a ±4 ppm/°C TC of the reference changes full scale by ±1 LSB/°C. The internal reference of the AD7634 provides excellent perform- Temperature Sensor ance and can be used in almost all applications. However, the The TEMP pin measures the temperature of the AD7634. To linearity performance is guaranteed only with an external reference. improve the calibration accuracy over the temperature range, the Internal Reference (REF = 5 V) (PDREF = Low, output of the TEMP pin is applied to one of the inputs of the PDBUF = Low) analog switch (such as ADG779), and the ADC itself is used to measure its own temperature. This configuration is shown To use the internal reference, the PDREF and PDBUF inputs in Figure 32. must be low. This enables the on-chip, band gap reference, buffer, and TEMP sensor, resulting in a 5.00 V reference on the REF pin. TEMP ADG779 The internal reference is temperature-compensated to 5.000 V TEMPERATURE ± 35 mV. The reference is trimmed to provide a typical drift of IN+ ANALOG INPUT SENSOR 3 ppm/°C. This typical drift characteristic is shown in Figure 19. AD7634 C C External 2.5 V Reference and Internal Buffer (REF = 5 V) Figure 32. Use of the Temperature Sensor (PDREF = High, PDBUF = Low) To use an external reference with the internal buffer, PDREF POWER SUPPLIES should be high and PDBUF should be low. This powers down The AD7634 uses five sets of power supply pins: the internal reference and allows the 2.5 V reference to be applied • AVDD: analog 5 V core supply to REFBUFIN producing 5 V on the REF pin. The internal ref- erence buffer is useful in multiconverter applications because • VCC: analog high voltage positive supply a buffer is typically required in these applications to avoid • VEE: high voltage negative supply reference coupling amongst the different converters. • DVDD: digital 5 V core supply External 5 V Reference (PDREF = High, PDBUF = High) • OVDD: digital input/output interface supply To use an external reference directly on the REF pin, PDREF and PDBUF should both be high. PDREF and PDBUF power Core Supplies down the internal reference and the internal reference buffer, The AVDD and DVDD supply the AD7634 analog and digital respectively. For improved drift performance, an external refer- cores, respectively. Sufficient decoupling of these supplies is ence, such as the ADR445 or ADR435, is recommended. required consisting of at least a 10 μF capacitor and a 100 nF capacitor on each supply. The 100 nF capacitors should be Reference Decoupling placed as close as possible to the AD7634. To reduce the number Whether using an internal or external reference, the AD7634 of supplies needed, the DVDD can be supplied through a simple voltage reference input (REF) has a dynamic input impedance; RC filter from the analog supply, as shown in Figure 27. therefore, it should be driven by a low impedance source with efficient decoupling between the REF and REFGND inputs. This High Voltage Supplies decoupling depends on the choice of the voltage reference but The high voltage bipolar supplies, VCC and VEE, are required usually consists of a low ESR capacitor connected to REF and and must be at least 2 V larger than the maximum input voltage. REFGND with minimum parasitic inductance. A 22 μF (X5R, For example, if using the ±10 V range, the supplies should be 1206 size) ceramic chip capacitor (or 47 μF low ESR tantalum ±12 V minimum. This allows for 40 V p-p fully differential capacitor) is appropriate when using either the internal refer- input (±10 V on each input IN+ and IN−). Sufficient decoup- ence or the ADR445/ADR435 external reference. ling of these supplies is also required consisting of at least a The placement of the reference decoupling is also important to 10 μF capacitor and a 100 nF capacitor on each supply. For the performance of the AD7634. The decoupling capacitor should unipolar operation, the VEE supply can be grounded with be mounted on the same side as the ADC right at the REF pin some slight THD performance degradation. with a thick PCB trace. The REFGND should also connect to Rev. A | Page 22 of 32 06406-030 AD7634 Digital Output Supply Power Down The OVDD supplies the digital outputs and allows direct interface Setting PD = high powers down the AD7634, thus reducing with any logic working between 2.3 V and 5.25 V. OVDD should supply currents to their minimums, as shown in Figure 23. be set to the same level as the system interface. Sufficient decoup- When the ADC is in power down, the current conversion ling is required consisting of at least a 10 μF capacitor and a 100 nF (if any) is completed and the digital bus remains active. To capacitor with the 100 nF capacitor placed as close as possible further reduce the digital supply currents, drive the inputs to to the AD7634. OVDD or OGND. Power Sequencing Power down can also be programmed with the configuration register. See the Software Configuration section for details. Note The AD7634 is independent of power supply sequencing and is that when using the configuration register, the PD input is a don’t very insensitive to power supply variations on AVDD over a wide care and should be tied to either high or low. frequency range, as shown in Figure 33. 75 CONVERSION CONTROL 70 CNVST The AD7634 is controlled by the input. A falling edge on CNVST is all that is necessary to initiate a conversion. A 65 detailed timing diagram of the conversion process is shown in 60 Figure 35. Once initiated, it cannot be restarted or aborted, even 55 by the power-down input, PD, until the conversion is complete. 50 CNVST CS RD The signal operates independently of and signals. 45 t 2 40 t 1 35 CNVST 30 1 10 100 1000 10000 FREQUENCY (kHz) BUSY Figure 33. AVDD PSRR vs. Frequency t 4 t 3 Power Dissipation vs. Throughput t 6 t 5 In impulse mode, the AD7634 automatically reduces its power MODE ACQUIRE CONVERT ACQUIRE CONVERT consumption at the end of each conversion phase. During the t t 7 8 acquisition phase, the operating currents are very low, which allows Figure 35. Basic Conversion Timing a significant power savings when the conversion rate is reduced (see Figure 34). This feature makes the AD7634 ideal for very CNVST Although is a digital signal, it should be designed with low power, battery-operated applications. special care with fast, clean edges and levels with minimum overshoot, undershoot, or ringing. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply The CNVST trace should be shielded with ground and a low value currents even further, drive the digital inputs close to the power (such as 50 Ω) serial resistor termination should be added close rails, that is, OVDD and OGND. to the output of the component that drives this line. 1000 PDREF = PDBUF = HIGH CNVST For applications where SNR is critical, the signal should have very low jitter. This can be achieved by using a dedicated CNVST CNVST oscillator for generation, or by clocking with a high frequency, low jitter clock, as shown in Figure 27. WARP MODE POWER 100 IMPULSE MODE POWER 10 1 1 10 100 1000 10000 100000 1000000 SAMPLING RATE (kSPS) Figure 34. Power Dissipation vs. Sample Rate Rev. A | Page 23 of 32 PSRR (dB) POWER DISSIPATION (mW) 06406-048 06406-051 06406-033 AD7634 INTERFACES CS = RD = 0 t DIGITAL INTERFACE 1 CNVST The AD7634 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The t 10 serial interface is multiplexed on the parallel data bus. The AD7634 BUSY t digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In 4 t 3 t most applications, the OVDD supply pin is connected to the host 11 system interface 2.5 V to 5.25 V digital supply. Finally, by using the DATA PREVIOUS CONVERSION DATA NEW DATA BUS D0/OB/2C input pin, both twos complement or straight binary coding can be used, except for in a 18-bit parallel interface. Figure 37. Master Parallel Data Timing for Reading (Continuous Read) CS RD Two signals, and , control the interface. When at least Slave Parallel Interface one of these signals is high, the interface outputs are in high In slave parallel reading mode, the data can be read either after impedance. Usually, CS allows the selection of each AD7634 each conversion, which is during the next acquisition phase, or in multicircuit applications and is held low in a single AD7634 during the following conversion, as shown in Figure 38 and design. RD is generally used to enable the conversion result on Figure 39, respectively. When the data is read during the conver- the data bus. sion, it is recommended that it is read-only during the first half RESET of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most The RESET input is used to reset the AD7634. A rising edge on critical analog conversion circuitry. RESET aborts the current conversion (if any) and tristates the data bus. The falling edge of RESET resets the AD7634 and clears CS the data bus and configuration register. See Figure 36 for the RESET timing details. t 9 RD RESET BUSY BUSY DATA BUS DATA CURRENT t 8 BUS CONVERSION CNVST t t 12 13 Figure 38. Slave Parallel Data Timing for Reading (Read After Convert) Figure 36. RESET Timing PARALLEL INTERFACE CS = 0 The AD7634 is configured to use the parallel interface when CNVST, t 1 RD the MODE[1:0] pins = 0, 1 or 2 for 18-/16-/8-bit interfaces, respectively, as detailed in Table 7. Master Parallel Interface BUSY CS RD t Data can be continuously read by tying and low, thus 4 requiring minimal microprocessor connections. However, in t 3 this mode, the data bus is always driven and cannot be used in shared bus applications (unless the device is held in RESET). DATA PREVIOUS BUS CONVERSION Figure 37 details the timing for this mode. t t 12 13 Figure 39. Slave Parallel Data Timing for Reading (Read During Convert) Rev. A | Page 24 of 32 06406-034 06406-036 06406-037 06406-035 AD7634 18-Bit Interface (Master or Slave) MASTER SERIAL INTERFACE The 18-bit interface is selected by setting MODE[1:0] = 0. In The pins multiplexed on D[12:4] and used for master serial this mode, the data output is straight binary. interface are: DIVSCLK[1:0], EXT/INT, INVSYNC, INVSCLK, RDC, SDOUT, SDCLK, and SYNC. 16-Bit and 8-Bit Interface (Master or Slave) INT In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2) Internal Clock (MODE[1:0] = 3, EXT/ = Low) interfaces, Pin A0 and Pin A1 allow a glueless interface to a The AD7634 is configured to generate and provide the serial 16- or 8-bit bus, as shown in Figure 40 (refer to Table 7 for data clock, SDCLK, when the EXT/INT pin is held low. The more details). By connecting Pin A0 and Pin A1 to an address AD7634 also generates a SYNC signal to indicate to the host line(s), the data can be read in two words for a 16-bit interface, when the serial data is valid. The SDCLK and the SYNC signals or three bytes for an 8-bit interface. This interface can be used can be inverted, if desired, using the INVSCLK and INVSYNC in both master and slave parallel reading modes. inputs, respectively. Depending on the input, RDC, the data can be read during the following conversion or after each con- CS, RD version. Figure 41 and Figure 42 show detailed timing diagrams of the following two modes. A1 Read During Convert (RDC = High) A0 Setting RDC = high allows the master read (previous conver- sion result) during conversion mode. Usually, because the AD7634 is used with a fast throughput, this mode is the most HI-Z HI-Z HIGH LOW D[17:2] WORD WORD recommended serial mode. In this mode, the serial clock and data switch on and off at appropriate instances, minimizing potential HI-Z HI-Z HIGH MID LOW D[17:10] feedthrough between digital activity and critical conversion BYTE BYTE BYTE decisions. In this mode, the SDCLK period changes because the t t t t 12 12 13 12 LSBs require more time to settle and the SDCLK is derived Figure 40. 8-Bit and16-Bit Parallel Interface from the SAR conversion cycle. In this mode, the AD7634 SERIAL INTERFACE generates a discontinuous SDCLK of two different periods The AD7634 is configured to use the serial interface and the host should use an SPI interface. when MODE[1:0]= 3. The AD7634 has a serial interface Read After Covert (RDC = Low, DIVSCLK[1:0] = 0 to 3) (SPI-compatible) multiplexed on the data pins D[17:4]. Setting RDC = low allows the read after conversion mode. Unlike Data Interface the other serial modes, the BUSY signal returns low after the 18 The AD7634 outputs 18 bits of data, MSB first, on the SDOUT pin. data bits are pulsed out and not at the end of the conversion phase, This data is synchronized with the 18 clock pulses provided on resulting in a longer BUSY width (See Table 4 for BUSY timing the SDCLK pin. The output data is valid on both the rising and specifications). The DIVSCLK[1:0] inputs control the SDCLK falling edge of the data clock. period and SDOUT data rate. As a result, the maximum through- Serial Configuration Interface put cannot be achieved in this mode. In this mode, the AD7634 The AD7634 can be configured through the serial configuration also generates a discontinuous SDCLK; however, a fixed period and register only in serial mode as the serial configuration pins are hosts supporting both SPI and serial ports can also be used. also multiplexed on the data pins D[17:14]. See the Hardware Configuration section and the Software Configuration section for more information. Rev. A | Page 25 of 32 06406-040 AD7634 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 MODE[1:0] = 3 EXT/INT = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SDCLK 12 3 16 17 18 t 18 t 27 SDOUT X D17 D16 D2 D1 D0 t t 16 23 t 22 Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 MODE[1:0] = 3 CS, RD t 3 CNVST t BUSY 28 t 30 t 29 t 25 SYNC t t 18 14 t 19 t t t 24 20 21 t 26 12 3 16 17 18 SDCLK t 15 t 27 SDOUT D17 D16 D2 D1 D0 X t t 16 23 t 22 Figure 42. Master Serial Data Timing for Reading (Read After Convert) Rev. A | Page 26 of 32 06406-039 06406-038 AD7634 CNVST SLAVE SERIAL INTERFACE Simultaneous sampling is possible by using a common signal. Note that the SDIN input is latched on the opposite edge The pins multiplexed on D[13:6] used for slave serial inter- of SDCLK used to shift out the data on SDOUT (SDCLK falling face are: EXT/INT, INVSCLK, SDIN, SDOUT, SDCLK, and edge when INVSCLK = low). Therefore, the MSB of the upstream RDERROR. converter follows the LSB of the downstream converter on the INT External Clock (MODE[1:0] = 3, EXT/ = High) next SDCLK cycle. In this mode, the 40 MHz SDCLK rate cannot be used because the SDIN-to-SDCLK setup time, t33, is less than Setting the EXT/INT = high allows the AD7634 to accept an the minimum time specified. (SDCLK-to-SDOUT delay, t , is 32 externally supplied serial data clock on the SDCLK pin. In this the same for all converters when simultaneously sampled.) For mode, several methods can be used to read the data. The external proper operation, the SDCLK edge for latching SDIN (or ½ serial clock is gated by CS. When CS and RD are both low, the period of SDCLK) needs to be data can be read after each conversion or during the following conversion. A clock can be either normally high or normally t = t + t 1/ 2SDCLK 32 33 low when inactive. For detailed timing diagrams, see Figure 44 Or the maximum SDCLK frequency needs to be and Figure 45. 1 f = SDCLK While the AD7634 is performing a bit decision, it is important 2(t + t ) 32 33 that voltage transients be avoided on digital input/output pins, If not using the daisy-chain feature, the SDIN input should or degradation of the conversion result may occur. This is par- always be tied either high or low. ticularly important during the last 550 ns of the conversion phase BUSY because the AD7634 provides error correction circuitry that can OUT correct for an improper bit decision made during the first part of the conversion phase. For this reason, it is recommended that BUSY BUSY AD7634 AD7634 any external clock provided is a discontinuous clock that transi- #2 #1 tions only when BUSY is low or, more importantly, that it does not (UPSTREAM) (DOWNSTREAM) DATA transition during the last 450 ns of BUSY high. RDC/SDIN SDOUT RDC/SDIN SDOUT OUT External Discontinuous Clock Data Read After CNVST CNVST Conversion CS CS Though the maximum throughput cannot be achieved using SDCLK SDCLK this mode, it is the most recommended of the serial slave modes. Figure 44 shows the detailed timing diagrams for this method. SDCLK IN CS IN After a conversion is completed, indicated by BUSY returning low, CNVST IN CS RD the conversion result can be read while both and are low. Figure 43. Two AD7634 Devices in a Daisy-Chain Configuration Data is shifted out MSB first with 18 clock pulses and, depending External Clock Data Read During Previous Conversion on the SDCLK frequency, can be valid on the falling and rising Figure 45 shows the detailed timing diagrams for this method. edges of the clock. During a conversion, while both CS and RD are low, the result One advantage of this method is that conversion performance is of the previous conversion can be read. The data is shifted out, not degraded because there are no voltage transients on the digital MSB first, with 18 clock pulses, and depending on the SDCLK interface during the conversion process. Another advantage is frequency, data can be valid on both the falling and rising edges the ability to read the data at any speed up to 40 MHz, which of the clock. The 18 bits have to be read before the current accommodates both the slow digital host interface and the fastest conversion is complete; otherwise, RDERROR is pulsed high serial reading. and can be used to interrupt the host interface to prevent Daisy-Chain Feature incomplete data reading. Also in the read after convert mode, the AD7634 provides a daisy- To reduce performance degradation due to digital activity, a fast chain feature for cascading multiple converters together using the discontinuous clock of at least 40 MHz is recommended to ensure serial data input pin, SDIN. This feature is useful for reducing that all the bits are read during the first half of the SAR conver- component count and wiring connections when desired, for sion phase. instance, in isolated multiconverter applications. See Figure 44 for the timing details. The daisy-chain feature should not be used in this mode because digital activity occurs during the second half of the SAR conver- An example of the concatenation of two devices is shown in sion phase likely resulting in performance degradation. Figure 43. Rev. A | Page 27 of 32 06406-041 AD7634 External Clock Data Read After/During Conversion discontinuous SDCLK whenever possible to minimize potential incorrect bit decisions. For the different modes, the use of a slower It is also possible to begin to read data after conversion and SDCLK, such as 20 MHz in warp mode, 15 MHz in normal mode, continue to read the last bits after a new conversion is initiated. and 13 MHz in impulse mode, can be used. This method allows the full throughput and the use of a slower SDCLK frequency. Again, it is recommended to use a MODE[1:0] = 3 EXT/INT = 1 INVSCLK = 0 RD = 0 CS BUSY t t t t 31 35 36 31 SDCLK X* 123 4 16 17 18 19 20 21 t 32 t 37 SDOUT D17 D16 D2 X17 X16 D15 D1 D0 t 16 SDIN X17 X16 X15 X2 X1 X0 Y17 Y16 t t 33 34 *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 44. Slave Serial Data Timing for Reading (Read After Convert) MODE[1:0] = 3 EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t t t t 31 35 36 31 SDCLK X* X* X* X* X* X* 123 17 18 t t 32 37 SDOUT D17 DATA = SDIN D16 D1 D0 t t 16 27 *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 45. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. A | Page 28 of 32 06406-042 06406-043 AD7634 it is not recommended to write to the SCP during the last 600 ns HARDWARE CONFIGURATION of conversion (BUSY = high) or performance degradation can The AD7634 can be configured at any time with the dedicated result. In addition, the SCP can be accessed in both serial master hardware pins WARP, IMPULSE, BIPOLAR, TEN, D0/OB/2C, and serial slave read during and read after convert modes. and PD for parallel mode (MODE[1:0] = 0, 1, or 2) or serial Note that at power up, the configuration register is undefined. SW hardware mode (MODE[1:0] = 3, HW/ = high). Programming The RESET input clears the configuration register (sets all bits the AD7634 for mode selection and input range configuration to 0), thus placing the configuration to 0 V to 5 V input, normal can be done before or during conversion. Like the RESET input, mode, and twos complemented output. the ADC requires at least one acquisition time to settle as indi- cated in Figure 46. See Table 6 for pin descriptions. Note that Table 11. Configuration Register Description these inputs are high impedance when using the software Bit Name Description configuration mode. 8 START START bit. With the SCP enabled (SCCS = low), when START is high, the first rising edge SOFTWARE CONFIGURATION of SCCLK (INVSCLK = low) begins to load the The pins multiplexed on D[17:14] used for software configura- register with the new configuration. tion are: HW/SW, SCIN, SCCLK, and SCCS. The AD7634 is 7 BIPOLAR Input Range Select. Used in conjunction with Bit 6, TEN, per the following: programmed using the dedicated write-only serial configurable Input Range BIPOLAR TEN port (SCP) for conversion mode, input range selection, output 0 V to 5 V Low Low coding, and power-down using the serial configuration register. 0 V to 10 V Low High See Table 11 for details of each bit in the configuration register. ±5 V High Low The SCP can only be used in serial software mode selected with ±10 V High High MODE[1:0] = 3 and HW/SW = low because the port is multi- 6 TEN Input Range Select. See Bit 7, BIPOLAR. plexed on the parallel interface. 5 PD Power Down. PD = low, normal operation. The SCP is accessed by asserting the port’s chip select, SCCS, PD = high, power down the ADC. The SCP is and then writing SCIN synchronized with SCCLK, which (like accessible while in power-down. To power-up SDCLK) is edge sensitive depending on the state of INVSCLK. the ADC, write PD = low on the next configu- ration setting. See Figure 47 for timing details. SCIN is clocked into the con- 4 IMPULSE Mode Select. Used in conjunction with Bit 3, figuration register MSB first. The configuration register is an WARP per the following: internal shift register that begins with Bit 8, the START bit. The Mode WARP IMPULSE th 9 SCCLK edge updates the register and allows the new settings to Normal Low Low be used. As indicated in the timing diagram, at least one acquisition Impulse Low High th time is required from the 9 SCCLK edge. Bits [1:0] are reserved Warp High Low bits and are not written to while the SCP is being updated. Normal High High 3 WARP Mode Select. See Bit 4, IMPULSE. The SCP can be written to at any time, up to 40 MHz, and it 2 OB/2C Output Coding is recommended to write to while the AD7634 is not busy con- OB/2C = low, use twos complement output. verting, as detailed in Figure 47. In this mode, the full 670 kSPS OB/2C = high, use straight binary output. is not attainable because the time required for SCP access is 1 RSV Reserved. (t31 + 9 × 1/ SCCLK + t8) minimum. If the full throughput is 0 RSV Reserved. required, the SCP can be written to during conversion; however HW/SW = 1 PD = 0 t t 8 8 CNVST BUSY BIPOLAR, TEN WARP, IMPULSE Figure 46. Hardware Configuration Timing Rev. A | Page 29 of 32 06406-047 AD7634 WARP = 0 OR 1 BIPOLAR = 0 OR 1 MODE[1:0] = 3 INVSCLK = 0 t IMPULSE = 0 OR 1 TEN = 0 OR 1 HW/SW = 0 PD = 0 8 CNVST BUSY t 31 SCCS t t t 31 35 36 SCCLK 123 4 5 67 89 t 37 t 34 SCIN X BIPOLAR TEN PD IMPULSE WARP OB/2C START X t 33 Figure 47. Serial Configuration Port Timing MICROPROCESSOR INTERFACING The AD7634 is ideally suited for traditional dc measurement The reading process can be initiated in response to the end-of- conversion signal (BUSY going low) using an interrupt line of applications supporting a microprocessor, and ac signal proc- the DSP. The serial peripheral interface (SPI) on the ADSP-219x essing applications interfacing to a digital signal processor. The is configured for master mode (MSTR) = 1, clock polarity bit AD7634 is designed to interface with a parallel 8-bit or 18-bit wide interface, or with a general-purpose serial port or I/O ports on a (CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable microcontroller. A variety of external buffers can be used with (TIMOD) = 0 by writing to the SPI control register (SPICLTx). the AD7634 to prevent digital noise from coupling into the ADC. It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbps allowing it to read an ADC SPI Interface result in less than 1.1 μs. When a higher sampling rate is desired, The AD7634 is compatible with SPI and QSPI digital hosts use one of the parallel interface modes. and DSPs, such as Blackfin® ADSP-BF53x and ADSP-218x/ DVDD ADSP-219x. Figure 48 shows an interface diagram between AD7634* ADSP-219x* the AD7634 and the SPI-equipped ADSP-219x. To accom- MODE[1:0] modate the slower speed of the DSP, the AD7634 acts as a slave BUSY PFx EXT/INT device, and data must be read after conversion. This mode also CS SPIxSEL (PFx) SDOUT MISOx allows the daisy-chain feature. The convert command could be RD SDCLK SCKx initiated in response to an internal timer interrupt. INVSCLK CNVST PFx OR TFSx *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 48. Interfacing the AD7634 to SPI Interface Rev. A | Page 30 of 32 06406-046 06406-044 AD7634 APPLICATION INFORMATION The DVDD supply of the AD7634 can be either a separate supply LAYOUT GUIDELINES or come from the analog supply, AVDD, or from the digital While the AD7634 has very good immunity to noise on the interface supply, OVDD. When the system digital supply is noisy, power supplies, exercise care with the grounding layout. To facili- or fast switching digital signals are present, and no separate supply tate the use of ground planes that can be easily separated, design is available, it is recommended to connect the DVDD digital supply the printed circuit board that houses the AD7634 so that the to the analog supply AVDD through an RC filter, and to connect analog and digital sections are separated and confined to certain the system supply to the interface digital supply OVDD and the areas of the board. Digital and analog ground planes should be remaining digital circuitry. See Figure 27 for an example of this joined in only one place, preferably underneath the AD7634, or configuration. When DVDD is powered from the system supply, as close as possible to the AD7634. If the AD7634 is in a system it is useful to insert a bead to further reduce high frequency spikes. where multiple devices require analog-to-digital ground connect- ions, the connections should still be made at one point only, a The AD7634 has four different ground pins: REFGND, AGND, star ground point, established as close as possible to the AD7634. DGND, and OGND. To prevent coupling noise onto the die, avoid radiating noise, • REFGND senses the reference voltage and, because it carries and reduce feedthrough: pulsed currents, should be a low impedance return to the reference. • Do not run digital lines under the device. • AGND is the ground to which most internal ADC analog • Do run the analog ground plane under the AD7634. signals are referenced; it must be connected with the least CNVST • Do shield fast switching signals, like or clocks, with resistance to the analog ground plane. digital ground to avoid radiating noise to other sections of • DGND must be tied to the analog or digital ground plane the board, and never run them near analog signal paths. depending on the configuration. • Avoid crossover of digital and analog signals. • OGND is connected to the digital system ground. • Run traces on different but close layers of the board, at right The layout of the decoupling of the reference voltage is important. angles to each other, to reduce the effect of feedthrough through To minimize parasitic inductances, place the decoupling capacitor the board. close to the ADC and connect it with short, thick traces. The power supply lines to the AD7634 should use as large a trace EVALUATING PERFORMANCE as possible to provide low impedance paths and reduce the effect A recommended layout for the AD7634 is outlined in the EVAL- of glitches on the power supply lines. Good decoupling is also AD7634CBZ evaluation board documentation. The evaluation important to lower the impedance of the supplies presented to board package includes a fully assembled and tested evaluation the AD7634, and to reduce the magnitude of the supply spikes. board, documentation, and software for controlling the board Decoupled ceramic capacitors, typically 100 nF, should be placed from a PC via the EVAL-CONTROL BRD3. on each of the power supplies pins, AVDD, DVDD, and OVDD, VCC, and VEE. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. Rev. A | Page 31 of 32 AD7634 OUTLINE DIMENSIONS 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 48 37 1 36 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 (PINS DOWN) 0.20 6.80 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 49. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.60 MAX 0.18 PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 PAD VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 25 12 0.40 13 24 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 0.02 NOM THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COPLANARITY 0.50 BSC SECTION OF THIS DATA SHEET. 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 50. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Notes Temperature Range Package Description Package Option AD7634BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 AD7634BCPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 AD7634BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 AD7634BSTZRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 2 EVAL-AD7634CBZ Evaluation Board 3 EVAL-CONTROL BRD3 Controller Board 1 Z = RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending with the CB designators. ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06406-0-3/11(A) Rev. A | Page 32 of 32 051706-A 080108-A