ANALOG DEVICES AD7626

16-Bit, 10 MSPS, PulSAR Differential ADC AD7626 FEATURES FUNCTIONAL BLOCK DIAGRAM REFIN REF VCM Throughput: 10 MSPS SNR: 91.5 dB 1.2V VIO ÷2 CLOCK 16-bit no missing codes BAND GAP LOGIC INL: ±0.45 LSB IN+ CAP CNV+, CNV– DAC IN– DNL: ±0.35 LSB Power dissipation: 136mW D+, D– SERIAL SAR 32-lead LFCSP (5 mm × 5 mm) DCO+, DCO– LVDS AD7626 CLK+, CLK– SAR architecture No latency/no pipeline delay Figure 1. 16-bit resolution with no missing codes GENERAL DESCRIPTION Zero error: ±1LSB Differential input range: ±4.096 V The AD7626 is a 16-bit, 10 MSPS, charge redistribution Serial LVDS interface successive approximation register (SAR) based architecture Self-clocked mode analog-to-digital converter (ADC). SAR architecture allows Echoed-clock mode unmatched performance both in noise (91.5 dB SNR) and in LVDS or CMOS option for conversion control (CNV signal) linearity (±0.45 LSB INL). The AD7626 contains a high speed, Reference options 16-bit sampling ADC, an internal conversion clock, and an Internal: 4.096 V internal buffered reference. On the CNV edge, it samples the External (1.2 V) buffered to 4.096 V voltage difference between the IN+ and IN− pins. The voltages External: 4.096 V on these pins swing in opposite phase between 0 V and REF. The 4.096 V reference voltage, REF, can be generated internally APPLICATIONS or applied externally. Digital imaging systems All converted results are available on a single LVDS self-clocked Digital X-ray or echoed-clock serial interface, reducing external hardware Digital MRI connections. CCD and IR cameras High speed data acquisition The AD7626 is housed in a 32-lead, 5 mm × 5 mm LFCSP with High dynamic range telecommunications receivers operation specified from −40°C to +85°C. Spectrum analysis Test equipment Table 1. Fast PulSAR® ADC Selection Input Type Resolution (Bits) 1 MSPS to <2 MSPS 2 MSPS to 3 MSPS 6 MSPS 10 MSPS Differential (Ground Sense) 16 AD7653 AD7667 AD7980 AD7983 True Bipolar 16 AD7671 Differential (Antiphase) 16 AD7677 AD7621 AD7625 AD7626 AD7623 AD7622 Differential (Antiphase) 18 AD7643 AD7641 AD7982 AD7984 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07648-001 AD7626 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications ....................................................................................... 1 Circuit Information .................................................................... 15 Functional Block Diagram .............................................................. 1 Converter Information .............................................................. 15 General Description ......................................................................... 1 Transfer Functions ..................................................................... 16 Revision History ............................................................................... 2 Analog Inputs ............................................................................. 16 Specif ica t ions ..................................................................................... 3 Typical Connection Diagram ................................................... 17 Timing Specifications .................................................................. 5 Driving the AD7626 ................................................................... 18 Timing Diagrams .......................................................................... 6 Voltage Reference Options ........................................................ 20 Absolute Maximum Ratings ............................................................ 7 Power Supply ............................................................................... 21 Thermal Resistance ...................................................................... 7 Digital Interface .......................................................................... 22 ESD Caution .................................................................................. 7 Applications Information .............................................................. 24 Pin Configuration and Function Descriptions ............................. 8 Layout, Decoupling, and Grounding ....................................... 24 Typical Performance Characteristics ........................................... 10 Outline Dimensions ....................................................................... 25 Terminology .................................................................................... 14 Ordering Guide .......................................................................... 25 REVISION HISTORY 1/10—Rev. 0 to Rev. A Changes to Description of Pin 5 and Pin 6, Table 6 ..................... 8 Changes to Power-Up Section ...................................................... 21 9/09—Revision 0: Initial Version Rev. A | Page 2 of 2 AD7626 SPECIFICATIONS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; REF = 4.096 V; all specifications T to T , unless otherwise noted. MIN MAX Table 2. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V − V −V +V V IN+ IN− REF REF Operating Input Voltage V , V to AGND −0.1 V + 0.1 V IN+ IN− REF Common-Mode Input Range V /2 − 0.05 V/2 V /2 + 0.05 V REF REF REF CMRR fIN = 1 MHz 68 dB Input Current Midscale input 168 μA THROUGHPUT Complete Cycle 100 ns Throughput Rate 0.1 10 MSPS DC ACCURACY Integral Linearity Error −1.5 ±0.45 +1.5 LSB No Missing Codes 16 Bits Differential Linearity Error −0.5 ±0.35 +0.5 LSB Transition Noise 0.6 LSB Zero Error, T to T −6 ±1 +6 LSB MIN MAX Zero Error Drift 0.5 ppm/°C Gain Error, TMIN to TMAX 8 20 LSB Gain Error Drift 0.7 ppm/°C 1 Power Supply Sensitivity VDD1 = 5 V ± 5% 0.4 LSB VDD2 = 2.5 V ± 5% 0.2 LSB AC ACCURACY f = 20 kHz, −0.5 dBFS IN Dynamic Range 90.5 91.5 dB Signal-to-Noise Ratio 90 91 dB Spurious-Free Dynamic Range 105 dB Total Harmonic Distortion −105.5 dB Signal-to-(Noise + Distortion) 89.5 91 dB f = 100 kHz, −0.5 dBFS IN Signal-to-Noise Ratio 91.3 dB Spurious-Free Dynamic Range 104.5 dB Total Harmonic Distortion −102.5 dB Signal-to-(Noise + Distortion) 91 dB f = 2.4 MHz, −1 dBFS IN Signal-to-Noise Ratio 88.5 dBFS Spurious-Free Dynamic Range 84 dB Total Harmonic Distortion −86 dB Signal-to-(Noise + Distortion) 85 dB f = 2.4 MHz, −6 dBFS IN Signal-to-Noise Ratio 89 dBFS Spurious-Free Dynamic Range 84 dB Total Harmonic Distortion −93 dB Signal-to-(Noise + Distortion) 88 dB −3 dB Input Bandwidth 95 MHz Aperture Jitter 0.25 ps rms INTERNAL REFERENCE Output Voltage REFIN @ 25°C 1.18 1.19 1.2 V Temperature Drift −40°C to +85°C ±15 ppm/°C Rev. A | Page 3 of  AD7626 Parameter Test Conditions/Comments Min Typ Max Unit REFERENCE BUFFER REFIN Input Voltage Range 1.18 1.2 1.22 V REF Output Voltage Range REF @ 25°C, EN0 = EN1 = 1 4.076 4.096 4.116 V Line Regulation VDD1 ± 5%, VDD2 ± 5% 5 mV EXTERNAL REFERENCE Voltage Range REF 4.096 V VCM PIN VCM Output REF/2 VCM Error −0.015 +0.015 V Output Impedance 5 kΩ LVDS I/O (ANSI-644) Data Format Serial LVDS twos complement Differential Output Voltage, V R = 100 Ω 245 290 454 mV OD L 2 Common-Mode Output Voltage, V R = 100 Ω 980 1130 1375 mV OCM L Differential Input Voltage, VID 100 650 mV Common-Mode Input Voltage, VICM 800 1575 mV POWER SUPPLIES Specified Performance VDD1 4.75 5 5.25 V VDD2 2.37 2.5 2.63 V VIO 2.37 2.5 2.63 V Operating Currents Static—Not Converting VDD1 3.5 4.5 mA VDD2 16.7 21.2 mA VIO 11.6 13.5 mA With Internal Reference 10 MSPS throughput VDD1 10.4 11.2 mA VDD2 23.5 27.8 mA VIO Echoed-clock mode 15.8 17.8 mA With External Reference 10 MSPS throughput VDD1 7.5 8.8 mA VDD2 23 28 mA VIO Echoed-clock mode 16.4 18.5 mA Power-Down EN0 = 0, EN1 = 0 VDD1 0.6 4 μA VDD2 0.8 10 μA VIO 1 5 μA 3 Power Dissipation Static—Not Converting 88 107 mW With Internal Reference 10 MSPS throughput 150 170 mW With External Reference 10 MSPS throughput 136 160 mW Power-Down 8 58 μW Energy per Conversion 10 MSPS throughput 13.6 nJ/sample TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 Using an external reference. 2 The ANSI-644 LVDS specification has a minimum output common mode (VOCM) of 1125 mV. 3 Power dissipation is for the AD7626 device only. In self-clocked interface mode, 0.9 mW is dissipated in the 100 Ω terminator. In echoed-clock interface mode, 1.8 mW is dissipated in two 100 Ω terminators. Rev. A | Page 4 of  AD7626 TIMING SPECIFICATIONS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit 1 Time Between Conversions t 100 10,000 ns CYC CNV High Time tCNVH 10 40 ns CNV to D (MSB) Ready tMSB 100 ns CNV to Last CLK (LSB) Delay tCLKL 72 ns 2 CLK Period t 3.33 4 (t − t + t)/n ns CLK CYC MSB CLKL CLK Frequency f 250 300 MHz CLK CLK to DCO Delay (Echoed-Clock Mode) tDCO 0 4 7 ns DCO to D Delay (Echoed-Clock Mode) tD 0 1 ns CLK to D Delay tCLKD 0 4 7 ns 1 The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid. 2 For the maximum CLK period, the window available to read data is t − t + t . Divide this time by the number of bits (n) to be read giving the maximum CLK± CYC MSB CLKL frequency that can be used for a given conversion CNV frequency. In echoed-clock interface mode, n = 16; in self-clocked interface mode, n = 18. Rev. A | Page 5 of  AD7626 TIMING DIAGRAMS SAMPLE N SAMPLE N + 1 t CYC t CNVH CNV– CNV+ ACQUISITION ACQUISITION ACQUISITION t CLKL t CLK 15 16 11 2 156 123 CLK– CLK+ t DCO 1 15 16 1 2 15 16 23 DCO– DCO+ t MSB t D t CLKD D+ D1 D0 D15 D14 D1 D0 D15 D14 D13 0 0 N – 1 N – 1 N N N N N + 1 N + 1 N + 1 D– Figure 2. Echoed-Clock Interface Mode Timing Diagram SAMPLE N SAMPLE N + 1 t CYC t CNVH CNV– CNV+ ACQUISITION ACQUISITION ACQUISITION t t CLK CLKL 1 17 18 1 2 3 4 17 18 23 CLK– CLK+ t MSB t CLKD D+ D15 D14 D1 D0 D1 D0 D15 1 1 N + 1 N N N N – 1 N – 1 N D– Figure 3. Self-Clocked Interface Mode Timing Diagram Rev. A | Page 6 of  07648-003 07648-004 0 0 0 0 AD7626 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Analog Inputs/Outputs 1 IN+, IN− to GND −0.3 V to REF + 0.3 V or Table 5. Thermal Resistance ±130 mA 2 Package Type θ θ Unit JA JC REF to GND −0.3 V to +6 V 32-Lead LFCSP_VQ 40 4 °C/W VCM, CAP2 to GND −0.3 V to +6 V CAP1, REFIN to GND −0.3 V to +2.7 V Supply Voltage ESD CAUTION VDD1 −0.3 V to +6 V VDD2, VIO −0.3 V to +3 V Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Input Current to Any Pin Except ±10 mA 3 Supplies −40°C to +85°C Operating Temperature Range (Commercial) Storage Temperature Range −65°C to +150°C Junction Temperature 150°C ESD 1 kV 1 See the Analog Inputs section. 2 Keep CNV± low for any external REF voltage > 4.3 V applied to the REF pin. 3 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 7 of  AD7626 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 GND 1 24 PIN 1 IN+ VDD2 2 23 INDICATOR IN– CAP1 3 22 REFIN 4 21 VCM AD7626 5 20 VDD1 EN0 TOP VIEW VDD1 EN1 6 19 (Not to Scale) VDD2 7 18 VDD2 CNV– 8 17 CLK+ NOTES 1. CONNECT THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS. Figure 4. Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1 VDD1 P Analog 5 V Supply. Decouple the 5 V supply with a 100 nF capacitor. 2 VDD2 P Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. The 2.5 V supply source should supply this pin first, then be traced to the other VDD2 pins (Pin 7 and Pin 18). 3 CAP1 AO Connect this pin to a 10 nF capacitor. 4 REFIN AI/O Prebuffer Reference Voltage. When using the internal reference, this pin outputs the band gap voltage and is nominally at 1.2 V. It can be overdriven with an external reference voltage such as the ADR280. In either internal or external reference mode, a 10 μF capacitor is required. If using an external 4.096 V reference (connected to REF), this pin is a no connect and does not require any capacitor. 5, 6 EN0, EN1 DI Enable. Operates from 2.5 V logic. The logic levels of these pins set the operation of the device as follows: EN1 = 0, EN0 = 0: power-down mode. EN1 = 0, EN0 = 1: external 1.2 V reference applied to the REFIN pin required. EN1 = 1, EN0 = 0: external 4.096 V reference applied to the REF pin required. EN1 = 1, EN0 = 1: internal reference and internal reference buffer in use. 7 VDD2 P Digital 2.5 V Supply. Decouple this pin with a 100 nF capacitor. 8, 9 CNV−, CNV+ DI Convert Input. These pins act as the conversion control pin. On the rising edge of these pins, the analog inputs are sampled and a conversion cycle is initiated. CNV+ works as a CMOS input when CNV− is grounded; otherwise, CNV+ and CNV− are differential LVDS inputs. 10, 11 D−, D+ DO LVDS Data Outputs. The conversion data is output serially on these pins. 12 VIO P Input/Output Interface Supply. Use a 2.5 V supply and decouple this pin with a 100 nF capacitor. 13 GND P Ground. Return path for the 100 nF capacitor connected to Pin 12. 14, 15 DCO−, DCO+ DO LVDS Buffered Clock Outputs. When DCO+ is grounded, the self-clocked interface mode is selected. In this mode, the 16-bit results on D are preceded by an initial 0 (which is output at the end of the previous conversion), followed by a 2-bit header (10) to allow synchronization of the data by the digital host with extra logic. The 1 in this header provides the reference to acquire the subsequent conversion result correctly. When DCO+ is not grounded, the echoed-clock interface mode is selected. In this mode, DCO± is a copy of CLK±. The data bits are output on the falling edge of DCO+ and can be captured in the digital host on the next rising edge of DCO+. 16, 17 CLK−, CLK+ DI LVDS Clock Inputs. This clock shifts out the conversion results on the falling edge of CLK+. 18 VDD2 P Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. 19, 20 VDD1 P Analog 5 V Supply. Isolate these pins from Pin 1 with a ferrite bead and decouple them with a 100 nF capacitor. 21 VCM AO Common-Mode Output. When using any reference scheme, this pin produces one-half the voltage present on the REF pin, which can be useful for driving the common mode of the input amplifiers. 22 IN− AI Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+. Rev. A | Page 8 of 28 07648-002 REF CNV+ 9 32 D– GND 10 31 REF D+ 11 30 REF VIO 12 29 GND 13 28 CAP2 14 27 GND DCO– 15 26 CAP2 DCO+ CLK– 16 25 CAP2 AD7626 1 Pin No. Mnemonic Type Description 23 IN+ AI Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN−. 24 GND P Ground. 25, 26, 28 CAP2 AO Connect all three CAP2 pins together and decouple them with the shortest trace possible to a single 10 μF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 27 (GND). 27 GND P Ground. Return path for the 10 μF capacitor connected to Pin 25, Pin 26, and Pin 28. 29, 30, 32 REF AI/O Buffered Reference Voltage. When using the internal reference or the 1.2 V external reference (REFIN input), the 4.096 V system reference is produced at this pin. When using an external reference, such as the ADR434 or the ADR444, the internal reference buffer must be disabled. In either case, connect all three REF pins together and decouple them with the shortest trace possible to a single 10 μF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 31 (GND). 31 GND P Ground. Return path for the 10 μF capacitor connected to Pin 29, Pin 30, and Pin 32. EP Exposed pad The exposed pad is located on the underside of the package. Connect the exposed pad to the ground plane of the PCB using multiple vias. See the Exposed Paddle section for more information. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DO = digital output; P = power. Rev. A | Page 9 of  AD7626 TYPICAL PERFORMANCE CHARACTERISTICS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; REF = 4.096 V; all plots at 10 MSPS unless otherwise noted. FFT plots for 2 MHz, 3 MHz, and 5 MHz input tones use band pass filter (±400 kHz pass bandwidth around fundamental frequency). 0 0 INPUT FREQUENCY = 10.37kHz INPUT FREQUENCY = 100kHz SNR = 91.85dB SNR = 91.323dB –20 –20 SINAD = 91.8dB SINAD = 91.047dB THD = –112.1dB THD = –102.543dB SFDR = 112.85dB SFDR = 104.529dB –40 –40 32k SAMPLES –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 03 10 0 50 70 90 05 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5.0 FREQUENCY (kHz) FREQUENCY (MHz) Figure 5. 10 kHz, −0.5 dB Input Tone, Zoomed View Figure 8.100 kHz, −0.5 dB Input Tone FFT, Full Frequency View 0 0 INPUT FREQUENCY = 2.0026MHz INPUT FREQUENCY = 2.0026MHz –0.5dB INPUT AMPLITUDE –6dB INPUT AMPLITUDE SNR = 87.4dBFS –20 SNR = 87.6dBFS –20 SINAD = 84.8dBFS SINAD = 87.6dBFS THD = –87.9dB THD = –101.6dB SFDR = 88.1dB SFDR = 101.9dB –40 –40 64k SAMPLES 64k SAMPLES –60 –60 THIRD HARMONIC –80 –80 FIFTH SECOND FIFTH THIRD HARMONIC HARMONIC HARMONIC HARMONIC SECOND –100 –100 HARMONIC –120 –120 –140 –140 –160 –160 –180 –180 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. FFT, 2 MHz, −0.5 dB Input Tone, Wide View Figure 9. FFT, 2 MHz, −6 dB Input Tone, Wide View 0 0 INPUT FREQUENCY = 3.00125MHz INPUT FREQUENCY = 3.00125MHz –0.5dB INPUT AMPLITUDE –6dB INPUT AMPLITUDE –20 SNR = 87.1dBFS –20 SNR = 88.48dBFS SINAD = 81.2dBFS SINAD = 88.3dBFS THD = –82.0dB THD = –97.2dB SFDR = 82.1dB SFDR = 98.3dB –40 –40 64k SAMPLES 64k SAMPLES –60 –60 THIRD HARMONIC FIFTH –80 –80 HARMONIC SECOND THIRD SECOND HARMONIC HARMONIC HARMONIC FOURTH FIFTH –100 –100 HARMONIC HARMONIC FOURTH HARMONIC –120 –120 –140 –140 –160 –160 –180 –180 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. FFT, 3 MHz, −6 dB Input Tone, Wide View Figure 7. FFT, 3 MHz, −0.5 dB Input Tone, Wide View Rev. A | Page 10 of  AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 07648-108 07648-404 07648-402 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 07648-118 07648-411 07648-409 AD7626 0 0 INPUT FREQUENCY = 5.00656128MHz INPUT FREQUENCY = 5.00656128MHz –0.5dB INPUT AMPLITUDE –0.5dB INPUT AMPLITUDE SNR = 86.7dBFS SNR = 86.7dBFS –20 –20 SINAD = 83.2dBFS SINAD = 83.2dBFS FUNDAMENTAL THD = –85.3dB THD = –85.3dB SFDR = 86.1dB SFDR = 86.1dB –40 –40 64k SAMPLES 64k SAMPLES –60 –60 THIRD THIRD HARMONIC HARMONIC –80 –80 FIFTH SECOND FIFTH HARMONIC HARMONIC HARMONIC –100 –100 FOURTH HARMONIC –120 –120 –140 –140 –160 –160 –180 –180 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 4.50 4.55 4.60 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. FFT, 5 MHz, −0.5 dB Input Tone, Wide View Figure 14. FFT, 5 MHz, −0.5 dB Input Tone Zoomed View 0 0 INPUT FREQUENCY = 5.00656128MHz INPUT FREQUENCY = 5.00656128MHz –6dB INPUT AMPLITUDE –6dB INPUT AMPLITUDE –20 SNR = 88.4dBFS –20 SNR = 88.4dBFS SINAD = 88.0dBFS SINAD = 88.0dBFS FUNDAMENTAL FUNDAMENTAL THD = –92.4dB THD = –92.4dB SFDR = 92.8dB SFDR = 92.8dB –40 –40 64k SAMPLES 64k SAMPLES –60 –60 THIRD THIRD –80 –80 HARMONIC HARMONIC SECOND HARMONIC FIFTH HARMONIC –100 –100 FIFTH FOURTH HARMONIC HARMONIC –120 –120 –140 –140 –160 –160 –180 –180 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 4.50 4.55 4.60 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. FFT, 5 MHz, −6 dB Input Tone, Wide View Figure 15. FFT, 5 MHz, −0.5 dB Input Tone Zoomed View –75 94 –50 –80 92 9.7MHz –60 –85 90 5MHz –70 –90 SNR 88 –95 –80 86 1MHz –100 –90 84 –105 –100 3MHz 82 –110 THD 2MHz –115 80 –110 –18 –15 –12 –9 –6 –3 0 10k 100k 1M 10M INPUT AMPLITUDE (dBFS) INPUT FREQUENCY (Hz) Figure 13. THD vs. Input Amplitudes at Input Frequency Tones of Figure 16. THD and SNR vs. Input Frequency (−0.5 dB Input Tone) 10 kHz to 9.7 MHz Rev. A | Page 11 of  AMPLITUDE (dB) AMPLITUDE (dB) THD (dB) 07648-211 07648-413 07648-406 SNR (dBFS) AMPLITUDE (dB) AMPLITUDE (dB) THD (dB) 07648-401 07648-407 07648-412 AD7626 92.0 92.0 91.8 91.8 91.6 91.6 91.4 91.4 91.2 91.2 EXTERNAL REFERENCE EXTERNAL REFERENCE 91.0 91.0 90.8 90.8 INTERNAL REFERENCE 90.6 90.6 INTERNAL REFERENCE 90.4 90.4 90.2 90.2 90.0 90.0 –40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. SNR vs. Temperature (−0.5 dB, 20 kHz Input Tone) Figure 20. SINAD vs. Temperature (−0.5 dB, 20 kHz Input Tone) 0.35 7 0.30 6 0.25 5 GAIN ERROR +INPUT CURRENT 0.20 4 0.15 3 0.10 2 0.05 –INPUT CURRENT 1 0 –0.05 0 ZERO ERROR –0.10 –1 –6 –4 –2 0 2 4 6 –40 –20 0 20 40 60 80 INPUT COMMON-MODE VOLTAGE (V) TEMPERATURE (°C) Figure 18. Input Current (IN+, IN−) vs. Differential Input Voltage (10 MSPS) Figure 21. Zero Error and Gain Error vs. Temperature –103.0 250,000 262,144 SAMPLES STD DEVIATION = 0.4829 –103.5 201,320 200,000 –104.0 EXTERNAL REFERENCE –104.5 150,000 –105.0 100,000 –105.5 –106.0 50,000 INTERNAL REFERENCE 30,651 30,073 –106.5 54 0 46 0 –107.0 0 –40 –20 0 20 40 60 80 FEC7 FEC8 FEC9 FECA FECB FECC FECD TEMPERATURE (°C) CODE (HEX) Figure 19. THD vs. Temperature (−0.5 dB, 20 kHz Input Tone) Figure 22. Histogram of 262,144 Conversions of a DC Input at the Code Center (Internal Reference) Rev. A | Page 12 of 2 THD (dB) SNR (dB) INPUT URRENT (mA) 07648-121 07648-212 07648-214 COUNT SINAD (dB) ZERO ERROR AND GAIN ERROR (LSB) 07648-301 07648-215 07648-022 AD7626 250,000 0.30 262,144 SAMPLES 0.25 STD DEVIATION = 0.4814 201,614 0.20 200,000 0.15 0.10 150,000 0.05 0 –0.05 100,000 –0.10 –0.15 50,000 30,250 –0.20 30,206 –0.25 0 41 33 0 0 –0.30 FEC8 FEC9 FECA FECB FECC FECD FECE 0 16,384 32,768 49,152 65,536 CODE (HEX) CODE Figure 23. Histogram of 262,144 Conversions of a DC Input Figure 25. Differential Nonlinearity vs. Code (25ºC) at the Code Center (External Reference) 140,000 0.8 129,601 128,084 262,144 SAMPLES +85°C STD DEVIATION = 0.5329 +25°C 0.6 120,000 –40°C 0.4 100,000 0.2 80,000 0 60,000 –0.2 40,000 –0.4 20,000 –0.6 2329 2130 00 0 –0.8 FEC6 FEC7 FEC8 FEC9 FECA FECB 0 16,384 32,768 49,152 65,536 CODE (HEX) CODE Figure 24. Histogram of 262,144 Conversions of a DC Input Figure 26. Integral Nonlinearity vs. Code vs. Temperature at the Code Transition Rev. A | Page 13 of  COUNT COUNT 07648-023 07648-024 INL (LSB) DNL (LSB) 07648-115 07648-112 AD7626 TERMINOLOGY Power Supply Rejection Ratio (PSRR) Common-Mode Rejection Ratio (CMRR) Variations in power supply affect the full-scale transition but not CMRR is defined as the ratio of the power in the ADC output the linearity of the converter. PSRR is the maximum change in at full-scale frequency, f, to the power of a 100 mV p-p sine the full-scale transition point due to a change in power supply wave applied to the common-mode voltage of VIN+ and VIN− voltage from the nominal value. at frequency, fS. Reference Voltage Temperature Coefficient CMRR (dB) = 10 log(Pf/Pf ) S The reference voltage temperature coefficient is derived from the where: typical shift of output voltage at 25°C on a sample of parts at the Pf is the power at frequency, f, in the ADC output. maximum and minimum reference output voltage (VREF) meas- PfS is the power at frequency, fS, in the ADC output. ured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as Differential Nonlinearity (DNL) Error V (Max)–V (Min) REF REF 6 TCV ( ppm/°C)= ×10 In an ideal ADC, code transitions are 1 LSB apart. Differential REF V (25°C)× (T –T ) REF MAX MIN nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing where: codes are guaranteed. V (Max) = maximum V at T , T(25°C), or T . REF REF MIN MAX V (Min) = minimum V at T , T(25°C), or T . REF REF MIN MAX Integral Nonlinearity (INL) Error V (25°C) = V at 25°C. REF REF Linearity error refers to the deviation of each individual code TMAX = +85°C. from a line drawn from negative full scale through positive full TMIN = −40°C. scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level Signal-to-Noise Ratio (SNR) 1½ LSB beyond the last code transition. The deviation is meas- SNR is the ratio of the rms value of the actual input signal to ured from the middle of each code to the true straight line. the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is Dynamic Range expressed in decibels. Dynamic range is the ratio of the rms value of the full scale to the rms noise measured for an input typically at −60 dB. The Signal-to-(Noise + Distortion) Ratio (SINAD) value for dynamic range is expressed in decibels. SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist Effective Number of Bits (ENOB) frequency, including harmonics but excluding dc. The value for ENOB is a measurement of the resolution with a sine wave SINAD is expressed in decibels. input. It is related to SINAD and is expressed in bits by Spurious-Free Dynamic Range (SFDR) ENOB = [(SINAD − 1.76)/6.02] dB SFDR is the difference, in decibels, between the rms amplitude Gain Error of the input signal and the peak spurious signal (including The first transition (from 100 … 000 to 100 …001) should occur harmonics). at a level ½ LSB above nominal negative full scale (−4.0959375 V Total Harmonic Distortion (THD) for the ±4.096 V range). The last transition (from 011 … 110 to THD is the ratio of the rms sum of the first five harmonic 011 … 111) should occur for an analog voltage 1½ LSB below components to the rms value of a full-scale input signal and the nominal full scale (+4.0959375 V for the ±4.096 V range). is expressed in decibels. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first Zero Error transition from the difference between the ideal levels. Zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale Gain Error Drift output code. The ratio of the gain error change due to a temperature change N Zero Error Drift of 1°C and the full-scale range (2 ). It is expressed in parts per million. The ratio of the zero error change due to a temperature change N of 1°C and the full scale code range (2 ). It is expressed in parts Least Significant Bit (LSB) per million. The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is V INp-p LSB (V)= N 2 Rev. A | Page 14 of  AD7626 THEORY OF OPERATION IN+ GND SWITCHES CONTROL LSB SW+ MSB 32,768C 16,384C 4C 2C C C REF CLK+, CLK– (4.096V) DCO+, DCO– DATA TRANSFER CONTROL COMP LOGIC D+, D– GND OUTPUT CODE 32,768C 16,384C 4C 2C C C SW– MSB LSB CNV+, CNV– LVDS INTERFACE GND CONVERSION CONTROL IN– Figure 27. ADC Simplified Schematic CIRCUIT INFORMATION When the conversion phase begins, SW+ and SW− are opened The AD7626 is a 10 MSPS, high precision, power effi- cient, 16-bit ADC that uses SAR-based architecture to first. The two capacitor arrays are then disconnected from the provide a performance of 91.5 dB SNR, ±0.45 LSB INL, inputs and connected to the GND input. Therefore, the differential and ±0.35 LSB DNL. voltage between the inputs (IN+ and IN−) captured at the end of the acquisition phase is applied to the comparator inputs, The AD7626 is capable of converting 10,000,000 samples per causing the comparator to become unbalanced. By switching second (10 MSPS). The device typically consumes 136 mW of each element of the capacitor array between GND and 4.096 V power. The AD7626 offers the added functionality of a high (the reference voltage), the comparator input varies by binary performance on-chip reference and on-chip reference buffer. weighted voltage steps (V /2, V /4 … V /65,536). The REF REF REF The AD7626 is specified for use with 5 V and 2.5 V supplies control logic toggles these switches, MSB first, to bring the (VDD1, VDD2). The interface from the digital host to the comparator back into a balanced condition. At the completion AD7626 uses 2.5 V logic only. The AD7626 uses an LVDS of this process, the control logic generates the ADC output code. interface to transfer data conversions. The CNV+ and CNV− The AD7626 digital interface uses low voltage differential inputs to the part activate the conversion of the analog input. signaling (LVDS) to enable high data transfer rates. The CNV+ and CNV− pins can be applied using a CMOS or The AD7626 conversion result is available for reading after LVDS source. t (time from the conversion start until MSB is available) has MSB The AD7626 is housed in a space-saving, 32-lead, 5 mm × elapsed. The user must apply a burst LVDS CLK± signal to the 5 mm LFCSP. AD7626 to transfer data to the digital host. CONVERTER INFORMATION The CLK± signal outputs the ADC conversion result onto the The AD7626 is a 10 MSPS ADC that uses SAR-based archi- data output D±. The bursting of the CLK± signal is illustrated tecture to incorporate a charge redistribution DAC. Figure 27 in Figure 41 and Figure 42 and is characterized as follows: shows a simplified schematic of the ADC. The capacitive DAC • The differential voltage on CLK± should be held steady consists of two identical arrays of 16 binary weighted capacitors state in the time between t and t . CLKL MSB that are connected to the two comparator inputs. • The AD7626 has two data read modes. For more During the acquisition phase, the terminals of the array tied information about the echoed-clock and self-clocked to the input of the comparator are connected to GND via SW+ interface modes, see the Digital Interface section. and SW−. All independent switches are connected to the analog inputs. In this way, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. A conversion phase is initiated when the acquisition phase is complete and the CNV input goes high. Note that the AD7626 can receive a CMOS or LVDS format CNV signal. Rev. A | Page 15 of  07648-030 AD7626 TRANSFER FUNCTIONS ANALOG INPUTS The AD7626 uses a 4.096 V reference. The AD7626 converts The analog inputs, IN+ and IN−, applied to the AD7626 must be the differential voltage of the antiphase analog inputs (IN+ 180° out of phase with each other. Figure 29 shows an equivalent and IN−) into a digital output. The analog inputs, IN+ and IN−, circuit of the input structure of the AD7626. require a 2.048 V common-mode voltage (REF/2). The two diodes provide ESD protection for the analog inputs, The 16-bit conversion result is in MSB first, twos complement IN+ and IN−. Care must be taken to ensure that the analog input format. signal does not exceed the reference voltage by more than 0.3 V. If the analog input signal exceeds this level, the diodes become The ideal transfer functions for the AD7626 are shown forward-biased and start conducting current. These diodes can in Figure 28 and Table 7. handle a forward-biased current of 130 mA maximum. However, if the supplies of the input buffer (for example, the supplies of the ADA4899-1 in Figure 33) are different from those of the 011 ... 111 reference, the analog input signal may eventually exceed the 011 ... 110 supply rails by more than 0.3 V. In such a case (for example, an 011 ... 101 input buffer with a short circuit), the current limitation can be used to protect the part. CNV VDD1 25pF 67Ω IN+ OR IN– 100 ... 010 100 ... 001 100 ... 000 –FSR –FSR + 1LSB +FSR – 1LSB –FSR + 0.5LSB +FSR – 1.5LSB Figure 29. Equivalent Analog Input Circuit ANALOG INPUT The analog input structure allows the sampling of the true Figure 28. ADC Ideal Transfer Functions (FSR = Full-Scale Range) differential signal between IN+ and IN−. By using these differ- Table 7. Output Codes and Ideal Input Voltages ential inputs, signals common to both inputs are rejected. The AD7626 shows some degradation in THD with higher analog Analog Input (IN+ − IN−) Digital Output Code input frequencies. Description REF = 4.096 V Twos Complement (Hex) 75 FSR − 1 LSB +4.095875V 0x7FFF Midscale + 1 LSB +125 μV 0x0001 70 Midscale 0 V 0x0000 Midscale − 1 LSB −125 μV 0xFFFF 65 −FSR + 1 LSB −4.095875 V 0x8001 −FSR − 4.096 V 0x8000 60 55 50 45 1 10 100 1k 10k 100k 1M 10M INPUT COMMON-MODE FREQUENCY (Hz) Figure 30. Analog Input CMRR vs. Frequency Rev. A | Page 16 of  ADC CODE (TWOS COMPLEMENT) 07648-031 CMRR (dB) 07648-010 07648-009 AD7626 TYPICAL CONNECTION DIAGRAM 8 V+ ADR434 ADR444 CAPACITOR ON OUTPUT FOR STABILITY C REF 1 10µF 1, 2 VDD1 10µF (5V) 100nF VDD2 (2.5V) 32 31 30 29 28 27 26 25 100nF 24 GND 1 VDD1 10nF IN+ 23 IN+ 2 VDD2 8 ADR280 PADDLE SEE THE DRIVING 22 IN– IN– 7 3 THE AD7625 SECTION CAP1 10µF 4 VCM VCM 21 REFIN VIO AD7626 3 10kΩ 10kΩ 5 EN0 VDD1 CONTROL FOR 20 VDD1 (5V) ENABLE FERRITE PINS 6 100nF 6 EN1 BEAD 19 VDD1 VDD2 7 VDD2 (2.5V) VDD2 VDD2 18 100nF (2.5V) 100nF 4 CONVERSION CONTROL CMOS (CNV+ ONLY) OR 8 9 10 11 12 13 14 15 16 17 LVDS CNV+ AND CNV– 5 USING 100Ω 100Ω TERMINATION RESISTOR 100Ω VIO (2.5V) 100Ω 100Ω DIGITAL INTERFACE SIGNALS DIGITAL HOST LVDS TRANSMIT AND RECEIVE 1 SEE THE LAYOUT, DECOUPLING, AND GROUNDING SECTION. 2 C IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESR AND ESL. REF 3 USE PULL-UP OR PULL-DOWN RESISTORS TO CONTROL EN0 AND EN1 DURING POWER-UP. EN0 AND EN1 INPUTS CAN BE FIXED IN HARDWARE OR CONTROLLED USING A DIGITAL HOST (EN0 = 0 AND EN1 = 0 PUTS THE ADC IN POWER-DOWN). 4 OPTION TO USE A CMOS (CNV+) OR LVDS (CNV±) INPUT TO CONTROL CONVERSIONS. 5 TO ENABLE SELF-CLOCKED MODE, TIE DCO+ TO GND. 6 CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE THE TRACE TO PIN 19 AND PIN 20 FROM THE TRACE TO PIN 1 USING A FERRITE BEAD SIMILAR TO WURTH 74279266. 7 SEE THE DRIVING THE AD7626 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS. 8 SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS. Figure 31. Typical Application Diagram Rev. A | Page 17 of  CNV– CNV+ REF D– GND D+ REF VIO REF GND CAP2 DCO– GND CAP2 DCO+ CAP2 CLK– CLK+ 07648-027 AD7626 DRIVING THE AD7626 ADA4899-1 Differential Analog Input Source U1 ANALOG INPUT Figure 33 shows an ADA4899-1 driving each differential input (UNIPOLAR 0V TO 4.096V) to the AD7626. 590Ω 20Ω Single-Ended-to-Differential Driver 56pF For applications using unipolar analog signals, a single- IN+ ended-to-differential driver (as shown in Figure 32) allows 590Ω AD7626 for a differential input into the part. This configuration, when provided with an input signal of 0 V to 4.096 V, produces a IN– 20Ω VCM differential ±4.096 V with midscale at 2.048 V. The one-pole U2 filter using R = 20 Ω and C = 56 pF provides a corner frequency ADA4899-1 56pF 100nF of 140 MHz. The VCM output of the AD7626 can be buffered 100nF and then used to provide the required 2.048 V common-mode V+ voltage. 50Ω Single-Ended or Fully Differential High Frequency Driver In applications that require higher input frequency tones, the AD8031, AD8032 ADA4932-1 can be used to drive the inputs to the AD7626. The V– ADA4932-1 is a differential driver, which also allows the user Figure 32. Single-Ended-to-Differential Driver Circuit Using ADA4899-1 the option of single-ended-to-differential conversion. Figure 34 shows the typical circuit for a 50 Ω source impedance (ac-coupled in this example). The input to the ADA4932-1 is configured to be balanced to the source impedance (in this case 50 Ω). Further information on balancing the input impedance to the source impedance can be found on the ADA4932-1 datasheet. The circuit shown in Figure 34 operates with an overall gain of ~0.5 when the termination input termination is taken into account. Alternatively, the ADA4932-1 can be used with a fully diffe- rential source—it acts as an inverting differential driver. 1 1 REF REF C C REF REF 2 2 10µF 10µF +V S 20Ω 0V TO V REF REF REFIN 56pF IN+ –V ADA4899-1 S AD7626 +V S IN– 20Ω GND VCM V TO 0V REF 56pF 2.048V –V S ADA4899-1 +V S VCM BUFFERED VCM PIN OUTPUT 0.1µF GIVES THE REQUIRED 2.048V AD8031, AD8032 COMMON-MODE SUPPLY FOR –V S ANALOG INPUTS. 1 SEE THE VOLTAGE REFERENCE OPTIONS SECTION. CONNECTION TO EXTERNAL REFERENCE SIGNALS IS DEPENDENT ON THE EN1 AND EN0 SETTINGS. 2 C IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESL AND ESR. REF DECOUPLE REF AND REFIN PINS AS PER THE EN1 AND EN0 RECOMMENDATIONS Figure 33. Driving the AD7626 from a Differential Analog Source Using ADA4899-1 Rev. A | Page 18 of 8 07648-025 07648-033 AD7626 499Ω R35 SINGLE-ENDED 499Ω ANALOG INPUT AD8031 AC-COUPLED C22 C24 50Ω SOURCE +7.25V 53.6Ω 0.1µF 0.1µF GND VDRV+ VCM GND 100nF GND GND 56pF +V V 20Ω VCM S OCM IN– 1 FB– 2 +IN 11 C 499Ω –OUT 3 –IN ADA4932-1 AD7626 10 +OUT 12 PD 4 20Ω FB+ 50Ω 53.6Ω IN+ –V S PAD 56pF –2.5V GND GND C15 0.1µF GND 499Ω Figure 34. High Frequency Input Drive Circuit Using the ADA4932-1; Single-Ended-to Differential Configuration Rev. A | Page 19 of  16 5 6 15 14 7 13 8 PAD 9 07648-130 AD7626 VOLTAGE REFERENCE OPTIONS Table 8. Voltage Reference Options Option EN1 EN0 Reference Mode The AD7626 allows flexible options for creating and buffering A 1 1 Power-up the reference voltage. The AD7626 conversions refer to 4.096 V Internal reference and internal only. The various options creating this 4.096 V reference are reference buffer in use controlled by the EN1 and EN0 pins (see Table 8). B 0 1 External 1.2 V reference applied to REFIN pin required C 1 0 External 4.096 V reference applied to REF pin required. 0 0 Power-down mode DECOUPLE THE REF AND REFIN PINS EXTERNALLY. 10µF 10µF REF REFIN A IN+ AD7626 IN– EN1 = 1 AND EN0 = 1 POWER-UP—INTERNAL REFERENCE AND REFERENCE BUFFER IN USE. NO EXTERNAL REFERENCE CIRCUITRY REQUIRED. Figure 35. Powered Up, Internal Reference and Internal Reference Buffer ADR280 1.2V (2.4V ≤ V+ ≥ 5.5V) CONNECT 1.2V EXTERNAL REFERENCE TO REFIN PIN. V V+ V+ OUT 1.2V REFIN INPUT IS BUFFERED INTERNALLY. 10µF 10µF IT CREATES A 4.096V REFERENCE FOR THE ADC. 0.1µF V– 0.1µF DECOUPLE THE REF AND REFIN PINS EXTERNALLY REF REFIN B IN+ AD7626 IN– EN1 = 0 AND EN0 = 1 EXTERNAL 1.2V REFERENCE CONNECTED TO REFIN PIN IS REQUIRED. Figure 36. External 1.2 V Reference Using Internal Reference Buffer V+ ADR434/ ADR444 (6.1V ≤ V ≥ 18V) 4.096V IN CONNECT BUFFERED 4.096V SIGNAL TO REF PIN. VIN V V 10µF DECOUPLE THE REF PIN EXTERNALLY. IN OUT AD8031 REFIN IS A NO CONNECT. 10µF 0.1µF 0.1µF GND NO CONNECT REF REFIN C IN+ AD7626 IN– EN1 = 1 AND EN0 = 0 EXTERNAL 4.096V REFERENCE CONNECTED TO REF PIN IS REQUIRED. Figure 37. External 4.096 V Reference Applied to REF Pin Rev. A | Page 20 of 2 07648-131 07648-133 07648-132 AD7626 Power-Up Wake-Up Time from EN1= 0, EN0 = 0 When powering up the AD7626 device, first apply the 2.5 V The AD7626 powers down when EN1 and EN0 are both set to VDD2 supply and VIO voltage to the device. After the VIO and 0. Selecting the correct reference choice from power-down, the 2.5 V VDD2 have been established, apply the 5 V VDD1 supply. user sets EN1 and EN0 to the required value shown in Table 8. If using an external reference with the AD7626, ensure that the The user may immediately apply CNV pulses to receive data EN0 and EN1 pins are connected to the correct logic values conversion results. Typical wake-up times for the selected associated with the reference option of choice and then apply reference settings are shown in Table 9. Each time represents the external reference voltage. Finally, apply the analog inputs to the duration from the EN1, EN0 logic transition to when the the ADC. output of the ADC is settled to 0.5 LSB accuracy. 25 VDD2 INTERNAL Table 9. Wake-Up Time from EN1=0, EN0 = 0 REFERENCE Wake-Up 20 Time (0.5 LSB VDD2 EXTERNAL REFERENCE Reference Mode EN1 EN0 Accuracy) VIO INTERNAL REFERENCE A Power-up 1 1 9.5 sec 15 Internal reference and inter- VIO EXTERNAL REFERENCE nal reference buffer in use 10 B External 1.2 V reference 0 1 25 ms VDD1 INTERNAL applied to REFIN pin REFERENCE C External 4.096 V reference 1 0 65 μs 5 applied to REF pin VDD1 EXTERNAL REFERENCE 0 POWER SUPPLY 01 2 4 6 80 THROUGHPUT (MSPS) The AD7626 uses both 5 V (VDD1) and 2.5 V (VDD2) power Figure 39. Current Consumption vs. Sampling Rate supplies, as well as a digital input/output interface supply (VIO). VIO allows a direct interface with 2.5 V logic only. VIO and VDD2 can be taken from the same 2.5 V source; however, it is 160 best practice to isolate the VIO and VDD2 pins using separate 140 traces as well as to decouple each pin separately. INTERNAL REFERENCE 120 The 5 V and 2.5 V supplies required for the AD7626 can be EXTERNAL REFERENCE generated using Analog Devices, Inc., LDOs such as 100 the ADP3330-2.5, ADP3330-5, ADP3334, and ADP1708. 80 90 VDD2 60 85 40 80 VDD1 20 75 0 70 01 1 2 3 4 5 6 7 8 90 THROUGHPUT (MSPS) 65 Figure 40. Power Dissipation vs. Sampling Rate 60 55 INTERNAL REFERENCE USED 50 1 10 100 1k 10k SUPPLY FREQUENCY (Hz) Figure 38. PSRR vs. Supply Frequency (350 mV pp Ripple on VDD2, 600 mV Ripple on VDD1) Rev. A | Page 21 of 2 PSRR (dB) 07648-011 POWER (mW) CURRENT (mA) 07648-236 07648-235 AD7626 The clock DCO± is a buffered copy of CLK± and is synchronous DIGITAL INTERFACE to the data, D±, which is updated on the falling edge of DCO + Conversion Control (t ). By maintaining good propagation delay matching between D All analog-to-digital conversions are controlled by the CNV± D± and DCO± through the board and the digital host, DCO signal. This signal can be applied in the form of a CNV+/CNV− can be used to latch D± with good timing margin for the shift LVDS signal, or it can be applied in the form of a 2.5 V CMOS register. logic signal to the CNV+ pin. The conversion is initiated by the Conversions are initiated by a rising edge CNV± pulse. The rising edge of the CNV± signal. CNV± pulse must be returned low (≤ t maximum) for CNVH After the AD7626 is powered up, the first conversion result valid operation. After a conversion begins, it continues until generated is invalid. Subsequent conversion results are valid completion. Additional CNV± pulses are ignored during the provided that the time between conversions does not exceed conversion phase. After the time, t , elapses, the host should MSB the maximum specification for t . CYC begin to burst the CLK±. Note that, tMSB, is the maximum time The two methods for acquiring the digital data output of the for the MSB of the new conversion result and should be used as AD7626 via the LVDS interface are described in the following the gating device for CLK±. The echoed clock, DCO±, and the sections. data, D, are driven in phase with D± being updated on the falling edge of DCO+; the host should use the rising edge of Echoed-Clock Interface Mode DCO+ to capture D±. The only requirement is that the 16 The digital operation of the AD7626 in echoed-clock interface CLK± pulses finish before the time (t ) elapses of the next CLKL mode is shown in Figure 41. This interface mode, requiring conversion phase or the data is lost. From the tCLKL to tMSB, D± only a shift register on the digital host, can be used with many and DCO± are driven to 0. Set CLK± to idle low between CLK± digital hosts (such as FPGA, shift register, and microprocessor). bursts. It requires three LVDS pairs (D±, CLK±, and DCO±) between each AD7626 and the digital host. SAMPLE N SAMPLE N + 1 t CYC t CNVH CNV– CNV+ ACQUISITION ACQUISITION ACQUISITION t CLKL t CLK 15 16 11 2 156 123 CLK– CLK+ t DCO 1 15 16 1 2 15 16 23 DCO– DCO+ t MSB t t D CLKD D+ D1 D0 D15 D14 D1 D0 D15 D14 D13 0 0 N – 1 N – 1 N N N N N + 1 N + 1 N + 1 D– Figure 41. Echoed-Clock Interface Mode Timing Diagram Rev. A | Page 22 of 2 07648-103 AD7626 Self-Clocked Mode The AD7626 data captured on each phase of the state machine clock is then compared. The location of the 1 in The digital operation of the AD7626 in self-clocked interface the header in each set of data acquired allows the user to mode is shown in Figure 42. This interface mode reduces the choose the state machine clock phase that occurs during number of traces between the ADC and the digital host to two the data valid window of D±. LVDS pairs (CLK± and D±) or to a single pair if sharing a common CLK±. Multiple AD7626 devices can share a common The self-clocked mode data capture method allows the digital CLK± signal. This can be useful in reducing the number of host to adapt its result capture timing to accommodate LVDS connections to the digital host. variations in propagation delay through any AD7626.For example, where data is captured from multiple AD7626s When the self-clocked interface mode is used, each ADC sharing a common input clock. data-word is preceded by a 010 sequence. The first zero is automatically on D± once tMSB has elapsed. The 2-bit header Conversions are initiated by a CNV± pulse. The CNV± pulse is then clocked out by the first two CLK± falling edges. This must be returned low (tCNVH maximum) for valid operation. header is used to synchronize D± of each conversion in the After a conversion begins, it continues until completion. digital host because, in this mode, there is no data clock output Additional CNV± pulses are ignored during the conversion synchronous to the data (D±) to allow the digital host to phase. After the time, tMSB, elapses, the host begins to burst acquire the data output. the CLK± signal to the AD7626. All 18 CLK± pulses are to be applied in the time window framed by t and the subsequent MSB Synchronization of the D± data to the digital host’s acquisition t . The required 18 CLK± pulses must finish before t CLKL CLKL clock is accomplished by using one state machine per AD7626 (referenced to the next conversion phase) elapses. Otherwise, device. For example, using a state machine that runs at the the data is lost because it is overwritten by the next conversion same speed as CLK± incorporates three phases of this clock result. frequency (120º apart). Each phase acquires the data D± as output by the ADC. Set CLK± to idle high between bursts of 18 CLK± pulses. The header bit and conversion data of the next ADC result are output on subsequent falling edges of CLK± during the next burst of the CLK± signal. SAMPLE N SAMPLE N + 1 t CYC t CNVH CNV– CNV+ ACQUISITION ACQUISITION ACQUISITION t t CLK CLKL 1 17 18 1 2 3 4 17 18 23 CLK– CLK+ t MSB t CLKD D+ D15 D1 D0 D15 D14 D1 D0 1 1 N + 1 N – 1 N – 1 N N N N D– Figure 42. Self-Clocked Interface Mode Timing Diagram Rev. A | Page 23 of 2 07648-104 0 0 0 0 AD7626 APPLICATIONS INFORMATION VIO Supply Decoupling LAYOUT, DECOUPLING, AND GROUNDING Decouple the VIO supply applied to Pin 12 to ground at Pin 13. When laying out the printed circuit board (PCB) for the AD7626, follow the practices described in this section to obtain the maxi- Layout and Decoupling of Pin 25 to Pin 32 mum performance from the converter. Connect the outputs of Pin 25, Pin 26, and Pin 28 together and decouple them to Pin 27 using a 10 μF capacitor with low ESR Exposed Paddle and low ESL. The AD7626 has an exposed paddle on the underside of the package. Reduce the inductance of the path connecting Pin 25, Pin 26, and Pin 28 by widening the PCB traces connecting these pins. • Solder the paddle directly to the PCB. Take a similar approach in the connections used for the • Connect the paddle to the ground plane of the board using reference pins of the AD7626. Connect Pin 29, Pin 30, and multiple vias, as shown in Figure 43. Pin 32 together using widened PCB traces to reduce inductance. • Decouple all supply pins except for Pin 12 (VIO) directly to In internal or external reference mode, a 4.096 V reference voltage the paddle, minimizing the current return path. is output on Pin 29, Pin 30, and Pin 32. Decouple these pins to • Pin 13 and Pin 24 can be connected directly to the paddle. Pin 31 using a 10 μF capacitor with low ESR and low ESL. Use vias to ground at the point where these pins connect to the paddle. Figure 43 shows an example of the recommended layout for the underside of the AD7626 device. Note the extended signal VDD1 Supply Routing and Decoupling trace connections and the outline of the capacitors decoupling The VDD1 supply is connected to Pin 1, Pin 19, and Pin 20. the signals applied to the REF pins (Pin 29, Pin 30, and Pin 32) Decouple the supply using a 100 nF capacitor at Pin 1. The user and to the CAP2 pins (Pin 25, Pin 26, and Pin 28). can connect this supply trace to Pin 19 and Pin 20. Use a series ferrite bead to connect the VDD1 supply from Pin 1 to Pin 19 and Pin 20. The ferrite bead isolates any high frequency noise or ringing on the VDD1 supply. Decouple the VDD1 supply to Pin 19 and Pin 20 using a 100 nF capacitor decoupled to ground at the exposed paddle. 24 23 22 21 20 19 18 17 25 16 PADDLE 26 15 4.096V 27 14 EXTERNAL REFERENCE (ADR434 OR ADR444) 28 13 29 12 30 11 31 10 32 9 12 345 678 Figure 43. PCB Layout and Decoupling Recommendations for Pin 24 to Pin 32 Rev. A | Page 24 of 2 07648-013 AD7626 OUTLINE DIMENSIONS 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 BSC TOP EXPOSED 3.25 4.75 VIEW BSC SQ PAD 3.10 SQ (BOTTOM VIEW) 2.95 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 1.00 0.02 NOM THE PIN CONFIGURATION AND 0.85 0.30 FUNCTION DESCRIPTIONS COPLANARITY 0.20 REF SECTION OF THIS DATA SHEET. 0.80 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 44. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD7626BCPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2 AD7626BCPZ-RL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2 2 EVAL-AD7626EDZ Evaluation Board 3 EVAL-CED1Z Converter Evaluation and Development Board 1 Z = RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CEDIZ for evaluation/demonstration purposes. 3 This board allows the PC to control and communicate with all Analog Devices evaluation boards with model numbers ending with the ED designator. Rev. A | Page 25 of 2 011708-A AD7626 NOTES Rev. A | Page 26 of 2 AD7626 NOTES Rev. A | Page 27 of 2 AD7626 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07648-0-1/10(A) Rev. A | Page 28 of 28