ANALOG DEVICES AD7625

16-Bit, 6 MSPS, PulSAR Differential ADC AD7625 FEATURES FUNCTIONAL BLOCK DIAGRAM REFIN REF VCM Throughput: 6 MSPS SNR: 93 dB 1.2V VIO ÷2 CLOCK INL: ±0.45 LSB typical, ±1 LSB maximum BAND GAP LOGIC DNL: ±0.3 LSB typical, ±0.5 LSB maximum IN+ CAP CNV+, CNV– DAC IN– Power dissipation: 135 mW 32-lead LFCSP (5 mm × 5 mm) D+, D– SERIAL SAR SAR architecture DCO+, DCO– LVDS AD7625 CLK+, CLK– No latency/no pipeline delay 16-bit resolution with no missing codes Figure 1. Zero error: ±1.5 LSB GENERAL DESCRIPTION Differential input voltage: ±4.096 V Serial LVDS interface The AD7625 is a 16-bit, 6 MSPS, charge redistribution successive Self-clocked mode approximation register (SAR) based architecture analog-to-digital Echoed-clock mode converter (ADC). SAR architecture allows unmatched perfor- Can use LVDS or CMOS for conversion control (CNV signal) mance both in noise (93 dB SNR) and in linearity (1 LSB). The Reference options AD7625 contains a high speed, 16-bit sampling ADC, an internal Internal: 4.096 V conversion clock, and an internal buffered reference. On the External (1.2 V) buffered to 4.096 V CNV± rising edge, it samples the voltage difference between the External: 4.096 V IN+ and IN− pins. The voltages on these pins swing in opposite phase between 0 V and REF. The 4.096 V reference voltage, REF, APPLICATIONS can be generated internally or applied externally. High dynamic range telecommunications All converted results are available on a single LVDS self-clocked Receivers or echoed-clock serial interface, reducing external hardware Digital imaging systems connections. High speed data acquisition Spectrum analysis The AD7625 is housed in a 32-lead, 5 mm × 5 mm LFCSP with Test equipment operation specified from −40°C to +85°C. Table 1. Fast PulSAR® ADC Selection Input Type Resolution (Bits) 1 MSPS to <2 MSPS 2 MSPS to 3 MSPS 6 MSPS Differential (Ground Sense) 16 AD7653 16 AD7667 16 AD7980 16 AD7983 True Bipolar 16 AD7671 Differential (Antiphase) 16 AD7677 AD7621 AD7625 16 AD7623 AD7622 18 AD7643 AD7641 18 AD7982 18 AD7984 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07652-001 AD7625 TABLE OF CONTENTS Features .............................................................................................. 1  Theory of Operation ...................................................................... 13  Applications ....................................................................................... 1  Circuit Information .................................................................... 13  Functional Block Diagram .............................................................. 1  Converter Information .............................................................. 13  General Description ......................................................................... 1  Transfer Functions ..................................................................... 14  Revision History ............................................................................... 2  Analog Inputs ............................................................................. 14  Specif ica t ions ..................................................................................... 3  Typical Connection Diagram ................................................... 15  Timing Specifications .................................................................. 5  Driving the AD7625 ................................................................... 16  Absolute Maximum Ratings ............................................................ 6  Voltage Reference Options ........................................................ 17  Thermal Resistance ...................................................................... 6  Power Supply ............................................................................... 18  ESD Caution .................................................................................. 6  Digital Interface .......................................................................... 19  Pin Configuration and Function Descriptions ............................. 7  Applications Information .............................................................. 21  Typical Performance Characteristics ............................................. 9  Layout, Decoupling, and Grounding ....................................... 21  Terminology .................................................................................... 12  Outline Dimensions ....................................................................... 22  Ordering Guide .......................................................................... 22  REVISION HISTORY 1/09—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD7625 SPECIFICATIONS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; REF = 4.096 V; all specifications T to T , unless otherwise noted. MIN MAX Table 2. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V − V −V +V V IN+ IN− REF REF Operating Input Voltage V , V to GND −0.1 V + 0.1 V IN+ IN− REF Common-Mode Input Range V /2 − 0.05 V/2 V /2 + 0.05 V REF REF REF Common-Mode Rejection Ratio fIN = 1 MHz 60 dB Input Current Midscale input 77 μA THROUGHPUT Complete Cycle 166 ns Throughput Rate 0.1 6 MSPS DC ACCURACY Integral Linearity Error −1 ±0.45 +1 LSB No Missing Codes 16 Bits Differential Linearity Error −0.5 ±0.3 +0.5 LSB Transition Noise 0.6 LSB Zero Error T to T −4 ±1.5 +4 LSB MIN MAX Zero Error Drift 0.5 ppm/°C Gain Error TMIN to TMAX 8 20 LSB Gain Error Drift 0.4 ppm/°C 1 Power Supply Sensitivity VDD1 = 5 V ± 5% 0.4 LSB VDD2 = 2.5 V ± 5% 0.2 LSB AC ACCURACY External Reference f = 20 kHz IN Dynamic Range 92.5 93.2 dB Signal-to-Noise Ratio 92 93 dB Spurious-Free Dynamic Range 106 dB Total Harmonic Distortion −105.5 dB Signal-to-(Noise + Distortion) 91.5 92 dB Internal Reference f = 20 kHz IN Dynamic Range 92.5 93.2 dB Signal-to-Noise Ratio 91.5 92.9 dB Spurious-Free Dynamic Range 106 dB Total Harmonic Distortion −105.5 dB Signal-to-(Noise + Distortion) 91 92.5 dB −3 dB Input Bandwidth 100 MHz Aperture Jitter 0.25 ps rms INTERNAL REFERENCE Output Voltage REFIN @ 25°C 1.2 V Temperature Drift −40°C to +85°C ±15 ppm/°C REFERENCE BUFFER REFIN Input Voltage Range 1.2 V REF Output Voltage Range 4.076 4.096 4.116 V Line Regulation VDD1 ± 5%, VDD2 ± 5% 5 mV EXTERNAL REFERENCE Voltage Range REF 4.096 V VCM PIN @ 25°C Output Voltage REF/2 V Output Impedance 4 5 6 kΩ Rev. 0 | Page 3 of 24 AD7625 Parameter Test Conditions/Comments Min Typ Max Unit LVDS I/O (ANSI-644) Data Format Serial LVDS twos complement Differential Output Voltage, VOD RL = 100 Ω 200 350 454 mV 2 Common-Mode Output Voltage, V R = 100 Ω 850 1250 1375 mV OCM L Differential Input Voltage, V 100 650 mV ID Common-Mode Input Voltage, V 800 1575 mV ICM POWER SUPPLIES Specified Performance VDD1 4.75 5 5.25 V VDD2 2.37 2.5 2.63 V VIO 2.37 2.5 2.63 V Operating Currents Static—Not Converting VDD1 4.5 7.8 mA VDD2 17 22.7 mA VIO Self-clocked mode and echoed- 11 13 mA clock mode With Internal Reference 6 MSPS throughput VDD1 11 15.4 mA VDD2 21.5 28.3 mA VIO Self-clocked mode and echoed- 13.5 16 mA clock mode Without Internal Reference 6 MSPS throughput VDD1 9 12.1 mA VDD2 21 26 mA VIO Self-clocked mode and echoed- 13.5 16 mA clock mode 3 Power Dissipation Static—Not Converting 95 130 mW With Internal Reference 6 MSPS throughput 145 190 mW Without Internal Reference 6 MSPS throughput 135 165 mW Energy per Conversion 6 MSPS throughput 22 nJ/sample TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 Using an external reference. 2 The ANSI-644 LVDS specification has a minimum output common mode (VOCM) of 1125 mV. 3 Power dissipation is for the AD7625 device only. In self-clocked interface mode, 9 mW is dissipated in the 100 Ω terminator. In echoed-clock interface mode, 18 mW is dissipated in two 100 Ω terminators. Rev. 0 | Page 4 of 24 AD7625 TIMING SPECIFICATIONS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit 1 Time Between Conversions t 166 10,000 ns CYC Acquisition Time tACQ 40 ns CNV± High Time tCNVH 10 40 ns CNV± to D± (MSB) Delay tMSB 145 ns CNV± to Last CLK± (LSB) Delay t 110 ns CLKL 2 CLK± Period t (t − t + t)/n 4 3.33 ns CLK CYC MSB CLK CLK± Frequency fCLK 250 300 MHz CLK± to DCO± Delay (Echoed-Clock Mode) tDCO 0 4 7 ns DCO± to D± Delay (Echoed-Clock Mode) tD 0 1 ns CLK± to D± Delay t 0 4 7 ns CLKD 1 The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid. 2 For the minimum CLK period, the window available to read data is t − t + t . Divide this time by the number of bits (n) that are read. In echoed-clock interface CYC MSB CLK mode, n = 16; in self-clocked interface mode, n = 18. Rev. 0 | Page 5 of 24 AD7625 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Analog Inputs/Outputs 1 IN+, IN− to GND −0.3 V to REF + 0.3 V or Table 5. Thermal Resistance ±130 mA 2 Package Type θ θ Unit JA JC REF to GND −0.3 V to +6 V 32-Lead LFCSP_VQ 40 4 °C/W VCM, CAP2 to GND −0.3 V to +6 V CAP1, REFIN to GND −0.3 V to +2.7 V Supply Voltage ESD CAUTION VDD1 −0.3 V to +6 V VDD2, VIO −0.3 V to +3 V Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Input Current to Any Pin Except ±10 mA 3 Supplies −40°C to +85°C Operating Temperature Range (Commercial) Storage Temperature Range −65°C to +150°C Junction Temperature 150°C ESD 1 kV 1 See the Analog Inputs section. 2 Keep CNV+/CNV− low for any external REF voltage > 4.3 V applied to the REF pin. 3 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 24 AD7625 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 GND 1 24 PIN 1 IN+ VDD2 2 23 INDICATOR IN– CAP1 3 22 REFIN 4 21 VCM AD7625 EN0 5 20 VDD1 TOP VIEW 6 19 VDD1 EN1 (Not to Scale) VDD2 VDD2 7 18 CNV– 8 17 CLK+ NOTES 1. CONNECT THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS. Figure 2. Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1 VDD1 P Analog 5 V Supply. Decouple the 5 V supply with a 100 nF capacitor. 2 VDD2 P Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. The 2.5 V supply source should supply this pin first and then be traced to the other VDD2 pins (Pin 7 and Pin 18). 3 CAP1 AO Connect this pin to a 10 nF capacitor. 4 REFIN AI/O Prebuffer Reference Voltage. When using the internal reference, this pin outputs the band gap voltage and is nominally at 1.2 V. It can be overdriven with an external reference voltage such as the ADR280. In either internal or external reference mode, a 10 μF capacitor is required. If using an external 4.096 V reference (connected to REF), this pin is a no connect and does not require any capacitor. 5, 6 EN0, EN1 DI Enable Pins. The logic levels of these pins set the operation of the device as follows: EN1 = 0, EN0 = 0: Illegal state. EN1 = 0, EN0 = 1: Enable internal buffer, disable internal reference. An external 1.2 V reference connected to the REFIN pin is required. EN1 = 1, EN0 = 0: Disable internal reference and reference buffer. An external 4.096 V reference connected to the REF pin is required. EN1 = 1, EN0 = 1: Enable internal reference and reference buffer. 7 VDD2 P Digital 2.5 V Supply. Decouple this pin with a 100 nF capacitor. 8, 9 CNV−, CNV+ DI Convert Input. These pins act as the conversion control pin. On the rising edge of these pins, the analog inputs are sampled and a conversion cycle is initiated. CNV+ works as a CMOS input when CNV− is grounded; otherwise, CNV+ and CNV− are differential LVDS inputs. 10, 11 D−, D+ DO LVDS Data Outputs. The conversion data is output serially on these pins. 12 VIO P Input/Output Interface Supply. Use a 2.5 V supply and decouple this pin with a 100 nF capacitor. 13 GND P Ground. Return path for the 100 nF capacitor connected to Pin 12. 14, 15 DCO−, DCO+ DO LVDS Buffered Clock Outputs. When DCO+ is grounded, the self-clocked interface mode is selected. In this mode, the 16-bit results on D± are preceded by a 2-bit header (10) to allow synchronization of the data by the digital host with simple logic. When DCO+ is not grounded, the echoed-clock inter- face mode is selected. In this mode, DCO± is a copy of CLK±. The data bits are output on the falling edge of DCO+ and can be latched in the digital host on the next rising edge of DCO+. 16, 17 CLK−, CLK+ DI LVDS Clock Inputs. This clock shifts out the conversion results on the falling edge of CLK+. 18 VDD2 P Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. 19, 20 VDD1 P Analog 5 V Supply. Isolate these pins from Pin 1 with a ferrite bead and decouple them with a 100 nF capacitor. 21 VCM AO Common-Mode Output. When using any reference scheme, this pin produces one-half the voltage present on the REF pin, which can be useful for driving the common mode of the input amplifiers. 22 IN− AI Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+. 23 IN+ AI Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN−. 24 GND P Ground. Rev. 0 | Page 7 of 24 07652-002 REF CNV+ 9 32 D– 10 31 GND REF D+ 11 30 REF VIO 12 29 GND 13 28 CAP2 14 27 GND DCO– 15 26 CAP2 DCO+ 16 CAP2 CLK– 25 AD7625 1 Pin No. Mnemonic Type Description 25, 26, 28 CAP2 AO Connect all three CAP2 pins together and decouple them with the shortest trace possible to a single 10 μF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 27 (GND). 27 GND P Ground. Return path for the 10 μF capacitor connected to Pin 25, Pin 26, and Pin 28. 29, 30, 32 REF AI/O Buffered Reference Voltage. When using the internal reference or the 1.2 V external reference (REFIN input), the 4.096 V system reference is produced at this pin. When using an external reference, such as the ADR434 or the ADR444, the internal reference buffer must be disabled. In either case, connect all three REF pins together and decouple them with the shortest trace possible to a single 10 μF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 31 (GND). 31 GND P Ground. Return path for the 10 μF capacitor connected to Pin 29, Pin 30, and Pin 32. EP Exposed Pad The exposed pad is located on the underside of the package. Connect the exposed pad to the ground plane of the PCB using multiple vias. See the Exposed Paddle section for more information. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DO = digital output; P = power. Rev. 0 | Page 8 of 24 AD7625 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 INPUT TONE = 2kHz SNR = 93.16dB –20 –20 SINAD = 92.09dB THD = –110.45dB SFDR = 111.37dB –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 45 FREQUENCY (MHz) FREQUENCY (kHz) Figure 3. FFT 2 kHz Input Tone, Full View Figure 6. FFT 2 kHz Input Tone, Zoom In on Input Tone and Harmonics 0 0 INPUT TONE = 100kHz INPUT TONE = 50kHz SNR = 92.91dB SNR = 93.04dB –20 –20 SINAD = 92.55dB SINAD = 92.63dB THD = –103.11dB THD = –103.57dB SFDR = –103.41dB SFDR = –102.69dB –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. FFT 50 kHz Input Tone Figure 7. FFT 100 kHz Input Tone 0.5 1.0 0.8 0.4 0.3 0.6 0.4 0.2 0.1 0.2 0 0 –0.2 –0.1 –0.2 –0.4 –0.3 –0.6 –0.8 –0.4 –0.5 –1.0 0 16,384 32,768 49,152 65,536 0 16,384 32,768 49,152 65,536 CODE CODE Figure 5. Differential Nonlinearity vs. Code Figure 8. Integral Nonlinearity vs. Code Rev. 0 | Page 9 of 24 DNL (LSB) AMPLITUDE (dB) AMPLITUDE (dB) 07652-007 07652-005 07652-015 INL (LSB) AMPLITUDE (dB) AMPLITUDE (dB) 07652-008 07652-006 07652-014 AD7625 –94 –100.5 –96 –0.5dBFS –101.0 –98 –100 INTERNAL REF –3dBFS –101.5 –1dBFS –102 –104 –102.0 –106 –10dBFS –108 –102.5 –110 EXTERNAL REF –5dBFS –112 –103.0 –114 –116 –103.5 0 20 40 60 80 100 120 –60 –40 –20 0 20 40 60 80 100 120 INPUT FREQUENCY (kHz) TEMPERATURE (°C) Figure 9. THD at Input Amplitudes of −0.5 dBFS to −10 dBFS vs. Frequency Figure 12. THD vs. Temperature (−0.5 dB, 20 kHz Input Tone) 93.8 93.2 93.6 93.0 DYNR vs. TEMP INTERNAL REF DYNR vs. TEMP EXTERNAL REF 93.4 92.8 SINAD vs. TEMP EXTERNAL REF 93.2 92.6 93.0 92.4 92.8 92.2 SINAD vs. TEMP INTERNAL REF SNR vs. TEMP EXTERNAL REF 92.6 SNR vs. TEMP INTERNAL REF 92.0 92.4 91.8 92.2 91.6 –60 –40 –20 0 20 40 60 80 100 120 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 10. Dynamic Range and SNR vs. Temperature Figure 13. SINAD vs. Temperature (−0.5 dB, 20 kHz Input Tone) (−0.5 dB, 20 kHz Input Tone) 120 12 100 10 80 IN+ 60 8 40 GAIN ERROR 6 20 IN– 0 4 –20 2 ZERO ERROR –40 –60 0 –6 –4 –2 0 2 4 6 –60 –40 –20 0 20 40 60 80 100 120 DIFFERENTIAL INPUT VOLTAGE (V) TEMPERATURE (°C) Figure 11. Input Current (IN+, IN−) vs. Differential Input Voltage (6 MSPS) Figure 14. Zero Error and Gain Error vs. Temperature Rev. 0 | Page 10 of 24 THD (dB) INPUT CURRENT (µA) SNR, DYNAMIC RANGE (dB) 07652-010 07652-018 07652-012 THD (dB) ZERO ERROR AND GAIN ERROR (LSB) SINAD (dB) 07652-020 07652-019 07652-021 AD7625 250,000 140,000 262,144 SAMPLES 129,601 262,144 SAMPLES 128,084 STD DEVIATION = 0.4829 STD DEVIATION = 0.5329 120,000 201,320 200,000 100,000 150,000 80,000 60,000 100,000 40,000 50,000 30,651 30,073 20,000 2130 2329 54 46 00 0 0 0 0 FEC7 FEC8 FEC9 FECA FECB FECC FECD FEC6 FEC7 FEC8 FEC9 FECA FECB CODE (HEX) CODE (HEX) Figure 15. Histogram of 262,144 Conversions of a DC Input Figure 17. Histogram of 262,144 Conversions of a DC Input at the Code Center (Internal Reference) at the Code Transition (Internal Reference) 250,000 262,144 SAMPLES STD DEVIATION = 0.4814 201,614 200,000 150,000 100,000 50,000 30,250 30,206 41 33 0 0 0 FEC8 FEC9 FECA FECB FECC FECD FECE CODE (HEX) Figure 16. Histogram of 262,144 Conversions of a DC Input at the Code Center (External Reference) Rev. 0 | Page 11 of 24 COUNT COUNT 07652-024 07652-022 COUNT 07652-023 AD7625 TERMINOLOGY Power Supply Rejection Ratio (PSRR) Common-Mode Rejection Ratio (CMRR) Variations in power supply affect the full-scale transition but not CMRR is defined as the ratio of the power in the ADC output at the linearity of the converter. PSRR is the maximum change in full-scale frequency, f, to the power of an 80 mV p-p sine wave the full-scale transition point due to a change in power supply applied to the common-mode voltage of VIN+ and VIN− at voltage from the nominal value. frequency fS. Reference Voltage Temperature Coefficient CMRR (dB) = 10log(Pf/Pf ) S The reference voltage temperature coefficient is derived from the where: typical shift of output voltage at 25°C on a sample of parts at the Pf is the power at frequency f in the ADC output. maximum and minimum reference output voltage (VREF) meas- PfS is the power at frequency fS in the ADC output. ured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as Differential Nonlinearity (DNL) Error V (Max)–V (Min) REF REF 6 TCV ( ppm/°C)= ×10 REF In an ideal ADC, code transitions are 1 LSB apart. Differential V (25°C)× (T –T ) REF MAX MIN nonlinearity is the maximum deviation from this ideal value. It where: is often specified in terms of resolution for which no missing V (Max) = maximum V at T , T(25°C), or T . REF REF MIN MAX codes are guaranteed. V (Min) = minimum V at T , T(25°C), or T . REF REF MIN MAX Integral Nonlinearity (INL) Error V (25°C) = V at 25°C. REF REF Linearity error refers to the deviation of each individual code T = +85°C. MAX from a line drawn from negative full scale through positive full TMIN = −40°C. scale. The point used as negative full scale occurs ½ LSB before Signal-to-Noise Ratio (SNR) the first code transition. Positive full scale is defined as a level SNR is the ratio of the rms value of the actual input signal to 1½ LSB beyond the last code transition. The deviation is meas- the rms sum of all other spectral components below the Nyquist ured from the middle of each code to the true straight line. frequency, excluding harmonics and dc. The value for SNR is Dynamic Range expressed in decibels. Dynamic range is the ratio of the rms value of the full scale to Signal-to-(Noise + Distortion) (SINAD) Ratio the rms noise measured for an input typically at −60 dB. The SINAD is the ratio of the rms value of the actual input signal to value for dynamic range is expressed in decibels. the rms sum of all other spectral components below the Nyquist Effective Number of Bits (ENOB) frequency, including harmonics but excluding dc. The value for ENOB is a measurement of the resolution with a sine wave SINAD is expressed in decibels. input. It is related to SINAD and is expressed in bits by Spurious-Free Dynamic Range (SFDR) ENOB = [(SINAD − 1.76)/6.02] dB SFDR is the difference, in decibels, between the rms amplitude Gain Error of the input signal and the peak spurious signal. The first transition (from 100 … 000 to 100 …001) should occur Total Harmonic Distortion (THD) at a level ½ LSB above nominal negative full scale (−4.0959375 V THD is the ratio of the rms sum of the first five harmonic for the ±4.096 V range). The last transition (from 011 … 110 to components to the rms value of a full-scale input signal and 011 … 111) should occur for an analog voltage 1½ LSB below is expressed in decibels. the nominal full scale (+4.0959375 V for the ±4.096 V range). Zero Error The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first Zero error is the difference between the ideal midscale input transition from the difference between the ideal levels. voltage (0 V) and the actual voltage producing the midscale output code. Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is V INp-p LSB (V)= N 2 Rev. 0 | Page 12 of 24 AD7625 THEORY OF OPERATION IN+ GND SWITCHES CONTROL LSB SW+ MSB 32,768C 16,384C 4C 2C C C REF CLK+, CLK– (4.096V) DCO+, DCO– DATA TRANSFER CONTROL COMP LOGIC D+, D– GND OUTPUT CODE 32,768C 16,384C 4C 2C C C SW– MSB LSB CNV+, CNV– LVDS INTERFACE GND CONVERSION CONTROL IN– Figure 18. ADC Simplified Schematic CIRCUIT INFORMATION When the conversion phase begins, SW+ and SW− are opened The AD7625 is a 6 MSPS, high precision, power efficient, 16-bit ADC that uses SAR based architecture to provide performance first. The two capacitor arrays are then disconnected from the of 93 dB SNR, ±0.45 LSB INL, and ±0.3 LSB DNL. inputs and connected to the GND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured at the end The AD7625 is capable of converting 6,000,000 samples per of the acquisition phase is applied to the comparator inputs, second (6 MSPS). The device typically consumes 135 mW. The causing the comparator to become unbalanced. By switching AD7625 offers the added functionality of a high performance each element of the capacitor array between GND and 4.096 V on-chip reference and on-chip reference buffer. (the reference voltage), the comparator input varies by binary The AD7625 is specified for use with 5 V and 2.5 V supplies weighted voltage steps (V /2, V /4 … V /65,536). The REF REF REF (VDD1, VDD2). The interface from the digital host to the control logic toggles these switches, MSB first, to bring the AD7625 uses 2.5 V logic only. The AD7625 uses an LVDS comparator back into a balanced condition. At the completion interface to transfer data conversions. The CNV+ and CNV− of this process, the control logic generates the ADC output code. inputs to the part activate the conversion of the analog input. The AD7625 digital interface uses low voltage differential The CNV+ and CNV− pins can be applied using a CMOS or signaling (LVDS) to enable high data transfer rates. LVDS source. The AD7625 conversion result is available for reading after t MSB The AD7625 is housed in a space-saving, 32-lead, 5 mm × (time from the conversion start until MSB is available) has 5 mm LFCSP. elapsed. The user must apply a burst LVDS CLK± signal to the CONVERTER INFORMATION AD7625 to transfer data to the digital host. The AD7625 is a 6 MSPS ADC that uses SAR based architecture The CLK± signal outputs the ADC conversion result onto the incorporating a charge redistribution DAC. Figure 18 shows a data output D±. The bursting of the CLK± signal is illustrated simplified schematic of the ADC. The capacitive DAC consists in Figure 29 and Figure 30 and is characterized as follows: The of two identical arrays of 16 binary weighted capacitors that are differential voltage on CLK± should be held to create logic low connected to the two comparator inputs. in the time between t and t . CLKL MSB During the acquisition phase, the terminals of the array tied The AD7625 has two data read modes. For more information to the input of the comparator are connected to GND via SW+ about the echoed-clock and self-clocked interface modes, see and SW−. All independent switches are connected to the analog the Digital Interface section. inputs. In this way, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. A conversion phase is initiated when the acquisition phase is complete and the CNV± input goes logic high. Note that the AD7625 can receive a CMOS (CNV+) or LVDS format (CNV±) signal. Rev. 0 | Page 13 of 24 07652-030 AD7625 TRANSFER FUNCTIONS ANALOG INPUTS The AD7625 uses a 4.096 V reference. The AD7625 converts The analog inputs, IN+ and IN−, applied to the AD7625 must be the differential voltage of the antiphase analog inputs (IN+ and 180° out of phase with each other. Figure 20 shows an equivalent IN−) into a digital output. The analog inputs, IN+ and IN−, circuit of the input structure of the AD7625. require a 2.048 V common-mode voltage (REF/2). The two diodes provide ESD protection for the analog inputs, The 16-bit conversion result is in MSB first, twos complement IN+ and IN−. Care must be taken to ensure that the analog input format. signal does not exceed the reference voltage by more than 0.3 V. If the analog input signal exceeds this level, the diodes become The ideal transfer functions for the AD7625 are shown in forward-biased and start conducting current. These diodes can Figure 19 and Table 7. handle a forward-biased current of 130 mA maximum. However, if the supplies of the input buffer (for example, the supplies of the ADA4899-1 in Figure 24) are different from those of the 011 ... 111 reference, the analog input signal may eventually exceed the 011 ... 110 011 ... 101 supply rails by more than 0.3 V. In such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the part. VDD1 CNV 25pF IN+ 250Ω 100 ... 010 OR IN– 100 ... 001 100 ... 000 –FSR –FSR + 1LSB +FSR – 1LSB –FSR + 0.5LSB +FSR – 1.5LSB Figure 20. Equivalent Analog Input Circuit ANALOG INPUT The analog input structure allows the sampling of the true Figure 19. ADC Ideal Transfer Functions (FSR = Full-Scale Range) differential signal between IN+ and IN−. By using these differ- Table 7. Output Codes and Ideal Input Voltages ential inputs, signals common to both inputs are rejected. The AD7625 shows some degradation in THD with higher analog Analog Input (IN+ − IN−) Digital Output Code input frequencies. Description REF = 4.096 V Twos Complement (Hex) 85 FSR − 1 LSB +4.0959375 V 0x1FFF 80 Midscale + 1 LSB +62.5 μV 0x0001 75 Midscale 0 V 0x0000 Midscale − 1 LSB −62.5 μV 0xFFFF 70 −FSR + 1 LSB −4.0959375 V 0x1001 65 −FSR −4.096 V 0x1000 60 55 50 45 40 1 10 100 1k 10k 100k 1M 10M INPUT COMMON-MODE FREQUENCY (Hz) Figure 21. Analog Input CMRR vs. Frequency Rev. 0 | Page 14 of 24 ADC CODE (TWOS COMPLEMENT) 07652-031 CMRR (dB) 07652-032 07652-009 AD7625 TYPICAL CONNECTION DIAGRAM 8 V+ ADR434 ADR444 CAPACITOR ON OUTPUT FOR STABILITY C REF 1 10µF 1, 2 VDD1 10µF (5V) 100nF VDD2 (2.5V) 32 31 30 29 28 27 26 25 100nF 24 GND 1 VDD1 10nF IN+ 23 IN+ 2 VDD2 8 ADR280 PADDLE SEE THE DRIVING 22 IN– IN– 7 3 THE AD7625 SECTION CAP1 10µF 4 VCM VCM 21 REFIN VIO AD7625 3 10kΩ 10kΩ 5 EN0 VDD1 CONTROL FOR 20 VDD1 (5V) ENABLE FERRITE PINS 6 100nF EN1 6 BEAD 19 VDD1 VDD2 7 VDD2 (2.5V) VDD2 VDD2 18 100nF (2.5V) 100nF 4 CONVERSION CONTROL CMOS (CNV+ ONLY) OR 8 9 10 11 12 13 14 15 16 17 LVDS CNV+ AND CNV– 5 USING 100Ω 100Ω TERMINATION RESISTOR 100Ω VIO (2.5V) 100Ω 100Ω DIGITAL INTERFACE SIGNALS DIGITAL HOST LVDS TRANSMIT AND RECEIVE 1 SEE THE LAYOUT, DECOUPLING, AND GROUNDING SECTION. 2 C IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESR AND ESL. REF 3 USE PULL-UP OR PULL-DOWN RESISTORS TO CONTROL EN0, EN1 DURING POWER-UP. EN0 AND EN1 INPUTS CAN BE FIXED IN HARDWARE OR CONTROLLED USING A DIGITAL HOST (EN0 = 0 AND EN1 = 0 IS AN ILLEGAL STATE). 4 OPTION TO USE A CMOS (CNV+) OR LVDS (CNV±) INPUT TO CONTROL CONVERSIONS. 5 TO ENABLE SELF-CLOCKED MODE, TIE DCO+ TO GND USING A PULL-DOWN RESISTOR. 6 CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE FROM PIN 1 USING A FERRITE BEAD SIMILAR TO WURTH 74279266. 7 SEE THE DRIVING THE AD7625 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS. 8 SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS. Figure 22. Typical Application Diagram Rev. 0 | Page 15 of 24 CNV– CNV+ REF D– GND D+ REF VIO REF GND CAP2 DCO– GND CAP2 DCO+ CAP2 CLK– CLK+ 07652-027 AD7625 DRIVING THE AD7625 ADA4899-1 Differential Analog Input Source U1 ANALOG INPUT Figure 24 shows an ADA4899-1 driving each differential input (UNIPOLAR 0V TO 4.096V) to the AD7625. 590Ω 33Ω Single-Ended-to-Differential Driver 56pF For applications using unipolar analog signals, a single-ended- IN+ to-differential driver, as shown in Figure 23, allows for a differ- 590Ω AD7625 ential input into the part. This configuration, when provided with an input signal of 0 V to 4.096 V, produces a differential IN– 33Ω VCM ±4.096 V with midscale at 2.048 V. The one-pole filter using U2 R = 33 Ω and C = 56 pF provides a corner frequency of 86 MHz. ADA4899-1 56pF 100nF The VCM output of the AD7625 can be buffered and then used 100nF to provide the required 2.048 V common-mode voltage. V+ 50Ω AD8031, AD8032 V– Figure 23. Single-Ended-to-Differential Driver Circuit 1 1 REF REF C C REF REF 2 2 10µF 10µF +V S 33Ω 0V TO V REF REFIN REF 56pF IN+ ADA4899-1 –V S AD7625 +V S IN– VCM 33Ω GND V TO 0V REF 56pF 2.048V –V ADA4899-1 S +V S VCM BUFFERED VCM PIN OUTPUT 0.1µF GIVES THE REQUIRED 2.048V AD8031, AD8032 COMMON-MODE SUPPLY FOR –V S ANALOG INPUTS. 1 SEE THE VOLTAGE REFERENCE OPTIONS SECTION. CONNECTION TO EXTERNAL REFERENCE SIGNALS IS DEPENDENT ON THE EN1 AND EN0 SETTINGS. 2 C IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESL AND ESR. REF THE REF AND REFIN PINS ARE DECOUPLED REGARDLESS OF EN1 AND EN0 SETTINGS. Figure 24. Driving the AD7625 from a Differential Analog Source Rev. 0 | Page 16 of 24 07652-025 07652-033 AD7625 1 VOLTAGE REFERENCE OPTIONS Table 8. Voltage Reference Options Option EN1 EN0 Reference Mode The AD7625 allows flexible options for creating and buffering A 1 1 Use internal reference and internal the reference voltage. The AD7625 conversions refer to 4.096 V reference buffer (both are enabled). only. The various options creating this 4.096 V reference are B 0 1 Use external 1.2 V reference with controlled by the EN1 and EN0 pins (see Table 8). internal reference buffer enabled. The internal reference is disabled. C 1 0 Use external 4.096 V reference with an external reference buffer. The internal reference and reference buffer are disabled. 1 EN1 = 0 and EN0 = 0 is an illegal state. A SETTING EN1 = 1 AND EN0 = 1 ENABLES THE INTERNAL REFERENCE AND REFERENCE BUFFER. DECOUPLE V+ THE REF AND REFIN PINS EXTERNALLY. ADR280 V+ ADR434 V+ ADR444 10µF 10µF V– C B SETTING EN1 = 1 AND EN0 = 0 DISABLES THE INTERNAL REFERENCE SETTING EN1 = 0 AND EN0 = 1 AND REFERENCE BUFFER. CONNECT THE DISABLES THE INTERNAL REFERENCE BUFFERED 4.096V SIGNAL TO AND ENABLES THE INTERNAL REFERENCE BUFFER. REF REFIN IN+ THE REF PIN. CONNECT A 1.2V REFERENCE TO THE REFIN PIN. THE 1.2V APPLIED TO THE REFIN PIN IS BUFFERED INTERNALLY TO CREATE A 4.096V REFERENCE FOR THE ADC. AD7625 IN– Figure 25. Voltage Reference Options Rev. 0 | Page 17 of 24 07652-026 AD7625 After VIO is established, apply the 2.5 V VDD2 supply to the POWER SUPPLY device followed by the 5 V VDD1 supply and then an external The AD7625 uses both 5 V (VDD1) and 2.5 V (VDD2) power reference (depending on the reference setting being used). supplies, as well as a digital input/output interface supply (VIO). Finally, apply the analog inputs to the ADC. VIO allows a direct interface with 2.5 V logic only. VIO and 25 VDD2 can be taken from the same 2.5 V source; however, it is best practice to isolate the VIO and VDD2 pins using separate VDD2 INTERNAL REF traces and also to decouple each pin separately. 20 The 5 V and 2.5 V supplies required for the AD7625 can be VDD2 EXTERNAL REF generated using Analog Devices, Inc., low dropout regulators 15 VIO (LDOs) such as the ADP3330-2.5, ADP3330-5, ADP3334, and ADP1708. 10 90 VDD1 INTERNAL REF VDD2 85 5 VDD1 EXTERNAL REF 80 VDD1 0 75 0 1000 2000 3000 4000 5000 6000 7000 SAMPLING RATE (kSPS) 70 Figure 27. Current Consumption vs. Sampling Rate 65 60 150 140 55 INTERNAL REFERENCE USED 130 50 1 10 100 1k 10k INTERNAL REF 120 SUPPLY FREQUENCY (Hz) Figure 26. PSRR vs. Supply Frequency 110 (350 mV pp Ripple on VDD2, 600 mV Ripple on VDD1) 100 EXTERNAL REF Power-Up 90 When powering up the AD7625 device, first apply the VIO 80 voltage to the device so that the EN1 and EN0 values can be set 70 for the reference option in use. Connect the EN0 and EN1 pins to pull-up/pull-down resistors to ensure that one or both of 60 0 1000 2000 3000 4000 5000 6000 7000 these pins is set to a nonzero value. EN0 = 0 and EN1 = 0 is an SAMPLING RATE (kSPS) illegal state that must be avoided. Figure 28. Power Dissipation vs. Sampling Rate Rev. 0 | Page 18 of 24 PSRR (dB) 07652-011 POWER DISSIPATION (mW) CURRENT (mA) 07652-017 07652-016 AD7625 DIGITAL INTERFACE Conversion Control The clock DCO± is a buffered copy of CLK± and is synchronous to the data, D±, which is updated on the falling edge of DCO+ All analog-to-digital conversions are controlled by the CNV (tD). By maintaining good propagation delay matching between signal. This signal can be applied in the form of a CNV+/CNV− D± and DCO± through the board and the digital host, DCO± LVDS signal, or it can be applied in the form of a 2.5 V CMOS can be used to latch D± with good timing margin for the shift logic signal to the CNV+ pin. The conversion is initiated by the register. rising edge of the CNV signal. Conversions are initiated by a CNV± pulse. The CNV± pulse After the AD7625 is powered up, the first conversion result must be returned low (≤t maximum) for valid operation. CNVH generated is invalid. Subsequent conversion results are valid After a conversion begins, it continues until completion. Addi- provided that the time between conversions does not exceed tional CNV± pulses are ignored during the conversion phase. the maximum specification for t . CYC After the time tMSB elapses, the host should begin to burst the The two methods for acquiring the digital data output of the CLK±. Note that tMSB is the maximum time for the MSB of the AD7625 via the LVDS interface are described in the following new conversion result and should be used as the gating device sections. for CLK±. The echoed clock, DCO±, and the data, D±, are Echoed-Clock Interface Mode driven in phase, with D± being updated on the falling edge of DCO+; the host should use the rising edge of DCO+ to capture The digital operation of the AD7625 in echoed-clock interface D±. The only requirement is that the 16 CLK pulses finish mode is shown in Figure 29. This interface mode, requiring before the time tCLKL elapses for the next conversion phase or the only a shift register on the digital host, can be used with many data is lost. From the time tCLKL to tMSB, D± and DCO± are digital hosts (FPGA, shift register, microprocessor, and so on). driven to 0s. Set CLK± to idle low between CLK± bursts. It requires three LVDS pairs (D±, CLK±, and DCO±) between each AD7625 and the digital host. SAMPLE N SAMPLE N + 1 t CYC t CNVH CNV– CNV+ t ACQ ACQUISITION ACQUISITION ACQUISITION t CLKL t CLK 15 16 11 2 156 123 CLK– CLK+ t DCO 1 15 16 1 2 15 16 23 DCO– DCO+ t MSB t t D CLKD D+ D1 D0 D15 D14 D1 D0 D15 D14 D13 0 0 N – 1 N – 1 N N N N N + 1 N + 1 N + 1 D– Figure 29. Echoed-Clock Interface Mode Timing Diagram Rev. 0 | Page 19 of 24 07652-003 AD7625 Self-Clocked Interface Mode The digital operation of the AD7625 in self-clocked interface Conversions are initiated by a CNV± pulse. The CNV± pulse mode is shown in Figure 30. This interface mode reduces the must be returned low (≤tCNVH maximum) for valid operation. number of wires between ADCs and the digital host to two LVDS After a conversion begins, it continues until completion. Addi- pairs per AD7625 (CLK± and D±) or to a single pair if sharing a tional CNV± pulses are ignored during the conversion phase. common CLK± using multiple AD7625 devices. Self-clocked After the time t elapses, the host should begin to burst the MSB interface mode facilitates the design of boards that use multiple CLK±. Note that t is the maximum time for the first bit of MSB AD7625 devices. The digital host can adapt the interfacing the header and should be used as the gating device for CLK±. scheme to account for differing propagation delays between CLK± is also used internally on the host to begin the internal each AD7625 device and the digital host. synchronization state machine. The next header bit and conversion results are output on subsequent falling edges of CLK±. The The self-clocked interface mode consists of preceding the results only requirement is that the 18 CLK± pulses finish before the of each ADC word with a 2-bit header on the data, D±. This time tCLKL elapses for the next conversion phase or the data is header is used to synchronize D± of each conversion in the lost. Set CLK± to idle high between bursts of 18 CLK± pulses. digital host. Synchronization is accomplished by one simple state machine per AD7625 device. For example, if the state machine is running at the same speed as CLK± with three phases, the state machine measures when the Logic 1 of the header occurs. SAMPLE N SAMPLE N + 1 t CYC t CNVH CNV– CNV+ t ACQ ACQUISITION ACQUISITION ACQUISITION t t CLK CLKL 17 18 1 2 3 4 17 18 1 23 CLK– CLK+ t MSB t CLKD D+ D15 D1 D0 D15 D14 D1 D0 1 1 N + 1 N – 1 N – 1 N N N N D– Figure 30. Self-Clocked Interface Mode Timing Diagram Rev. 0 | Page 20 of 24 07652-004 0 0 0 0 AD7625 APPLICATIONS INFORMATION supply to Pin 19 and Pin 20 using a 100 nF capacitor to GND. LAYOUT, DECOUPLING, AND GROUNDING This GND connection can be placed a short distance away from When laying out the printed circuit board (PCB) for the AD7625, the exposed paddle. follow the practices described in this section to obtain the maxi- VIO Supply Decoupling mum performance from the converter. Decouple the VIO supply applied to Pin 12 to ground at Pin 13. Exposed Paddle Layout and Decoupling of Pin 25 to Pin 32 The AD7625 has an exposed paddle on the underside of the package. Connect the outputs of Pin 25, Pin 26, and Pin 28 together and decouple them to Pin 27 using a 10 μF capacitor with low ESR • Solder the paddle directly to the PCB. and low ESL. • Connect the paddle to the ground plane of the board using Reduce the inductance of the path connecting Pin 25, Pin 26, multiple vias, as shown in Figure 31. and Pin 28 by widening the PCB traces connecting these pins. • Decouple all supply pins except for Pin 12 (VIO) directly to the paddle, minimizing the current return path. A similar approach should be taken in the connections used for • Pin 13 and Pin 24 can be connected directly to the paddle. the reference pins of the AD7625. Connect Pin 29, Pin 30, and Use vias to ground at the point where these pins connect to Pin 32 together using widened PCB traces to reduce inductance. the paddle. In internal or external reference mode, a 4.096 V reference voltage is output on Pin 29, Pin 30, and Pin 32. Decouple these pins to VDD1 Supply Routing and Decoupling Pin 31 using a 10 μF capacitor with low ESR and low ESL. The VDD1 supply is connected to Pin 1, Pin 19, and Pin 20. The Figure 31 shows an example of the recommended layout for supply should be decoupled using a 100 nF capacitor at Pin 1. the underside of the AD7625 device. Note the extended signal The user can connect this supply trace to Pin 19 and Pin 20. Use trace connections and the outline of the capacitors decoupling a series ferrite bead to connect the VDD1 supply from Pin 1 to the signals applied to the REF pins (Pin 29, Pin 30, and Pin 32) Pin 19 and Pin 20. The ferrite bead isolates any high frequency and to the CAP2 pins (Pin 25, Pin 26, and Pin 28). noise or ringing on the VDD1 supply. Decouple the VDD1 24 23 22 21 20 19 18 17 25 16 Paddle 26 15 4.096V 27 14 EXTERNAL REFERENCE (ADR434 OR ADR444) 28 13 29 12 30 11 31 10 32 9 1 234 567 8 Figure 31. PCB Layout and Decoupling Recommendations for Pin 24 to Pin 32 Rev. 0 | Page 21 of 24 07652-013 AD7625 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 BSC TOP EXPOSED 3.25 4.75 VIEW BSC SQ PAD 3.10 SQ (BOTTOM VIEW) 2.95 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 1.00 0.02 NOM THE PIN CONFIGURATION AND 0.85 0.30 FUNCTION DESCRIPTIONS COPLANARITY 0.20 REF SECTION OF THIS DATA SHEET. 0.80 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 32. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7625BCPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2 1 AD7625BCPZ-RL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2 1, 2 EVAL-AD7625EDZ Evaluation Board 1, 3 EVAL-CED1Z Converter Evaluation and Development Board 1 Z = RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z for evaluation/demonstration purposes. 3 This board allows the PC to control and communicate with all Analog Devices evaluation boards with model numbers ending with the ED designator. Rev. 0 | Page 22 of 24 011708-A AD7625 NOTES Rev. 0 | Page 23 of 24 AD7625 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07652-0-1/09(0) Rev. 0 | Page 24 of 24