ANALOG DEVICES AD7622

® 16-Bit, 1.5 LSB INL, 2 MSPS PulSAR ADC AD7622 FEATURES FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND DVDD DGND Throughput 2 MSPS (wideband warp and warp mode) AGND 1.5 MSPS (normal mode) OVDD AD7622 AVDD OGND INL: ±0.5 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR) REF REF AMP 16-bit resolution with no missing codes SERIAL PORT Dynamic range: 92.5 dB typical 16 IN+ SWITCHED D[15:0] CAP DAC IN– SINAD: 91 dB minimum @ 20 kHz (VREF = 2.5 V) SER/PAR PARALLEL THD: −115 dB typical @ 20 kHz (VREF = 2.5 V) INTERFACE BUSY 2.048 V internal reference: typical drift 8 ppm/°C; TEMP output PDREF RD CLOCK PDBUF CS Differential input range: ±VREF (VREF up to 2.5 V) CONTROL LOGIC AND PD OB/2C No pipeline delay (SAR architecture) CALIBRATION CIRCUITRY RESET BYTESWAP Parallel (16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface SPI®/QSPI™/MICROWIRE™/DSP compatible WARP NORMAL CNVST Single 2.5 V supply operation Figure 1. Power dissipation 70 mW typical @ 2 MSPS with internal REF Table 1. PulSAR 48-Lead ADC Selection 2 μW in power-down mode 100 to 500 to 650 to Type/kSPS 250 570 1000 >1000 Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ Pseudo AD7651, AD7650, AD7653, Pin compatible with other PulSAR 48-lead ADCs Differential AD7660, AD7652, AD7667 AD7661 AD7664, APPLICATIONS AD7666 Medical instruments True Bipolar AD7665 AD7610, AD7612, High speed data acquisition/high dynamic data acquisition AD7663 AD7671 Digital signal processing True AD7675 AD7676 AD7677 AD7621, Differential AD7622, Spectrum analysis AD7623 Instrumentation 18-Bit AD7631, AD7679 AD7634, AD7641, Communications Multichannel/ AD7678 AD7674 AD7643 ATE Simultaneous AD7654 AD7655 GENERAL DESCRIPTION 1.50 POSITIVE INL = +0.43 LSB NEGATIVE INL = –0.49 LSB The AD7622 is a 16-bit, 2 MSPS, charge redistribution SAR, 1.00 fully differential, analog-to-digital converter (ADC) that operates from a single 2.5 V power supply. The part contains a 0.50 high speed, 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and 0 both serial and parallel system interface ports. It features two very high sampling rate modes (wideband warp and warp) and –0.50 a fast mode (normal) for asynchronous rate applications. The AD7622 is hardware factory calibrated and tested to ensure ac –1.00 parameters, such as signal-to-noise ratio (SNR), in addition to the more traditional dc parameters of gain, offset, and linearity. –1.50 0 16384 32768 49152 65536 The AD7622 is available in Pb-free only packages with CODE operation specified from −40°C to +85°C. Figure 2. Integral Nonlinearity vs. Code Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INL (LSB) 06023-005 06023-001 AD7622 TABLE OF CONTENTS Features .............................................................................................. 1 Multiplexed Inputs ..................................................................... 17 Applications....................................................................................... 1 Driver Amplifier Choice ........................................................... 18 General Description ......................................................................... 1 Voltage Reference Input ............................................................ 19 Functional Block Diagram .............................................................. 1 Power Supply............................................................................... 20 Revision History ............................................................................... 2 Conversion Control ................................................................... 20 Specifications..................................................................................... 3 Interfaces.......................................................................................... 21 Timing Specifications....................................................................... 5 Digital Interface.......................................................................... 21 Absolute Maximum Ratings............................................................ 7 Parallel Interface......................................................................... 21 ESD Caution.................................................................................. 7 Serial interface ............................................................................ 22 Pin Configuration and Function Descriptions............................. 8 Master Serial Interface............................................................... 22 Terminology .................................................................................... 11 Slave Serial Interface .................................................................. 24 Typical Performance Characteristics ........................................... 12 Microprocessor Interfacing....................................................... 26 Applications Information .............................................................. 15 Application Hints ........................................................................... 27 Circuit Information.................................................................... 15 Layout .......................................................................................... 27 Converter Operation.................................................................. 15 Evaluating the AD7622 Performance ...................................... 27 Modes of Operation ................................................................... 15 Outline Dimensions ....................................................................... 28 Transfer Functions...................................................................... 16 Ordering Guide .......................................................................... 28 Typical Connection Diagram........................................................ 17 Analog Inputs.............................................................................. 17 REVISION HISTORY 6/06—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7622 SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V − V −V +V V IN+ IN− REF REF 1 Operating Input Voltage V , V to AGND −0.1 AVDD V IN+ IN− Analog Input CMRR f = 100 kHz 58 dB IN Input Current 2 MSPS throughput 3.5 μA 2 Input Impedance THROUGHPUT SPEED Complete Cycle Wideband warp, warp modes 500 ns Throughput Rate Wideband warp, warp modes 0.001 2 MSPS Time Between Conversions Wideband warp, warp modes 1 ms Complete Cycle Normal mode 667 ns Throughput Rate Normal mode 0 1.5 MSPS DC ACCURACY 3 4 Integral Linearity Error T to T = −40°C to +85°C −1.5 ±0.5 +1.5 LSB MIN MAX No Missing Codes 16 Bits Differential Linearity Error −1 +1.25 LSB Transition Noise VREF = 2.5 V 0.5 LSB Transition Noise VREF = 2.048 V 0.6 LSB 5 Zero Error, T to T −10 +10 LSB MIN MAX Zero Error Temperature Drift ±0.5 ppm/°C 5 Gain Error, T to T −8 +8 LSB MIN MAX Gain Error Temperature Drift ±0.5 ppm/°C Power Supply Sensitivity AVDD = 2.5 V ± 5% ±4 LSB AC ACCURACY 6 Dynamic Range VREF = 2.5 V 91.5 92.5 dB Signal-to-Noise fIN = 20 kHz, VREF = 2.5 V 91 92 dB f = 20 kHz, V = 2.048 V 89.5 90.5 dB IN REF f = 100 kHz, V = 2.5 V 91 dB IN REF Spurious-Free Dynamic Range f = 20 kHz, V = 2.5 V 117 dB IN REF fIN = 20 kHz, VREF = 2.048 V 110 dB fIN = 100 kHz, VREF = 2.5 V 101 dB Total Harmonic Distortion fIN = 20 kHz, VREF = 2.5 V −115 dB f = 20 kHz, V = 2.048 V −109 dB IN REF f = 100 kHz, V = 2.5 V −100 dB IN REF Signal-to-(Noise + Distortion) f = 20 kHz, V = 2.5 V 91 92 dB IN REF fIN = 20 kHz, VREF = 2.048 V 89.5 90.5 dB fIN = 100 kHz, VREF = 2.5 V 91 dB −3 dB Input Bandwidth 50 MHz SAMPLING DYNAMICS Aperture Delay 1 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 140 ns INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 2.038 2.048 2.058 V Temperature Drift −40°C to +85°C ±8 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V Turn-On Settling Time CREF = 10 μF 5 ms Rev. 0 | Page 3 of 28 AD7622 Parameter Conditions Min Typ Max Unit REFBUFIN Output Voltage REFBUFIN @ 25°C 1.19 V REFBUFIN Output Resistance 6.33 kΩ EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 1.8 2.5 AVDD + 0.1 V Current Drain 2 MSPS throughput 150 μA REFERENCE BUFFER PDREF = high, PDBUF = low REFBUFIN Input Voltage Range REF = 2.048 V typ 1.05 1.2 1.30 V REFBUFIN Input Current REFBUFIN = 1.2 V 1 nA TEMPERATURE PIN Voltage Output @ 25°C 278 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.7 kΩ DIGITAL INPUTS Logic Levels V −0.3 +0.6 V IL V 1.7 5.25 V IH I −1 +1 μA IL IIH −1 +1 μA DIGITAL OUTPUTS 7 Data Format 8 Pipeline Delay VOL ISINK = 500 μA 0.4 V VOH ISOURCE = −500 μA OVDD − 0.3 V POWER SUPPLIES Specified Performance AVDD 2.37 2.5 2.63 V DVDD 2.37 2.5 2.63 V 9 OVDD 2.30 3.6 V 10 Operating Current 2 MSPS throughput 11 AVDD With internal reference 24 mA AVDD Without internal reference 23 mA DVDD 2.5 mA 12 OVDD 1 mA 11 Power Dissipation 10 With Internal Reference 2 MSPS throughput 70 85 mW 10 Without Internal Reference 2 MSPS throughput 65 80 mW 12 In Power-Down Mode PD = high 2 μW 13 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 When using an external reference. With the internal reference, the input range is −0.1 V to VREF. 2 See Analog Inputs section. 3 Linearity is tested using endpoints, not best fit. 4 LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV. 5 See Voltage Reference Input section. These specifications do not include the error contribution from the external reference. 6 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 7 Parallel or serial 16-bit. 8 Conversion results are available immediately after completed conversion. 9 See the Absolute Maximum Ratings section. 10 In wideband and warp modes. Tested in parallel reading mode. 11 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high. 12 With all digital inputs forced to OVDD. 13 Consult sales for extended temperature range. Rev. 0 | Page 4 of 28 AD7622 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (Refer to Figure 31 and Figure 32) 1 Convert Pulse Width t 15 70 ns 1 2 3 Time Between Conversions (Warp Mode /Normal Mode) t2 500/667 ns CNVST t3 23 ns Low to BUSY High Delay BUSY High All Modes (Except Master Serial Read After Convert) Warp Mode/Normal Mode t 360/485 ns 4 Aperture Delay t 1 ns 5 End of Conversion to BUSY Low Delay t6 10 ns Conversion Time (Warp Mode/Normal Mode) t7 360/485 ns Acquisition Time (Warp Mode/Normal Mode) t8 140/182 ns RESET Pulse Width t 15 ns 9 4 RESET Low to BUSY High Delay t 10 ns 38 4 BUSY High Time from RESET Low t 500 ns 39 PARALLEL INTERFACE MODES (Refer to Figure 33 to Figure 36 ) CNVST t 360/485 ns Low to Data Valid Delay (Warp Mode/Normal Mode) 10 Data Valid to BUSY Low Delay t 2 ns 11 Bus Access Request to Data Valid t12 20 ns Bus Relinquish Time t13 2 15 ns 5 MASTER SERIAL INTERFACE MODES (Refer to Figure 37 and Figure 38) CS t14 10 ns Low to SYNC Valid Delay 5 CS t15 10 ns Low to Internal SCLK Valid Delay CS t 10 ns Low to SDOUT Delay 16 CNVST t 15/135 ns Low to SYNC Delay (Warp Mode/Normal Mode) 17 SYNC Asserted to SCLK First Edge Delay t18 2 ns 6 Internal SCLK Period t19 8 20 ns 6 Internal SCLK High t20 2 ns 6 Internal SCLK Low t 3 ns 21 6 SDOUT Valid Setup Time t 1 ns 22 6 SDOUT Valid Hold Time t 0 ns 23 6 SCLK Last Edge to SYNC Delay t24 0 ns CS t25 10 ns High to SYNC HI-Z CS t26 10 ns High to Internal SCLK HI-Z CS t 10 ns High to SDOUT HI-Z 27 6 BUSY High in Master Serial Read After Convert t See Table 4 ns 28 CNVST t29 375/500 ns Low to SYNC Asserted Delay (Warp Mode/Normal Mode) SYNC Deasserted to BUSY Low Delay t30 13 ns SLAVE SERIAL INTERFACE MODES (Refer to Figure 40 and Figure 41) External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 1 8 ns SDIN Setup Time t 5 ns 33 SDIN Hold Time t 5 ns 34 External SCLK Period t 12.5 ns 35 External SCLK High t36 5 ns External SCLK Low t37 5 ns See Notes on next page. Rev. 0 | Page 5 of 28 AD7622 1 See the Conversion Control section. 2 All timings for wideband warp mode are the same as warp mode. 3 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 4 See the Digital Interface section and the RESET section. 5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C of 10 pF; otherwise, the load is 60 pF maximum. L 6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications. Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t 3 3 3 3 ns 18 Internal SCLK Period Minimum t 8 16 32 64 ns 19 Internal SCLK Period Maximum t19 20 40 60 140 ns Internal SCLK High Minimum t20 2 8 16 32 ns Internal SCLK Low Minimum t21 2 8 16 32 ns SDOUT Valid Setup Time Minimum t 1 5 15 5 ns 22 SDOUT Valid Hold Time Minimum t 0 0.5 10 28 ns 23 SCLK Last Edge to SYNC Delay Minimum t 0 0.5 9 26 ns 24 BUSY High Width Maximum Warp Mode t28 0.64 0.92 1.47 2.57 μs Normal Mode t28 0.76 1.04 1.59 2.69 μs 500µA I OL TO OUTPUT 1.4V PIN C L 50pF 2V 0.8V 500µA I OH t t DELAY DELAY NOTE 2V 2V IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND 0.8V 0.8V SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 4. Voltage Reference Levels for Timing Figure 3. Load Circuit for Digital Interface Timing, SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. 0 | Page 6 of 28 06023-002 06023-003 AD7622 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Analog Inputs/Outputs rating only; functional operation of the device at these or any 1 IN+ , IN−, REF, REFBUFIN, TEMP, AVDD + 0.3 V to other conditions above those indicated in the operational INGND, REFGND to AGND AGND − 0.3 V section of this specification is not implied. Exposure to absolute Ground Voltage Differences maximum rating conditions for extended periods may affect AGND, DGND, OGND ±0.3 V device reliability. Supply Voltages AVDD, DVDD −0.3 V to +2.7 V OVDD −0.3 V to +3.8 V AVDD to DVDD ±2.8 V AVDD, DVDD to OVDD −3.8 V to +2.8 V Digital Inputs −0.3 V to +5.5 V 2 PDREF, PDBUF ±20 mA 3 Internal Power Dissipation 700 mW 4 Internal Power Dissipation 2.5 W Junction Temperature 125°C Storage Temperature Range –65°C to +125°C 1 See Analog Inputs section. 2 See Voltage Reference Input section. 3 Specification is for the device in free air: 48-Lead LQFP; θ = 91°C/W, θ = 30°C/W. JA JC 4 Specification is for the device in free air: 48-Lead LFCSP; θ = 26°C/W. JA ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 28 AD7622 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 AGND 36 AGND PIN 1 AVDD 2 IDENTIFIER 35 CNVST 3 DGND 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS AD7622 WARP 6 31 RD TOP VIEW NORMAL 7 30 DGND (Not to Scale) SER/PAR 8 29 BUSY 9 D0 28 D15 10 D1 27 D14 11 D2/DIVSCLK[0] 26 D13 D3/DIVSCLK[1] 12 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin 1 No. Mnemonic Type Description 1, 36, AGND P Analog Power Ground. 41, 42 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3 DGND P Digital Power Ground. 4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. 5 OB/2C DI Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI Conversion Mode Selection. When WARP = high and NORMAL = high, this selects wideband warp mode with slightly improved linearity and THD. When WARP = high and NORMAL = low, this selects warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and a minimum conversion rate must be applied to guarantee full specified accuracy. 7 NORMAL DI Conversion Mode Selection. When NORMAL = low and WARP = low, this input selects normal mode where full accuracy is maintained independent of the minimum conversion rate. 8 SER/PAR DI/O Serial/Parallel Selection Input. When SER/PAR = high, the serial interface is selected and some bits of the data bus are used as a serial port; the remaining data bits are high impedance outputs. When SER/PAR = low, the parallel port is selected. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of the interface mode. 11, 12 D[2:3] DI/O When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. or DIVSCLK[0:1] When SER/PAR = high, serial clock division selection. When using serial master read after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. 13 D4 DI/O When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus. or EXT/INT When SER/PAR = high, serial clock source select. This input is used to select the internally generated (master) or external (slave) serial data clock. When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output. When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated by CS, connected to the SCLK input. Rev. 0 | Page 8 of 28 D4/EXT/INT PDBUF D5/INVSYNC PDREF D6/INVSCLK REFBUFIN D7/RDC/SDIN TEMP OGND AVDD OVDD IN+ DVDD AGND DGND AGND D8/SDOUT NC D9/SCLK IN– D10/SYNC REFGND REF D11/RDERROR 06023-004 AD7622 Pin 1 No. Mnemonic Type Description 14 D5 DI/O When SER/PAR = low, this output is used as Bit 5 of the parallel port data output bus. or INVSYNC When SER/PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D6 DI/O When SER/PAR = low, this output is used as Bit 6 of the parallel port data output bus. or INVSCLK When SER/PAR] = high, invert SCLK select. In all serial modes, this input is used to invert the SCLK signal. 16 D7 DI/O When SER/PAR = low, this output is used as bit 7 of the parallel port data output bus. or RDC When SER/PAR = high, read during convert. When using serial master mode (EXT/INT = low), RDC is used to select the read mode. When RDC = high, the previous conversion result is output on SDOUT during conversion and the period of SCLK changes (see the Master Serial Interface section). When RDC = low (read after convert), the current result can be output on SDOUT only when the conversion is complete. or SDIN When SER/PAR = low, serial data in. When using serial slave mode, (EXT/INT = high), SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read sequence. If not used, connect to OVDD or OGND. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (2.5 V or 3 V). 19 DVDD P Digital Power. Nominally at 2.5 V. 20 DGND P Digital Power Ground. 21 D8 DO When SER/PAR = low, this output is used as Bit 8 of the parallel port data output bus. or SDOUT When SER/PAR = high, serial data output. In serial mode, this pin is used as the serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7622 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In master mode, EXT/INT = low, SDOUT is valid on both edges of SCLK. In slave mode, EXT/INT = high: 2 When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. 2 When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge. 22 D9 DI/O When SER/PAR = low, this output is used as Bit 9 of the parallel port data output bus. or SCLK When SER/PAR = high, serial clock. In all serial modes, this pin is used as the serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated, depends on the logic state of the INVSCLK pin. 23 D10 DO When SER/PAR = low, this output is used as Bit 10 of the parallel port data output bus. or SYNC When SER/PAR = high, frame synchronization. In serial master mode (EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid. 24 D11 DO When SER/PAR = low, this output is used as Bit 11 of the parallel port data output bus. or RDERROR When SER/PAR = high, read error. In serial slave mode (EXT/INT = high), this output is used as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. D[12:15] DO 25 to Bit 12 to Bit 15 of the parallel port data output bus. These pins are always outputs, regardless of 28 the interface mode. 29 BUSY DO Busy Output. Transitions high when a conversion is started and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data-ready clock signal. 30 DGND P Digital Power Ground. Rev. 0 | Page 9 of 28 AD7622 Pin 1 No. Mnemonic Type Description 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode. 33 RESET DI Reset Input. When high, resets the AD7622. Current conversion, if any, is aborted. Falling edge of RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the RESET section. If not used, this pin can be tied to DGND. 34 PD DI Power-Down Input. When high, power downs the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 37 REF AI/O Reference Output/Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal reference and buffer. Refer to the Voltage Reference Input section. 38 REFGND AI Reference Input Analog Ground. 39 IN− AI Differential Negative Analog Input. 40 NC No Connect. 43 IN+ AI Differential Positive Analog Input. 45 TEMP AO Temperature Sensor Analog Output. Normally, 278 mV @ 25°C with a temperature coefficient of 1 mV/°C. This pin can be used to measure the temperature of the AD7622. See the Temperature Sensor section. 46 REFBUFIN AI/O Internal Reference Output/Reference Buffer Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical) band gap output on this pin, which needs external decoupling. The internal fixed gain reference buffer uses this to produce 2.048 V on the REF pin. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section. 47 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down and an external reference must been used. 48 PDBUF DI Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. 2 With an SCLK period ≥ (2 × t ). With an SCLK period < (2 × t ), SDOUT is valid on the next rising edge with INVSCLK = low and next falling edge with INVSCLK = high. 32 32 Rev. 0 | Page 10 of 28 AD7622 TERMINOLOGY Integral Nonlinearity Error (INL) Total Harmonic Distortion (THD) Linearity error refers to the deviation of each individual code THD is the ratio of the rms sum of the first five harmonic from a line drawn from negative full scale through positive full components to the rms value of a full-scale input signal and is scale. The point used as negative full scale occurs ½ LSB before expressed in decibels. the first code transition. Positive full scale is defined as a level Signal to (Noise + Distortion) Ratio (SINAD) 1½ LSB beyond the last code transition. The deviation is SINAD is the ratio of the rms value of the actual input signal to measured from the middle of each code to the true straight line. the rms sum of all other spectral components below the Nyquist Differential Nonlinearity Error (DNL) frequency, including harmonics but excluding dc. The value for In an ideal ADC, code transitions are 1 LSB apart. Differential SINAD is expressed in decibels. nonlinearity is the maximum deviation from this ideal value. It Spurious-Free Dynamic Range (SFDR) is often specified in terms of resolution for which no missing The difference, in decibels (dB), between the rms amplitude of codes are guaranteed. the input signal and the peak spurious signal. Gain Error Effective Number of Bits (ENOB) The first transition (from 000…00 to 000…01) should occur for an analog voltage ½ LSB above the nominal negative full scale ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by (−2.0479688 V for the ±2.048 V range). The last transition (from 111…10 to 111…11) should occur for an analog voltage ENOB = [(SINADdB − 1.76)/6.02] 1½ LSB below the nominal full scale (+2.0479531 V for the ±2.048 V range). The gain error is the deviation of the Aperture Delay difference between the actual level of the last transition and the Aperture delay is a measure of the acquisition performance and actual level of the first transition from the difference between is measured from the falling edge of the CNVST input to when the ideal levels. the input signal is held for a conversion. Zero Error Transient Response The zero error is the difference between the ideal midscale The time required for the AD7622 to achieve its rated accuracy input voltage (0 V) and the actual voltage producing the after a full-scale step function is applied to its input. midscale output code. Reference Voltage Temperature Coefficient Dynamic Range It is derived from the typical shift of output voltage at 25°C on a It is the ratio of the rms value of the full scale to the rms noise sample of parts maximum and minimum reference output measured with the inputs shorted together. The value for voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is dynamic range is expressed in decibels. expressed in ppm/°C using Signal-to-Noise Ratio (SNR) V() Max −V (Min) 6 REF REF () TCV ppm/°C = ×10 REF SNR is the ratio of the rms value of the actual input signal to the V() 25°C×() T −T REF MAX MIN rms sum of all other spectral components below the Nyquist where: frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. V (Max) = Maximum V at T , T(25°C), or T REF REF MIN MAX VREF (Min) = Minimum VREF at TMIN, T(25°C), or TMAX VREF (25°C) = VREF at 25°C TMAX = +85°C TMIN = –40°C Rev. 0 | Page 11 of 28 AD7622 TYPICAL PERFORMANCE CHARACTERISTICS 1.50 1.25 POSITIVE INL = +0.43 LSB NEGATIVE INL = –0.49 LSB 1.00 1.00 0.75 0.50 0.50 0.25 0 0 –0.50 –0.25 –0.50 –1.00 –0.75 –1.50 –1.00 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE Figure 6. Integral Nonlinearity vs. Code Figure 9. Differential Nonlinearity vs. Code 250000 200000 σ = 0.5 σ = 0.5 V = 2.5V V = 2.048V REF 171449 REF 196433 200000 160000 150000 120000 100000 80000 50640 37789 50000 27695 36872 40000 00 44 76 00 784 457 00 10 0 0 7FF8 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 7FF8 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 CODES IN HEX CODES IN HEX Figure 7. Histogram of 261,120 Conversions of a DC Input at Figure 10. Histogram of 261,120 Conversions of a DC Input at the Code Center (External Reference) the Code Center (Internal Reference) 2.0486 4 2.0484 3 GAIN ERROR 2.0482 2 2.0480 1 2.0478 0 ZERO ERROR 2.0476 –1 2.0474 –2 2.0472 –3 2.0470 –4 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Typical Reference Voltage Output vs. Temperature (2 Units) Figure 11. Zero Error, Gain Error vs. Temperature Rev. 0 | Page 12 of 28 COUNTS INL (LSB) V (V) REF 06023-007 06023-005 06023-006 ZERO ERROR, GAIN ERROR (LSB) COUNTS DNL (LSB) 06023-010 06023-009 06023-008 AD7622 0 0 f = 2MSPS f = 2MSPS S S –20 –20 f = 20.1kHz f =100.7kHz IN IN SNR = 92dB SNR = 91dB –40 –40 THD = –117dB THD = –100dB SFDR = 103dB SFDR = 101dB –60 –60 SINAD = 92dB SINAD = 90.5dB –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 12. FFT 20 kHz Figure 15. FFT 100 kHz 94 16.0 95 16.0 93 15.6 93 SNR 91 15.2 92 15.5 89 14.8 91 SINAD 87 14.4 SINAD ENOB 85 14.0 90 15.0 ENOB SNR 83 13.6 89 81 13.2 88 14.5 79 12.8 87 77 12.4 75 12.0 86 14.0 1 10 100 1000 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY (kHz) TEMPERATURE (°C) Figure 13. SNR, SINAD, and ENOB vs. Frequency Figure 16. SNR, SINAD, and ENOB vs. Temperature –70 120 –80 120 SFDR 110 –80 –90 110 100 SFDR –90 90 –100 100 80 –100 THD –110 THD 70 90 –110 60 –120 80 50 –120 40 –130 70 –130 SECOND THIRD HARMONIC THIRD 30 HARMONIC SECOND HARMONIC HARMONIC –140 20 –140 60 1 10 100 1000 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY (kHz) TEMPERATURE (°C) Figure 14. THD, Harmonics, and SFDR vs. Frequency Figure 17. THD, Harmonics, and SFDR vs. Temperature Rev. 0 | Page 13 of 28 THD, HARMONICS (dB) SNR, SINAD (dB) AMPLITUDE (dB of Full Scale) 06023-011 SFDR (dB) ENOB (Bits) 06023-013 06023-012 SNR, SINAD (dB) THD, HARMONICS (dB) AMPLITUDE (dB of Full Scale) 06023-014 06023-016 SFDR (dB) 06023-015 ENOB (Bits) AD7622 100k 93.0 AVDD 10k SNR 92.5 1k DVDD 100 SINAD 92.0 OVDD = 3.3V, ALL MODES 10 1 91.5 OVDD = 2.5V, ALL MODES 0.1 PDREF = PDBUF = HIGH 0.01 91.0 –60 –50 –40 –30 –20 –10 0 10 100 1k 10k 100k 1M 10M INPUT LEVEL (dB) SAMPLING RATE (SPS) Figure 18. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 20. Operating Currents vs. Sample Rate 20 16 18 14 OVDD = 2.5V @ 85°C 16 12 OVDD = 2.5V @ 25°C 14 10 DVDD 12 8 OVDD, 3.3V 10 6 OVDD = 3.3V @ 25°C OVDD, 2.5V 8 4 OVDD = 3.3V @ 85°C 6 2 AVDD 4 0 4 50 100 150 200 –55 –35 –15 5 25456585 105 125 C (pF) TEMPERATURE (°C) L Figure 19. Power-Down Operating Currents vs. Temperature Figure 21. Typical Delay vs. Load Capacitance CL Rev. 0 | Page 14 of 28 SNR, SINAD REFERRED TO FULL SCALE (dB) OPERATING CURRENTS (µA) 06023-017 06023-018 OPERATING CURRENTS (µA) t DELAY (ns) 12 06023-020 06023-019 AD7622 APPLICATIONS INFORMATION IN+ AGND SWITCHES CONTROL LSB SW+ MSB 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC REFGND OUTPUT CODE 32,768C 16,384C 4C 2C C C SW– MSB LSB CNVST AGND IN– Figure 22. ADC Simplified Schematic CIRCUIT INFORMATION comparator to become unbalanced. By switching each element The AD7622 is a very fast, low power, single-supply, precise of the capacitor array between REFGND and REF, the comparator 16-bit ADC using successive approximation architecture. The input varies by binary weighted voltage steps (V /2, V /4 REF REF AD7622 features different modes to optimize performances throughVREF/65536). The control logic toggles these switches, according to the applications. In warp mode, the AD7622 is starting with the MSB first, to bring the comparator back into a capable of converting 2,000,000 samples per second (2 MSPS). balanced condition. After the completion of this process, the The AD7622 provides the user with an on-chip track-and-hold, control logic generates the ADC output code and brings BUSY successive approximation ADC that does not exhibit any output low. pipeline or latency, making it ideal for multiple multiplexed MODES OF OPERATION channel applications. The AD7622 features three modes of operations: wideband The AD7622 can operate from a single 2.5 V supply and warp, warp, and normal. Each of these modes is more suitable interface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed for specific applications. in a 48-lead LQFP package or a tiny 48-lead LFCSP package, NORMAL which combines space savings with flexibility and allows the The wideband warp (WARP = high, = high) and AD7622 to be configured as either a serial or a parallel NORMAL warp (WARP = high, = low) modes allow the fastest interface. The AD7622 is pin-to-pin compatible with other conversion rate of up to 2 MSPS. However, in these modes, the PulSAR ADC’s and is a speed upgrade of the AD7677. full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two CONVERTER OPERATION consecutive conversions is longer than 1 ms (for instance after The AD7622 is a successive approximation ADC based on a power-up), the first conversion result should be ignored. These charge redistribution DAC. Figure 22 shows the simplified modes make the AD7622 ideal for applications where both high schematic of the ADC. The capacitive DAC consists of two accuracy and fast sample rates are required. Wideband warp identical arrays of 16 binary weighted capacitors that are mode offers slightly improved linearity and THD over warp mode. connected to the two comparator inputs. Normal mode (NORMAL = low, WARP = low) is the fastest During the acquisition phase, terminals of the array tied to the mode (1.5 MSPS) without any limitation on time between comparator’s input are connected to AGND via SW+ and SW−. conversions. This mode makes the AD7622 ideal for All independent switches are connected to the analog inputs. asynchronous applications, such as data acquisition systems, Therefore, the capacitor arrays are used as sampling capacitors where both high accuracy and fast sample rates are required. and acquire the analog signal on the IN+ and IN− inputs. A conversion phase is initiated once the acquisition phase is complete CNVST and the input goes low. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured at the end of the acquisition phase is applied to the comparator inputs, causing the Rev. 0 | Page 15 of 28 06023-021 AD7622 TRANSFER FUNCTIONS Using the OB/2C digital input, the AD7622 offers two output Table 7. Output Codes and Ideal Input Voltages codings: straight binary and twos complement. The LSB size Digital Output Code (Hex) with V = 2.048 V is 2 × V / 65536 which is 62.5 μV. Refer to REF REF Analog Input Straight Twos Description V = 2.048 V Binary Complement Figure 23 and Table 7 for the ideal transfer characteristic. REF 1 1 FSR −1 LSB +2.047938 V 0xFFFF 0x7FFF FSR − 2 LSB +2.047875 V 0xFFFE 0x7FFE 111...111 Midscale + 1 LSB +62.5 μV 0x8001 0x0001 111...110 111...101 Midscale 0 V 0x8000 0x0000 Midscale − 1 LSB −62.5 μV 0x7FFF 0xFFFF −FSR + 1 LSB −2.047938 V 0x0001 0x8001 2 2 −FSR −2.048 V 0x0000 0x8000 1 This is also the code for overrange analog input (VIN+ − VIN− above +V − V ). REF REFGND 2 This is also the code for underrange analog input (VIN+ − VIN− below 000...010 −V + V ). REF REFGND 000...001 000...000 –FSR + 1 LSB +FSR – 1 LSB –FSR –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 23. ADC Ideal Transfer Function DIGITAL SUPPLY (2.5V) NOTE 5 DIGITAL 10Ω INTERFACE ANALOG SUPPLY SUPPLY (2.5V) (2.5V OR 3.3V) 100nF 10µF 10µF 100nF 100nF 10µF AVDD AGND DGND DVDD OVDD OGND SERIAL PORT REF NOTE 3 SCLK C REF REFBUFIN 10µF 100nF SDOUT REFGND NOTE 4 BUSY NOTE 2 NOTE 7 MICROCONVERTER/ 50Ω MICROPROCESSOR/ 15Ω D CNVST DSP U1 IN+ 50pF ANALOG INPUT + AD7622 C 2.7nF OB/2C C NOTE 1 SER/PAR OVDD WARP NORMAL NOTE 2 CS 15Ω CLOCK U2 IN– ANALOG RD INPUT – NOTE 3 C C 2.7nF 50pF PDREF PDBUF PD RESET NOTE 1 10kΩ NOTE 6 1. SEE ANALOG INPUTS SECTION. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4. A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTION, SEE POWER-UP SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 24. Typical Connection Diagram Rev. 0 | Page 16 of 28 ADC CODE (Straight Binary) 06023-022 06023-023 AD7622 TYPICAL CONNECTION DIAGRAM switches. CIN is typically 12 pF and is mainly the ADC sampling Figure 24 shows a typical connection diagram for the AD7622. capacitor. During the conversion phase, when the switches are Different circuitry shown in this diagram is optional and is opened, the input impedance is limited to CPIN. RIN and CIN discussed in the following sections. make a 1-pole, low-pass filter that has a typical −3 dB cutoff ANALOG INPUTS frequency of 50 MHz, thereby reducing an undesirable aliasing effect and limiting the noise coming from the inputs. Figure 25 shows an equivalent circuit of the input structure of the AD7622. Because the input impedance of the AD7622 is very high, the AD7622 can be directly driven by a low impedance source The two diodes, D1 and D2, provide ESD protection for the without gain error. To further improve the noise filtering achieved analog inputs IN+ and IN−. Care must be taken to ensure that by the AD7622’s analog input circuit, an external 1-pole RC the analog input signal never exceeds the supply rails by more filter between the amplifier’s outputs and the ADC analog than 0.3 V, because this causes the diodes to become forward- inputs can be used, as shown in Figure 24. However, large source biased and to start conducting current. These diodes can handle impedances significantly affect the ac performance, especially a forward-biased current of 100 mA maximum. For instance, the total harmonic distortion (THD). The maximum source these conditions could eventually occur when the input buffer’s impedance depends on the amount of THD that can be U1 or U2 supplies are different from AVDD. In such a case, an tolerated. The THD degrades as a function of the source input buffer with a short-circuit current limitation can be used impedance and the maximum input frequency, as shown in to protect the part. Figure 27. AVDD –60 D 1 R C IN IN –65 IN+ OR IN– R = 500Ω S C PIN D –70 2 AGND –75 Figure 25. AD7622 Simplified Analog Input –80 R = 100Ω S –85 The analog input of the AD7622 is a true differential structure. R = 50Ω S –90 By using this differential input, small signals common to both inputs are rejected, as shown in Figure 26, representing the –95 R = 15Ω S typical CMRR over frequency with internal and external references. –100 75 –105 1 10 100 1000 70 INPUT FREQUENCY (kHz) EXT REF Figure 27. THD vs. Analog Input Frequency and Source Resistance 65 MULTIPLEXED INPUTS INT REF 60 When using the full 2 MSPS throughput in multiplexed applications for a full-scale step, the RC filter, as shown in 55 Figure 24, does not settle in the required acquisition time, t8. These values are chosen to optimize the best SNR performance 50 of the AD7622. To use the full 2 MSPS throughput in multiplexed applications, the RC should be adjusted to satisfy t (which is 8 45 ~ 7 × RC time constant). However, lowering R and C increases 1 10 100 1000 10000 the RC filter bandwidth and allows more noise into the AD7622, FREQUENCY (kHz) which degrades SNR. To preserve the SNR performance in these Figure 26. Analog Input CMRR vs. Frequency applications using the RC filter shown in Figure 24, the AD7622 During the acquisition phase for ac signals, the impedance of should be run with t8 > 280 ns; or approximately 1/(t7 + t8) ~ the analog inputs, IN+ and IN−, can be modeled as a parallel 1.55 MSPS in wideband and warp modes. combination of capacitor C and the network formed by the PIN series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 175 Ω and is a lumped component comprised of some serial resistors and the on resistance of the Rev. 0 | Page 17 of 28 CMRR (dB) 06023-024 06023-025 THD (dB) 06023-026 AD7622 DRIVER AMPLIFIER CHOICE The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs a 10 pF external Although the AD7622 is easy to drive, the driver amplifier compensation capacitor that should have good linearity as an needs to meet the following requirements: NPO ceramic or mica type. Moreover, the use of a noninverting • For multichannel, multiplexed applications, the driver 1 gain arrangement is recommended and helps to obtain the amplifier and the AD7622 analog input circuit must be best signal-to-noise ratio. able to settle for a full-scale step of the capacitor array at an The AD8022 can also be used when a dual version is needed 16-bit level (0.0015%). In the amplifier’s data sheet, settling and a gain of 1 is present. The AD829 is an alternative in at 0.1% to 0.01% is more commonly specified. This could applications where high frequency (above 100 kHz) performance is differ significantly from the settling time at a 16-bit level not required. In applications with a gain of 1, an 82 pF and should be verified prior to driver selection. The compensation capacitor is required. The AD8610 is an option AD8021 op amp, which combines ultralow noise and high when low bias current is needed in low frequency applications. gain bandwidth, meets this settling time requirement even when used with gains up to 13. Refer to Table 8 for some recommended op amps. • The noise generated by the driver amplifier needs to be Table 8. Recommended Driver Amplifiers kept as low as possible to preserve the SNR and transition Amplifier Typical Application noise performance of the AD7622. The noise coming from ADA4841-x Very low noise, low distortion, low power, the driver is filtered by the AD7622 analog input circuit low frequency 1-pole, low-pass filter made by RIN and CIN or by the AD829 Very low noise, low frequency external filter, if one is used. The SNR degradation due AD8021 Very low noise, high frequency to the amplifier is AD8022 Very low noise, high frequency, dual AD8610/AD8620 Low bias current, low frequency, single/dual ⎛ ⎞ ⎜ ⎟ 45 ⎜ ⎟ SNR = 20log Single-to-Differential Driver LOSS ⎜ ⎟ πf πf 2 −3dB 2 −3dB 2 ⎜ ⎟ 45 + () Ne + () Ne ⎜ N+ N− ⎟ For applications using unipolar analog signals, a single-ended- 2 2 ⎝ ⎠ to-differential driver, as shown in Figure 28, allows for a where: differential input into the part. This configuration, when provided an input signal of 0 to VREF, produces a differential f–3dB is the input bandwidth of the AD7622 (50 MHz) or ±VREF with midscale at VREF/2. The 1-pole filter using R = 15 Ω the cutoff frequency of the input RC filter shown in Figure 24 and C = 2.7nF provides a corner frequency of 3.9 MHz. (3.9 MHz), if one is used. N is the noise factor of the amplifier (1 in buffer If the application can tolerate more noise, the AD8139 configuration). differential driver can be used. e and e are the equivalent input voltage noise densities N+ N− of the op amps connected to IN+ and IN−, in nV/√Hz. U1 This approximation can be used when the resistances used AD8021 ANALOG INPUT (UNIPOLAR 0V TO 2.048V) around the amplifier are small. If larger resistances are 10pF used, their noise contributions should also be root-sum 590Ω 15Ω squared. IN+ 590Ω 2.7nF For instance, when using op amps with an equivalent input AD7622 noise density of 2.1 nV/√Hz, such as the AD8021, with a 15Ω U2 IN– REF 5kΩ noise gain of 1 when configured as a buffer, degrades the AD8021 2.7nF SNR by only 0.1 dB when using the RC filter in Figure 24, 5kΩ 10pF 100nF 10µF and by 1.3 dB without it. Figure 28. Single-Ended-to-Differential Driver Circuit • The driver needs to have a THD performance suitable to (Internal Reference Buffer Used) that of the AD7622. Figure 14 gives the THD vs. frequency that the driver should exceed. Rev. 0 | Page 18 of 28 06023-041 AD7622 VOLTAGE REFERENCE INPUT The advantages of directly using the external voltage reference are: The AD7622 allows the choice of either a very low temperature • The SNR and dynamic range improvement (about 1.7 dB) drift internal voltage reference, an external 1.2 V reference that resulting from the use of a reference voltage very close to can be buffered using the internal reference buffer, or an the supply (2.5 V) instead of a typical 2.048 V reference external reference. when the internal reference is used. This is calculated by Unlike many ADCs with internal references, the internal 2.048 ⎛ ⎞ SNR= 20log ⎜ ⎟ reference of the AD7622 provides excellent performance and 2.50 ⎝ ⎠ can be used in almost all applications. • The power savings when the internal reference is powered Internal Reference (PDBUF = Low, PDREF = Low) down (PDREF high). To use the internal reference, the PDREF and PDBUF inputs PDREF and PDBUF power down the internal reference and must both be low. This produces a 1.2 V band gap output on the internal reference buffer, respectively. The input current REFBUFIN, which is amplified by the internal buffer and of PDREF and PDBUF should never exceed 20 mA. This can results in a 2.048 V reference on the REF pin. occur when the driving voltage is above AVDD (for instance, at power-up). In this case, a 125 Ω series resistor is recommended. The internal reference is temperature compensated to 2.048 V ± 10 mV. The reference is trimmed to provide a typical drift of Reference Decoupling 8 ppm/°C. This typical drift characteristic is shown in Figure 8. Whether using an internal or external reference, the AD7622 The output resistance of REFBUFIN is 6.33 kΩ (minimum) voltage reference input (REF) has a dynamic input impedance; when the internal reference is enabled. It is necessary to therefore, it should be driven by a low impedance source with decouple this with a ceramic capacitor greater than 100 nF. efficient decoupling between the REF and REFGND inputs. Therefore, the capacitor provides an RC filter for noise reduction. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF Because the output impedance of REFBUFIN is typically and REFGND with minimum parasitic inductance. A 10 μF 6.33 kΩ, relative humidity (among other industrial contaminates) (X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum can directly affect the drift characteristics of the reference. capacitor) is appropriate when using either the internal Typically, a guard ring is used to reduce the effects of drift reference or one of the recommended reference voltages. under such circumstances. However, because the AD7622 has a fine lead pitch, guarding this node is not practical. Therefore, in The placement of the reference decoupling is also important to these industrial and other types of applications, it is recommended the performance of the AD7622. The decoupling capacitor to use a conformal coating, such as Dow Corning® 1-2577 or should be mounted on the same side as the ADC right at the HumiSeal® 1B73. REF pin with a thick PCB trace. The REFGND should also connect to the reference decoupling capacitor with the shortest distance. External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) For applications that use multiple AD7622 devices, it is more To use an external reference along with the internal buffer, effective to use an external reference with the internal reference PDREF should be high and PDBUF should be low. This powers buffer to buffer the reference voltage. However, because the down the internal reference and allows an external 1.2 V reference buffers are not unity gain, ratiometric, simultaneously reference to be applied to REFBUFIN, producing 2.048 V sampled designs should use an external reference and external (typically) on the REF pin. buffer, such as the AD8031/AD8032; therefore, preserving the same reference level for all converters. External 2.5 V Reference (PDBUF = High, PDREF = High) The voltage reference temperature coefficient (TC) directly To use an external 2.5 V reference directly on the REF pin, impacts full scale; therefore, in applications where full-scale PDREF and PDBUF should both be high. accuracy matters, care must be taken with the TC. For instance, For improved drift performance, an external reference, such as a ±15 ppm/°C TC of the reference changes full scale by ±1 LSB/°C. the AD780, ADR421, ADR431, or ADR441, can be used. Note that V can be increased to AVDD + 0.1 V. Because the REF input range is defined in terms of V , this would essentially REF increase the range to 0 V to 2.8 V with an AVDD = 2.7 V. Rev. 0 | Page 19 of 28 AD7622 A simple power-on reset circuit, as shown in Figure 24, can be Temperature Sensor used to minimize the digital interface. As OVDD powers up, the The TEMP pin measures the temperature of the AD7622. To capacitor is shorted and brings RESET high; it is then charged improve the calibration accuracy over the temperature range, returning RESET to low. However, this circuit only works when the output of the TEMP pin is applied to one of the inputs of powering up the AD7622 because the power-down mode the analog switch (such as, ADG779), and the ADC itself is (PD = high) does not power down any of the supplies and as a used to measure its own temperature. This configuration is result, RESET is low. shown in Figure 29. It should be noted that the digital interface remains active even TEMP ADG779 during the acquisition phase. To reduce the operating digital supply currents even further, drive the digital inputs close to TEMPERATURE ANALOG INPUT IN+ SENSOR (UNIPOLAR) the power rails (that is, OVDD and OGND). AD7622 C AD8021 C CONVERSION CONTROL Figure 29. Use of the Temperature Sensor CNVST The AD7622 is controlled by the input. A falling edge CNVST POWER SUPPLY on is all that is necessary to initiate a conversion. Detailed timing diagrams of the conversion process are shown The AD7622 uses three sets of power supply pins: an analog in Figure 31. Once initiated, it cannot be restarted or aborted, 2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a even by the power-down input, PD, until the conversion is digital input/output interface supply OVDD. The OVDD supply complete. The CNVST signal operates independently of CS and allows direct interface with any logic working between 2.3 V RD signals. and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from t 2 the analog supply, as shown in Figure 24. t 1 Power Sequencing CNVST The AD7622 is independent of power supply sequencing and thus free from supply induced voltage latch-up. In addition, it is BUSY very insensitive to power supply variations over a wide t 4 frequency range, as shown in Figure 30. t 3 t 6 t 5 65.0 MODE ACQUIRE CONVERT ACQUIRE CONVERT 62.5 t t 7 8 60.0 EXT REF Figure 31. Basic Conversion Timing 57.5 For optimal performance, the rising edge of CNVST should not 55.0 occur after the maximum CNVST low time, t , or until the end 1 INT REF 52.5 of conversion. 50.0 Although CNVST is a digital signal, it should be designed with 47.5 special care with fast, clean edges and levels with minimum overshoot and undershoot or ringing. 45.0 1 10 100 1000 10000 FREQUENCY (kHz) The CNVST trace should be shielded with ground and a low Figure 30. PSRR vs. Frequency value serial resistor (for example, 50 Ω) termination should be added close to the output of the component that drives this line. Power-Up In addition, a 50 pF capacitor is recommended to further reduce At power-up, or when returning to operational mode from the the effects of overshoot and undershoot as shown in Figure 24. power-down mode (PD = high), the AD7622 engages an initialization process. During this time, the first 128 conversions For applications where SNR is critical, the CNVST signal should should be ignored or the RESET input could be pulsed to have very low jitter. This can be achieved by using a dedicated engage a faster initialization process. Refer to the Digital oscillator for generation, or by clocking with a CNVST CNVST Interface section for RESET and timing details. high frequency, low jitter clock, as shown in Figure 24. Rev. 0 | Page 20 of 28 PSRR (dB) 06023-029 06023-027 06023-030 AD7622 INTERFACES CS = RD = 0 DIGITAL INTERFACE t 1 CNVST The AD7622 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The t 10 serial interface is multiplexed on the parallel data bus. The AD7622 BUSY digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic t 4 t 3 with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic t 11 high output voltage. In most applications, the OVDD supply pin DATA PREVIOUS CONVERSION DATA NEW DATA of the AD7622 is connected to the host system interface 2.5 V BUS 2C or 3.3 V digital supply. By using the OB/ input pin, either Figure 33. Master Parallel Data Timing for Reading (Continuous Read) twos complement or straight binary coding can be used. Slave Parallel Interface CS RD The two signals and control the interface. When at least In slave parallel reading mode, the data can be read either after one of these signals is high, the interface outputs are in high each conversion, which is during the next acquisition phase, or impedance. Usually, CS allows the selection of each AD7622 in during the following conversion, as shown in Figure 34 and multicircuit applications and is held low in a single AD7622 Figure 35, respectively. When the data is read during the design. RD is generally used to enable the conversion result on conversion, it is recommended that it is read-only during the the data bus. first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface RESET and the most critical analog conversion circuitry. The RESET input is used to reset the AD7622 and generate a fast initialization. A rising edge on RESET aborts the current CS conversion (if any) and tristates the data bus. The falling edge of RESET clears the data bus and engages the initialization process indicated by pulsing BUSY high. Conversions can take place RD after the falling edge of BUSY. Refer to Figure 32 for the RESET timing details. t 9 BUSY RESET CNVST DATA CURRENT BUS CONVERSION DATA t t 12 13 Figure 34. Slave Parallel Data Timing for Reading (Read After Convert) BUSY t t t 38 39 8 CS = 0 Figure 32. RESET Timing CNVST, t 1 RD PARALLEL INTERFACE The AD7622 is configured to use the parallel interface when PAR SER/ is held low. BUSY t 4 Master Parallel Interface t 3 Data can be continuously read by tying CS and RD low, thus requiring minimal microprocessor connections. However, in DATA PREVIOUS this mode, the data bus is always driven and cannot be used in BUS CONVERSION shared bus applications, unless the device is held in RESET. t t 12 13 Figure 33 details the timing for this mode. Figure 35. Slave Parallel Data Timing for Reading (Read During Convert) Rev. 0 | Page 21 of 28 06023-031 04761-033 06023-042 04761-032 AD7622 8-Bit Interface (Master or Slave) MASTER SERIAL INTERFACE The BYTESWAP pin allows a glueless interface to an 8-bit bus. Internal Clock As shown in Figure 36, when BYTESWAP is low, the LSB byte is The AD7622 is configured to generate and provide the serial output on D[7:0] and the MSB is output on D[15:8]. When data clock SCLK when the EXT/ pin = low. The AD7622 INT BYTESWAP is high, the LSB and MSB bytes are swapped, and also generates a SYNC signal to indicate to the host when the the LSB is output on D[15:8] and the MSB is output on D[7:0]. serial data is valid. The serial clock SCLK and the SYNC signal By connecting BYTESWAP to an address line, the 16-bit data can be inverted. Depending on the state of the read during can be read in two bytes on either D[15:8] or D[7:0]. This convert input, RDC/SDIN, the data can be read after each interface can be used in both master and slave parallel reading conversion or during the following conversion. Figure 37 and modes. Figure 38 show detailed timing diagrams of these two modes. Usually, because the AD7622 is used with a fast throughput, the CS master read during conversion mode, RDC/SDIN = high, is the most recommended serial mode. In this mode, the serial clock RD and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion BYTESWAP decisions. In this mode, the SCLK period changes because the LSBs require more time to settle and the SCLK is derived from the HI-Z HI-Z SAR conversion cycle. PINS D[15:8] HIGH BYTE LOW BYTE t t t 12 12 13 In read after conversion mode, RDC/SDIN = low, it should be HI-Z HI-Z PINS D[7:0] LOW BYTE HIGH BYTE noted that unlike other modes, the BUSY signal returns low after the 16 data bits are pulsed out and not at the end of the Figure 36. 8-Bit and 16-Bit Parallel Interface conversion phase, resulting in a longer BUSY width. As a result, SERIAL INTERFACE the maximum throughput cannot be achieved in this mode. The AD7622 is configured to use the serial interface when In addition, in read after convert mode, the SCLK frequency SER/ = high. The AD7622 outputs 16 bits of data, MSB PAR can be slowed down to accommodate different hosts using the first, on the SDOUT pin. This data is synchronized with the DIVSCLK[1:0] inputs. Refer to Table 4 for the SCLK timing 16 clock pulses provided on the SCLK pin. The output data is details when using these inputs. valid on both the rising and falling edge of the data clock. Rev. 0 | Page 22 of 28 06023-034 AD7622 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 3 CNVST BUSY t 28 t 30 t 29 t 25 SYNC t t 18 14 t 19 t t t 24 20 21 t 26 1 2 3 14 15 16 SCLK t 15 t 27 SDOUT D15 D14 D2 D1 D0 X t t 16 23 t 22 Figure 37. Master Serial Data Timing for Reading (Read After Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 14 19 t t 20 21 t 24 t 26 t 15 SCLK 12 3 14 15 16 t 18 t 27 SDOUT X D15 D14 D2 D1 D0 t t 16 23 t 22 Figure 38. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 23 of 28 06023-036 06023-035 AD7622 SLAVE SERIAL INTERFACE External Clock Finally, in this mode only, the AD7622 provides a daisy-chain feature using the RDC/SDIN pin for cascading multiple converters The AD7622 is configured to accept an externally supplied together. This feature is useful for reducing component count serial data clock on the SCLK pin when the EXT/ pin is INT and wiring connections when desired, as, for instance, in held high. In this mode, several methods can be used to read isolated multiconverter applications. the data. The external serial clock is gated by CS. When CS and are both low, the data can be read after each conversion or RD An example of the concatenation of two devices is shown in during the following conversion. The external clock can be Figure 39. Simultaneous sampling is possible by using a either a continuous or a discontinuous clock. A discontinuous common CNVST signal. It should be noted that the RDC/SDIN clock can be either normally high or normally low when input is latched on the edge of SCLK opposite to the one used to inactive. Figure 40 and Figure 41 show the detailed timing shift out the data on SDOUT. Therefore, the MSB of the diagrams of these methods. upstream converter just follows the LSB of the downstream converter on the next SCLK cycle. While the AD7622 is performing a bit decision, it is important BUSY that voltage transients be avoided on digital input/output pins OUT or degradation of the conversion result could occur. This is particularly important during the second half of the conversion BUSY BUSY phase because the AD7622 provides error correction circuitry AD7622 AD7622 #2 #1 that can correct for an improper bit decision made during (UPSTREAM) (DOWNSTREAM) DATA the first half of the conversion phase. For this reason, it is SDOUT RDC/SDIN SDOUT RDC/SDIN OUT recommended that when an external clock is being provided, CNVST CNVST a discontinuous clock is toggled only when BUSY is low or, CS CS more importantly, that it does not transition during the latter SCLK SCLK half of BUSY high. External Discontinuous Clock Data Read After Conversion SCLK IN CS IN Though the maximum throughput cannot be achieved using CNVST IN this mode, it is the most recommended of the serial slave Figure 39. Two AD7622 Devices in a Daisy-Chain Configuration modes. Figure 40 shows the detailed timing diagrams of this External Clock Data Read During Previous Conversion method. After a conversion is complete, indicated by BUSY returning low, the conversion result can be read while both CS Figure 41 shows the detailed timing diagrams of this method. and are low. Data is shifted out MSB first with 16 clock RD During a conversion, while CS and RD are both low, the result pulses and is valid on the rising and falling edges of the clock. of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses and is valid on both the rising Among the advantages of this method is the fact that conversion and falling edge of the clock. The 16 bits have to be read before performance is not degraded because there are no voltage the current conversion is complete; otherwise, RDERROR is transients on the digital interface during the conversion process. pulsed high and can be used to interrupt the host interface to Another advantage is the ability to read the data at any speed up prevent incomplete data reading. There is no daisy-chain to 80 MHz, which accommodates both the slow digital host feature in this mode, and the RDC/SDIN input should always interface and the fast serial reading. be tied either high or low. It is also possible to begin to read data after conversion and To reduce performance degradation due to digital activity, a fast continue to read the last bits after a new conversion is initiated. discontinuous clock (at least 60 MHz when normal mode is In this reading mode, it is recommended to pause digital used, or 80 MHz when warp mode is used) is recommended to activity just prior to initiating a conversion (SCLK should be ensure that all the bits are read during the first half of the SAR held high or low). Once the conversion has begun, the reading conversion phase. can continue. In addition, in this mode, the use of a slower clock speed can be used to read the data because the total If the maximum throughput is not used, thus allowing more reading time is the acquisition time, t8 + half of the conversion acquisition time, then the use of a slower clock speed can be time, t7 (t8 + ½ × t7, see the External Clock Data Read During used to read the data. Previous Conversion section). Rev. 0 | Page 24 of 28 06023-037 AD7622 RD = 0 EXT/INT = 1 INVSCLK = 0 CS BUSY t 35 t t 36 37 SCLK 12 3 14 15 16 17 18 t 31 t 32 X D15 D14 D13 D1 X15 X14 SDOUT D0 t 16 t 34 SDIN X15 X14 X13 X1 X0 Y15 Y14 t 33 Figure 40. Slave Serial Data Timing for Reading (Read After Convert) EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t 3 t 35 t t 36 37 SCLK 12 3 14 15 16 t 31 t 32 SDOUT X D15 D14 D13 D1 D0 t 16 Figure 41. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 25 of 28 06023-039 06023-038 AD7622 SPI Interface (ADSP-219x) MICROPROCESSOR INTERFACING Figure 42 shows an interface diagram between the AD7622 and The AD7622 is ideally suited for traditional dc measurement an SPI-equipped DSP, the ADSP-219x. To accommodate the applications supporting a microprocessor, and ac signal processing slower speed of the DSP, the AD7622 acts as a slave device and applications interfacing to a digital signal processor. The data must be read after conversion. This mode also allows the AD7622 is designed to interface with a parallel 8-bit or 16-bit daisy-chain feature. The convert command can be initiated in wide interface or with a general-purpose serial port or I/O ports response to an internal timer interrupt. The 16-bit output data on a microcontroller. A variety of external buffers can be used are read with three SPI byte access. The reading process can be with the AD7622 to prevent digital noise from coupling into the initiated in response to the end-of-conversion signal (BUSY ADC. The SPI Interface (ADSP-219x) section illustrates the use going low) using an interrupt line of the DSP. The serial peripheral of the AD7622 with the ADSP-219x SPI-equipped DSP. interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock phase bit (CPHA) = 1, and the SPI interrupt enable (TIMOD) = 00 by writing to the SPI control register (SPICLTx). It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbps, allowing it to read an ADC result in less than 1 μs. When a higher sampling rate is desired, it is recommended to use one of the parallel interface modes. DVDD 1 AD7622 ADSP-219x MODE0 BUSY PFx MODE1 CS SPIxSEL (PFx) EXT/INT SDOUT MISOx SCLK SCKx RD CNVST PFx OR TFSx INVSCLK 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 42. Interfacing the AD7622 to ADSP-219x Rev. 0 | Page 26 of 28 06023-040 AD7622 APPLICATION HINTS LAYOUT The DVDD supply of the AD7622 can be either a separate supply or come from the analog supply, AVDD, or from the While the AD7622 has very good immunity to noise on the digital interface supply, OVDD. When the system digital supply power supplies, exercise care with the grounding layout. To is noisy, or fast switching digital signals are present, and no facilitate the use of ground planes that can be easily separated, separate supply is available, it is recommended to connect the design the printed circuit board that houses the AD7622 so that DVDD digital supply to the analog supply AVDD through an the analog and digital sections are separated and confined to RC filter, and to connect the system supply to the interface certain areas of the board. Digital and analog ground planes digital supply OVDD and the remaining digital circuitry. Refer should be joined in only one place, preferably underneath the to Figure 24 for an example of this configuration. When DVDD AD7622, or as close as possible to the AD7622. If the AD7622 is is powered from the system supply, it is useful to insert a bead in a system where multiple devices require analog-to-digital to further reduce high frequency spikes. ground connections, the connections should still be made at one point only, a star ground point, established as close as The AD7622 has four different ground pins: REFGND, AGND, possible to the AD7622. DGND, and OGND. REFGND senses the reference voltage and, because it carries pulsed currents, should have a low impedance To prevent coupling noise onto the die, avoid radiating noise, return to the reference. AGND is the ground to which most and reduce feedthrough: internal ADC analog signals are referenced; it must be connected • Do not run digital lines under the device. with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the • Run the analog ground plane under the AD7622. configuration. OGND is connected to the digital system ground. • Shield fast switching signals, like CNVST or clocks, with The layout of the decoupling of the reference voltage is digital ground to avoid radiating noise to other sections of important. To minimize parasitic inductances, place the the board, and never run them near analog signal paths. decoupling capacitor close to the ADC and connect it with short, thick traces. • Avoid crossover of digital and analog signals. EVALUATING THE AD7622 PERFORMANCE • Run traces on different but close layers of the board, at right A recommended layout for the AD7622 is outlined in the angles to each other, to reduce the effect of feedthrough documentation of the EVAL-AD7622-CB evaluation board for through the board. the AD7622. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and The power supply lines to the AD7622 should use as large a software for controlling the board from a PC via the EVAL- trace as possible to provide low impedance paths and reduce the CONTROL BRD3. effect of glitches on the power supply lines. Good decoupling is also important to lower the impedance of the supplies presented to the AD7622, and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, and OVDD. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. Rev. 0 | Page 27 of 28 PAD AD7622 OUTLINE DIMENSIONS 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 0.40 25 12 13 24 0.30 0.25 MIN 5.50 REF PADDLE CONNECTED TO AGND. 0.80 MAX 1.00 THIS CONNECTION IS NOT 12° MAX 0.65 TYP 0.85 REQUIRED TO MEET THE 0.05 MAX ELECTRICAL PERFORMANCES. 0.80 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 43. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters 0.75 9.00 1.60 0.60 BSC SQ MAX 0.45 37 48 1 36 PIN 1 7.00 TOP VIEW BSC SQ 1.45 (PINS DOWN) 0.20 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 MAX PLANE 0.27 VIEW A COPLANARITY 0.50 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 44. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7622BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7622BCPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7622BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 1 AD7622BSTZRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 2 EVAL-AD7622CB Evaluation Board 3 EVAL-CONTROL BRD3 Controller Board 1 Z = Pb-free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06023–0–6/06(0) TTTT Rev. 0 | Page 28 of 28