ANALOG DEVICES AD7621

® 16-Bit, 2 LSB INL, 3 MSPS PulSAR ADC AD7621 FEATURES FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND DVDD DGND Throughput 3 MSPS (wideband warp and warp mode) AGND OVDD 2 MSPS (normal mode) AD7621 AVDD OGND 1.25 MSPS (impulse mode) REF REF AMP SERIAL 2.048 V internal reference PORT 16 IN+ Differential input range: ±V (V up to 2.5 V) SWITCHED REF REF D[15:0] CAP DAC IN– SER/PAR INL: ±2 LSB maximum, ±1 LSB typical PARALLEL INTERFACE BUSY 16-bit resolution with no missing codes PDREF RD CLOCK SINAD: 89 dB typical @ 100 kHz PDBUF CS THD: −101 dB typical @ 100 kHz CONTROL LOGIC AND PD OB/2C CALIBRATION CIRCUITRY No pipeline delay (SAR architecture) RESET BYTESWAP Parallel (16- or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface WARP CNVST IMPULSE SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible 2.5 V single-supply operation Figure 1. Power dissipation: 65 mW typical @ 3 MSPS Table 1. PulSAR Selection 48-lead LQFP and 48-lead LFCSP_VQ packages 800 to Speed upgrade of the AD7677 Type/kSPS 100 to 250 500 to 570 1000 >1000 Pseudo AD7651 AD7650/52 AD7653 APPLICATIONS Differential AD7660/61 AD7664/66 AD7667 Medical instruments True Bipolar AD7663 AD7665 AD7671 High speed data acquisition True Digital signal processing Differential AD7675 AD7676 AD7677 AD7621 Communications 18-Bit AD7678 AD7679 AD7674 AD7641 Instrumentation Multichannel/ Spectrum analysis Simultaneous AD7654 AD7655 ATE GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1. Fast Throughput. The AD7621 is a 16-bit, 3 MSPS, charge redistribution SAR, The AD7621 is a 3 MSPS, charge redistribution, fully differential analog-to-digital converter (ADC) that 16-bit SAR ADC. operates from a single 2.5 V power supply. It contains a high speed 16-bit sampling ADC, an internal conversion clock, an 2. Superior Linearity. internal reference (and buffer), error correction circuits, and The AD7621 has no missing 16-bit code. both serial and parallel system interface ports. It features two 3. Internal Reference. very high sampling rate modes (wideband warp and warp), a The AD7621 has a 2.048 V internal reference with a fast mode (normal) for asynchronous rate applications, and a typical drift of ±7 ppm/°C. reduced power mode (impulse) for low power applications 4. Single-Supply Operation. where the power is scaled with the throughput. Operation is The AD7621 operates from a 2.5 V single supply and specified from −40°C to +85°C. typically dissipates 65 mW. In impulse mode, its power dissipation decreases with the throughput. 5. Serial or Parallel Interface. Versatile parallel (16- or 8-bit bus) or 2-wire serial interface arrangement compatible with 2.5 V, 3.3 V, or 5 V logic. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved. 04565-001 AD7621 TABLE OF CONTENTS Specifications..................................................................................... 3 Voltage Reference Input ............................................................ 18 Timing Specifications....................................................................... 5 Power Supply............................................................................... 19 Serial Clock Timing Specifications ............................................ 6 Power Dissipation vs. Throughput .......................................... 20 Absolute Maximum Ratings............................................................ 7 Conversion Control ................................................................... 20 ESD Caution.................................................................................. 7 Interfaces.......................................................................................... 21 Pin Configuration and Function Descriptions............................. 8 Digital Interface.......................................................................... 21 Terminology .................................................................................... 11 Parallel Interface......................................................................... 21 Typical Performance Characteristics ........................................... 12 Serial Interface ............................................................................ 22 Theory of Operation ...................................................................... 15 Master Serial Interface............................................................... 22 Circuit Information.................................................................... 15 Slave Serial Interface .................................................................. 24 Converter Operation.................................................................. 15 Microprocessor Interfacing....................................................... 26 Modes of Operation ................................................................... 15 Application ...................................................................................... 27 Transfer Functions...................................................................... 16 Layout .......................................................................................... 27 Typical Connection Diagram ................................................... 17 Evaluating the AD7621 Performance ...................................... 27 Analog Inputs.............................................................................. 17 Outline Dimensions ....................................................................... 28 Driver Amplifier Choice............................................................ 17 Ordering Guide .......................................................................... 29 REVISION HISTORY 5/05 — Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7621 SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range V + − V − −V V V IN IN REF REF 1 Operating Input Voltage VIN+, VIN− to AGND −0.1 AVDD V Analog Input CMRR fIN = 100 kHz 55 dB Input Current 3 MSPS throughput 25 μA 2 Input Impedance THROUGHPUT SPEED Complete Cycle Wideband warp, warp modes 333 ns Throughput Rate Wideband warp, warp modes 0.001 3 MSPS Time Between Conversions Wideband warp, warp modes 1 ms Complete Cycle Normal mode 500 ns Throughput Rate Normal mode 0 2 MSPS Complete Cycle Impulse mode 800 ns Throughput Rate Impulse mode 0 1.25 MSPS DC ACCURACY All modes 3 4 Integral Linearity Error VREF = 2.048 V, PDREF = high −2 ±1 +2 LSB No Missing Codes V = 2.048 V, PDREF = high 16 Bits REF Differential Linearity Error V = 2.048 V, PDREF = high −1 +2 LSB REF Transition Noise V = 2.5 V 0.69 LSB REF Transition Noise VREF = 2.048 V 0.82 LSB 5 Zero Error, TMIN to TMAX −30 +30 LSB Zero Error Temperature Drift ±1 ppm/°C 5 Gain Error, T to T −0.38 +0.38 % of FSR MIN MAX Gain Error Temperature Drift ±2 ppm/°C Power Supply Sensitivity AVDD = 2.5 V ± 5% ±3 LSB AC ACCURACY 6 Dynamic Range f = 20 kHz, V = 2.5 V 90.5 dB IN REF Signal-to-Noise fIN = 20 kHz, VREF = 2.5 V 88 90 dB fIN = 20 kHz, VREF = 2.048 V 86 88 dB fIN = 100 kHz, VREF = 2.5 V 89.2 dB Spurious-Free Dynamic Range f = 20 kHz 103 dB IN f = 100 kHz 101 dB IN Total Harmonic Distortion f = 20 kHz –102 dB IN fIN = 100 kHz −100 dB Signal-to-(Noise + Distortion) fIN = 20 kHz, VREF = 2.5 V 87.5 89.8 dB fIN = 20 kHz, VREF = 2.048 V 87.5 dB f = 100 kHz, V = 2.5 V 89 dB IN REF –3 dB Input Bandwidth 50 MHz SAMPLING DYNAMICS Aperture Delay 1 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 50 ns INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 2.038 2.048 2.058 V Temperature Drift –40°C to +85°C ±7 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V Rev. 0 | Page 3 of 32 AD7621 Parameter Conditions Min Typ Max Unit Turn-On Settling Time CREF = 10 μF 5 ms REFBUFIN Output Voltage REFBUFIN @ 25°C 1.2 V REFBUFIN Output Resistance 6.33 kΩ EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 1.8 2.048 AVDD V Current Drain 3 MSPS throughput 250 μA REFERENCE BUFFER PDREF = high, PDBUF = low REFBUFIN Input Voltage Range 1.05 1.2 1.30 V TEMPERATURE PIN Voltage Output @ 25°C 273 mV Temperature Sensitivity 0.85 mV/°C Output Resistance 4.7 kΩ DIGITAL INPUTS Logic Levels V –0.3 +0.6 V IL V 1.7 5.25 V IH I –1 +1 μA IL IIH –1 +1 μA DIGITAL OUTPUTS 7 Data Format 8 Pipeline Delay VOL ISINK = 500 μA 0.4 V VOH ISOURCE = –500 μA OVDD − 0.3 V POWER SUPPLIES Specified Performance AVDD 2.37 2.5 2.63 V DVDD 2.37 2.5 2.63 V 9 OVDD 2.30 3.6 V 10 Operating Current 3 MSPS throughput 11 AVDD With internal reference 25.2 mA DVDD 3.6 mA OVDD 1 mA 11 Power Dissipation 10 With Internal Reference 3 MSPS throughput 70 86 mW 10 Without Internal Reference 3 MSPS throughput 65 80 mW 12 With Internal Reference 1.25 MSPS throughput 42 55 mW 12 Without Internal Reference 1.25 MSPS throughput 37 50 mW 13 In Power-Down Mode PD = high 600 μW 14 TEMPERATURE RANGE Specified Performance T to T –40 +85 °C MIN MAX 1 When using an external reference. With the internal reference, the input range is −0.1 V to V . REF 2 See the Analog Inputs section. 3 Linearity is tested using endpoints, not best fit. Tested with an external reference at 2.048 V. 4 LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV. 5 See the Voltage Reference Input section. These specifications do not include the error contribution from the external reference. 6 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 7 Parallel or serial 16-bit. 8 Conversion results are available immediately after completed conversion. 9 See the Absolute Maximum Ratings section. 10 In warp mode. Tested in parallel reading mode. 11 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high. 12 In impulse mode. Tested in parallel reading mode. 13 With all digital inputs forced to OVDD. 14 Consult factory for extended temperature range. Rev. 0 | Page 4 of 32 AD7621 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (Refer to Figure 31 and Figure 32) 1 Convert Pulse Width t1 15 70 ns 2 3 Time Between Conversions (Warp Mode/Normal Mode/Impulse Mode) t 333/500/800 ns 2 CNVST Low to BUSY High Delay t 23 ns 3 BUSY High All Modes (Except Master Serial Read After Convert) t 283/430/560 ns 4 Aperture Delay t5 1 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t 283/430/560 ns 7 Acquisition Time (Warp Mode/Normal Mode/Impulse Mode) t 50/70/50 ns 8 RESET Pulse Width t 15 ns 9 4 RESET Low to BUSY High Delay t38 10 ns 4 BUSY High Time from RESET Low t39 600 ns PARALLEL INTERFACE MODES (Refer to Figure 33 and Figure 35) CNVST Low to DATA Valid Delay t10 283/430/560 ns (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY Low Delay t 2 ns 11 Bus Access Request to DATA Valid t 20 ns 12 Bus Relinquish Time t13 2 15 ns 5 MASTER SERIAL INTERFACE MODES (Refer to Figure 37 and Figure 38) CS Low to SYNC Valid Delay t14 10 ns 5 CS Low to Internal SCLK Valid Delay t15 10 ns CS Low to SDOUT Delay t 10 ns 16 CNVST Low to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) t 12/137/263 ns 17 SYNC Asserted to SCLK First Edge Delay t18 0.5 ns 6 Internal SCLK Period t19 8 12 ns 6 Internal SCLK High t20 2 ns 6 Internal SCLK Low t 3 ns 21 6 SDOUT Valid Setup Time t 1 ns 22 6 SDOUT Valid Hold Time t23 0 ns 6 SCLK Last Edge to SYNC Delay t24 0 ns CS High to SYNC HI-Z t25 10 ns CS High to Internal SCLK HI-Z t 10 ns 26 CS High to SDOUT HI-Z t 10 ns 27 6 BUSY High in Master Serial Read after Convert t See Table 4 28 CNVST Low to SYNC Asserted Delay (All Modes) t29 275/400/500 ns SYNC Deasserted to BUSY Low Delay t30 13 ns Rev. 0 | Page 5 of 32 AD7621 Parameter Symbol Min Typ Max Unit 5 SLAVE SERIAL INTERFACE MODES (Refer to Figure 40 and Figure 41) External SCLK Setup Time t 5 ns 31 External SCLK Active Edge to SDOUT Delay t32 1 8 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t 12.5 ns 35 External SCLK High t 5 ns 36 External SCLK Low t 5 ns 37 1 See the Conversion Control section. 2 All timings for wideband warp mode are the same as warp mode. 3 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. 4 See the Digital Interface, and RESET sections. 5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications. SERIAL CLOCK TIMING SPECIFICATIONS Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SCLK First Edge Delay Minimum t18 0.5 3 3 3 ns Internal SCLK Period Minimum t 8 16 32 64 ns 19 Internal SCLK Period Maximum t 12 25 50 100 ns 19 Internal SCLK High Minimum t 2 6 15 31 ns 20 Internal SCLK Low Minimum t21 3 7 16 32 ns SDOUT Valid Setup Time Minimum t22 1 5 5 5 ns SDOUT Valid Hold Time Minimum t23 0 0.5 10 28 ns SCLK Last Edge to SYNC Delay Minimum t 0 0.5 9 26 ns 24 BUSY High Width Maximum (Wideband and Warp Modes) t 0.500 0.720 1.160 2.040 μs 28 BUSY High Width Maximum (Normal Mode) t 0.650 0.870 1.310 2.190 μs 28 BUSY High Width Maximum (Impulse Mode) t28 0.780 1.000 1.440 2.320 μs 500μAI 2V OL 0.8V t t DELAY DELAY TO OUTPUT 1.4V 2V 2V PIN C L 0.8V 0.8V 50pF Figure 3. Voltage Reference Levels for Timing 500μAI OH NOTE IN SERIAL INTERFACE MODES, THE SYNC, SCLK AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD. C OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. 0 | Page 6 of 32 04565-002 05665-003 AD7621 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Analog Inputs/Outputs rating only; functional operation of the device at these or any 1 IN+ , IN−, REF, REFBUFIN, TEMP, AVDD + 0.3 V to other conditions above those indicated in the operational INGND, REFGND to AGND AGND − 0.3 V section of this specification is not implied. Exposure to absolute Ground Voltage Differences maximum rating conditions for extended periods may affect AGND, DGND, OGND ±0.3 V device reliability. Supply Voltages AVDD, DVDD –0.3 V to +2.7 V ESD CAUTION OVDD –0.3 V to +3.8 V AVDD to DVDD ±2.8 V ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge AVDD to OVDD +2.8 V to −3.8 V 2 without detection. Although this product features OVDD to DVDD ≤ +0.3 V if DVDD < 2.3 V patented or proprietary protection circuitry, damage may Digital Inputs −0.3 V to +5.5 V occur on devices subjected to high energy ESD. 3 PDREF, PDBUF ±20 mA Therefore, proper ESD precautions should be taken to 4 Internal Power Dissipation 700 mW avoid performance degradation or loss of functionality. 5 Internal Power Dissipation 2.5 W Junction Temperature 125°C Storage Temperature Range –65°C to +125°C 1 See the Analog Inputs section. 2 See the Power Supply section. 3 See the Voltage Reference Input section. 4 Specification is for the device in free air: 48-Lead LQFP; θ = 91°C/W, JA θJC = 30°C/W. 5 Specification is for the device in free air: 48-Lead LFCSP; θ = 26°C/W. JA Rev. 0 | Page 7 of 32 AD7621 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 AGND 36 AGND PIN 1 AVDD 2 IDENTIFIER CNVST 35 NC 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS AD7621 WARP 6 31 RD TOP VIEW IMPULSE 7 30 DGND (Not to Scale) SER/PAR 8 29 BUSY 9 D0 28 D15 10 D1 27 D14 11 D2/DIVSCLK[0] 26 D13 D3/DIVSCLK[1] 12 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT Figure 4. Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 41, 42 AGND P Analog Power Ground Pin. 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3, 40 NC No Connect. 4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. 5 OB/2C DI Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI Conversion Mode Selection. When WARP = high and IMPULSE = high, this selects wideband mode with slightly improved linearity and THD. When WARP = high and IMPULSE = low, this selects warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When WARP = low and IMPULSE = low, this input selects normal mode where full accuracy is maintained independent of the minimum conversion rate. 7 IMPULSE DI Conversion Mode Selection. When IMPULSE = high and WARP = low, this input selects impulse mode, a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When high, the serial interface is selected and some bits of the data bus are used as a serial port; the remaining data bits are high impedance outputs. When SER/PAR = low, the parallel port is selected. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. 11, 12 D[2:3] DI/O When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. or When SER/PAR = high, serial clock division selection. When using serial master read after convert DIVSCLK[0:1] mode (EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. 13 D4 DI/O When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus. or EXT/INT When SER/PAR = high, serial clock source select. This input is used to select the internally generated (master ) or external (slave) serial data clock. When EXT/INT = low: master mode. The internal serial clock is selected on SCLK output. When EXT/INT = high: slave mode. The output data is synchronized to an external clock signal, gated by CS, connected to the SCLK input. Rev. 0 | Page 8 of 32 D4/EXT/INT PDBUF D5/INVSYNC PDREF D6/INVSCLK REFBUFIN D7/RDC/SDIN TEMP OGND AVDD OVDD IN+ DVDD AGND DGND AGND D8/SDOUT NC D9/SCLK IN– D10/SYNC REFGND REF D11/RDERROR 04565-004 AD7621 1 Pin No. Mnemonic Type Description 14 D5 DI/O When SER/PAR = low this output is used as Bit 5 of the parallel port data output bus. or INVSYNC When SER/PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D6 DI/O PAR When SER/ = low this output is used as Bit 6 of the parallel port data output bus. or INVSCLK Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal. 16 D7 DI/O Bit 7 of the Parallel Port Data Output Bus. or RDC When SER/PAR = high, read during convert. When using Serial Master mode (EXT/INT = low), RDC is used to select the read mode. When RDC = high, the previous conversion result is read during current conversion and the period of SCLK changes (see the Master Serial Interface section). When RDC = low (read after convert), the current result is read after conversion. or SDIN Serial Data In. When using serial slave mode, (EXT/INT = high), SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read sequence. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (2.5 V or 3 V). 19 DVDD P Digital Power. Nominally at 2.5 V. 20 DGND P Digital Power Ground. 21 D8 DO When SER/PAR = low this output is used as Bit 8 of the parallel port data output bus. or SDOUT When SER/PAR = high, serial data output. In serial mode, this pin is used as the serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7621 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In master mode (EXT/INT = low). SDOUT is valid on both edges of SCLK. In slave mode (EXT/INT = high): When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge. 22 D9 DI/O Parallel Port Data Output Bus Bit 9. When SER/PAR = low, this output is used as Bit 9 of the parallel port data output bus. or SCLK Serial Clock. When SER/PAR = high, serial clock. In all serial modes, this pin is used as the serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D10 DO When SER/PAR = low, this output is used as Bit 10 of the parallel port data output bus. or SYNC When SER/PAR = high, frame synchronization. In serial master mode (EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid. 24 D11 DO Parallel Port Data Output Bus Bit 11. When SER/PAR = low, this output is used as Bit 11 of the parallel port data output bus. or RDERROR Read Error. When SER/PAR = high, read error. In serial slave mode (EXT/INT = high), this output is used as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. 25 to 28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. 29 BUSY DO Busy Output. Transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal. 30 DGND P Digital Power Ground. 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. Rev. 0 | Page 9 of 32 AD7621 1 Pin No. Mnemonic Type Description 32 CS DI CS Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. is also used to gate the external clock in slave serial mode. 33 RESET DI Reset Input. When high, reset the AD7621. Current conversion if any is aborted. Falling edge of RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If not used, this pin can be tied to DGND. 34 PD DI Power-Down Input. When high, power down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 36 AGND P Analog Power Ground Pin. 37 REF AI/O Reference Output/Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal reference and buffer. Refer to the Voltage Reference Input section. 38 REFGND AI Reference Input Analog Ground. 39 IN− AI Differential Negative Analog Input. 43 IN+ AI Differential Positive Analog Input. 45 TEMP AO Temperature Sensor Analog Output. 46 REFBUFIN AI/O Internal Reference Output/Reference Buffer Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical) bandgap output on this pin, which needs external decoupling. The internal fixed gain reference buffer uses this to produce 2.048V on the REF pin. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section. 47 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down and an external reference must been used. 48 PDBUF DI Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. Rev. 0 | Page 10 of 32 AD7621 TERMINOLOGY Integral Nonlinearity Error (INL) Signal-to-(Noise + Distortion) Ratio (SINAD) Linearity error refers to the deviation of each individual code SINAD is the ratio of the rms value of the actual input signal to from a line drawn from negative full-scale through positive full- the rms sum of all other spectral components below the Nyquist scale. The point used as negative full-scale occurs ½ LSB before frequency, including harmonics but excluding dc. The value for the first code transition. Positive full-scale is defined as a level SINAD is expressed in decibels. 1½ LSBs beyond the last code transition. The deviation is Spurious-Free Dynamic Range (SFDR) measured from the middle of each code to the true straight line. The difference, in decibels (dB), between the rms amplitude of Differential Nonlinearity Error (DNL) the input signal and the peak spurious signal. In an ideal ADC, code transitions are 1 LSB apart. Differential Effective Number of Bits (ENOB) nonlinearity is the maximum deviation from this ideal value. It ENOB is a measurement of the resolution with a sine wave is often specified in terms of resolution for which no missing input. It is related to SINAD and is expressed in bits by codes are guaranteed. ENOB = [(SINADdB − 1.76)/6.02] Gain Error Aperture Delay The first transition (from 000…00 to 000…01) should occur for Aperture delay is a measure of the acquisition performance an analog voltage ½ LSB above the nominal negative full-scale CNVST measured from the falling edge of the input to when (−2.0479688 V for the ±2.048 V range). The last transition the input signal is held for a conversion. (from 111…10 to 111…11) should occur for an analog voltage 1½ LSBs below the nominal full-scale (2.0479531 V for the Transient Response ±2.048 V range). The gain error is the deviation of the The time required for the AD7621 to achieve its rated accuracy difference between the actual level of the last transition and the after a full-scale step function is applied to its input. actual level of the first transition from the difference between the ideal levels. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the Zero Error typical shift of output voltage at 25°C on a sample of parts at the The zero error is the difference between the ideal midscale maximum and minimum reference output voltage (V ) REF input voltage (0 V) and the actual voltage producing the measured at T , T(25°C), and T . It is expressed in ppm/°C as MIN MAX midscale output code. V (Max) – V (Min) REF REF 6 TCV (ppm/°C)= ×10 Dynamic Range REF V (25°C)× (T – T ) REF MAX MIN Dynamic range is the ratio of the rms value of the full-scale to the rms noise measured with the inputs shorted together. The where: value for dynamic range is expressed in decibels. VREF (Max) = maximum VREF at TMIN, T (25°C), or TMAX VREF (Min) = minimum VREF at TMIN, T (25°C), or TMAX Signal-to-Noise Ratio (SNR) V (25°C) = V at 25°C REF REF SNR is the ratio of the rms value of the actual input signal to the T = +85°C MAX rms sum of all other spectral components below the Nyquist T = –40°C MIN frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Rev. 0 | Page 11 of 32 AD7621 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –1.0 –0.5 –1.5 –2.0 –1.0 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 160000 160000 149969 σ = 0.69 σ = 0.82 140000 140000 127317 120000 120000 100000 100000 80000 80000 60842 59637 54791 60000 60000 51847 40000 40000 20000 20000 6644 6376 2415 2080 0 176 128 0 013 50 0 0 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 CODE IN HEX CODE IN HEX Figure 9. Histogram of 261,120 Conversions of a DC Input Figure 6. Histogram of 261,120 Conversions of a DC Input at the Code Center (Internal Reference) at the Code Center (External Reference) 10 2.0530 2.0525 8 2.0520 6 4 2.0515 2.0510 2 –FS 0 2.0505 2.0500 –2 2.0495 –4 ZERO ERROR –6 2.0490 2.0485 –8 +FS –10 2.0480 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 10. Zero Error, Positive and Negative Full Scale vs. Temperature Figure 7. Typical Reference Voltage Output vs. Temperature (3 Units) Rev. 0 | Page 12 of 32 V (V) COUNTS REF INL (LSB) 04565-005 04565-007 04565-006 ZERO SCALE, FULL-SCALE ERROR (LSB) COUNTS DNL (LSB) 04565-008 04565-010 04565-009 AD7621 0 0 f = 3MSPS f = 3MSPS S S f = 20.1kHz f = 98.79kHz IN IN –20 –20 SNR = 90.1dB SNR = 89.9dB THD = –103.2dB THD = –104.9dB –40 –40 SFDR = 103.8dB SFDR = 106.6dB SINAD = 89.9dB SINAD = 89.8dB –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 FREQUENCY (kHz) FREQUENCY (kHz) Figure 14. FFT 100 kHz Figure 11. FFT 20 kHz 92 16.0 95 16.0 93 15.6 91 SNR 91 15.2 SNR 90 15.5 89 14.8 SINAD 89 87 14.4 SINAD 88 15.0 85 14.0 ENOB 83 13.6 87 ENOB 81 13.2 86 14.5 79 12.8 85 77 12.4 84 14.0 75 12.0 1 10 100 1000 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY (kHz) TEMPERATURE (°C) Figure 12. SNR, SINAD and ENOB vs. Frequency Figure 15. SNR, SINAD, and ENOB vs. Temperature –70 120 –80 110 SFDR –75 110 –85 105 SFDR –80 100 –90 100 –85 90 –95 95 –90 80 –100 90 THD –95 70 –105 85 –100 60 –110 80 THD –105 50 THIRD HARMONIC –115 75 THIRD SECOND HARMONIC –110 HARMONIC 40 –120 70 –115 30 SECOND –125 65 HARMONIC –120 20 –130 60 1 10 100 1000 –55 –35 –15 5 25 45 65 85 105 125 FREQUENCY (kHz) TEMPERATURE (°C) Figure 13. THD, Harmonics, and SFDR vs. Frequency Figure 16. THD, Harmonics, and SFDR vs. Temperature Rev. 0 | Page 13 of 32 THD, HARMONICS (dB) SNR, SINAD (dB) AMPLITUDE (dB of Full-Scale) 04565-011 ENOB (Bits) SFDR (dB) 04565-012 04565-013 THD, HARMONICS (dB) SNR, SINAD (dB) AMPLITUDE (dB of Full-Scale) 04565-014 ENOB (Bits) 04565-015 SFDR (dB) 04565-016 AD7621 91.0 100k AVDD, WARP/NORMAL SNR 10k 90.5 1k AVDD, IMPULSE SINAD 100 OVDD = 3.3V, ALL MODES 90.0 10 DVDD, ALL MODES OVDD, 2.5V, ALL MODES 1 PDREF = PDBUF = HIGH 89.5 0.1 –60 –50 –40 –30 –20 –10 0 10 100 1k 10k 100M 1M 10M INPUT LEVEL (dB) SAMPLING RATE (SPS) Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 19. Operating Current vs. Sample Rate 16 280 20 OVDD = 2.5V @ 85°C 14 270 18 OVDD = 2.5V @ 25°C AVDD 12 260 16 OVDD, 3.3V 10 250 14 OVDD = 3.3V @ 85°C OVDD, 2.5V OVDD = 3.3V @ 25°C 8 240 12 6 230 10 4 220 8 2 210 6 DVDD 0 200 4 0 50 100 150 200 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) C (pF) L Figure 18. Power-Down Operating Currents vs. Temperature Figure 20. Typical Delay vs. Load Capacitance C L Rev. 0 | Page 14 of 32 DVDD, OVDD (μA) SNR, SINAD REFERRED TO FULL-SCALE (dB) 04565-017 AVDD (μA) 04565-019 OPERATING CURRENTS (μA) t DELAY (ns) 12 04565-022 04565-020 AD7621 THEORY OF OPERATION IN+ AGND SWITCHES CONTROL LSB SW+ MSB 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC REFGND OUTPUT CODE 32,768C 16,384C 4C 2C C C SW– MSB LSB CNVST AGND IN– Figure 21. ADC Simplified Schematic phase is applied to the comparator inputs, causing the CIRCUIT INFORMATION comparator to become unbalanced. By switching each element The AD7621 is a very fast, low power, single-supply, precise, of the capacitor array between REFGND and REF, the 16-bit analog-to-digital converter (ADC) using successive comparator input varies by binary weighted voltage steps approximation architecture. The AD7621 features different (V /2, V /4 through V /65536). The control logic toggles REF REF REF modes to optimize performances according to the applications. these switches, starting with the MSB first, in order to bring the In warp mode, the AD7621 is capable of converting 3,000,000 comparator back into a balanced condition. After the samples per second (3 MSPS). completion of this process, the control logic generates the ADC The AD7621 provides the user with an on-chip track-and-hold, output code and brings BUSY output low. successive approximation ADC that does not exhibit any MODES OF OPERATION pipeline or latency, making it ideal for multiple multiplexed The AD7621 features four modes of operation: wideband warp, channel applications. warp, normal, and impulse. Each of these modes is more The AD7621 can be operated from a single 2.5 V supply and suitable to specific applications. be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic. It Wideband warp (WARP = high, IMPULSE = high) and warp is housed in 48-lead LQFP or tiny LFCSP packages that (WARP = high, IMPULSE = low) modes allow the fastest combine space savings with flexibility, allowing the AD7621 conversion rate up to 3 MSPS. However, in these modes, the full to be configured as either a serial or parallel interface. The specified accuracy is guaranteed only when the time between AD7621 is pin-to-pin-compatible with, and a speed upgrade conversions does not exceed 1 ms. If the time between two of, the AD7677. consecutive conversions is longer than 1 ms (after power up), CONVERTER OPERATION the first conversion result should be ignored. These modes The AD7621 is a successive approximation analog-to-digital make the AD7621 ideal for applications where both high converter (ADC) based on a charge redistribution DAC. Figure 21 accuracy and fast sample rate are required. Wideband warp shows the simplified schematic of the ADC. The capacitive mode offers slightly improved linearity and THD over warp DAC consists of two identical arrays of 16 binary weighted mode. capacitors which are connected to the two comparator inputs. Normal mode (WARP = low, IMPULSE = low) is the fastest During the acquisition phase, terminals of the array tied to the mode (2 MSPS) without any limitation on time between comparator’s input are connected to AGND via SW+ and SW−. conversions. This mode makes the AD7621 ideal for All independent switches are connected to the analog inputs. asynchronous applications such as data acquisition systems, Thus, the capacitor arrays are used as sampling capacitors and where both high accuracy and fast sample rate are required. acquire the analog signal on IN+ and IN− inputs. A conversion Impulse mode (WARP = low, IMPULSE = high), the lowest phase is initiated once the acquisition phase is complete and the power dissipation mode, allows power saving between CNVST input goes low. When the conversion phase begins, conversions. The maximum throughput in this mode is SW+ and SW− are opened first. The two capacitor arrays are 1.25 MSPS. In this mode, the ADC powers down circuits after then disconnected from the inputs and connected to the conversion making the AD7621 ideal for battery-powered REFGND input. Therefore, the differential voltage between the applications. inputs (IN+ and IN−) captured at the end of the acquisition Rev. 0 | Page 15 of 32 04565-024 AD7621 TRANSFER FUNCTIONS Table 7. Output Codes and Ideal Input Voltages Using the OB/2C digital input, the AD7621 offers two output Digital Output Code codings: straight binary and twos complement. The LSB size Analog Input Straight Twos with V = 2.048 V is 2 × V /65536, which is 62.5 μV. Refer to REF REF Description V = 2.048 V Binary Complement REF Figure 22 and Table 7 for the ideal transfer characteristic. 1 1 FSR −1 LSB +2.047938 V 0xFFFF 0x7FFF FSR − 2 LSB +2.047875 V 0xFFFE 0x7FFE Midscale + 1 LSB +62.5 μV 0x8001 0x0001 111...111 111...110 Midscale 0 V 0x8000 0x0000 111...101 Midscale − 1 LSB −62.5 μV 0x7FFF 0xFFFF −FSR + 1 LSB −2.047938 V 0x0001 0x8001 2 2 −FSR −2.048 V 0x0000 0x8000 1 This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND). 2 This is also the code for underrange analog input (V − V below IN+ IN− 000...010 −VREF + VREFGND). 000...001 000...000 –FSR+1 LSB +FSR–1 LSB –FSR –FSR+0.5 LSB +FSR–1.5 LSB ANALOG INPUT Figure 22. ADC Ideal Transfer Function DIGITAL SUPPLY (2.5V) NOTE 5 DIGITAL 10Ω INTERFACE ANALOG SUPPLY SUPPLY (2.5V) (2.5V OR 3.3V) 100nF 10μF 10μF 100nF 100nF 10μF AVDD AGND DGND DVDD OVDD OGND SERIAL PORT REF NOTE 3 SCLK C REF REFBUFIN 10μF 100nF SDOUT REFGND NOTE 4 BUSY NOTE 2 NOTE 7 MICROCONVERTER/ 50Ω MICROPROCESSOR/ 10Ω D CNVST DSP U1 IN+ 50pF ANALOG INPUT + AD7621 OB/2C C 1nF C SER/PAR NOTE 1 OVDD WARP IMPULSE NOTE 2 CS 10Ω RD CLOCK U2 IN– ANALOG INPUT – NOTE 3 C 1nF 50pF C PD PDREF PDBUF RESET NOTE 1 10kΩ NOTE 6 1. SEE ANALOG INPUT SECTION. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4. A 10μF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTION, SEE POWER UP SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 23. Typical Connection Diagram Rev. 0 | Page 16 of 32 ADC CODE (Straight Binary) 04565-025 04565-026 AD7621 comprised of some serial resistors and the on resistance of the TYPICAL CONNECTION DIAGRAM switches. C is typically 12 pF and is mainly the ADC sampling IN Figure 23 shows a typical connection diagram for the AD7621. capacitor. During the conversion phase, when the switches are Different circuitry from that shown in this diagram are optional opened, the input impedance is limited to CPIN. RIN and CIN and are discussed below. make a one-pole, low-pass filter that has a typical −3 dB cutoff frequency of 50 MHz, thereby reducing an undesirable aliasing ANALOG INPUTS effect while limiting noise from the inputs. Figure 24 shows an equivalent circuit of the input structure of the AD7621. Since the input impedance of the AD7621 is very high, the AD7621 can be directly driven by a low impedance source The two diodes, D1 and D2, provide ESD protection for the without gain error. To further improve the noise filtering analog inputs, IN+ and IN−. Care must be taken to ensure that achieved by the AD7621 analog input circuit, an external, one- the analog input signal never exceeds the supply rails by more pole RC filter between the amplifier’s outputs and the ADC than 0.3 V as this causes the diodes to become forward-biased analog inputs can be used, as shown in Figure 23. However, and start conducting current. These diodes can handle a large source impedances significantly affect the ac performance, forward-biased current of 100 mA maximum. For instance, especially total harmonic distortion (THD). The maximum these conditions could eventually occur when the input buffer’s source impedance depends on the amount of THD that can be U1 or U2 supplies are different from AVDD. In such a case, an tolerated. The THD degrades as a function of the source input buffer with a short-circuit current limitation can be used impedance and the maximum input frequency, as shown in to protect the part. Figure 26. AVDD –60 PDBUF = PDREF = LOW D 1 R C IN IN –65 IN+ OR IN– –70 C D PIN 2 R = 500Ω S AGND –75 –80 Figure 24. AD7621 Simplified Analog Input. –85 R = 100Ω S The analog input of AD7621 is a true differential structure. By –90 using this differential input, small signals common to both R = 50Ω S –95 inputs are rejected, as shown in Figure 25, representing the typical CMRR over frequency with internal and external –100 R = 10Ω S references. –105 1 10 100 1k 75 INPUT FREQUENCY (kHz) Figure 26. THD vs. Analog Input Frequency and Source Resistance 70 DRIVER AMPLIFIER CHOICE 65 Although the AD7621 is easy to drive, the driver amplifier EXT REF needs to meet the following requirements: 60 • Together, the driver amplifier and the AD7621 analog INT REF 55 input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the 50 amplifier data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from 45 the settling time at a 16-bit level and should be verified 1 10 100 1k 10k FREQUENCY (kHz) prior to driver selection. The AD8021 op amp, which combines ultralow noise and high gain bandwidth, meets Figure 25. Analog Input CMRR vs. Frequency this settling time requirement even when used with gains During the acquisition phase for ac signals, the impedance of up to 13. the analog inputs, IN+ and IN−, can be modeled as a parallel combination of Capacitor C and the network formed by the PIN • The noise generated by the driver amplifier needs to be series connection of RIN and CIN. CPIN is primarily the pin kept as low as possible in order to preserve the SNR and capacitance. RIN is typically 350 Ω and is a lumped component transition noise performance of the AD7621. The noise Rev. 0 | Page 17 of 32 CMRR (dB) 04565-027 04565-099 THD (dB) 04565-029 AD7621 coming from the driver is filtered by the AD7621 analog input circuit one-pole, low-pass filter made by R and C IN IN U1 ANALOG INPUT AD8021 or by the external filter, if one is used. The SNR (UNIPOLAR 0V TO 2.048V) 10pF degradation due to the amplifier is 590Ω 10Ω ⎛ ⎞ IN+ 53 ⎜ ⎟ 590Ω 1nF SNR = 20log LOSS ⎜ ⎟ 2 AD7621 ⎜ ⎟ 2809+πf () Ne −3dB N ⎝ ⎠ 10Ω U2 IN– 1kΩ REF AD8021 where: 1nF 1kΩ 10pF 100nF f–3dB is the input bandwidth of the AD7621 (50 MHz) or 10μF the cutoff frequency of the input filter (16 MHz), if one is used. Figure 27. Single-Ended-to-Differential Driver Circuit (Internal Reference Buffer Used) N is the noise factor of the amplifier (+1 in buffer configuration). VOLTAGE REFERENCE INPUT is the equivalent input voltage noise density of the op eN The AD7621 allows the choice of either a very low temperature amp, in nV/√Hz. drift internal voltage reference or an external reference. For instance, a driver with an equivalent input noise Unlike many ADCs with internal references, the internal density of 2.1 nV/√Hz, like the AD8021 with a noise gain reference of the AD7621 provides excellent performance and of +1 when configured as a buffer, degrades the SNR by can be used in almost all applications. only 0.33 dB when using the RC filter in Figure 23, and by 1 dB without. Internal Reference (PDBUF = Low, PDREF = Low) • The driver needs to have a THD performance suitable to To use the internal reference, the PDREF and PDBUF inputs that of the AD7621. Figure 13 gives the THD vs. frequency must be low. This produces a 1.2 V band gap output on that the driver should exceed. REFBUFIN which, amplified by the internal buffer, results in a 2.048 V reference on the REF pin. The AD8021 meets these requirements and is appropriate for The internal reference is temperature-compensated to 2.048 V ± almost all applications. The AD8021 needs a 10 pF external 10 mV. The reference is trimmed to provide a typical drift of compensation capacitor that should have good linearity as an 7 ppm/°C. This typical drift characteristic is shown in Figure 7. NPO ceramic or mica type. Moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the The output resistance of the REFBUFIN is 6.33 kΩ (minimum) best signal-to-noise ratio. when the internal reference is enabled. It is necessary to decouple this with a ceramic capacitor greater than 100 nF. The AD8022 can also be used when a dual version is needed Thus, the capacitor provides an RC filter for noise reduction. and a gain of 1 is present. The AD829 is an alternative in applications where high frequency (above 100 kHz) performance Since the output impedance of REFBUFIN is typically 6.33 kΩ, is not required. In applications with a gain of 1, an 82 pF relative humidity (among other industrial contaminates) can compensation capacitor is required. The AD8610 is an option directly affect the drift characteristics of the reference. Typically, when low bias current is needed in low frequency applications. a guard ring is used to reduce the effects of drift under such Single-to-Differential Driver circumstances. However, since the AD7621 has a fine lead pitch, guarding this node is not practical. Therefore, in these For applications using unipolar analog signals, a single-ended- industrial and other types of applications, it is recommended to to-differential driver, as shown in Figure 27, allows for a use a conformal coating such as Dow Corning 1-2577 or differential input into the part. This configuration, when Humiseal 1B73. provided an input signal of 0 to V , will produce a differential REF ±V with midscale at V /2. The one-pole filter using R = 10 Ω REF REF External 1.2 V Reference and Internal Buffer and C = 1 nF provides a corner frequency of 16 MHz. (PDREF = High, PBBUF = Low) To use an external reference with the internal buffer, PDREF If the application can tolerate more noise, the AD8139 should be high and PDBUF should be low. This powers down differential driver can be used. the internal reference and allows the 1.2 V reference to be applied to REFBUFIN. Rev. 0 | Page 18 of 32 04565-030 AD7621 External Reference (PDBUF = High, PRBUF = High) Temperature Sensor To use an external reference directly on the REF pin, PDREF The TEMP pin measures the temperature of the AD7621. To and PDBUF should both be high. improve the calibration accuracy over the temperature range, the output of the TEMP pin is applied to one of the inputs of the For improved drift performance, an external reference, such as analog switch (such as, ADG779), and the ADC itself is used to the AD780 or ADR431, can be used. The advantages of directly measure its own temperature. This configuration is shown in using the external voltage reference are: Figure 28. • SNR and dynamic range improvement (about 1.7 dB) TEMP ADG779 resulting from the use of a reference voltage very close to the supply (2.5 V) instead of a typical 2.048 V reference TEMPERATURE ANALOG INPUT IN+ SENSOR when the internal reference is used. This is calculated by (UNIPOLAR) AD7621 C AD8021 C ⎛ 2.048⎞ SNR= 20log⎜ ⎟ 2.50 ⎝ ⎠ Figure 28. Use of the Temperature Sensor • Power savings when the internal reference is powered POWER SUPPLY down (PBREF = PDBUF = high). The AD7621 uses three sets of power supply pins: an analog 2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a PDREF and PDBUF power down the internal reference and the digital input/output interface supply OVDD. The OVDD supply internal reference buffer, respectively. allows direct interface with any logic working between 2.3 V Reference Decoupling and 5.25 V. To reduce the number of supplies needed, the digital Whether using an internal or external reference, the AD7621 core (DVDD) can be supplied through a simple RC filter from voltage reference input (REF) has a dynamic input impedance; the analog supply as shown in Figure 23. therefore, it should be driven by a low impedance source with Power Sequencing efficient decoupling between the REF and REFGND inputs. The AD7621 is independent of power supply sequencing once This decoupling depends on the choice of the voltage reference, OVDD does not exceed DVDD by more than 0.3 V until but usually consists of a low ESR capacitor connected to REF DVDD = 2.3 V during any time; for instance, at power-up or and REFGND with minimum parasitic inductance. A 10 μF power-down (see the Absolute Maximum Ratings section). (X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum Additionally, it is very insensitive to power supply variations capacitor) is appropriate when using either the internal over a wide frequency range as shown in Figure 29. reference or one of these recommended reference voltages: 75 • The low noise, low temperature drift ADR431 and AD780 • The low power ADR291 70 • The low cost AD1582 65 The placement of the reference decoupling is also important to EXT REF the performance of the AD7621. The decoupling capacitor 60 should be mounted on the same side as the ADC right at the INT REF REF pin with a thick PCB trace. The REFGND should also 55 connect to the reference decoupling capacitor with the shortest distance. 50 For applications that use multiple AD7621 devices, it is more 45 effective to use the internal reference buffer in order to buffer 1 10 100 1k 10k FREQUENCY (kHz) the reference voltage. Figure 29. PSRR vs. Frequency The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a ±15 ppm/°C TC of the reference changes full-scale by ±1 LSB/°C. Rev. 0 | Page 19 of 32 PSRR (dB) 04565-098 04565-031 AD7621 Power-Up CONVERSION CONTROL At power-up, or returning to operational mode from the power- The AD7621 is controlled by the CNVST input. A falling edge down mode (PD = high), the AD7621 engages an initialization on CNVST is all that is necessary to initiate a conversion. process. During this time, the first 128 conversions should be Detailed timing diagrams of the conversion process are shown ignored or the RESET input could be pulsed to engage a faster in Figure 31. Once initiated, it cannot be restarted or aborted, initialization process. Refer to the Digital Interface section for even by the power-down input, PD, until the conversion is RESET and timing details. CNVST CS complete. The signal operates independently of and A simple power-on reset circuit, as shown in Figure 23, can be RD signals. used to minimize the digital interface. As OVDD powers up, the t 2 capacitor is shorted and brings RESET high; it is then charged t 1 t 1 returning RESET to low. However, this circuit only works when CNVST powering up the AD7621 because the power down mode (PD = high) does not power down any of the supplies. As a result, RESET is low. BUSY t 4 POWER DISSIPATION VS. THROUGHPUT t 3 t 6 t 5 In impulse mode, the AD7621 automatically reduces its power consumption at the end of each conversion phase. During the MODE ACQUIRE CONVERT ACQUIRE CONVERT acquisition phase, the operating currents are very low which t t 7 8 allows a significant power saving when the conversion rate is Figure 31. Basic Conversion Timing reduced (see Figure 30). This feature makes the AD7621 ideal for very low power, battery-operated applications. For optimal performance, the rising edge of CNVST should not CNVST occur after the maximum low time, t1, or until the end It should be noted that the digital interface remains active even of conversion. during the acquisition phase. To reduce the operating digital supply currents even further, drive the digital inputs close to the CNVST Although is a digital signal, it should be designed with power rails (that is, OVDD and OGND). special care with fast, clean edges, and levels with minimum overshoot, undershoot, or ringing. 100k WARP MODE POWER The CNVST trace should be shielded with ground and a low value (such as 50 Ω) serial resistor termination should be added close to the output of the component that drives this line. Also, 10k a 60 pF capacitor is recommended to further reduce the effects of overshoot and undershoot as shown in Figure 23. IMPULSE MODE POWER CNVST For applications where SNR is critical, the signal should 1k have very low jitter. This can be achieved by using a dedicated oscillator for CNVST generation, or by clocking CNVST with a high frequency, low jitter clock, as shown in Figure 23. PDREF = PDBUF = HIGH 100 100 1k 10k 100k 1M 10M SAMPLING RATE (SPS) Figure 30. Power Dissipation vs. Sample Rate Rev. 0 | Page 20 of 32 POWER DISSIPATION (μW) 04565-032 04565-034 AD7621 INTERFACES DIGITAL INTERFACE PARALLEL INTERFACE The AD7621 has a versatile digital interface that can be set up The AD7621 is configured to use the parallel interface when as either a serial or parallel interface with the host system. The PAR SER/ is held low. serial interface is multiplexed on the parallel data bus. The Master Parallel Interface AD7621 digital interface also accommodates 2.5 V, 3.3 V, or 5 V Data can be continuously read by tying CS and RD low thus logic with either OVDD at 2.5 V or 3.3 V. OVDD defines the requiring minimal microprocessor connections. However, in logic high output voltage. In most applications, the OVDD this mode the data bus is always driven and cannot be used in supply pin of the AD7621 is connected to the host system shared bus applications (unless the device is held in RESET). interface 2.5 V or 3.3 V digital supply. Finally, by using the Figure 33 details the timing for this mode. 2C OB/ input pin, both twos complement or straight binary CS = RD = 0 coding can be used. t 1 CNVST CS RD The two signals, and , control the interface. When at least one of these signals is high, the interface outputs are in high t 10 impedance. Usually, CS allows the selection of each AD7621 in BUSY t 4 multicircuit applications and is held low in a single AD7621 t 3 t 11 RD design. is generally used to enable the conversion result on the data bus. DATA PREVIOUS CONVERSION DATA NEW DATA BUS RESET Figure 33. Master Parallel Data Timing for Reading (Continuous Read) The RESET input is used to reset the AD7621 and generate a Slave Parallel Interface fast initialization. A rising edge on RESET aborts the current In slave parallel reading mode, the data can be read either after conversion (if any) and tristates the data bus. The falling edge of each conversion, which is during the next acquisition phase, or RESET clears the data bus and engages the initialization process during the following conversion, as shown in Figure 34 and indicated by pulsing BUSY high. Conversions can take place Figure 35, respectively. When the data is read during the after the falling edge of BUSY. Refer to Figure 32 for the RESET conversion, it is recommended that it is read-only during the timing details. first half of the conversion phase. This avoids any potential t 9 feedthrough between voltage transients on the digital interface RESET and the most critical analog conversion circuitry. CNVST CS DATA RD BUSY t t t 38 39 8 BUSY Figure 32. RESET Timing DATA CURRENT BUS CONVERSION t t 12 13 Figure 34. Slave Parallel Data Timing for Reading (Read After Convert) Rev. 0 | Page 21 of 32 04565-035 04565-037 04565-036 AD7621 CS = 0 SERIAL INTERFACE CNVST, t 1 RD The AD7621 is configured to use the serial interface when SER/PAR is held high. The AD7621 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data BUSY t 4 is valid on both the rising and falling edge of the data clock. t 3 MASTER SERIAL INTERFACE Internal Clock DATA PREVIOUS BUS CONVERSION The AD7621 is configured to generate and provide the serial t t 12 13 data clock SCLK when the EXT/INT pin is held low. The Figure 35. Slave Parallel Data Timing for Reading (Read During Convert) AD7621 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the 8-Bit Interface (Master or Slave) SYNC signal can be inverted, if desired. Depending on the read The BYTESWAP pin allows a glueless interface to an 8-bit bus. during convert input, RDC/SDIN, the data can be read after As shown in Figure 36, when BYTESWAP is low, the LSB byte is each conversion or during the following conversion. Figure 37 output on D[7:0] and the MSB is output on D[15:8]. When and Figure 38 show detailed timing diagrams of these two BYTESWAP is high, the LSB and MSB bytes are swapped, and modes. the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16-bit data Usually, because the AD7621 is used with a fast throughput, the can be read in two bytes on either D[15:8] or D[7:0]. This master read during conversion mode is the most recommended interface can be used in both master and slave parallel reading serial mode. In this mode, the serial clock and data toggle at modes. appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions. In this mode, the SCLK period changes since the LSBs require more time to CS settle and the SCLK is derived from the SAR conversion cycle. RD In read after conversion mode, unlike other modes, the BUSY signal returns low after the 16 data bits are pulsed out and not at BYTESWAP the end of the conversion phase resulting in a longer BUSY width. As a result, the maximum throughput cannot be HI-Z HI-Z PINS D[15:8] HIGH BYTE LOW BYTE achieved in this mode. t t t 12 12 13 HI-Z HI-Z PINS D[7:0] LOW BYTE HIGH BYTE Figure 36. 8-Bit and 16-Bit Parallel Interface Rev. 0 | Page 22 of 32 04565-039 04565-038 AD7621 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 3 CNVST t BUSY 28 t 30 t 29 t 25 SYNC t t 18 14 t 19 t t t 24 20 21 t 26 12 3 14 15 16 SCLK t 15 t 27 SDOUT D15 D14 D2 D1 D0 X t t 16 23 t 22 Figure 37. Master Serial Data Timing for Reading (Read After Convert) RDC/SDIN = 1 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 19 14 t t 20 21 t 24 t 26 t 15 SCLK 12 3 14 15 16 t 18 t 27 SDOUT X D15 D14 D2 D1 D0 t t 16 23 t 22 Figure 38. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 23 of 32 04565-040 04565-041 AD7621 CNVST common signal. It should be noted that the RDC/SDIN SLAVE SERIAL INTERFACE input is latched on the edge of SCLK opposite to the one used to External Clock shift out the data on SDOUT. Hence, the MSB of the upstream The AD7621 is configured to accept an externally supplied converter just follows the LSB of the downstream converter on INT serial data clock on the SCLK pin when the EXT/ pin is the next SCLK cycle. held high. In this mode, several methods can be used to read BUSY the data. The external serial clock is gated by CS. When CS and OUT RD are both low, the data can be read after each conversion or BUSY BUSY during the following conversion. The external clock can be AD7621 AD7621 either a continuous or a discontinuous clock. A discontinuous #2 #1 (UPSTREAM) (DOWNSTREAM) clock can be either normally high or normally low when DATA RDC/SDIN SDOUT RDC/SDIN SDOUT inactive. Figure 40 and Figure 41 show the detailed timing OUT diagrams of these methods. CNVST CNVST CS CS While the AD7621 is performing a bit decision, it is important SCLK SCLK that voltage transients be avoided on digital input/output pins or degradation of the conversion result could occur. This is SCLK IN particularly important during the second half of the conversion CS IN phase because the AD7621 provides error correction circuitry CNVST IN that can correct for an improper bit decision made during the Figure 39. Two AD7621 Devices in a Daisy-Chain Configuration first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it External Clock Data Read During Previous Conversion is a discontinuous clock that is toggling only when BUSY is low Figure 41 shows the detailed timing diagrams of this method. or, more importantly, that it does not transition during the latter CS RD During a conversion, while both and are low, the result half of BUSY high. of the previous conversion can be read. The data is shifted out, External Discontinuous Clock Data Read After MSB first, with 16 clock pulses and is valid on both the rising Conversion and falling edge of the clock. The 16 bits have to be read before the current conversion is complete, otherwise; RDERROR is Though the maximum throughput cannot be achieved using pulsed high and can be used to interrupt the host interface to this mode, it is the most recommended of the serial slave prevent incomplete data reading. There is no daisy-chain modes. Figure 40 shows the detailed timing diagrams of this feature in this mode and RDC/SDIN input should always be method. After a conversion is complete, indicated by BUSY tied either high or low. returning low, the conversion result can be read while both CS and RD are low. Data is shifted out MSB first with 16 clock To reduce performance degradation due to digital activity, a fast pulses and is valid on the rising and falling edges of the clock. discontinuous clock (at least 30 MHz when impulse mode is used, 60 MHz when normal mode is used, or 80 MHz when Among the advantages of this method is the fact that warp mode is used) is recommended to ensure that all the bits conversion performance is not degraded because there are no are read during the first half of the SAR conversion phase. voltage transients on the digital interface during the conversion process. Another advantage is the ability to read the data at any It is also possible to begin to read data after conversion and speed up to 80 MHz, which accommodates both the slow digital continue to read the last bits after a new conversion has been host interface and the fastest serial reading. initiated. However, this is not recommended when using the fastest throughput of any mode since the acquisition times are Finally, in this mode only, the AD7621 provides a daisy-chain only 70 ns, 100 ns, and 50 ns for warp, normal, and impulse feature using the RDC/SDIN pin for cascading multiple modes. converters together. This feature is useful for reducing component count and wiring connections when desired, as, for If the maximum throughput is not used, thus allowing more instance, in isolated multiconverter applications. acquisition time, then the use of a slower clock speed can be used to read the data. An example of the concatenation of two devices is shown in Figure 39. Simultaneous sampling is possible by using a Rev. 0 | Page 24 of 32 04565-042 AD7621 RD = 0 EXT/INT = 1 INVSCLK = 0 CS BUSY t 35 t t 36 37 SCLK 12 3 14 15 16 17 18 t 31 t 32 X SDOUT D15 D14 D13 D1 D0 X15 X14 t 16 t 34 SDIN X15 X14 X13 X1 X0 Y15 Y14 t 33 Figure 40. Slave Serial Data Timing for Reading (Read After Convert) EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t 3 t 35 t t 36 37 SCLK 12 3 14 15 16 t 31 t 32 X D1 SDOUT D15 D14 D13 D0 t 16 Figure 41. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 25 of 32 04565-043 04565-044 AD7621 going low) using an interrupt line of the DSP. The serial MICROPROCESSOR INTERFACING peripheral interface (SPI) on the ADSP-219x is configured for The AD7621 is ideally suited for traditional dc measurement master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock applications supporting a microprocessor, and ac signal phase bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00 processing applications interfacing to a digital signal processor. by writing to the SPI control register (SPICLTx). It should be The AD7621 is designed to interface with a parallel 8-bit or noted that to meet all timing requirements, the SPI clock should 16-bit wide interface, or with a general-purpose serial port or be limited to 17 Mb/s allowing it to read an ADC result in less I/O ports on a microcontroller. A variety of external buffers can than 1 μs. When a higher sampling rate is desired, use one of be used with the AD7621 to prevent digital noise from coupling the parallel interface modes. into the ADC. The following section illustrates the use of the DVDD AD7621 with an ADSP-219x SPI-equipped DSP. AD7621* ADSP-219x* SPI Interface (ADSP-219x) SER/PAR BUSY PFx Figure 42 shows an interface diagram between the AD7621 and EXT/INT CS SPIxSEL (PFx) an SPI-equipped DSP, ADSP-219x. To accommodate the slower SDOUT MISOx speed of the DSP, the AD7621 acts as a slave device and data RD SCLK SCKx must be read after conversion. This mode also allows the daisy- INVSCLK CNVST PFx OR TFSx chain feature. The convert command could be initiated in *ADDITIONAL PINS OMITTED FOR CLARITY response to an internal timer interrupt. The reading process can be initiated in response to the end-of-conversion signal (BUSY Figure 42. Interfacing the AD7621 to SPI Interface Rev. 0 | Page 26 of 32 04565-045 AD7621 APPLICATION LAYOUT The DVDD supply of the AD7621 can be either a separate supply or come from the analog supply, AVDD, or from the While the AD7621 has very good immunity to noise on the digital interface supply, OVDD. When the system digital supply power supplies, exercise care with the grounding layout. To is noisy, or fast switching digital signals are present, and no facilitate the use of ground planes that can be easily separated, separate supply is available, it is recommended to connect the design the printed circuit board that houses the AD7621 so that DVDD digital supply to the analog supply AVDD through an the analog and digital sections are separated and confined to RC filter, and to connect the system supply to the interface certain areas of the board. Digital and analog ground planes digital supply OVDD and the remaining digital circuitry. Refer should be joined in only one place, preferably underneath the to Figure 23 for an example of this configuration. When DVDD AD7621, or as close as possible to the AD7621. If the AD7621 is is powered from the system supply, it is useful to insert a bead in a system where multiple devices require analog-to-digital to further reduce high frequency spikes. ground connections, the connections should still be made at one point only, a star ground point, established as close as The AD7621 has four different ground pins: REFGND, AGND, possible to the AD7621. DGND, and OGND. REFGND senses the reference voltage and, because it carries pulsed currents, should be a low impedance To prevent coupling noise onto the die, avoid radiating noise, return to the reference. AGND is the ground to which most and to reduce feedthrough: internal ADC analog signals are referenced; it must be • Do not run digital lines under the device. connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane • Do run the analog ground plane under the AD7621. depending on the configuration. OGND is connected to the digital system ground. CNVST • Do shield fast switching signals, like or clocks, with digital ground to avoid radiating noise to other sections of The layout of the decoupling of the reference voltage is the board, and never run them near analog signal paths. important. To minimize parasitic inductances, place the decoupling capacitor close to the ADC and connect it with • Avoid crossover of digital and analog signals. short, thick traces. • Run traces on different but close layers of the board, at right EVALUATING THE AD7621 PERFORMANCE angles to each other, to reduce the effect of feedthrough A recommended layout for the AD7621 is outlined in the through the board. documentation of the EVAL-AD7621CB evaluation board for The power supply lines to the AD7621 should use as large a the AD7621. The evaluation board package includes a fully trace as possible to provide low impedance paths and reduce the assembled and tested evaluation board, documentation, and effect of glitches on the power supply lines. Good decoupling is software for controlling the board from a PC via the EVAL- also important to lower the impedance of the supplies presented CONTROLBRD3. to the AD7621, and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, and OVDD. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. Rev. 0 | Page 27 of 32 PAD AD7621 OUTLINE DIMENSIONS 0.75 9.00 BSC 1.60 0.60 SQ MAX 0.45 48 37 1 36 PIN 1 7.00 TOP VIEW BSC SQ 1.45 (PINS DOWN) 0.20 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 MAX 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 43. 48-Lead Low Profile Quad Flatpack (LQFP) [ST-48] Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED 5.25 TOP 6.75 VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 25 0.40 12 24 13 0.30 0.25 MIN 5.50 REF 0.80 MAX PADDLE CONNECTED TO GND. 1.00 12° MAX THIS CONNECTION IS NOT 0.65 TYP 0.85 REQUIRED TO MEET THE 0.05 MAX ELECTRICAL PERFORMANCES 0.80 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 44. 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 7 mm × 7 mm Body, Very Thin Quad [CP-48-1] Dimensions shown in millimeters Rev. 0 | Page 28 of 32 AD7621 ORDERING GUIDE Model Temperature Range Package Description Package Option AD7621ACP −40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-48-1 AD7621ACPRL −40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-48-1 1 AD7621ACPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-48-1 1 AD7621ACPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale (LFCSP_VQ) CP-48-1 AD7621AST −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP) ST-48 AD7621ASTRL −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP) ST-48 1 AD7621ASTZ −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP) ST-48 1 AD7621ASTZRL −40°C to +85°C 48-Lead Low Profile Quad Flatpack (LQFP) ST-48 2 EVAL-AD7621CB Evaluation Board 3 EVAL-CONTROLBRD3 Controller Board 1 Z = Pb-free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. Rev. 0 | Page 29 of 32 AD7621 NOTES Rev. 0 | Page 30 of 32 AD7621 NOTES Rev. 0 | Page 31 of 32 AD7621 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04565–0–5/05(0) Rev. 0 | Page 32 of 32