ANALOG DEVICES AD7612

16-Bit, 750 kSPS, Unipolar/Bipolar ® Programmable Input PulSAR ADC AD7612 FEATURES FUNCTIONAL BLOCK DIAGRAM Multiple pins/software programmable input ranges: TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND 5 V, 10 V, ±5 V, ±10 V OVDD AGND AD7612 Pins or serial SPI®-compatible input ranges/mode selection REF OGND AVDD AMP Throughput SERIAL DATA REF PDREF PORT 750 kSPS (warp mode) SERIAL PDBUF CONFIGURATION 600 kSPS (normal mode) 16 IN+ PORT SWITCHED D[15:0] CAP DAC 500 kSPS (impulse mode) IN– SER/PAR INL: ±0.75 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR) BYTESWAP 16-bit resolution with no missing codes PARALLEL OB/2C CLOCK INTERFACE CNVST SNR: 92 minimum (5 V) @ 2 kHz, 94 dB typical (±10 V) @ 2 kHz BUSY PD CONTROL LOGIC AND THD: −107 dB typical RD CALIBRATION CIRCUITRY RESET CS iCMOS™ process technology 5 V internal reference: typical drift 3 ppm/°C; TEMP output WARP IMPULSE BIPOLAR TEN No pipeline delay (SAR architecture) Figure 1. Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection Power dissipation: 190 mW @ 750 kSPS 100 kSPS to 500 kSPS to 800 kSPS to >1000 Type 250 kSPS 570 kSPS 1000 kSPS kSPS Pb-free, 48-lead LQFP and LFCSP (7 mm × 7 mm) packages Pseudo AD7651 AD7650 AD7653 APPLICATIONS Differential AD7660 AD7652 AD7667 AD7661 AD7664 Process control AD7666 Medical instruments True Bipolar AD7663 AD7665 AD7612 High speed data acquisition AD7671 Digital signal processing True AD7675 AD7676 AD7677 AD7621 Differential AD7622 Instrumentation AD7623 Spectrum analysis 18-Bit, True AD7678 AD7679 AD7674 AD7641 ATE Differential AD7643 Multichannel/ AD7654 GENERAL DESCRIPTION Simultaneous AD7655 The AD7612 is a 16-bit charge redistribution successive PRODUCT HIGHLIGHTS approximation register (SAR), architecture analog-to-digital 1. Programmable input range and mode selection. converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS Pins or serial port for selecting input range/mode select. high voltage process. The device is configured through hardware or via a dedicated write only serial configuration port for input 2. Fast throughput. range and operating mode. The AD7612 contains a high speed In warp mode, the AD7612 is 750 kSPS. 16-bit sampling ADC, an internal conversion clock, an internal 3. Superior Linearity. reference (and buffer), error correction circuits, and both serial No missing 16-bit code. ±1.5 LSB max INL. and parallel system interface ports. A falling edge on CNVST 4. Internal Reference. samples the analog input on IN+ with respect to a ground 5 V internal reference with a typical drift of ±3 ppm/°C sense, IN−. The AD7612 features four different analog input and an on-chip temperature sensor. ranges and three different sampling modes: warp mode for the fastest throughput, normal mode for the fastest asynchronous 5. Serial or Parallel Interface. throughput, and impulse mode where power consumption is Versatile parallel (16- or 8-bit bus) or 2-wire serial interface scaled linearly with throughput. Operation is specified from arrangement compatible with 3.3 V or 5 V logic. −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06265-001 AD7612 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs ............................................................................. 20 Applications....................................................................................... 1 Driver Amplifier Choice ........................................................... 21 General Description ......................................................................... 1 Voltage Reference Input/Output .............................................. 21 Functional Block Diagram .............................................................. 1 Power Supplies............................................................................ 22 Product Highlights ........................................................................... 1 Conversion Control ................................................................... 23 Revision History ............................................................................... 2 Interfaces.......................................................................................... 24 Specifications..................................................................................... 3 Digital Interface.......................................................................... 24 Timing Specifications .................................................................. 5 Parallel Interface......................................................................... 24 Absolute Maximum Ratings............................................................ 7 Serial Interface ............................................................................ 25 ESD Caution.................................................................................. 7 Master Serial Interface............................................................... 25 Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 27 Typical Performance Characteristics ........................................... 12 Hardware Configuration ........................................................... 29 Terminology .................................................................................... 16 Software Configuration ............................................................. 29 Theory of Operation ...................................................................... 17 Microprocessor Interfacing....................................................... 30 Overview...................................................................................... 17 Application Information................................................................ 31 Converter Operation.................................................................. 17 Layout Guidelines....................................................................... 31 Modes of Operation ................................................................... 18 Evaluating Performance ............................................................ 31 Transfer Functions...................................................................... 18 Outline Dimensions....................................................................... 32 Typical Connection Diagram ................................................... 19 Ordering Guide .......................................................................... 32 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7612 SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range, VIN VIN+ − VIN− = 0 V to 5 V −0.1 +5.1 V VIN+ − VIN− = 0V to 10 V −0.1 +10.1 V V − V = ±5 V −5.1 +5.1 V IN+ IN− V − V = ±10 V −10.1 +10.1 V IN+ IN− VIN− to AGND −0.1 +0.1 V Analog Input CMRR fIN = 100 kHz 75 dB 1 Input Current VIN = ±5 V, ±10 V @ 750 kSPS 220 μA Input Impedance See Analog Inputs section THROUGHPUT SPEED Complete Cycle In warp mode 1.33 μs 2 Throughput Rate In warp mode 1 750 kSPS Time Between Conversions In warp mode 1 ms Complete Cycle In normal mode 1.67 μs Throughput Rate In normal mode 0 600 kSPS Complete Cycle In impulse mode 2 μs Throughput Rate In impulse mode 0 500 kSPS DC ACCURACY 3 4 Integral Linearity Error −1.5 ±0.75 +1.5 LSB 3 No Missing Codes 16 Bits 3 Differential Linearity Error −1 +1.5 LSB Transition Noise 0.55 LSB Zero Error (Unipolar or Bipolar) −35 +35 LSB Zero Error Temperature Drift ±1 ppm/°C Bipolar Full-Scale Error −50 +50 LSB Unipolar Full-Scale Error −70 +70 LSB Full-Scale Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% 3 LSB AC ACCURACY 5 Dynamic Range VIN = 0 V to 5 V, fIN = 2 kHz, −60 dB 92.5 93.5 dB VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz, −60 dB 94 dB V = ±10 V, f = 2 kHz, −60 dB 94.5 dB IN IN Signal-to-Noise Ratio V = 0 V to 5 V, 0 V to 10 V, f = 2 kHz 92 93 dB IN IN VIN = ±5 V, ±10 V, fIN = 2 kHz 94 dB Signal-to-(Noise + Distortion) (SINAD) VIN = ±5 V, fIN = 2 kHz 92.5 dB VIN = 0 V to 10 V, ±5 V, fIN = 2 kHz 93 dB V = ±10 V, f = 2 kHz 93.5 dB IN IN Total Harmonic Distortion f = 2 kHz −107 dB IN Spurious-Free Dynamic Range fIN = 2 kHz 107 dB –3 dB Input Bandwidth VIN = 0 V to 5 V 45 MHz Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 500 ns INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 4.965 5.000 5.035 V Temperature Drift –40°C to +85°C ±3 ppm/°C Line Regulation AVDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time C = 22 μF 10 ms REF Rev. 0 | Page 3 of 32 AD7612 Parameter Conditions/Comments Min Typ Max Unit REFERENCE BUFFER PDREF = high REFBUFIN Input Voltage Range 2.4 2.5 2.6 V EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 4.75 5 AVDD + 0.1 V Current Drain 750 kSPS throughput 250 μA TEMPERATURE PIN Voltage Output @ 25°C 311 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.33 kΩ DIGITAL INPUTS Logic Levels VIL −0.3 +0.6 V V 2.1 OVDD + 0.3 V IH I −1 +1 μA IL IIH −1 +1 μA DIGITAL OUTPUTS Data Format Parallel or serial 16-bit 6 Pipeline Delay VOL ISINK = 500 μA 0.4 V V I = –500 μA OVDD − 0.6 V OH SOURCE POWER SUPPLIES Specified Performance 7 AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V VCC 7 15 15.75 V VEE −15.75 −15 0 V 8 , 9 Operating Current @ 750 kSPS throughput AVDD With Internal Reference 19.5 mA With Internal Reference Disabled 18 mA DVDD 6.5 mA OVDD 0.5 mA VCC VCC = 15 V, with internal reference buffer 3 mA VCC = 15 V 2.3 mA VEE VEE = −15 V 2 mA Power Dissipation @ 750 kSPS throughput With Internal Reference PDREF = PDBUF = low 205 230 mW With Internal Reference Disabled PDREF = PDBUF = high 190 210 mW 10 In Power-Down Mode PD = high 10 μW 11 TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +85 °C 1 With V = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 70 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section. IN 2 All specified performance is guaranteed up to 750 kSPS throughout, however throughputs up to 900 kSPS can be used with some linearity performance degradation. 3 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference. 4 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference. 5 All specifications in decibels are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 6 Conversion results are available immediately after completed conversion. 7 4.75 V or V – 0.1 V, whichever is larger. REF 8 Tested in parallel reading mode. 9 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low. 10 With all digital inputs forced to OVDD. 11 Consult sales for extended temperature range. Rev. 0 | Page 4 of 32 AD7612 TIMING SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (See Figure 33 and Figure 34) Convert Pulse Width t1 10 ns Time Between Conversions t2 1 Warp Mode/Normal Mode/Impulse Mode 1.33/1.67/2 μs CNVST Low to BUSY High Delay t 35 ns 3 BUSY High All Modes (Except Master Serial Read After Convert) t 4 Warp Mode/Normal Mode/Impulse Mode 950/1250/1450 ns Aperture Delay t5 2 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time t 7 Warp Mode/Normal Mode/Impulse Mode 950/1250/1450 ns Acquisition Time t8 Warp Mode/Normal Mode/Impulse Mode 380 ns RESET Pulse Width t9 10 ns PARALLEL INTERFACE MODES (See Figure 35 and Figure 37) CNVST Low to DATA Valid Delay t10 Warp Mode/Normal Mode/Impulse Mode 910/1160/1410 ns DATA Valid to BUSY Low Delay t 20 ns 11 Bus Access Request to DATA Valid t 40 ns 12 Bus Relinquish Time t 2 15 ns 13 2 MASTER SERIAL INTERFACE MODES (See Figure 39 and Figure 40) CS Low to SYNC Valid Delay t 10 ns 14 2 t 10 ns CS Low to Internal SDCLK Valid Delay 15 CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay, Read During Convert t17 Warp Mode/Normal Mode/Impulse Mode 65/315/560 ns SYNC Asserted to SDCLK First Edge Delay t 3 ns 18 3 Internal SDCLK Period t 30 45 ns 19 3 Internal SDCLK High t20 15 ns 3 Internal SDCLK Low t21 10 ns 3 SDOUT Valid Setup Time t22 4 ns 3 SDOUT Valid Hold Time t 5 ns 23 3 SDCLK Last Edge to SYNC Delay t 5 ns 24 CS High to SYNC HI-Z t 10 ns 25 CS High to Internal SDCLK HI-Z t26 10 ns CS High to SDOUT HI-Z t27 10 ns 3 BUSY High in Master Serial Read After Convert t28 See Table 4 CNVST Low to SYNC Delay, Read After Convert Warp Mode/Normal Mode/Impulse Mode t 830/1070/1310 ns 29 SYNC Deasserted to BUSY Low Delay t30 25 ns Rev. 0 | Page 5 of 32 AD7612 Parameter Symbol Min Typ Max Unit 2 SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES (See Figure 42, Figure 43, and Figure 45) External SDCLK, SCCLK Setup Time t31 5 ns External SDCLK Active Edge to SDOUT Delay t 2 18 ns 32 SDIN/SCIN Setup Time t 5 ns 33 SDIN/SCIN Hold Time t 5 ns 34 External SDCLK/SCCLK Period t35 25 ns External SDCLK/SCCLK High t36 10 ns External SDCLK/SCCLK Low t37 10 ns 1 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load C of 10 pF; otherwise, the load is 60 pF maximum. L 3 In serial master read during convert mode. See Table 4 for serial master read after convert mode. Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns Internal SDCLK Period Minimum t19 30 60 120 240 ns Internal SDCLK Period Maximum t19 45 90 180 360 ns Internal SDCLK High Minimum t 15 30 60 120 ns 20 Internal SDCLK Low Minimum t 10 25 55 115 ns 21 SDOUT Valid Setup Time Minimum t 4 20 20 20 ns 22 SDOUT Valid Hold Time Minimum t23 5 8 35 90 ns SDCLK Last Edge to SYNC Delay Minimum t24 5 7 35 90 ns BUSY High Width Maximum t28 Warp Mode 1.65 2.35 3.75 6.53 μs Normal Mode 1.9 2.6 4.00 6.78 μs Impulse Mode 2.15 2.85 4.25 7.03 μs 1.6mA I OL TO OUTPUT 1.4V PIN 2V C L 60pF 0.8V t t DELAY DELAY 500µA I OH 2V 2V NOTES 0.8V 0.8V 1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. C L Figure 2. Load Circuit for Digital Interface Timing, Figure 3. Voltage Reference Levels for Timing SDOUT, SYNC, and SCLK Outputs, C = 10 pF L Rev. 0 | Page 6 of 32 06265-002 06265-003 AD7612 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Analog Inputs/Outputs 1 1 rating only; functional operation of the device at these or any IN+ , IN− to AGND VEE − 0.3 V to VCC + 0.3 V other conditions above those indicated in the operational REF, REFBUFIN, TEMP, AVDD + 0.3 V to AGND − 0.3 V section of this specification is not implied. Exposure to absolute REFGND to AGND maximum rating conditions for extended periods may affect Ground Voltage Differences device reliability. AGND, DGND, OGND ±0.3 V Supply Voltages ESD CAUTION AVDD, DVDD, OVDD −0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD ±7 V VCC to AGND, DGND –0.3 V to +16.5 VEE to GND +0.3 V to −16.5 Digital Inputs −0.3 V to OVDD + 0 .3 V 2 PDREF, PDBUF ±20 mA 3 Internal Power Dissipation 700 mW 4 Internal Power Dissipation 2.5 W Junction Temperature 125°C Storage Temperature Range −65°C to +125°C 1 See the Analog Inputs section. 2 See the Voltage Reference Input section. 3 Specification is for the device in free air: 48-Lead LFQP; θJA = 91°C/W, θ = 30°C/W. JC 4 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. Rev. 0 | Page 7 of 32 AD7612 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 36 AGND BIPOLAR PIN 1 2 AVDD 35 CNVST AGND 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS AD7612 6 31 WARP RD TOP VIEW 7 30 IMPULSE TEN (Not to Scale) 8 29 SER/PAR BUSY 9 28 D15/SCCS D0 10 27 D14/SCCLK D1 11 26 D13/SCIN D2/DIVSCLK[0] 12 25 D3/DIVSCLK[1] D12/HW/SW 13 14 15 16 17 18 19 20 21 22 23 24 Figure 4. Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1, 3, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. 4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. 2 5 OB/2C DI Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low, the MSB is inverted resulting in a twos complement output from its internal shift register. 2 6 WARP DI Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following: Conversion Mode WARP IMPULSE Normal Low Low Impulse Low High Warp High Low Normal High High See the Modes of Operation section for a more detailed description. 2 7 IMPULSE DI Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the Modes of Operation section for a more detailed description. 8 SER/PAR DI Serial/Parallel Selection Input. When SER/PAR = low, the parallel mode is selected. When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port and the remaining data bits are high impedance outputs. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the state of SER/PAR. 11, 12 D[2:3] or DI/O In parallel mode, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. DIVSCLK[0:1] Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high, EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial data clock that clocks the data output. In other serial modes, these pins are high impedance outputs. Rev. 0 | Page 8 of 32 D4/EXT/INT PDBUF D5/INVSYNC PDREF D6/INVSCLK REFBUFIN D7/RDC/SDIN TEMP AVDD OGND OVDD IN+ AGND DVDD VEE DGND VCC D8/SDOUT D9/SDCLK IN– D10/SYNC REFGND D11/RDERROR REF 06265-004 AD7612 1 Pin No. Mnemonic Type Description 13 D4 or DI/O In parallel mode, this output is used as Bit 4 of the parallel port data output bus. EXT/INT Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or external (slave) serial data clock for the AD7612 output data. When EXT/INT = low, master mode; the internal serial data clock is selected on SDCLK output. When EXT/INT = high, slave mode; the output data is synchronized to an external clock signal (gated by CS) connected to the SDCLK input. 14 D5 or DI/O In parallel mode, this output is used as Bit 5 of the parallel port data output bus. INVSYNC Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low). This input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D6 or DI/O In parallel mode, this output is used as Bit 6 of the parallel port data output bus. INVSCLK In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK. When INVSCLK = low, the rising edge of SDCLK/SCCLK are used. When INVSCLK = high, the falling edge of SDCLK/SCCLK are used. 16 D7 or DI/O In parallel mode, this output is used as Bit 7 of the parallel port data output bus. RDC or Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low) RDC is used to select the read mode. Refer to the Master Serial Interface section. When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable in this mode. When RDC = high, the previous conversion result is read during the current conversion. SDIN Serial Data In. In serial slave mode (SER/PAR = high EXT/INT = high) SDIN can be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence. 17 OGND P Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be connected to the system digital ground ideally at the same potential as AGND and DGND. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors. 19 DVDD P Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied from AVDD. 20 DGND P Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital ground ideally at the same potential as AGND and OGND. 21 D8 or DO In parallel mode, this output is used as Bit 8 of the parallel port data output bus. SDOUT Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7612 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. When EXT/INT = low, (master mode) SDOUT is valid on both edges of SDCLK. When EXT/INT = high, (slave mode). When INVSCLK = low, SDOUT is updated on SDCLK rising edge. When INVSCLK = high, SDOUT is updated on SDCLK falling edge. 22 D9 or DI/O In parallel mode, this output is used as Bit 9 of the parallel port data output bus. SDCLK Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. 23 D10 or DO In parallel mode, this output is used as Bit 10 of the parallel port data output bus. SYNC Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT output is valid. Rev. 0 | Page 9 of 32 AD7612 1 Pin No. Mnemonic Type Description 24 D11 or DO In parallel mode, this output is used as Bit 11 of the parallel port data output bus. RDERROR Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an incomplete data read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. 25 D12 or DI/O In parallel mode, this output is used as Bit 12 of the parallel port data output bus. HW/SW Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7612 by hardware or software. See the Hardware Configuration section and Software Configuration section. When HW/SW = low, the AD7612 is configured through software using the serial configuration register. When HW/SW = high, the AD7612 is configured through dedicated hardware input pins. 26 D13 or DI/O In parallel mode, this output is used as Bit 13 of the parallel port data output bus. SCIN Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is used to serially write in, MSB first, the configuration data into the serial configuration register. The data on this input is latched with SCCLK. See the Software Configuration section. 27 D14 or DI/O In parallel mode, this output is used as Bit 14 of the parallel port data output bus. SCCLK Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state of the INVSCLK pin. See the Software Configuration section. 28 D15 or DI/O In parallel mode, this output is used as Bit 15 of the parallel port data output bus. SCCS Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input enables the serial configuration port. See the Software Configuration section. 29 BUSY DO Busy Output. Transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal. Note that in master read after convert mode (SER/PAR = high, EXT/INT = low, RDC = low) the busy time changes according to Table 4. 2 30 TEN DI Input Range Select. Used in conjunction with BIPOLAR per the following: Input Range BIPOLAR TEN 0 V to 5 V Low Low 0 V to 10 V Low High ±5 V High Low ±10 V High High 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. 32 DI CS Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode (not used for serial programmable port). 33 RESET DI Reset Input. When high, reset the AD7612. Current conversion, if any, is aborted. The falling edge of RESET resets the data outputs to all zero’s (with OB/2C = high) and clears the configuration register. See the Digital Interface section. If not used, this pin can be tied to OGND. 2 34 PD DI Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. The digital interface remains active during power down. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 2 36 BIPOLAR DI Input Range Select. See description for Pin 30. 37 REF AI/O Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is required with or without the internal reference and buffer. See the Reference Decoupling section. 38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane. 39 IN− AI Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground. 40 VCC P High Voltage Positive Supply. Normally +7 V to +15 V. 41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges). Rev. 0 | Page 10 of 32 AD7612 1 Pin No. Mnemonic Type Description 43 IN+ AI Analog Input. Referenced to IN−. 45 TEMP AO Temperature Sensor Analog Output. 46 REFBUFIN AI Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference Input section. 47 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down, and an external reference must be used. 48 PDBUF DI Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. 2 PAR SW In serial configuration mode (SER/ = high, HW/ = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the Hardware Configuration section and Software Configuration section. Rev. 0 | Page 11 of 32 AD7612 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C. 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.5 –1.0 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 180 180 NEGATIVE INL NEGATIVE DNL POSITIVE INL POSITIVE DNL 160 160 140 140 120 120 100 100 80 80 60 60 40 40 20 20 0 0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 INL DISTRIBUTION (LSB) DNL DISTRIBUTION (LSB) Figure 6. Integral Nonlinearity Distribution (239 Devices) Figure 9. Differential Nonlinearity Distribution (239 Devices) 200k 140k 130570 σ = 0.55 181942 128400 σ = 0.52 180k 120k 160k 100k 140k 120k 80k 100k 60k 80k 60k 40k 47749 40k 31321 20k 20k 1232 00 15 93 0 0 0001 917 0 0 0 0 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 8007 CODE IN HEX CODE IN HEX Figure 7. Histogram of 261,120 Conversions of a DC Input Figure 10. Histogram of 261,120 Conversions of a DC Input at the Code Center at the Code Transition Rev. 0 | Page 12 of 32 INL (LSB) NUMBER OF UNITS COUNTS 06265-007 06265-006 06265-005 DNL (LSB) NUMBER OF UNITS COUNTS 06265-010 06265-009 06265-008 AD7612 0 95.0 f = 750kSPS ±10V SNR S ±5V f = 19.99kHz SINAD IN –20 0V TO +10V SNR = 93.23dB 0V TO +5V THD = –107.5dB SFDR = 113.9dB –40 94.5 SINAD = 93.1dB –60 –80 94.0 –100 –120 93.5 –140 –160 –180 93.0 0 125 250 375 –60 –50 –40 –30 –20 –10 0 FREQUENCY (kHz) INPUT LEVEL (dB) Figure 11. FFT 20 kHz Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale) 96 16.0 –70 120 SNR 110 94 15.8 SFDR SINAD –80 100 92 15.6 90 –90 90 15.4 80 ENOB 88 15.2 –100 70 THD 60 15.0 86 THIRD –110 HARMONIC 50 14.8 84 40 –120 14.6 82 SECOND 30 HARMONIC 14.4 80 –130 20 1 10 100 1 10 100 FREQUENCY (kHz) FREQUENCY (kHz) Figure 12. SNR, SINAD, and ENOB vs. Frequency Figure 15. THD, Harmonics, and SFDR vs. Frequency 96 96 ±10V ±10V ±5V ±5V 0V TO +10V 0V TO +10V 0V TO +5V 0V TO +5V 95 95 94 94 93 93 92 92 91 91 90 90 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. SINAD vs. Temperature Figure 13. SNR vs. Temperature Rev. 0 | Page 13 of 32 SNR, SINAD (dB) SNR (dB) AMPLITUDE (dB of Full Scale) 06265-013 ENOB (Bits) 06265-011 06265-012 THD, HARMONICS (dB) SINAD (dB) SNR, SINAD (dB) SFDR (dB) 06265-014 06265-016 06265-015 AD7612 –96 124 ±10V 0V TO +10V ±5V ±5V –98 0V TO +10V 122 ±10V 0V TO +5V 0V TO +5V –100 120 –102 –104 118 –106 116 –108 114 –110 –112 112 –114 110 –116 108 –118 –120 106 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. THD vs. Temperature Figure 20. SFDR vs. Temperature (Excludes Harmonics) 5 5.002 4 5.001 3 POSITIVE FULL SCALE ERROR 5.000 2 ZERO 1 ERROR 4.999 0 NEGATIVE 4.998 FULL SCALE ERROR –1 –2 4.997 –3 4.996 –4 –5 4.995 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Zero Error, Positive and Negative Full Scale vs. Temperature Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices) 60 100000 10000 50 1000 40 100 30 10 1 AVDD, WARP/NORMAL 20 DVDD, ALL MODES 0.1 AVDD, IMPULSE VCC +15V, VEE –15V, 10 ALL MODES 0.01 OVDD, ALL MODES PDREF = PDBUF = HIGH 0 0.001 08 123 456 7 10 100 1000 10000 100000 1000000 REFERENCE DRIFT (ppm/°C) SAMPLING RATE (SPS) Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices) Figure 22. Operating Currents vs. Sample Rate Rev. 0 | Page 14 of 32 ZERO ERROR, FULL SCALE ERROR (LSB) THD (dB) NUMBER OF UNITS 06265-019 06265-018 06265-017 OPERATING CURRENTS (µA) VREF (V) SFDR (dB) 06265-020 06265-021 06265-022 AD7612 50 700 PD = PDBUF = PDREF = HIGH OVDD = 2.7V @ 85°C 45 600 OVDD = 2.7V @ 25°C 40 500 35 30 400 VEE, –15V 25 OVDD = 5V @ 85°C VCC, +15V 300 DVDD 20 OVDD OVDD = 5V @ 25°C AVDD 15 200 10 100 5 0 0 0 50 100 150 200 –55 –35 –15 5 25 45 65 85 105 TEMPERATURE (°C) C (pF) L Figure 23. Power-Down Operating Currents vs. Temperature Figure 24. Typical Delay vs. Load Capacitance C L Rev. 0 | Page 15 of 32 POWER-DOWN OPERATING CURRENTS (nA) 06265-023 t DELAY (ns) 12 06265-024 AD7612 TERMINOLOGY Least Significant Bit (LSB) Total Harmonic Distortion (THD) The least significant bit, or LSB, is the smallest increment that THD is the ratio of the rms sum of the first five harmonic can be represented by a converter. For an analog-to-digital con- components to the rms value of a full-scale input signal and verter with N bits of resolution, the LSB expressed in volts is is expressed in decibels. V INp-p Signal-to-(Noise + Distortion) Ratio (SINAD) LSB(V)= N 2 SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist Integral Nonlinearity Error (INL) frequency, including harmonics but excluding dc. The value for Linearity error refers to the deviation of each individual code SINAD is expressed in decibels. from a line drawn from negative full-scale through positive full- scale. The point used as negative full-scale occurs a ½ LSB before Spurious-Free Dynamic Range (SFDR) the first code transition. Positive full-scale is defined as a level The difference, in decibels (dB), between the rms amplitude of 1½ LSBs beyond the last code transition. The deviation is meas- the input signal and the peak spurious signal. ured from the middle of each code to the true straight line. Effective Number of Bits (ENOB) Differential Nonlinearity Error (DNL) ENOB is a measurement of the resolution with a sine wave In an ideal ADC, code transitions are 1 LSB apart. Differential input. It is related to SINAD and is expressed in bits by nonlinearity is the maximum deviation from this ideal value. It ENOB = [(SINADdB − 1.76)/6.02] is often specified in terms of resolution for which no missing codes are guaranteed. Aperture Delay Aperture delay is a measure of the acquisition performance Bipolar Zero Error measured from the falling edge of the CNVST input to when The difference between the ideal midscale input voltage (0 V) the input signal is held for a conversion. and the actual voltage producing the midscale output code. Transient Response Unipolar Offset Error The time required for the AD7612 to achieve its rated accuracy The first transition should occur at a level ½ LSB above analog after a full-scale step function is applied to its input. ground. The unipolar offset error is the deviation of the actual transition from that point. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the Full-Scale Error typical shift of output voltage at 25°C on a sample of parts at the The last transition (from 111…10 to 111…11) should occur for maximum and minimum reference output voltage (VREF) meas- an analog voltage 1½ LSB below the nominal full-scale. The full- ured at T , T(25°C), and T . It is expressed in ppm/°C as MIN MAX scale error is the deviation in LSB (or % of full-scale range) of the actual level of the last transition from the ideal level and V (Max)–V (Min) REF REF 6 includes the effect of the offset error. Closely related is the gain TCV ( ppm/°C)= ×10 REF V (25°C)× (T –T ) REF MAX MIN error (also in LSB or % of full-scale range), which does not include the effects of the offset error. where: VREF (Max) = maximum VREF at TMIN, T(25°C), or TMAX. Dynamic Range VREF (Min) = minimum VREF at TMIN, T(25°C), or TMAX. Dynamic range is the ratio of the rms value of the full-scale to VREF (25°C) = VREF at 25°C. the rms noise measured for an input typically at −60 dB. The T = +85°C. MAX value for dynamic range is expressed in decibels. T = –40°C. MIN Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Rev. 0 | Page 16 of 32 AD7612 THEORY OF OPERATION IN+ REF REFGND SWITCHES CONTROL MSB LSB SW A 32,768C 16,384C 4C 2C C C BUSY CONTROL COMP LOGIC IN– OUTPUT 65,536C CODE SW B CNVST Figure 25. ADC Simplified Schematic OVERVIEW CONVERTER OPERATION The AD7612 is a very fast, low power, precise, 16-bit analog-to- The AD7612 is a successive approximation ADC based on a digital converter (ADC) using successive approximation capacitive charge redistribution DAC. Figure 25 shows the simplified digital-to-analog (CDAC) architecture. schematic of the ADC. The CDAC consists of two identical arrays of 16 binary weighted capacitors, which are connected The AD7612 can be configured at any time for one of four input to the two comparator inputs. ranges and conversion mode with inputs in parallel and serial hardware modes or by a dedicated write only, SPI-compatible During the acquisition phase, terminals of the array tied to the interface via a configuration register in serial software mode. comparator’s input are connected to AGND via SW+ and SW−. The AD7612 uses Analog Device’s patented iCMOS high voltage All independent switches are connected to the analog inputs. process to accommodate 0 to 5 V, 0 to 10 V, ±5 V, and ±10 V Thus, the capacitor arrays are used as sampling capacitors and input ranges without the use of conventional thin films. Only acquire the analog signal on IN+ and IN− inputs. A conversion one acquisition cycle, t8, is required for the inputs to latch to the phase is initiated once the acquisition phase is complete and the correct configuration. Resetting or power cycling is not CNVST input goes low. When the conversion phase begins, SW+ required for reconfiguring the ADC. and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND The AD7612 features different modes to optimize performance input. Therefore, the differential voltage between the inputs according to the applications. It is capable of converting 750,000 (IN+ and IN−) captured at the end of the acquisition phase is samples per second (750 kSPS) in warp mode, 600 kSPS in normal applied to the comparator inputs, causing the comparator to mode, and 500 kSPS in impulse mode. become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies The AD7612 provides the user with an on-chip track-and-hold, by binary weighted voltage steps (V /2, V /4 through V / REF REF REF successive approximation ADC that does not exhibit any pipe- 65536). The control logic toggles these switches, starting with line or latency, making it ideal for multiple multiplexed channel the MSB first, in order to bring the comparator back into a applications. balanced condition. For unipolar input ranges, the AD7612 typically requires three After the completion of this process, the control logic generates supplies; VCC, AVDD (which can supply DVDD), and OVDD the ADC output code and brings the BUSY output low. which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic. For bipolar input ranges, the AD7612 requires the use of the additional VEE supply. The device is housed in Pb-free, 48-lead LQFP or tiny LFCSP 7 mm × 7 mm packages that combine space savings with flexi- bility. In addition, the AD7612 can be configured as either a parallel or serial SPI-compatible interface. Rev. 0 | Page 17 of 32 06265-025 AD7612 Impulse Mode MODES OF OPERATION Setting WARP = low and IMPULSE = high uses the lowest power The AD7612 features three modes of operation: warp, normal, dissipation mode and allows power saving between conversions. and impulse. Each of these modes is more suitable to specific The maximum throughput in this mode is 500 kSPS and in this applications. The mode is configured with the input pins, WARP mode, the ADC powers down circuits after conversion making and IMPULSE, or via the configuration register. See Table 6 for the AD7612 ideal for battery-powered applications. the pin details and the Hardware Configuration section and Software Configuration section for programming the mode TRANSFER FUNCTIONS selection with either pins or configuration register. Note that Using the OB/2C digital input or via the configuration register, when using the configuration register, the WARP and IMPULSE the AD7612 offers two output codings: straight binary and twos inputs are don’t cares and should be tied to either high or low. complement. See Figure 26 and Table 7 for the ideal transfer char- acteristic and digital output codes for the different analog input Warp Mode ranges, V . Note that when using the configuration register, the IN Setting WARP = high and IMPULSE = low allow the fastest con- 2C OB/ input is a don’t care and should be tied to either high or low. version rate up to 750 kSPS. However, in this mode, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two 111...111 consecutive conversions is longer than 1 ms (after power-up), 111...110 111...101 the first conversion result should be ignored since in warp mode, the ADC performs a background calibration during the SAR conversion process. This calibration can drift if the time between conversions exceeds 1 ms thus causing the first conversion to appear offset. This mode makes the AD7612 ideal for applications where both high accuracy and fast sample rate are required. In 000...010 addition, the AD7612 can run up to 900 kSPS throughput with 000...001 some performance degradation, mainly dc linearity. 000...000 –FSR + 1 LSB +FSR –1LSB –FSR Normal Mode –FSR + 0.5 LSB +FSR – 1.5 LSB Setting WARP = IMPULSE = low or WARP = IMPULSE = high ANALOG INPUT allows the fastest mode (600 kSPS) without any limitation on Figure 26. ADC Ideal Transfer Function time between conversions. This mode makes the AD7612 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. Table 7. Output Codes and Ideal Input Voltages VREF = 5 V Digital Output Code Description V = 5 V V = 10 V V = ±5 V V = ±10 V Straight Binary Twos Complement IN IN IN IN 1 1 FSR − 1 LSB 4.999924 V 9.999847 V +4.999847 V +9.999695 V 0xFFFF 0x7FFF FSR − 2 LSB 4.999847 V 9.999695 V +4.999695 V +9.999390 V 0xFFFE 0x7FFE Midscale + 1 LSB 2.500076 V 5.000153 V +152.6 μV +305.2 μV 0x8001 0x0001 Midscale 2.5 V 5.000000 V 0 V 0 V 0x8000 0x0000 Midscale − 1 LSB 2.499924 V 4.999847 V −152.6 μV −305.2 μV 0x7FFF 0xFFFF −FSR + 1 LSB 76.3 μV 152.6 μV −4.999847 V −9.999695 V 0x0001 0x8001 2 2 −FSR 0 V 0 V −5 V −10 V 0x0000 0x8000 1 This is also the code for overrange analog input (V − V above V − V ). IN+ IN− REF REFGND 2 This is also the code for overrange analog input (VIN+ − VIN− below VREF − VREFGND). Rev. 0 | Page 18 of 32 ADC CODE (Straight Binary) 06265-026 AD7612 TYPICAL CONNECTION DIAGRAM Figure 27 shows a typical connection diagram for the AD7612 using the internal reference, serial data interface, and serial configuration port. Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections. DIGITAL SUPPLY (5V) NOTE 5 DIGITAL INTERFACE ANALOG SUPPLY SUPPLY (5V) (2.5V, 3.3V, or 5V) 100nF 10µF 10µF 100nF 100nF 10µF AVDD AGND DGND DVDD OVDD OGND +7V TO +15.75V SUPPLY MICROCONVERTER/ VCC BUSY 100nF 10µF MICROPROCESSOR/ DSP SDCLK SERIAL PORT 1 SDOUT 100nF 10µF SCCLK –7V TO –15.75V VEE SERIAL SUPPLY PORT 2 SCIN NOTE 6 NOTE 3 REF SCCS C REF REFBUFIN NOTE 7 22µF NOTE 4 100nF D CNVST REFGND AD7612 OB/2C NOTE 2 OVDD SER/PAR IN+ U1 HW/SW ANALOG INPUT + BIPOLAR C 2.7nF C TEN CLOCK WARP ANALOG IMPULSE IN– NOTE 3 INPUT– NOTE 1 PDREF PDBUF PD RD CS RESET NOTES 1. SEE ANALOG INPUT SECTION. ANALOG INPUT(–) IS REFERENCED TO AGND ±0.1V. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) +2V] and VEE = [VIN(MIN) –2V] FOR BIPOLAR INPUT RANGES. FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLY SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port Rev. 0 | Page 19 of 32 06265-027 AD7612 ANALOG INPUTS For instance, by using IN− to sense a remote signal ground, ground potential differences between the sensor and the local Input Range Selection ADC ground are eliminated. In parallel mode and serial hardware mode, the input range is 100 selected by using the BIPOLAR (bipolar) and TEN (10 Volt range) inputs. See Table 6 for pin details and the Hardware Configuration 90 section and Software Configuration section for programming 80 the mode selection with either pins or configuration register. Note 70 that when using the configuration register, the BIPOLAR and 60 TEN inputs are don’t cares and should be tied to either high or low. 50 Input Structure 40 Figure 28 shows an equivalent circuit for the input structure of 30 the AD7612. 20 0TO 5V 10 RANGE ONLY AVDD VCC 0 1 10 100 1000 10000 FREQUENCY (kHz) D1 D3 C R IN IN IN+ OR IN– Figure 29. Analog Input CMRR vs. Frequency C D2 PIN D4 During the acquisition phase for ac signals, the impedance of VEE the analog inputs, IN+ and IN−, can be modeled as a parallel AGND combination of Capacitor CPIN and the network formed by the Figure 28. AD7612 Simplified Analog Input series connection of RIN and CIN. CPIN is primarily the pin capac- The four diodes, D1 to D4, provide ESD protection for the analog itance. RIN is typically 70 Ω and is a lumped component comprised inputs, IN+ and IN−. Care must be taken to ensure that the analog of serial resistors and the on resistance of the switches. CIN is pri- input signal never exceeds the supply rails by more than 0.3 V, marily the ADC sampling capacitor and depending on the input because this causes the diodes to become forward-biased and to range selected is typically 48 pF in the 0 V to 5 V range, typically 24 pF in the 0 V to 10 V and ±5 V ranges and typically 12 pF in start conducting current. These diodes can handle a forward- the ±10 V range. During the conversion phase, when the switches biased current of 120 mA maximum. For instance, these conditions are opened, the input impedance is limited to C . could eventually occur when the input buffer’s U1 supplies are PIN different from AVDD, VCC, and VEE. In such a case, an input Since the input impedance of the AD7612 is very high, it can be buffer with a short-circuit current limitation can be used to protect directly driven by a low impedance source without gain error. To the part although most op amps’ short circuit current is <100 mA. further improve the noise filtering achieved by the AD7612 analog Note that D3 and D4 are only used in the 0 V to 5 V range to input circuit, an external, one-pole RC filter between the ampli- allow for additional protection in applications that are switching fier’s outputs and the ADC analog inputs can be used, as shown from the higher voltage ranges. in Figure 27. However, large source impedances significantly This analog input structure allows the sampling of the differential affect the ac performance, especially total harmonic distortion signal between IN+ and IN−. By using this differential input, (THD). The maximum source impedance depends on the amount small signals common to both inputs are rejected as shown in of THD that can be tolerated. The THD degrades as a function Figure 29, which represents the typical CMRR over frequency. of the source impedance and the maximum input frequency. Rev. 0 | Page 20 of 32 06265-028 CMRR (dB) 06265-029 AD7612 The AD8021 meets these requirements and is appropriate for DRIVER AMPLIFIER CHOICE almost all applications. The AD8021 needs a 10 pF external Although the AD7612 is easy to drive, the driver amplifier must compensation capacitor that should have good linearity as an meet the following requirements: NPO ceramic or mica type. Moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the • For multichannel, multiplexed applications, the driver best signal-to-noise ratio. amplifier and the AD7612 analog input circuit must be able to settle for a full-scale step of the capacitor array at The AD8022 can also be used when a dual version is needed a 16-bit level (0.0015%). For the amplifier, settling at 0.1% and a gain of 1 is present. The AD829 is an alternative in appli- to 0.01% is more commonly specified. This differs signifi- cations where high frequency (above 100 kHz) performance is not cantly from the settling time at a 16-bit level and should required. In applications with a gain of 1, an 82 pF compensation be verified prior to driver selection. The AD8021 op amp capacitor is required. The AD8610 is an option when low bias combines ultra-low noise and high gain bandwidth and current is needed in low frequency applications. meets this settling time requirement even when used with Since the AD7612 uses a large geometry, high voltage input gains of up to 13. switch, the best linearity performance is obtained when using • The noise generated by the driver amplifier needs to be the amplifier at its maximum full power bandwidth. Gaining kept as low as possible to preserve the SNR and transition the amplifier to make use of the more dynamic range of the noise performance of the AD7612. The noise coming from ADC results in increased linearity errors. For applications the driver is filtered by the external 1-pole low-pass filter requiring more resolution, the use of an additional amplifier as shown in Figure 27. The SNR degradation due to the with gain should precede a unity follower driving the AD7612. amplifier is See Table 8 for a list of recommended op amps. ⎛ ⎞ Table 8. Recommended Driver Amplifiers ⎜ ⎟ V ⎜ ⎟ NADC SNR = 20log Amplifier Typical Application LOSS ⎜ ⎟ π 2 2 ⎜ V + f () Ne ⎟ ADA4841-x 12 V supply, very low noise, low distortion, ⎜ NADC −3dB N ⎟ 2 ⎝ ⎠ low power, low frequency AD829 ±15 V supplies, very low noise, low frequency where: AD8021 ±12 V supplies, very low noise, high frequency VNADC is the noise of the ADC, which is: AD8022 ±12 V supplies, very low noise, high V frequency, dual INp-p 2 2 AD8610/AD8620 ±13 V supplies, low bias current, low V = NADC SNR frequency, single/dual 20 10 VOLTAGE REFERENCE INPUT/OUTPUT f is the cutoff frequency of the input filter (3.9 MHz). –3dB N is the noise factor of the amplifier (+1 in buffer The AD7612 allows the choice of either a very low temperature configuration). drift internal voltage reference, an external reference or an external buffered reference. eN is the equivalent input voltage noise density of the op amp, in nV/√Hz. The internal reference of the AD7612 provides excellent perfor- mance and can be used in almost all applications. However, the • The driver needs to have a THD performance suitable to linearity performance is guaranteed only with an external reference. that of the AD7612. Figure 15 shows the THD vs. frequency that the driver should exceed. Rev. 0 | Page 21 of 32 AD7612 Temperature Sensor Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) The TEMP pin measures the temperature of the AD7612. To improve the calibration accuracy over the temperature range, the To use the internal reference, the PDREF and PDBUF inputs output of the TEMP pin is applied to one of the inputs of the must be low. This enables the on-chip band gap reference, buffer, analog switch (such as ADG779), and the ADC itself is used to and TEMP sensor resulting in a 5.00 V reference on the REF pin. measure its own temperature. This configuration is shown The internal reference is temperature-compensated to 5.000 V in Figure 30. ±35 mV. The reference is trimmed to provide a typical drift of TEMP Figure 19. 3 ppm/°C. This typical drift characteristic is shown in ADG779 AD8021 External 2.5 V Reference and Internal Buffer (REF = 5 V) TEMPERATURE ANALOG INPUT IN+ SENSOR (UNIPOLAR) (PDREF = High, PDBUF = Low) AD7612 C C To use an external reference with the internal buffer, PDREF should be high and PDBUF should be low. This powers down Figure 30. Use of the Temperature Sensor the internal reference and allows the 2.5 V reference to be applied POWER SUPPLIES to REFBUFIN producing 5 V on the REF pin. The internal ref- erence buffer is useful in multiconverter applications since a The AD7612 uses five sets of power supply pins: buffer is typically required in these applications. • AVDD: analog 5 V core supply External 5 V Reference (PDREF = High, PDBUF = High) • VCC: analog high voltage positive supply To use an external reference directly on the REF pin, PDREF and PDBUF should both be high. PDREF and PDBUF power • VEE: high voltage negative supply down the internal reference and the internal reference buffer, respectively. For improved drift performance, an external ref- • DVDD: digital 5 V core supply erence such as the ADR445 or ADR435 is recommended. • OVDD: digital input/output interface supply Reference Decoupling Core Supplies Whether using an internal or external reference, the AD7612 The AVDD and DVDD supply the AD7612 analog and digital voltage reference input (REF) has a dynamic input impedance; cores respectively. Sufficient decoupling of these supplies is therefore, it should be driven by a low impedance source with required consisting of at least a 10 μF capacitor and 100 nF on efficient decoupling between the REF and REFGND inputs. This each supply. The 100 nF capacitors should be placed as close as decoupling depends on the choice of the voltage reference, but possible to the AD7612. To reduce the number of supplies needed, usually consists of a low ESR capacitor connected to REF and the DVDD can be supplied through a simple RC filter from the REFGND with minimum parasitic inductance. A 22 μF (X5R, analog supply, as shown in Figure 27. 1206 size) ceramic chip capacitor (or 47 μF tantalum capacitor) is appropriate when using either the internal reference or the High Voltage Supplies ADR445/ADR435 external reference. The high voltage bipolar supplies, VCC and VEE are required The placement of the reference decoupling is also important to and must be at least 2 V larger than the maximum input, V . IN the performance of the AD7612. The decoupling capacitor should For example, if using the bipolar 10 V range, the supplies should be mounted on the same side as the ADC right at the REF pin be ±12 V minimum. Sufficient decoupling of these supplies is with a thick PCB trace. The REFGND should also connect to also required consisting of at least a 10 μF capacitor and 100 nF the reference decoupling capacitor with the shortest distance on each supply. For unipolar operation, the VEE supply can be and to the analog ground plane with several vias. grounded with some slight THD performance degradation. For applications that use multiple AD7612 or other PulSAR Digital Output Supply devices, it is more effective to use the internal reference buffer The OVDD supplies the digital outputs and allows direct interface to buffer the external 2.5 V reference voltage. with any logic working between 2.3 V and 5.25 V. OVDD should be set to the same level as the system interface. Sufficient decou- The voltage reference temperature coefficient (TC) directly impacts pling is required consisting of at least a 10 μF capacitor and 100 nF full scale; therefore, in applications where full-scale accuracy with the 100 nF placed as close as possible to the AD7612. matters, care must be taken with the TC. For instance, a ±15 ppm/°C TC of the reference changes full-scale by ±1 LSB/°C. Rev. 0 | Page 22 of 32 06265-030 AD7612 Power Down Power Sequencing Setting PD = high powers down the AD7612, thus reducing The AD7612 is independent of power supply sequencing and is supply currents to their minimums as shown in Figure 23. When very insensitive to power supply variations on AVDD over a wide the ADC is in power down, the current conversion (if any) is frequency range as shown in Figure 31. completed and the digital bus remains active. To further reduce 80 the digital supply currents, drive the inputs to OVDD or OGND. EXT REF 75 INT REF Power down can also be programmed with the configuration 70 register. See the Software Configuration section for details. Note 65 that when using the configuration register, the PD input is a 60 don’t care and should be tied to either high or low. 55 CONVERSION CONTROL 50 CNVST The AD7612 is controlled by the input. A falling edge 45 CNVST on is all that is necessary to initiate a conversion. Detailed 40 timing diagrams of the conversion process are shown in Figure 33. 35 Once initiated, it cannot be restarted or aborted, even by the 30 power-down input, PD, until the conversion is complete. The 1 10 100 1000 10000 CNVST CS RD signal operates independently of and signals. FREQUENCY (kHz) Figure 31. AVDD PSRR vs. Frequency t 2 t 1 Power Dissipation vs. Throughput CNVST In impulse mode, the AD7612 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows BUSY t 4 a significant power savings when the conversion rate is reduced t 3 t (see Figure 32). This feature makes the AD7612 ideal for very 6 t 5 low power, battery-operated applications. MODE ACQUIRE CONVERT ACQUIRE CONVERT It should be noted that the digital interface remains active even t t 7 8 during the acquisition phase. To reduce the operating digital supply Figure 33. Basic Conversion Timing currents even further, drive the digital inputs close to the power Although CNVST is a digital signal, it should be designed with rails (that is, OVDD and OGND). special care with fast, clean edges, and levels with minimum 1000 PDREF = PDBUF = HIGH overshoot, undershoot, or ringing. CNVST The trace should be shielded with ground and a low value (such as 50 Ω) serial resistor termination should be added close WARP MODE POWER 100 to the output of the component that drives this line. For applications where SNR is critical, the CNVST signal should have very low jitter. This can be achieved by using a dedicated 10 CNVST CNVST IMPULSE MODE POWER oscillator for generation, or by clocking with a high frequency, low jitter clock, as shown in Figure 27. 1 1 10 100 1000 SAMPLING RATE (kSPS) Figure 32. Power Dissipation vs. Sample Rate Rev. 0 | Page 23 of 32 PSRR (dB) POWER DISSIPATION (mW) 06265-032 06265-031 06265-033 AD7612 INTERFACES CS = RD = 0 DIGITAL INTERFACE t 1 CNVST The AD7612 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The t 10 serial interface is multiplexed on the parallel data bus. The AD7612 BUSY digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In t 4 t 3 most applications, the OVDD supply pin is connected to the host t 11 system interface 2.5 V to 5.25 V digital supply. Finally, by using DATA PREVIOUS CONVERSION DATA NEW DATA the OB/2C input pin, both twos complement or straight binary BUS coding can be used. Figure 35. Master Parallel Data Timing for Reading (Continuous Read) CS RD Two signals, and , control the interface. When at least one of Slave Parallel Interface these signals is high, the interface outputs are in high impedance. In slave parallel reading mode, the data can be read either after CS Usually, allows the selection of each AD7612 in multi-circuit each conversion, which is during the next acquisition phase, or applications and is held low in a single AD7612 design. RD is gen- during the following conversion, as shown in Figure 36 and erally used to enable the conversion result on the data bus. Figure 37, respectively. When the data is read during the conver- RESET sion, it is recommended that it is read only during the first half of the conversion phase. This avoids any potential feedthrough The RESET input is used to reset the AD7612. A rising edge on between voltage transients on the digital interface and the most RESET aborts the current conversion (if any) and tristates the critical analog conversion circuitry. data bus. The falling edge of RESET resets the AD7612 and clears the data bus and configuration register. See Figure 34 for the CS RESET timing details. t 9 RESET RD BUSY BUSY DATA BUS t 8 DATA CURRENT BUS CONVERSION CNVST t t 12 13 Figure 34. RESET Timing Figure 36. Slave Parallel Data Timing for Reading (Read After Convert) PARALLEL INTERFACE The AD7612 is configured to use the parallel interface when CS = 0 SER/PAR is held low. CNVST, t 1 RD Master Parallel Interface CS RD Data can be continuously read by tying and low, thus requiring minimal microprocessor connections. However, in BUSY t 4 this mode, the data bus is always driven and cannot be used in t 3 shared bus applications (unless the device is held in RESET). Figure 35 details the timing for this mode. DATA PREVIOUS BUS CONVERSION t t 12 13 Figure 37. Slave Parallel Data Timing for Reading (Read During Convert) Rev. 0 | Page 24 of 32 06265-034 06265-036 06265-037 06265-035 AD7612 MASTER SERIAL INTERFACE 8-Bit Interface (Master or Slave) The pins multiplexed on D[10:2] and used for master serial inter- The BYTESWAP pin allows a glueless interface to an 8-bit bus. face are DIVSCLK[0], DIVSCLK[1], EXT/INT, INVSYNC, As shown in Figure 38, when BYTESWAP is low, the LSB byte is INVSCLK, RDC, SDOUT, SDCLK and SYNC. output on D[7:0] and the MSB is output on D[15:8]. When BYTESWAP is high, the LSB and MSB bytes are swapped; the PAR INT Internal Clock (SER/ = high, EXT/ = Low) LSB is output on D[15:8] and the MSB is output on D[7:0]. By The AD7612 is configured to generate and provide the serial connecting BYTESWAP to an address line, the 16-bit data can data clock, SDCLK, when the EXT/INT pin is held low. The be read in two bytes on either D[15:8] or D[7:0]. This interface can be used in both master and slave parallel reading modes. AD7612 also generates a SYNC signal to indicate to the host when the serial data is valid. The SDCLK, and the SYNC sig- nals can be inverted, if desired using the INVSCLK and INVSYNC CS inputs, respectively. Depending on the input, RDC, the data can be read during the following conversion or after each conver- RD sion. Figure 39 and Figure 40 show detailed timing diagrams of these two modes. BYTESWAP Read During Convert (RDC = High) Setting RDC = high allows the master read (previous conversion HI-Z HI-Z PINS D[15:8] HIGH BYTE LOW BYTE result) during conversion mode. Usually, because the AD7612 is t t t 12 12 13 used with a fast throughput, this mode is the most recommended HI-Z HI-Z PINS D[7:0] LOW BYTE HIGH BYTE serial mode. In this mode, the serial clock and data toggle at appro- priate instances, minimizing potential feed through between digital Figure 38. 8-Bit and 16-Bit Parallel Interface activity and critical conversion decisions. In this mode, the SDCLK period changes since the LSBs require more time to settle and SERIAL INTERFACE the SDCLK is derived from the SAR conversion cycle. In this The AD7612 has a serial interface (SPI-compatible) multiplexed mode, the AD7612 generates a discontinuous SDCLK of two on the data pins D[15:2]. The AD7612 is configured to use the different periods and the host should use an SPI interface. PAR serial interface when SER/ is held high. Read During Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) Data Interface Setting RDC = low allows the read after conversion mode. Unlike The AD7612 outputs 16 bits of data, MSB first, on the SDOUT the other serial modes, the BUSY signal returns low after the 16 pin. This data is synchronized with the 16 clock pulses provided data bits are pulsed out and not at the end of the conversion phase, on the SDCLK pin. The output data is valid on both the rising resulting in a longer BUSY width (refer to Table 4 for BUSY timing and falling edge of the data clock. specifications). The DIVSCLK[1:0] inputs control the SDCLK Serial Configuration Interface period and SDOUT data rate. As a result, the maximum through- The AD7612 can be configured through the serial configuration put cannot be achieved in this mode. In this mode, the AD7612 register only in serial mode as the serial configuration pins are also generates a discontinuous SDCLK however, a fixed period and also multiplexed on the data pins D[15:12]. Refer to the Hardware hosts supporting both SPI and serial ports can also be used. Configuration section and Software Configuration section for more information. Rev. 0 | Page 25 of 32 06265-038 AD7612 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 EXT/INT = 0 CS, RD t 3 CNVST BUSY t 28 t 30 t 29 t 25 SYNC t t 18 14 t 19 t t t 24 20 21 t 26 12 3 14 15 16 SDCLK t 15 t 27 SDOUT D15 D14 D2 D1 D0 X t t 16 23 t 22 Figure 39. Master Serial Data Timing for Reading (Read After Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t 1 CNVST t 3 BUSY t 17 t 25 SYNC t t 19 14 t t 20 21 t 24 t 26 t 15 SDCLK 12 3 14 15 16 t 18 t 27 SDOUT X D15 D14 D2 D1 D0 t t 16 23 t 22 Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 26 of 32 06265-040 06265-039 AD7612 edge of SDCLK used to shift out the data on SDOUT (SDCLK SLAVE SERIAL INTERFACE falling edge when INVSCLK = low). Therefore, the MSB of the The pins multiplexed on D[11:4] used for slave serial upstream converter follows the LSB of the downstream con- interface are: EXT/INT, INVSCLK, SDIN, SDOUT, verter on the next SDCLK cycle. In this mode, the 40 MHz SDCLK and RDERROR. SDCLK rate cannot be used since the SDIN to SDCLK setup time, t33, is less than the minimum time specified. (SDCLK to PAR INT External Clock (SER/ = High, EXT/ = High) SDOUT delay, t32, is the same for all converters when simul- Setting the EXT/INT = high allows the AD7612 to accept an taneously sampled). For proper operation, the SDCLK edge for externally supplied serial data clock on the SDCLK pin. In this latching SDIN (or ½ period of SDCLK) needs to be: mode, several methods can be used to read the data. The exter- t = t + t 1 / 2SDCLK 32 33 nal serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following Or the max SDCLK frequency needs to be: conversion. A clock can be either normally high or normally low 1 f = SDCLK when inactive. For detailed timing diagrams, see Figure 42 and 2(t + t ) 32 33 Figure 43. If not using the daisy-chain feature, the SDIN input should be While the AD7612 is performing a bit decision, it is important tied either high or low. that voltage transients be avoided on digital input/output pins, BUSY or degradation of the conversion result may occur. This is par- OUT ticularly important during the last 475 ns of the conversion phase BUSY BUSY because the AD7612 provides error correction circuitry that can AD7612 AD7612 correct for an improper bit decision made during the first part #2 #1 (UPSTREAM) (DOWNSTREAM) of the conversion phase. For this reason, it is recommended that DATA RDC/SDIN SDOUT RDC/SDIN SDOUT any external clock provided, is a discontinuous clock that transi- OUT tions only when BUSY is low, or, more importantly, that it does not CNVST CNVST transition during the last 475 ns of BUSY high. CS CS SCLK SCLK External Discontinuous Clock Data Read After Conversion SCLK IN Though the maximum throughput cannot be achieved using CS IN CNVST IN this mode, it is the most recommended of the serial slave modes. Figure 41. Two AD7612 Devices in a Daisy-Chain Configuration Figure 42 shows the detailed timing diagrams for this method. After a conversion is complete, indicated by BUSY returning low, External Clock Data Read During Previous Conversion CS RD the conversion result can be read while both and are low. Figure 43 shows the detailed timing diagrams for this method. Data is shifted out MSB first with 16 clock pulses and, depending CS RD During a conversion, while both and are low, the result on the SDCLK frequency, can be valid on the falling and rising of the previous conversion can be read. Data is shifted out MSB edges of the clock. first with 16 clock pulses and, depending on the SDCLK frequency, One advantage of this method is that conversion performance is can be valid on the falling and rising edges of the clock. The not degraded because there are no voltage transients on the digital 16 bits have to be read before the current conversion is complete; interface during the conversion process. Another advantage is otherwise, RDERROR is pulsed high and can be used to interrupt the ability to read the data at any speed up to 40 MHz, which the host interface to prevent incomplete data reading. accommodates both the slow digital host interface and the fastest To reduce performance degradation due to digital activity, a fast serial reading. discontinuous clock of at least 40 MHz is recommended to ensure Daisy-Chain Feature that all the bits are read during the first half of the SAR Also in the read after convert mode, the AD7612 provides a daisy- conversion phase. chain feature for cascading multiple converters together using The daisy-chain feature should not be used in this mode since the serial data input, SDIN, pin. This feature is useful for reduce- digital activity occurs during the second half of the SAR ing component count and wiring connections when desired, for conversion phase likely resulting in performance degradation. instance, in isolated multiconverter applications. See Figure 42 for the timing details. An example of the concatenation of two devices is shown in Figure 41. Simultaneous sampling is possible by using a common CNVST signal. Note that the SDIN input is latched on the opposite Rev. 0 | Page 27 of 32 06265-041 AD7612 discontinuous SDCLK whenever possible to minimize potential External Clock Data Read After/During Conversion incorrect bit decisions. For the different modes, the use of a slower It is also possible to begin to read data after conversion and SDCLK such as 20 MHz in warp mode, 15 MHz in normal mode continue to read the last bits after a new conversion has been and 13 MHz in impulse mode can be used. initiated. This method allows the full throughput and the use of a slower SDCLK frequency. Again, it is recommended to use a SER/PAR = 1 EXT/INT = 1 INVSCLK = 0 RD = 0 CS BUSY t t t t 31 35 36 31 SDCLK X* 1 2 3 4 14 15 16 17 18 19 t 32 t 37 SDOUT D15 D14 X15 X14 D13 D2 D1 D0 t 16 SDIN X15 X14 X13 X2 X1 X0 Y15 Y14 t t 33 34 *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 42. Slave Serial Data Timing for Reading (Read After Convert) SER/PAR = 1 EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t t t t 31 35 36 31 SDCLK X* X* X* X* X* X* 123 15 16 t 32 t 37 SDOUT D15 D14 D1 D0 DATA = SDIN t t 16 27 *A DISCONTINUOUS SDCLK IS RECOMMENDED. Figure 43. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. 0 | Page 28 of 32 06265-043 06265-042 AD7612 HARDWARE CONFIGURATION recommended to write to the SCP during the last 475 ns of con- version (BUSY = high) or performance degradation can result. The AD7612 can be configured at any time with the dedicated In addition, the SCP can be accessed in both serial master and hardware pins WARP, IMPULSE, BIPOLAR, TEN, OB/2C, and serial slave read during and read after convert modes. PAR PD for parallel mode (SER/ = low) or serial hardware mode PAR SW (SER/ = high, HW/ = high). Programming the AD7612 Note that at power up, the configuration register is undefined. for mode selection and input range configuration can be done The RESET input clears the configuration register (sets all bits before or during conversion. Like the RESET input, the ADC to 0), thus placing the configuration to 0 V to 5 V input, normal requires at least one acquisition time to settle as indicated in mode, and twos complemented output. Figure 44. See Table 6 for pin descriptions. Note that these inputs Table 9. Configuration Register Description are high impedance when using the software configuration mode. Bit Name Description 8 START SCCS START bit. With the SCP enabled ( = low), SOFTWARE CONFIGURATION when START is high, the first rising edge of SCCLK The pins multiplexed on D[15:12] used for software configura- (INVSCLK = low) begins to load the register with the new configuration. tion are: HW/SW, SCIN, SCCLK, and SCCS. The AD7612 is 7 BIPOLAR Input Range Select. Used in conjunction with programmed using the dedicated write-only serial configurable Bit 6, TEN, per the following: port (SCP) for conversion mode, input range selection, output Input Range BIPOLAR TEN coding, and power-down using the serial configuration register. 0 V to 5 V Low Low See Table 9 for details of each bit in the configuration register. 0 V to 10 V Low High The SCP can only be used in serial software mode selected with ±5 V High Low PAR SW SER/ = high and HW/ = low since the port is multiplexed ±10 V Low High on the parallel interface. 6 TEN Input Range Select. See Bit 7, BIPOLAR. 5 PD Power Down. The SCP is accessed by asserting the port’s chip select, SCCS, PD = Low, normal operation. and then writing SCIN synchronized with SCCLK, which (like PD = High, power down the ADC. The SCP is accessi- ble while in power down. To power up the ADC, SDCLK) is edge sensitive depending on the state of INVSCLK. write PD = low on the next configuration setting. See Figure 45 for timing details. SCIN is clocked into the con- 4 IMPULSE Mode Select. Used in conjunction with Bit 3, figuration register MSB first. The configuration register is an WARP per the following: th internal shift register that begins with Bit 8, the start bit. The 9 Mode WARP IMPULSE SPPCLK edge updates the register and allows the new settings to be Normal Low Low used. As indicated in the timing diagram, at least one acquisition Impulse Low High th time is required from the 9 SCCLK edge. Bits [1:0] are reserved Warp High Low bits and are not written to while the SCP is being updated. Normal High High 3 WARP Mode Select. See Bit 4, IMPULSE. The SCP can be written to at any time, up to 40 MHz, and it is 2 OB/2C Output Coding recommended to write to while the AD7612 is not busy convert- OB/2C = Low, use twos complement output. ing, as detailed in Figure 45. In this mode, the full 750 kSPS is not 2C OB/ = High, use straight binary output. attainable because the time required for SCP access is (t + 8 × 1/ 31 1 RSV Reserved. SCCLK +t8) minimum. If the full throughput is required, the 0 RSV Reserved. SCP can be written to during conversion, however it is not HW/SW = 0 PD = 0 SER/PAR = 0, 1 t t 8 8 CNVST BUSY BIPOLAR, TEN WARP, IMPULSE Figure 44. Hardware Configuration Timing Rev. 0 | Page 29 of 32 06265-044 AD7612 WARP = 0 OR 1 BIP = 0 OR 1 SER/PAR = 1 INVSCLK = 0 t IMPULSE = 0 OR 1 TEN = 0 OR 1 HW/SW = 0 PD = 0 8 CNVST BUSY t 31 SCCS t t t 31 35 36 SCCLK 123 4 5 67 89 t 37 t 34 SCIN X BIPOLAR TEN PD IMPULSE WARP OB/2C START X t 33 Figure 45. Serial Configuration Port Timing MICROPROCESSOR INTERFACING the DSP. The serial peripheral interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, clock polarity bit The AD7612 is ideally suited for traditional dc measurement (CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable applications supporting a microprocessor, and ac signal processing (TIMOD) = 0 by writing to the SPI control register (SPICLTx). applications interfacing to a digital signal processor. The AD7612 is designed to interface with a parallel 8-bit or 16-bit wide It should be noted that to meet all timing requirements, the SPI interface, or with a general-purpose serial port or I/O ports on a clock should be limited to 17 Mbps allowing it to read an ADC microcontroller. A variety of external buffers can be used with result in less than 1 μs. When a higher sampling rate is desired, the AD7612 to prevent digital noise from coupling into the ADC. use one of the parallel interface modes. SPI Interface DVDD 1 1 AD7612 ADSP-219x The AD7612 is compatible with SPI and QSPI digital hosts and DSPs such as Blackfin® ADSP-BF53x and ADSP-218x/ADSP-219x. SER/PAR BUSY PFx Figure 46 shows an interface diagram between the AD7612 and EXT/INT CS SPIxSEL (PFx) the SPI-equipped ADSP-219x. To accommodate the slower speed SDOUT MISOx RD SCLK SCKx of the DSP, the AD7612 acts as a slave device, and data must be INVSCLK CNVST PFx OR TFSx read after conversion. This mode also allows the daisy-chain feature. The convert command could be initiated in response to 1 ADDITIONAL PINS OMITTED FOR CLARITY. an internal timer interrupt. Figure 46. Interfacing the AD7612 to SPI Interface The reading process can be initiated in response to the end-of- conversion signal (BUSY going low) using an interrupt line of Rev. 0 | Page 30 of 32 06265-046 06265-045 AD7612 APPLICATION INFORMATION LAYOUT GUIDELINES The DVDD supply of the AD7612 can be either a separate supply or come from the analog supply, AVDD, or from the digital inter- While the AD7612 has very good immunity to noise on the face supply, OVDD. When the system digital supply is noisy, or power supplies, exercise care with the grounding layout. To facil- fast switching digital signals are present, and no separate supply is itate the use of ground planes that can be easily separated, design available, it is recommended to connect the DVDD digital supply the printed circuit board that houses the AD7612 so that the to the analog supply AVDD through an RC filter, and to connect analog and digital sections are separated and confined to certain the system supply to the interface digital supply OVDD and the areas of the board. Digital and analog ground planes should be remaining digital circuitry. See Figure 27 for an example of this joined in only one place, preferably underneath the AD7612, or configuration. When DVDD is powered from the system supply, as close as possible to the AD7612. If the AD7612 is in a system it is useful to insert a bead to further reduce high frequency spikes. where multiple devices require analog-to-digital ground connec- tions, the connections should still be made at one point only, a The AD7612 has four different ground pins: REFGND, AGND, star ground point, established as close as possible to the AD7612. DGND, and OGND. To prevent coupling noise onto the die, avoid radiating noise, • REFGND senses the reference voltage and, because it carries and to reduce feedthrough: pulsed currents, should be a low impedance return to the reference. • Do not run digital lines under the device. • AGND is the ground to which most internal ADC analog • Do run the analog ground plane under the AD7612. signals are referenced; it must be connected with the least CNVST resistance to the analog ground plane. • Do shield fast switching signals, like or clocks, with digital ground to avoid radiating noise to other sections of • DGND must be tied to the analog or digital ground plane the board, and never run them near analog signal paths. depending on the configuration. • Avoid crossover of digital and analog signals. • OGND is connected to the digital system ground. • Run traces on different but close layers of the board, at right The layout of the decoupling of the reference voltage is important. angles to each other, to reduce the effect of feedthrough through To minimize parasitic inductances, place the decoupling capacitor the board. close to the ADC and connect it with short, thick traces. The power supply lines to the AD7612 should use as large a trace EVALUATING PERFORMANCE as possible to provide low impedance paths and reduce the effect A recommended layout for the AD7612 is outlined in the EVAL- of glitches on the power supply lines. Good decoupling is also AD7612CB evaluation board documentation. The evaluation important to lower the impedance of the supplies presented to board package includes a fully assembled and tested evaluation the AD7612, and to reduce the magnitude of the supply spikes. board, documentation, and software for controlling the board Decoupled ceramic capacitors, typically 100 nF, should be placed from a PC via the EVAL-CONTROL BRD3. on each of the power supplies pins, AVDD, DVDD, and OVDD, VCC, and VEE. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. Rev. 0 | Page 31 of 32 PAD AD7612 OUTLINE DIMENSIONS 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 48 37 1 36 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 (PINS DOWN) 0.20 6.80 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 47. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 25 12 0.40 24 13 0.30 0.25 MIN 5.50 REF PADDLE CONNECTED TO VEE. 0.80 MAX 1.00 THIS CONNECTION IS NOT 12° MAX 0.65 TYP REQUIRED TO MEET THE 0.85 0.05 MAX ELECTRICAL PERFORMANCES. 0.80 0.02 NOM COPLANARITY 0.50 BSC 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7612BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7612BCPZ-RL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 1 AD7612BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 1 AD7612BSTZ-RL −40°C to +85°C 48-Lead Low Profile Quad Flat Package (LQFP) ST-48 2 EVAL-AD7612CB Evaluation Board 3 EVAL-CONTROL BRD3 Controller Board 1 Z = Pb-free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices. evaluation boards ending with the CB designators. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06265-0-10/06(0) Rev. 0 | Page 32 of 32 051706-A