ANALOG DEVICES AD7609

8-Channel Differential DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC Data Sheet AD7609 FEATURES APPLICATIONS 8 simultaneously sampled inputs Power line monitoring and protection systems True differential inputs Multiphase motor control True bipolar analog input ranges: ±10 V, ±5 V Instrumentation and control systems Single 5 V analog supply and 2.3 V to 5.25 V V Multiaxis positioning systems DRIVE Fully integrated data acquisition solution Data acquisition systems (DAS) Analog input clamp protection COMPANION PRODUCTS Input buffer with 1 MΩ analog input impedance External References: ADR421, ADR431 Second-order antialiasing analog filter Digital Isolators: ADuM1402, ADuM5000, ADuM5402 On-chip accurate reference and reference buffer Power: ADIsimPower, Supervisor Parametric Search 18-bit ADC with 200 kSPS on all channels Additional companion products on the AD7609 product page Oversampling capability with digital filter Flexible parallel/serial interface Table 1. High Resolution, Bipolar Input, Simultaneous SPI/QSPI™/MICROWIRE™/DSP compatible Sampling DAS Solutions Performance Single- True Number of 7 kV ESD rating on analog input channels Ended Differential Simultaneous 98 dB SNR, −107 dB THD Resolution Inputs Inputs Sampling Channels Dynamic range: up to 105 dB typical 1 18 Bits AD7608 AD7609 8 Low power: 100 mW 16 Bits AD7606 8 Standby mode: 25 mW AD7606-6 6 64-lead LQFP package AD7606-4 4 14 Bits AD7607 8 1 Patent pending. FUNCTIONAL BLOCK DIAGRAM AV AV REGCAP REGCAP REFCAPB REFCAPA CC CC 1MΩ R FB V1+ CLAMP T/H SECOND- V1– CLAMP 2.5V 2.5V ORDER LPF R 1MΩ FB LDO LDO 1MΩ R FB REFIN/REFOUT V2+ CLAMP T/H SECOND- V2– CLAMP ORDER LPF R FB 1MΩ REF SELECT 2.5V REF AGND 1MΩ R FB V3+ CLAMP T/H OS 2 SECOND- V3– CLAMP ORDER LPF R 1MΩ FB OS 1 OS 0 1MΩ R FB V4+ CLAMP T/H D A SECOND- OUT V4– CLAMP ORDER LPF SERIAL R 1MΩ FB D B OUT 8:1 MUX PARALLEL/ 1MΩ R RD/SCLK FB 18-BIT DIGITAL V5+ CLAMP SERIAL SAR FILTER CS T/H SECOND- INTERFACE V5– CLAMP ORDER LPF R 1MΩ FB PAR/SER SEL V DRIVE 1MΩ R FB V6+ CLAMP T/H SECOND- PARALLEL DB[15:0] V6– CLAMP ORDER LPF R 1MΩ FB AD7609 1MΩ R FB V7+ CLAMP T/H SECOND- V7– CLAMP ORDER LPF CLK OSC R FB 1MΩ 1MΩ R FB BUSY CONTROL V8+ CLAMP T/H INPUTS SECOND- FRSTDATA V8– CLAMP ORDER LPF R 1MΩ FB AGND CONVST A CONVST B RESET RANGE Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09760-001 AD7609 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Converter Details ....................................................................... 21 Applications ....................................................................................... 1 Analog Input ............................................................................... 21 Companion Products ....................................................................... 1 ADC Transfer Function ............................................................. 22 Functional Block Diagram .............................................................. 1 Internal/External Reference ...................................................... 23 Revision History ............................................................................... 2 Typical Connection Diagram ................................................... 24 General Description ......................................................................... 3 Power-Down Modes .................................................................. 24 Specifications ..................................................................................... 4 Conversion Control ................................................................... 25 Timing Specifications .................................................................. 7 Digital Interface .............................................................................. 26 Absolute Maximum Ratings .......................................................... 11 Parallel Interface (PAR/SER SEL = 0) ...................................... 26 Thermal Resistance .................................................................... 11 Serial Interface (PAR/SER SEL = 1) ......................................... 26 ESD Caution ................................................................................ 11 Reading During Conversion ..................................................... 27 Pin Configuration and Function Descriptions ........................... 12 Digital Filter ................................................................................ 28 Typical Performance Characteristics ........................................... 15 Layout Guidelines....................................................................... 32 Terminology .................................................................................... 19 Outline Dimensions ....................................................................... 34 Theory of Operation ...................................................................... 21 Ordering Guide .......................................................................... 34 REVISION HISTORY 2/12—Rev. 0 to Rev. A Changes to Analog Input Ranges Section .................................... 21 7/11—Revision 0: Initial Version Rev. A | Page 2 of 36 Data Sheet AD7609 GENERAL DESCRIPTION The AD7609 is an 18-bit, 8-channel, true differential, The AD7609 operates from a single 5 V supply and can simultaneous sampling analog-to-digital data acquisition accommodate ±10 V and ±5 V true bipolar differential input system (DAS). The part contains analog input clamp protection, signals while sampling at throughput rates up to 200 kSPS for a second-order antialiasing filter, a track-and-hold amplifier, an all channels. The input clamp protection circuitry can tolerate 18-bit charge redistribution successive approximation analog- voltages up to ±16.5 V. The AD7609 has 1 MΩ analog input to-digital converter (ADC), a flexible digital filter, a 2.5 V impedance regardless of sampling frequency. The single supply reference and reference buffer, and high speed serial and operation, on-chip filtering, and high input impedance elimi- parallel interfaces. nate the need for driver op amps and external bipolar supplies. The AD7609 antialiasing filter has a −3 dB cutoff frequency of 32 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the −3 dB bandwidth. Rev. A | Page 3 of 36 AD7609 Data Sheet SPECIFICATIONS VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V; fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise 1 noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE f = 1 kHz sine wave unless otherwise noted IN 2, 3 Signal-to-Noise Ratio (SNR) Oversampling by 16; ±10 V range; fIN = 160 Hz 98 101 dB Oversampling by 16; ±5 V range; fIN = 160 Hz 100 dB No oversampling; ±10 V range 90 91 dB No oversampling; ±5 V range 89.5 90.5 dB 2 Signal-to-(Noise + Distortion) (SINAD) No oversampling; ±10 V range 89.5 91 dB No oversampling; ±5 V range 89 90 dB Dynamic Range No oversampling; ±10 V range 91.5 dB No oversampling; ±5 V range 90.5 dB 2, 3 Total Harmonic Distortion (THD) No oversampling; ±10 V range −107 −97 dB No oversampling; ±5 V range −110 −96 dB 2 Peak Harmonic or Spurious Noise (SFDR) −108 dB 2 Intermodulation Distortion (IMD) fa = 1 kHz, fb = 1.1 kHz Second-Order Terms −110 dB Third-Order Terms −106 dB 2 Channel-to-Channel Isolation f on unselected channels up to 160 kHz −95 dB IN ANALOG INPUT FILTER Full Power Bandwidth −3 dB, ±10 V range 32 kHz −3 dB, ±5 V range 23 kHz −0.1 dB, ±10 V range 13 kHz −0.1 dB, ±5 V range 10 kHz tGROUP DELAY ±10 V range 7.1 µs ±5 V range 10.2 µs DC ACCURACY Resolution No missing codes 18 Bits 2 4 Differential Nonlinearity ±0.75 −0.99/+2 LSB 2 Integral Nonlinearity ±3 ±7.5 LSB Total Unadjusted Error (TUE) ±10 V range ±10 LSB ±5 V range ±90 LSB 2, 5 Positive Full-Scale Error External reference ±8 ±140 LSB Internal reference ±40 LSB Positive Full-Scale Error Drift External reference ±2 ppm/°C Internal reference ±7 ppm/°C 2 Positive Full-Scale Error Matching ±10 V range 12 80 LSB ±5 V range 40 100 LSB 2, 6 Bipolar Zero Code Error ±10 V range ±3 ±24 LSB ± 5 V range ±3 ±48 LSB Bipolar Zero Code Error Drift ±10 V range 10 µV/°C ± 5 V range 5 µV/°C 2 Bipolar Zero Code Error Matching ±10 V range 2.7 30 LSB ±5 V range 13 65 LSB 2, 5 Negative Full-Scale Error External reference ±8 ±140 LSB Internal reference ±40 LSB Negative Full-Scale Error Drift External reference ±4 ppm/°C Internal reference ±8 ppm/°C 2 Negative Full-Scale Error Matching ±10 V range 12 80 LSB ±5 V range 40 100 LSB Rev. A | Page 4 of 36 Data Sheet AD7609 Parameter Test Conditions/Comments Min Typ Max Unit ANALOG INPUT Differential Input Voltage Ranges VIN = Vx+ − (Vx−) RANGE = 1; ±10 V −20 +20 V RANGE = 0; ±5 V −10 +10 V Absolute Voltage Input ±10 V range, see the Analog Input Clamp −10 +10 V Protection section ±5 V range, see the Analog Input Clamp −5 +5 V Protection section Common-Mode Input Range −4 ±5 +4 V CMRR −70 dB Analog Input Current 10 V, see Figure 28 5.4 µA 5 V, see Figure 28 2.5 µA 7 Input Capacitance 5 pF Input Impedance 1 MΩ REFERENCE INPUT/OUTPUT Reference Input Voltage Range 2.475 2.5 2.525 V DC Leakage Current ±1 µA 7 Input Capacitance REF SELECT = 1 7.5 pF Reference Output Voltage REFIN/REFOUT 2.49/ V 2.505 Reference Temperature Coefficient ±10 ppm/°C LOGIC INPUTS Input High Voltage (VINH) 0.7 × VDRIVE V Input Low Voltage (VINL) 0.3 × VDRIVE V Input Current (IIN) ±2 µA 7 Input Capacitance (C ) 5 pF IN LOGIC OUTPUTS Output High Voltage (VOH) ISOURCE = 100 µA VDRIVE − 0.2 V Output Low Voltage (V ) I = 100 µA 0.2 V OL SINK Floating-State Leakage Current ±1 ±20 µA 7 Floating-State Output Capacitance 5 pF Output Coding Twos complement CONVERSION RATE Conversion Time All eight channels included 4 µs Track-and-Hold Acquisition Time 1 µs Throughput Rate Per channel, all eight channels included 200 kSPS POWER REQUIREMENTS AVCC 4.75 5.25 V VDRIVE 2.3 5.25 V I Digital inputs = 0 V or V TOTAL DRIVE Normal Mode (Static) 16 22 mA 8 Normal Mode (Operational) f = 200 kSPS 20 28.5 mA SAMPLE Standby Mode 5 8 mA Shutdown Mode 2 11 µA Rev. A | Page 5 of 36 AD7609 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit Power Dissipation Normal Mode (Static) 80 115.5 mW 8 Normal Mode (Operational) fSAMPLE = 200 kSPS 100 157 mW Standby Mode 25 42 mW Shutdown Mode 10 60.5 µW 1 Temperature range for B version is −40°C to +85°C. 2 See the Terminology section. 3 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel and serial modes with V = 5 V, SNR typically reduces DRIVE by 1.5 dB and THD by 3 dB. 4 LSB means least significant bit. With ±5 V input range, 1 LSB = 76.29 µV. With ±10 V input range, 1 LSB = 152.58 µV. 5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section. 7 Sample tested during initial release to ensure compliance. 8 Operational power/current figure includes contribution when running in oversampling mode. Rev. A | Page 6 of 36 Data Sheet AD7609 TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/ internal reference, TA = TMIN to TMAX, 1 unless otherwise noted. Table 3. Limit at TMIN, TMAX Parameter Min Typ Max Unit Description PARALLEL/SERIAL/BYTE MODE t 1/throughput rate CYCLE 5 µs Parallel mode, reading during; or after conversion V = 2.7 V to 5.25 V; or DRIVE serial mode: V = 3.3 V to 5.25 V, reading during a conversion using D A DRIVE OUT and DOUTB lines 5 µs Parallel mode reading after conversion VDRIVE = 2.3 V 10.1 µs Serial mode reading after conversion; VDRIVE = 2.7 V, DOUTA and DOUTB lines 11.5 µs Serial mode reading after a conversion; V = 2.3 V, D A and D B lines DRIVE OUT OUT t Conversion time CONV 3.45 4 4.15 µs Oversampling off 7.87 9.1 µs Oversampling by 2 16.05 18.8 µs Oversampling by 4 33 39 µs Oversampling by 8 66 78 µs Oversampling by 16 133 158 µs Oversampling by 32 257 315 µs Oversampling by 64 tWAKE-UP STANDBY 100 µs STBY rising edge to CONVST x rising edge; power-up time from standby mode tWAKE-UP SHUTDOWN Internal Reference 30 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode External Reference 13 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode tRESET 50 ns RESET high pulse width tOS_SETUP 20 ns BUSY to OS x pin setup time t 20 ns BUSY to OS x pin hold time OS_HOLD t 45 ns CONVST x high to BUSY high 1 t2 25 ns Minimum CONVST x low pulse t3 25 ns Minimum CONVST x high pulse t4 0 ns BUSY falling edge to CS falling edge setup time 2 t 0.5 ms Maximum delay allowed between CONVST A, CONVST B rising edges 5 t 25 ns Maximum time between last CS rising edge and BUSY falling edge 6 t 25 ns Minimum delay between RESET low to CONVST x high 7 PARALLEL READ OPERATION t 0 ns CS to RD setup time 8 t 0 ns 9 CS to RD hold time t10 RD low pulse width 19 ns VDRIVE above 4.75 V 24 ns V above 3.3 V DRIVE 30 ns V above 2.7 V DRIVE 37 ns V above 2.3 V DRIVE t11 15 ns RD high pulse width t12 22 ns CS high pulse width (see Figure 5); CS and RD linked Rev. A | Page 7 of 36 AD7609 Data Sheet Limit at TMIN, TMAX Parameter Min Typ Max Unit Description t13 Delay from CS until DB[15:0] three-state disabled 19 ns V above 4.75 V DRIVE 24 ns V above 3.3 V DRIVE 30 ns V above 2.7 V DRIVE 37 ns VDRIVE above 2.3 V 3 t14 Data access time after RD falling edge 19 ns VDRIVE above 4.75 V 24 ns V above 3.3 V DRIVE 30 ns V above 2.7 V DRIVE 37 ns V above 2.3 V DRIVE t15 6 ns Data hold time after RD falling edge t16 6 ns CS to DB[15:0] hold time t 22 ns Delay from CS rising edge to DB[15:0] three-state enabled 17 SERIAL READ OPERATION fSCLK Frequency of serial read clock 20 MHz V above 4.75 V DRIVE 15 MHz V above 3.3 V DRIVE 12.5 MHz V above 2.7 V DRIVE 10 MHz VDRIVE above 2.3 V t18 Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid 18 ns V above 4.75 V DRIVE 23 ns V above 3.3 V DRIVE 35 ns VDRIVE = 2.3 V to 2.7 V 3 t19 Data access time after SCLK rising edge 20 ns VDRIVE above 4.75 V 26 ns V above 3.3 V DRIVE 32 ns V above 2.7 V DRIVE 39 ns V above 2.3 V DRIVE t20 0.4 tSCLK ns SCLK low pulse width t21 0.4 tSCLK ns SCLK high pulse width t22 7 SCLK rising edge to DOUTA/DOUTB valid hold time t 22 ns CS rising edge to D A/D B three-state enabled 23 OUT OUT FRSTDATA OPERATION t24 Delay from CS falling edge until FRSTDATA three-state disabled 18 ns V above 4.75 V DRIVE 23 ns V above 3.3 V DRIVE 30 ns VDRIVE above 2.7 V 35 ns VDRIVE above 2.3 V t25 ns Delay from CS falling edge until FRSTDATA high, serial mode 18 ns V above 4.75 V DRIVE 23 ns V above 3.3 V DRIVE 30 ns V above 2.7 V DRIVE 35 ns VDRIVE above 2.3 V t26 Delay from RD falling edge to FRSTDATA high 19 ns VDRIVE above 4.75 V 23 ns V above 3.3 V DRIVE 30 ns V above 2.7 V DRIVE 35 ns V above 2.3 V DRIVE Rev. A | Page 8 of 36 Data Sheet AD7609 Limit at TMIN, TMAX Parameter Min Typ Max Unit Description t27 Delay from RD falling edge to FRSTDATA low 22 ns V = 3.3 V to 5.25 V DRIVE 29 ns V = 2.3 V to 2.7 V DRIVE th t Delay from 18 SCLK falling edge to FRSTDATA low 28 20 ns VDRIVE = 3.3 V to 5.25 V 27 ns VDRIVE = 2.3 V to 2.7 V t29 29 ns Delay from CS rising edge until FRSTDATA three-state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (30% to 70% of VDD) and timed from a voltage level of 1.6 V. 2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets. 3 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins. Timing Diagrams t 5 CONVST A/ CONVST B t CYCLE t 2 CONVST A/ t CONVST B 3 t CONV t 1 BUSY t 4 CS t 7 t RESET RESET Figure 2. CONVST x Timing—Reading After a Conversion t 5 CONVST A/ CONVST B t CYCLE t 2 CONVST A/ t CONVST B 3 t CONV t 1 BUSY t 6 CS t 7 t RESET RESET Figure 3. CONVST x Timing—Reading During a Conversion CS t 9 t t 8 11 t 10 t RD 16 t 13 t t 17 14 t 15 V1 V1 V2 V2 V8 V8 DATA: INVALID [17:2] [1:0] [17:2] [1:0] [17:2] [1:0] DB[15:0] t t 26 27 t 29 t 24 FRSTDATA Figure 4. Parallel Mode Separate CS and RD Pulses Rev. A | Page 9 of 36 09760-002 09760-004 09760-003 AD7609 Data Sheet t 12 CS, RD t t 16 13 t 17 V1 V1 V2 V2 V7 V7 V8 V8 DATA: [17:2] [1:0] [17:2] [1:0] [17:2] [1:0] [17:2] [1:0] DB[15:0] FRSTDATA CS RD Figure 5. and Linked Parallel Mode CS t t 21 20 SCLK t 19 t 22 t t 23 18 D A, OUT DB17 DB14 DB13 DB1 DB0 D B OUT t t 29 t 25 28 FRSTDATA Figure 6. Serial Read Operation Rev. A | Page 10 of 36 09760-005 09760-006 Data Sheet AD7609 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational AV to AGND −0.3 V to +7 V CC section of this specification is not implied. Exposure to absolute V to AGND −0.3 V to AV + 0.3 V DRIVE CC maximum rating conditions for extended periods may affect 1 Analog Input Voltage to AGND ±16.5 V device reliability. Digital Input Voltage to AGND −0.3 V to VDRIVE + 0.3 V THERMAL RESISTANCE Digital Output Voltage to AGND −0.3 V to VDRIVE + 0.3 V θ is specified for the worst-case conditions, that is, a device REFIN to AGND −0.3 V to AV + 0.3 V JA CC soldered in a circuit board for surface-mount packages. These Input Current to Any Pin Except ±10 mA 1 Supplies specifications apply to a 4-layer board. Operating Temperature Range Table 5. Thermal Resistance B Version −40°C to +85°C Package Type θ θ Unit JA JC Storage Temperature Range −65°C to +150°C 64-Lead LQFP 45 11 °C/W Junction Temperature 150°C Pb/SN Temperature, Soldering Reflow (10 sec to 30 sec) 240(+0)°C ESD CAUTION Pb-Free Temperature, Soldering Reflow 260(+0)°C ESD (All Pins Except Analog Inputs) 2 kV ESD (Analog Input Pins Only) 7 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. A | Page 11 of 36 AD7609 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 AV AV CC CC ANALOG INPUT PIN 1 2 47 AGND AGND DECOUPLING CAPACITOR PIN OS 0 3 46 REFGND POWER SUPPLY OS 1 4 45 REFCAPB GROUND PIN 5 44 OS 2 REFCAPA 6 43 DATA OUTPUT REFGND PAR/SER SEL AD7609 7 42 REFIN/REFOUT STBY TOP VIEW DIGITAL OUTPUT (Not to Scale) RANGE 8 41 AGND DIGITAL INPUT 9 40 AGND CONVST A REFERENCE INPUT/OUTPUT 10 39 REGCAP CONVST B 11 38 AV RESET CC 12 37 AV RD/SCLK CC 13 36 REGCAP CS BUSY 14 35 AGND FRSTDATA 15 34 REF SELECT DB0 16 33 DB15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 7. Pin Configuration Table 6. Pin Function Descriptions 1 Pin No. Type Mnemonic Description 1, 37, 38, 48 P AV Analog Supply Voltage 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end CC amplifiers and to the ADC core. These supply pins should be decoupled to AGND. 2, 26, 35, P AGND Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7609. All 40, 41, 47 analog input signals and external reference signals should be referred to these pins. All six of these AGND pins should connect to the AGND plane of a system. 23 P V Logic Power Supply Input. The voltage (2.3 V to 5 V) supplied at this pin determines the operating DRIVE voltage of the interface. This pin is nominally at the same supply as the supply of the host interface (that is, DSP, FPGA). 36, 39 P REGCAP Decoupling Capacitor Pins for Voltage Output from Internal Regulator. These output pins should be decoupled separately to AGND using a 1 μF capacitor. The voltage on these output pins is in the range of 2.5 V to 2.7 V. 49, 51, 53, AI+ V1+ to V8+ Analog Input V1+ to Analog Input V8+. These pins are the positive terminal of the true differential 55, 57, 59, analog inputs. The analog input range of these channels is determined by the RANGE pin. 61, 63 50, 52, 54, AI− V1− to V8− Analog Input V1− to Analog Input V8−. These are the negative terminals of the true differential 56, 58, 60, analog inputs. The analog input range of these channels is determined by the RANGE pin. The signal 62, 64 on this pin should be 180° out of phase with the corresponding Vx+ pin. 42 REF REFIN/ Reference Input/ Reference Output. The on-chip reference of 2.5 V is available on this pin for external REFOUT use if the REF SELECT pin is set to a logic high. Alternatively, the internal reference can be disabled by setting the REF SELECT pin to a logic low and an external reference of 2.5 V can be applied to this input. See the Internal/External Reference section. Decoupling is required on this pin for both the internal or external reference options. A 10 µF capacitor should be applied from this pin to ground close to the REFGND pins. 34 DI REF SELECT Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal reference is selected and is enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. 44, 45 REF REFCAPA, Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled to REFCAPB AGND using a low ESR 10 μF ceramic capacitor. 43, 46 REF REFGND Reference Ground Pins. These pins should be connected to AGND. Rev. A | Page 12 of 36 DB1 V8– DB2 V8+ DB3 V7– DB4 V7+ DB5 V6– DB6 V6+ V V5– DRIVE DB7/D A V5+ OUT DB8/D B V4– OUT V4+ AGND V3– DB9 V3+ DB10 V2– DB11 V2+ DB12 V1– DB13 V1+ DB14 09760-007 Data Sheet AD7609 1 Pin No. Type Mnemonic Description 8 DI RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic change on this pin has an immediate effect on the analog input range. Changing this pin during a conversion is not recommended. See the Analog Input section for more details. 6 DI PAR/ Parallel/Serial Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel interface is selected. If this pin is tied to a logic high, the serial interface is selected. SER SEL In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA and DB8/DOUTB pins function as serial data outputs. When the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to AGND. 9, 10 DI CONVST A, Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to initiate CONVST B conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A and CONVST B can be shorted together and a single conversion start signal applied. Alternatively, CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4, and CONVST B can be used to initiate simultaneous sampling on the other analog inputs (V5, V6, V7, and V8). This is only possible when oversampling is not switched on. When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold circuitry for their respective analog inputs is set to hold. This function allows a phase delay to be created inherently between the sets of analog inputs. 13 DI CS Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the output bus (DB[15:0]) is enabled and the conversion result is output on the parallel data bus lines. In serial mode, the CS is used to frame the serial read transfer and clocks out the MSB of the serial output data. 12 DI RD/SCLK Parallel Data Read Control Input When Parallel Interface is Selected (RD)/Serial Clock Input When Serial Interface is Selected (SCLK). When both CS and RD are logic low in parallel mode, the output bus is enabled. In parallel mode, two RD pulses are required to read the full 18 bits of conversion results from each channel. The first RD pulse outputs DB[17:2], and the second RD pulses outputs DB[1:0]. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the data output lines, D A and D B, out of three-state and clocks out the MSB of the OUT OUT conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data outputs, DOUTA and DOUTB. For further information, see the Conversion Control section. 14 DO BUSY Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and indicates that the conversion process has started. The BUSY output remains high until the conversion process for all channels is complete. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and will be available to be read after a time, t4. Any data read while BUSY is high should be complete before the falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high. 11 DI RESET Reset Input. When set to logic high, the rising edge of RESET resets the AD7609. The part must receive a RESET pulse after power-up. To achieve the specified performance after the RESET signal, the t WAKE_UP time should elapse between power-on and the RESET pulse. The RESET high pulse should be SHUTDOWN typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers reset to all zeros. 15 DO FRSTDATA Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on either the parallel or serial interface. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, indicating that the result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low following the third falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS as this clocks out the MSB of V1 on DOUTA. It returns low on the 18th SCLK falling edge after the CS falling edge. See the Conversion Control section for more details. 7 DI STBY Standby Mode Input. This pin is used to place the AD7609 into one of two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin, as shown in Table 8. When in standby mode, all circuitry except the on-chip reference, regulators, and regulator buffers is powered down. When in shutdown mode, all circuitry is powered down. Rev. A | Page 13 of 36 AD7609 Data Sheet 1 Pin No. Type Mnemonic Description 5, 4, 3 DI OS [2:0] Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2 is the MSB control bit, and OS 0 is the LSB control bit. See the Digital Filter section for additional details on the oversampling mode of operation and Table 9 for oversampling bit decoding. 33 DO/DI DB15 Parallel Output Data Bits, Data Bit 15. When PAR/SER SEL = 0, this pin acts as three-state parallel digital output pin. This pin is used to output DB17 of the conversion result during the first RD pulse and DB1 of the same conversion result during the second RD pulse. When PAR/SER SEL = 1, this pin should be tied to AGND. 32 DO/DI DB14 Parallel Output Data Bits, Data Bit 14. When PAR/SER SEL = 0, this pin acts as three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB16 of the conversion result during the first RD pulse and DB0 of the same conversion result during the second RD pulse. When PAR/SER SEL = 1, this pin should be tied to AGND. 31 to 27 DO DB[13:9] Parallel Output Data Bits, Data Bit 13 to Data Bit 9. When PAR/SER SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB15 to DB11 of the conversion result during the first RD pulse and output 0 during the second RD pulse. When PAR/SER SEL = 1, these pins should be tied to AGND. 24 DO DB7/D A Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (D A). When PAR/SER SEL = 0, this OUT OUT pins acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB9 of the conversion result. When PAR/SER SEL = 1, this pin functions as DOUTA and outputs serial conversion data. See the Conversion Control section for further details. 25 DO DB8/DOUTB Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (D B). When PAR/SER SEL = 0, this OUT pins acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB10 of the conversion result. When PAR/SER SEL = 1, this pin functions as D B and outputs OUT serial conversion data. See the Conversion Control section for further details. 22 to 16 DO DB[6:0] Parallel Output Data Bits, Data Bit 6 to Data Bit 0. When PAR/SER SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB8 to DB2 of the conversion result during the first RD pulse and output 0 during the second RD pulse. When PAR/SER SEL = 1, these pins should be tied to AGND. 1 Refers to classification of pin type; P denotes power, AI denotes analog input, REF denotes reference, DI denotes digital input, DO denotes digital output. Rev. A | Page 14 of 36 Data Sheet AD7609 TYPICAL PERFORMANCE CHARACTERISTICS 3 0 AV , V = 5V 2 CC DRIVE INTERNAL REFERENCE –20 ±10V RANGE f = 200 kSPS 1 SAMPLE –40 f = 1kHz IN 16384 POINT FFT –60 0 SNR = 91.52dB THD = –111.05dB –80 ±10V RANGE –1 AV , V = 5V CC DRIVE –100 T = 25°C A f = 200 kSPS –2 SAMPLE –120 WCP INL = 1.69 LSB WCN INL = –1.3 LSB –140 –3 –160 0 20k 40k 60k 80k 100k INPUT FREQUENCY (Hz) CODE Figure 8. FFT Plot, ±10 V Range Figure 11. Typical INL, ±10 V Range 1.0 ±10V RANGE 0.8 0 AV , V = 5V CC DRIVE T = 25°C AV , V = 5V A CC DRIVE 0.6 f = 200 kSPS SAMPLE INTERNAL REFERENCE –20 WCP DNL = 0.33 LSB ±5V RANGE WCN DNL = –0.32 LSB 0.4 f = 200kSPS SAMPLE –40 f = 1kHz IN 0.2 16,384 POINT FFT –60 SNR = 91.12dB 0 THD = –109.77dB –80 –0.2 –0.4 –100 –0.6 –120 –0.8 –140 –1.0 –160 0 20k 40k 60k 80k 100k INPUT FREQUENCY (Hz) CODE Figure 9. FFT Plot, ±5 V Range Figure 12. Typical DNL, ±10 V Range 3 0 2 AV , V = 5V CC DRIVE –20 INTERNAL REFERENCE ±10V RANGE 1 f = 12.5kSPS SAMPLE –40 f = 1Hz IN 8192 POINT FFT –60 0 SNR = 100.71dB THD: –111.74dB –80 –1 ±5V RANGE AV , V = 5V –100 CC DRIVE T = 25°C A –2 f = 200 kSPS SAMPLE –120 WCP INL = 1.56 LSB WCN INL = –1.22 LSB –140 –3 –160 0 1 2 3 4 5 6 INPUT FREQUENCY (kHz) CODE Figure 10. FFT Plot, ±10 V Range Figure 13. Typical INL, ±5 V Range Rev. A | Page 15 of 36 SNR (dB) AMPLITUDE (dB) AMPLITUDE (dB) 09760-109 09760-009 09760-008 DNL (LSB) INL (LSB) INL (LSB) 0 0 0 32,768 32,768 32,768 65,536 65,536 65,536 98,304 98,304 98,304 131,072 131,072 131,072 163,840 163,840 163,840 196,608 196,608 196,608 229,376 229,376 229,376 09760-012 09760-010 09760-011 AD7609 Data Sheet 1.0 ±5V RANGE 0.8 AV , V = 5V CC DRIVE 40 T = 25°C A 0.6 f = 200 kSPS SAMPLE 32 WCP INL = 0.45 LSB PFS ERROR WCN INL = –0.38 LSB 0.4 24 0.2 16 NFS ERROR 0 8 –0.2 0 –0.4 –8 –0.6 –16 –0.8 –24 ±10V RANGE –1.0 –32 AV , V = 5V CC DRIVE EXTERNAL REFERENCE –40 –40 –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) CODE Figure 17. NFS and PFS Error Matching Figure 14. Typical DNL, ±5 V Range 10 80 60 8 40 ±10V RANGE 6 20 ±5V RANGE 4 0 –20 AV , V = 5V 2 CC DRIVE f = 200 kSPS SAMPLE –40 T = 25°C A EXTERNAL REFERENCE 0 SOURCE RESISTANCE IS MATCHED ON 200kSPS –60 THE V– INPUT AV , V = 5V CC DRIVE ±10V AND ±5V RANGE EXTERNAL REFERENCE –2 –80 01 20k 40k 60k 80k 100k20k –40 –25 –10 5 20 35 50 65 80 SOURCE RESISTANCE (Ω) TEMPERATURE (°C) Figure 18. PFS and NFS Error vs. Source Resistance Figure 15. NFS Error vs. Temperature 105 80 AV ,V = 5V CC DRIVE f CHANGES WITH OS RATE SAMPLE 60 T = 25°C A 100 INTERNAL REFERENCE ±10V RANGE 40 20 95 0 ±5V RANGE 90 –20 NO OS ±10V RANGE OS × 2 –40 OS × 4 85 OS × 8 OS × 16 –60 200kSPS OS × 32 AV , V = 5V CC DRIVE OS × 64 EXTERNAL REFERENCE 80 –80 10 100 10k 10k 100k –40 –25 –10 5 20 35 50 65 80 INPUT FREQUENCY (Hz) TEMPERATURE (°C) Figure 19. SNR vs. Input Frequency, ±10 V Range Figure 16. PFS Error vs. Temperature Rev. A | Page 16 of 36 PFS ERROR (LSB) NFS ERROR (LSB) DNL (LSB) 0 32,768 65,536 98,304 131,072 163,840 196,608 229,376 09760-118 09760-117 09760-013 PFS/NFS ERROR (%FS) SNR (dBs) NFS/PFS CHANNEL MATCHING (LSB) 09760-218 09760-017 09760-219 0 Data Sheet AD7609 105 8 AV , V = 5V CC DRIVE f CHANGES WITH OS RATE SAMPLE 6 T = 25°C A INTERNAL REFERENCE 100 ±5V RANGE 4 95 2 0 90 ±5V RANGE NO OS OS × 2 –2 OS × 4 ±10V RANGE 85 OS × 8 OS × 16 200 kSPS –4 OS × 32 AV ,V = 5V CC DRIVE OS × 64 EXTERNAL REFERENCE 80 –6 10 100 10k 10k 100k –40 –20 20 40 60 80 TEMPERATURE (°C) INPUT FREQUENCY (Hz) Figure 20. SNR vs. Input Frequency, ±5 V Range Figure 23. Bipolar Zero Code Error vs. Temperature –60 ±10V RANGE 16 AV , V = 5V CC DRIVE T = 25°C –70 A 12 f = 200 kSPS SAMPLE R MATCHED ±5V RANGE SOURCE ON V +, V – INPUTS 8 x x –80 4 –90 ±10V RANGE 0Ω 0 10Ω 500Ω –100 1.2kΩ –4 5kΩ 10kΩ –8 –110 –12 200kSPS AV , V = 5V CC DRIVE –120 EXTERNAL REFERENCE 1 10 100 –16 FREQUENCY (kHz) –40 –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) Figure 21. THD vs. Input Frequency for Various Source Impedances, Figure 24. Bipolar Zero Code Error Matching Between Channels ±10 V Range –50 –40 AV , V = 5V CC DRIVE ±5V RANGE INTERNAL REFERENCE –60 AV , V = 5V –50 CC DRIVE AD7609 RECOMMENDED DECOUPLING USED T = 25°C A f = 200kSPS SAMPLE –70 f = 200 kSPS SAMPLE T = 25°C A –60 R MATCHED SOURCE ON V +, V – INPUTS –80 x x ±10V RANGE –70 –90 ±5V RANGE –80 –100 0Ω 10Ω –90 –110 500Ω 1.2kΩ 5kΩ –100 –120 10kΩ –130 –110 –140 –120 0 20 40 60 80 100 120 140 160 1 10 100 NOISE FREQUENCY (kHz) FREQUENCY (kHz) Figure 25. Channel-to-Channel Isolation Figure 22. THD vs. Input Frequency for Various Source Impedances, ±5 V Range Rev. A | Page 17 of 36 SNR (dBs) THD (dB) THD (dB) 09760-019 09760-020 09760-018 CHANNEL-TO-CHANNEL ISOLATION (dB) BIPOLAR ZERO CODE ERROR MATCHING (LSB) BIPOLAR ZERO ERROR (LSB) 09760-023 09760-224 09760-225 AD7609 Data Sheet 110 22 20 105 ±10V RANGE 18 100 ±5V RANGE 16 95 14 90 12 AV = V = 5V CC DRIVE AV , V = 5V CC DRIVE 85 T = 25°C A T = 25°C 10 A INTERNAL REFERENCE INTERNAL REFERENCE f SCALES WITH OS RATIO f VARIES WITH OS RATE SAMPLE SAMPLE 80 8 NO OS OS × 2 OS × 4 OS × 8 OS × 16 OS × 32 OS × 64 NO OS OS × 2 OS × 4 OS × 8 OS × 16 OS × 32 OS × 64 OVERSAMPLING RATIO OVERSAMPLING RATIO Figure 26. Dynamic Range vs. Oversampling Ratio Figure 29. Supply Current vs. Oversampling Rate 140 2.5010 130 2.5005 AV = 5.25V CC 120 AV = 5V CC ±10V RANGE 110 2.5000 ±5V RANGE 100 2.4995 AV = 4.75V CC 90 2.4990 80 AV , V = 5V CC DRIVE INTERNAL REFERENCE AD7609 RECOMMENDED DECOUPLING USED 70 2.4985 f = 200kSPS SAMPLE T = 25°C A 60 0 100 200 300 400 500 600 700 800 900 1000 1100 2.4980 –40 –25 –10 5 20 35 50 65 80 AV NOISE FREQUENCY (kHz) CC TEMPERATURE (°C) Figure 27. Reference Output Voltage vs. Temperature for Different Supply Figure 30. PSRR Voltages 10 0 AV , V = 5V CC DRIVE AV , V = 5V CC DRIVE –10 T = 25°C A f = 200kSPS SAMPLE f = 200kSPS SAMPLE 5 –20 INTERNAL REFERENCE –30 0 –40 –50 ±5V RANGE –5 –60 ±10V RANGE –70 +25°C V+ +25°C V– –80 –10 +85°C V– +85°C V+ –40°C V– –90 –40°C V+ –15 –100 10 100 1k 10k 100k –20 –15 –10 –5 0 5 10 15 20 DIFFERENTIAL ANALOG INPUT VOLTAGE (Vx+ – (Vx–)) (V) FREQUENCY (Hz) Figure 28. Analog Input Current vs. Input Voltage Over Temperature Figure 31. CMRR vs. Common-Mode Ripple Frequency Rev. A | Page 18 of 36 REFOUT VOLTAGE (V) CURRENT (µA) DYNAMIC RANGE (dB) 09760-023 09760-025 09760-029 AV SUPPLY CURRENT (mA) POWER SUPPLY REJECTION RATIO (dB) CC CMRR (dB) 09760-028 09760-130 09760-227 Data Sheet AD7609 TERMINOLOGY Signal-to-(Noise + Distortion) Ratio Integral Nonlinearity The measured ratio of signal-to-(noise + distortion) at the The maximum deviation from a straight line passing through output of the ADC. The signal is the rms amplitude of the the endpoints of the ADC transfer function. The endpoints of fundamental. Noise is the sum of all nonfundamental signals the transfer function are zero scale, a ½ LSB below the first code up to half the sampling frequency (f /2, excluding dc). The ratio S transition, and full scale at ½ LSB above the last code transition. depends on the number of quantization levels in the digitization Differential Nonlinearity process: the more levels, the smaller the quantization noise. The The difference between the measured and the ideal 1 LSB theoretical signal-to-(noise + distortion) ratio for an ideal N-bit change between any two adjacent codes in the ADC. converter with a sine wave input is given by Bipolar Zero Code Error Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB The deviation of the midscale transition (all 1s to all 0s) from Thus, for an 18-bit converter, this is 110.12 dB. the ideal VIN voltage, that is, AGND. Total Harmonic Distortion (THD) Bipolar Zero Code Error Match The ratio of the rms sum of the harmonics to the fundamental. The difference in bipolar zero code error between any two input For the AD7609, it is defined as channels. THD (dB) = Positive Full-Scale Error 2 2 2 2 2 2 2 2 The last transition (from 011 . . . 10 to 011 . . . 11 in twos V +V +V +V +V +V +V +V 2 3 4 5 6 7 8 9 20log complement coding) should occur for an analog voltage 1½ V 1 LSB below the nominal full scale (9.99977 V for the ±10 V where: range and 4.99988 V for the ±5 V range). The positive full-scale V1 is the rms amplitude of the fundamental. error is the deviation of the actual level of the last transition V2 to V9 are the rms amplitudes of the second through ninth from the ideal level. harmonics. Positive Full-Scale Error Match Peak Harmonic or Spurious Noise The difference in positive full-scale error between any two input The ratio of the rms value of the next largest component in the channels. ADC output spectrum (up to f /2, excluding dc) to the rms value S Negative Full-Scale Error of the fundamental. Normally, the value of this specification is The first transition (from 100 . . . 00 to 100 . . . 01 in twos determined by the largest harmonic in the spectrum, but for complement coding) should occur for an analog voltage ½ LSB ADCs where the harmonics are buried in the noise floor, it is above the negative full scale (−9.999923 V for the ±10 V range determined by a noise peak. and −4.9999618 for the ±5 V range). The negative full-scale Intermodulation Distortion error is the deviation of the actual level of the first transition With inputs consisting of sine waves at two frequencies, fa and fb, from the ideal level. any active device with nonlinearities creates distortion products Negative Full-Scale Error Match at sum and difference frequencies of mfa ± nfb, where m, n = 0, The difference in negative full-scale error between any two 1, 2, 3. Intermodulation distortion terms are those for which input channels. neither m nor n is equal to 0. For example, the second-order Track-and-Hold Acquisition Time terms include (fa + fb) and (fa − fb), and the third-order terms The track-and-hold amplifier returns to track mode at the end include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). of the conversion. The track-and-hold acquisition time is the The calculation of the intermodulation distortion is per the time required for the output of the track-and-hold amplifier to THD specification, where it is the ratio of the rms sum of the reach its final value, within ±1 LSB, after the end of the conversion. individual distortion products to the rms amplitude of the See the Track-and-Hold Amplifiers section for more details. sum of the fundamentals expressed in decibels (dB). Rev. A | Page 19 of 36 AD7609 Data Sheet Power Supply Rejection (PSR) Channel-to-Channel Isolation Variations in power supply affect the full-scale transition but Channel-to-channel isolation is a measure of the level of crosstalk not the converter’s linearity. Power supply rejection is the between any two channels. It is measured by applying a full-scale, maximum change in full-scale transition point due to a change 10 kHz sine wave signal to all unselected input channels and in power supply voltage from the nominal value. The power determining the degree to which the signal attenuates in the supply rejection ratio is defined as the ratio of the power in selected channel with a 1 kHz signal. the ADC output at full-scale frequency, f, to the power of a Common-Mode Rejection Ratio (CMRR) 200 mV p-p sine wave applied to the ADC V and V supplies DD SS CMRR is defined as the ratio of the power in the ADC of Frequency f . S common-mode input at full-scale frequency, f, to the power in PSRR (dB) = 10 log (Pf/Pf ) the output of a full-scale p-p sine wave applied to the common- S mode voltage of V X+ and V X− of frequency, f , IN IN S where: Pf is equal to the power at Frequency f in the ADC output. CMRR (dB) = 20 log (Pf/PfS) PfS is equal to the power at Frequency fS coupled onto the VDD where: and VSS supplies. Pf is equal to the power at Frequency f in the ADC input. PfS is equal to the power at Frequency fS in the ADC output. Rev. A | Page 20 of 36 Data Sheet AD7609 THEORY OF OPERATION Analog Input Clamp Protection CONVERTER DETAILS Figure 32 shows the analog input structure of the AD7609. The AD7609 is a data acquisition system that employs a high Each AD7609 analog input contains clamp protection circuitry. speed, low power, charge redistribution successive approxima- Despite a single 5 V supply operation, this analog input clamp tion analog-to-digital converter (ADC) and allows the protection allows for an input overvoltage up to ±16.5 V. simultaneous sampling of eight true differential analog input R channels. The analog inputs on the AD7609 can accept true FB bipolar input signals. The RANGE pin is used to select either 1MΩ Vx+ CLAMP ±10 V or ±5 V as the input range. The AD7609 operates from 1MΩ Vx– CLAMP a single 5 V supply. SECOND- ORDER The AD7609 contains input clamp protection, input signal R LPF FB scaling amplifiers, a second-order antialiasing filter, track-and- Figure 32. Analog Input Circuitry hold amplifiers, an on-chip reference, reference buffers, a high Figure 33 shows the current vs. voltage characteristic of the speed ADC, a digital filter, and high speed parallel and serial clamp circuit. For input voltages up to ±16.5 V, no current flows interfaces. Sampling on the AD7609 is controlled using in the clamp circuit. For input voltages above ±16.5 V, the CONVST x signals. AD7609 clamp circuitry turns on and clamps the analog input ANALOG INPUT to ±16.5 V. A series resister should be placed on the analog Analog Input Ranges input channels to limit the current to ±10 mA for input voltages above ±16.5 V. In an application where there is a series resistance The AD7609 can handle true bipolar input voltages. The logic on an analog input channel, VINx+, a corresponding resistance level on the RANGE pin determines the analog input range of is required on the VINx− channel (see Figure 34). If there is no all analog input channels. If this pin is tied to a logic high, the corresponding resister on the Vx− channel, this results in an analog input range is ±10 V for all channels. If this pin is tied offset error on that channel. It is recommended that the input to a logic low, the analog input range is ±5 V for all channels. overvoltage clamp protection circuitry be used to protect the A logic change on this pin has an immediate effect on the AD7609 against transient overvoltage events. It is not recom- analog input range; however, there is a settling time of 80 µs mended to leave the AD7609 in a condition where the clamp typically, in addition to the normal acquisition time requirement. protection circuitry is active (in normal or power-down The recommended practice is to hardwire the RANGE pin conditions) for extended periods because this may degrade the according to the desired input range for the system signals. bipolar zero code error performance of the AD7609. During normal operation, the applied analog input voltage should AV , V = 5V CC DRIVE remain within the analog input range selected via the RANGE 30 T = 25°C A pin. A RESET pulse must be applied to the part to ensure the 20 analog input channels are configured for the range selected. 10 When in a power-down mode, it is recommended to tie the 0 analog inputs together or both analog input pins (Vx+, Vx−) to GND. As per the Analog Input Clamp Protection section, the –10 overvoltage clamp protection is recommended for use in –20 transient overvoltage conditions, and should not remain active for extended periods. Stressing the analog inputs outside of –30 these conditions may degrade the Bipolar Zero Code error and –40 THD performance of the AD7609. –50 Analog Input Impedance –20 –15 –10 –5 0 5 10 15 20 SOURCE VOLTAGE (V) The analog input impedance of the AD7609 is 1 MΩ. This is a Figure 33. Input Protection Clamp Profile fixed input impedance and does not vary with the AD7609 sam- R pling frequency. This high analog input impedance eliminates FB AD7609 the need for a driver amplifier in front of the AD7609 allowing 1MΩ +10V R VINx+ CLAMP for direct connection to the source or sensor. With the need for –10V C 1MΩ R +10V VINx– CLAMP a driver amplifier eliminated, bipolar supplies can be removed –10V from the signal chain, which are often a source of noise in a system. R FB Figure 34. Input Resistance Matching on the Analog Input Rev. A | Page 21 of 36 INPUT CLAMP CURRENT (mA) 09760-129 09760-031 09760-033 AD7609 Data Sheet Analog Input Antialiasing Filter The conversion clock for the part is internally generated, and the conversion time for all channels is 4 µs on the AD7609. The An analog antialiasing filter is also provided on the AD7609. BUSY signal returns low after all eight conversions to indicate the The filter is a second-order Butterworth. Figure 35 and end of the conversion process. On the falling edge of BUSY, the Figure 36 show the frequency and phase response respectively track-and-hold amplifiers return to track mode. New data can of the analog antialiasing filter. In the ±5 V range, the −3 dB be read from the output register via the parallel, or serial frequency is typically 23 kHz. In the ±10 V range, the −3 dB interface after BUSY goes low; or, alternatively, data from the frequency is typically 32 kHz. previous conversion can be read while BUSY is high. Reading data 0 10V DIFF from the AD7609 while a conversion is in progress has little –5 effect on performance and allows a faster throughput to be 5V DIFF achieved. With a V > 3.3 V, the SNR is reduced by ~1.5 dB DRIVE –10 when reading during a conversion. –15 ADC TRANSFER FUNCTION –20 The output coding of the AD7609 is twos complement. The –25 designed code transitions occur midway between successive TEMP 0.1dB 3dB integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is –40°C 13,354Hz 33,520Hz –30 10V 25°C 12,769Hz 32,397Hz 85°C 12,427Hz 31,177Hz FSR/262,144 for the AD7609. The FSR for the AD7609 is 40 V –40°C 10,303Hz 24,365Hz –35 for the ±10 V range and 20 V for the ±5 V range. The ideal 5V 25°C 9619Hz 23,389Hz 85°C 9326Hz 22,607Hz transfer characteristic for the AD7609 is shown in Figure 37. –40 100 1k 10k 100k V+ ± (V–) REF ±10V CODE = × 131,072 × FREQUENCY (Hz) 10V 2.5V V+ ± (V–) REF Figure 35. Analog Antialiasing Filter Frequency Response ±5V CODE = × 131,072 × 5V 2.5V 14 13 011...111 12 011...110 11 +FSR – (–FSR) 10 ±5V RANGE 000...001 LSB = 18 2 000...000 9 111...111 8 ±10V RANGE 7 100...010 6 100...001 100...000 5 –FS + 1/2LSB 0V – 1LSB +FS – 3/2LSB 4 ANALOG INPUT 3 Figure 37. AD7609 Transfer Characteristic AV , V = 5V CC DRIVE 2 f = 200kSPS SAMPLE 1 The LSB size is dependent on the analog input range selected T = 25°C A 0 (see Table 7). 10 1k 10k 100k INPUT FREQUENCY (Hz) Table 7. Output Codes and Ideal Input Values Figure 36. Analog Antialiasing Filter Phase Response Analog Track-and-Hold Amplifiers Analog Input Input Digital (V+ − (V−) V+ − (V−) Output The track-and-hold amplifiers on the AD7609 allow the ADC to Description 10 V Range 5 V Range Code (Hex) accurately acquire an input sine wave of full-scale amplitude FSR − 0.5 LSB +19.99992 V 9.999961 V 0x1FFFF to 18-bit resolution. The track-and-hold amplifiers sample Midscale + 1 LSB +152.58 µV 76 µV 0x00001 their respective inputs simultaneously on the rising edge of Midscale 0 V 0 V 0x00000 CONVST x. The aperture time for track-and-hold (that is, the Midscale – 1 LSB −152.58 µV −76 µV 0x3FFFF delay time between the external CONVST x signal and the −FSR + 1 LSB −19.99984 V −9.99992 V 0x20001 track-and-hold actually going into hold) is well matched, by design, −FSR −20 V −10 V 0x20000 across all eight track-and-holds on one device and from device to device. This matching allows more than one AD7609 device to be sampled simultaneously in a system. The end of the conversion process across all eight channels is indicated by the falling edge of BUSY; and it is at this point that the track-and-holds return to track mode and the acquisition time for the next set of conversions begins. Rev. A | Page 22 of 36 ATTENUATION (dB) PHASE DELAY (µs) 09760-133 09760-032 ADC CODE 09760-034 Data Sheet AD7609 REFIN/REFOUT INTERNAL/EXTERNAL REFERENCE SAR The AD7609 contains an on-chip 2.5 V band gap reference. The REFCAPB BUF REFIN/REFOUT pin allows access to the 2.5 V reference that 10µF generates the on-chip 4.5 V reference internally, or it allows an REFCAPA external reference of 2.5 V to be applied to the AD7609. An 2.5V REF externally applied reference of 2.5 V is also amplified to 4.5 V using the internal buffer. This 4.5 V buffered reference is the reference used by the SAR ADC. Figure 38. Reference Circuitry The REF SELECT pin is a logic input pin that allows the user to select between the internal reference and the external reference. V DRIVE If this pin is set to logic high, the internal reference is selected AD7609 AD7609 AD7609 and is enabled; if this pin is set to logic low, the internal refer- REF SELECT REF SELECT REF SELECT ence is disabled and an external reference voltage must be REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT applied to the REFIN/REFOUT pin. The internal reference buffer is always enabled. After a reset, the AD7609 operates in + 10µF 100nF 100nF the reference mode selected by the REF SELECT pin. Decoupling is required on the REFIN/REFOUT pin for both the internal or external reference options. A 10 µF ceramic capacitor is Figure 39. Single External Reference Driving Multiple AD7609 required on the REFIN/REFOUT to ground close to the REFIN/REFOUT Pins REFGND pins. The AD7609 contains a reference buffer configured to amplify the REF voltage up to ~4.5 V, as shown AD7609 AD7609 AD7609 in Figure 38. The REFCAPA and REFCAPB pins must be REF SELECT REF SELECT REF SELECT shorted together externally and a ceramic capacitor of 10 μF REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT applied to REFGND to ensure the reference buffer is in closed-loop operation. The reference voltage available at the REFIN/REFOUT pin is 2.5 V. 100nF 100nF 100nF When the AD7609 is configured in external reference mode, ADR421 the REFIN/REFOUT pin is a high input impedance pin. For 0.1µF applications using multiple AD7609 devices, the following Figure 40. Internal Reference Driving Multiple AD7609 REFIN Pins configurations are recommended depending on the application requirements. External Reference Mode One ADR421 external reference can be used to drive the REFIN/REFOUT pins of all AD7609 devices (see Figure 39). In this configuration, each AD7609 REFIN/REFOUT pin should be decoupled with a 100 nF decoupling capacitor. Internal Reference Mode One AD7609 device, configured to operate in the internal reference mode, can be used to drive the remaining AD7609 devices, which are configured to operate in external reference mode (see Figure 40). The REFIN/REFOUT pin of the AD7609, configured in internal reference mode, should be decoupled using a 10 µF ceramic decoupling capacitor. The other AD7609 devices, configured in external reference mode, should use a 100 nF decoupling capacitor on their REFIN/REFOUT pins. Rev. A | Page 23 of 36 09760-035 09760-036 09760-037 AD7609 Data Sheet TYPICAL CONNECTION DIAGRAM POWER-DOWN MODES Figure 41 shows the typical connection diagram for the There are two power-down modes available on the AD7609. AD7609. There are four AVCC supply pins on the part that The STBY pin controls whether the AD7609 is in normal mode can be tied together and decoupled using a 100 nF capacitor at or one of the two power-down modes. The two power-down each supply pin and a 10 µF capacitor at the supply source. The modes available are standby mode and shutdown mode. The AD7609 can operate with the internal reference or an externally power-down mode is selected through the state of the RANGE applied reference. In this configuration, the AD7609 is config- STBY pin when the pin is low. Table 8 shows the configurations ured to operate with the internal reference. When using a single required to choose the desired power-down mode. When the AD7609 device on the board, the REFIN/REFOUT pin should AD7609 is placed in standby mode, the current consumption is be decoupled with a 10 µF capacitor. In an application with 8 mA maximum and power-up time is approximately 100 µs multiple AD7609 devices, see the Internal/External Reference because the capacitor on the REFCAPA/REFCAPB pins must section. The REFCAPA and REFCAPB pins are shorted together charge up. In standby mode, the on-chip reference and and decoupled with a 10 µF ceramic capacitor. regulators remain powered up and the amplifiers and ADC core are powered down. When the AD7609 is placed in shutdown The V supply is connected to the same supply as the pro- DRIVE mode, the current consumption is 11 µA maximum and power cessor. The voltage on V controls the voltage value of the DRIVE up time is about 13 ms. In shutdown mode, all circuitry output logic signals. For layout, decoupling, and grounding is powered down. When the AD7609 is powered up from hints, see the Layout Guidelines section. shutdown mode, a reset signal must be applied to the AD7609 After supplies are applied to the AD7609, a reset should be after the required power-up time has elapsed. applied to the AD7609 to ensure that it is configured for the correct mode of operation. Table 8. Power-Down Mode Selection STBY Power-Down Mode RANGE Standby 0 1 Shutdown 0 0 ANALOG SUPPLY DIGITAL SUPPLY 1 VOLTAGE 5V VOLTAGE +2.3V TO +5V + 1µF 10µF 100nF 100nF REFIN/REFOUT 2 AV V REGCAP CC DRIVE REFCAPA PARALLEL + DB0 TO DB15 INTERFACE 10µF REFCAPB REFGND CONVST A, B CS V1+ RD V1– BUSY V2+ AD7609 V2– RESET V3+ OS 2 V3– OS 1 OVERSAMPLING V4+ OS 0 EIGHT DIFFERENTIAL V4– V5+ ANALOG INPUT PAIRS REF SELECT V DRIVE V5– V6+ PAR/SER SEL V6– RANGE V7+ V DRIVE V7– STBY V8+ AGND V8– 1 DECOUPLING SHOWN ON THE AV PIN APPLIES TO EACH AV PIN (PIN 1, PIN 37, PIN 38, PIN 48). CC CC DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV PIN 37 AND PIN 38. CC 2 DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). Figure 41. Typical Connection Diagram Rev. A | Page 24 of 36 MICROPROCESSOR/ MICROCONVERTER/ DSP 09760-038 Data Sheet AD7609 Simultaneously Sampling Two Sets of Channels CONVERSION CONTROL The AD7609 also allows the analog input channels to be Simultaneous Sampling on All Analog Input Channels sampled simultaneously in two sets. This can be used in power The AD7609 allows simultaneous sampling of all analog input line protection and measurement systems to compensate for channels. All channels are sampled simultaneously when both phase differences between PT and CT transformers. In a 50 Hz CONVST x pins (CONVST A, CONVST B) are tied together. A system, this allows for up to 9° of phase compensation, and in a single CONVST x signal is used to control both CONVST x inputs. 60 Hz system, it allows for up to 10° of phase compensation. The rising edge of this common CONVST x signal initiates This is accomplished by pulsing the two CONVST x pins inde- simultaneous sampling on all analog input channels. pendently and is only possible if oversampling is not in use. The AD7609 contains an on-chip oscillator that is used to CONVST A is used to initiate simultaneous sampling of the first perform the conversions. The conversion time for all ADC set of channels (V1 to V4). CONVST B is used to initiate channels is t . The BUSY signal indicates to the user when CONV simultaneous sampling on the second set of analog input conversions are in progress, so that when the rising edge of channels (V5 to V8), as illustrated in Figure 42. On the rising CONVST x is applied, BUSY goes logic high and transitions low edge of CONVST A, the track-and-hold amplifiers for the first at the end of the entire conversion process. The falling edge of set of channels are placed into hold mode. On the rising edge the BUSY signal is used to place all eight track-and-hold of CONVST B, the track-and-hold amplifiers for the second set amplifiers back into track mode. The falling edge of BUSY also of channels are placed into hold mode. The conversion process indicates that the new data can now be read from the parallel begins after both rising edges of CONVST x have occurred; bus (DB[15:0]) or the serial data lines, D A and D B. OUT OUT therefore, BUSY goes high on the rising edge of the later CONVST x signal. The falling edge of BUSY also indicates that the new data can now be read from the parallel bus or the serial data lines, D A and D B. There is no change to the data OUT OUT read process when using two separate CONVST x signals. Connect all unused analog input channel to AGND. The results for any unused channels are still included in the data read because all channels are always converted. V1 TO V4 TRACK-AND-HOLD ENTER HOLD V5 TO V8 TRACK-AND-HOLD ENTER HOLD t 5 CONVST A CONVST B AD7609 CONVERTS ON ALL 8 CHANNELS BUSY t CONV CS, RD V1 V2 V8 DATA: DB[15:0] FRSTDATA Figure 42. Simultaneous Sampling on Channel Sets Using Independent CONVST A/CONVST B Signals—Parallel Mode Rev. A | Page 25 of 36 09760-039 AD7609 Data Sheet DIGITAL INTERFACE The AD7609 provides two interface options: a parallel interface AD7609 INTERRUPT and a high speed serial interface. The required interface mode is BUSY 14 selected via the PAR/SER SEL pin. 13 CS RD 12 DIGITAL The operation of the interface modes is described in the HOST 33:16 DB[15:0] following sections. CS Figure 43. AD7609 Interface Diagram: One AD7609 Using the Parallel Bus; PARALLEL INTERFACE (PAR/SER SEL = 0) RD and Shorted Together Data can be read from the AD7609 via the parallel data bus with SERIAL INTERFACE (PAR/SER SEL = 1) CS RD standard and signals. To read the data over the parallel PAR CS RD bus, the /SER SEL pin should be tied low. The and To read data back from the AD7609 over the serial interface, input signals are internally gated to enable the conversion result the PAR/SER SEL pin should be tied high. The CS and SCLK onto the data bus. The data lines, DB15 to DB0, leave their high signals are used to transfer data from the AD7609. The AD7609 CS RD impedance state when both and are logic low. has two serial data output pins, D A and D B. Data can be OUT OUT read back from the AD7609 using one or both of these D OUT The rising edge of the CS input signal three-states the bus and lines. For the AD7609, conversion results from Channel V1 to the falling edge of the CS input signal takes the bus out of the Channel V4 first appear on D A, whereas conversion results OUT high impedance state. CS is the control signal that enables the from Channel V5 to Channel V8 first appear on DOUTB. data lines; it is the function that allows multiple AD7609 The CS falling edge takes the data output lines (D A and OUT CS devices to share the same parallel data bus. The signal can DOUTB) out of three-state and clocks out the MSB of the conver- RD be permanently tied low, and the signal can be used to sion result. The rising edge of SCLK clocks all subsequent data access the conversion results, as shown in Figure 4. A read CS bits onto the serial data outputs, DOUTA and DOUTB. The operation of new data can take place after the BUSY signal input can be held low for the entire serial read or it can be goes low (Figure 2), or, alternatively, a read operation of data pulsed to frame each channel read of 18 SCLK cycles. from the previous conversion process can take place while BUSY is high (Figure 3). Figure 44 shows a read of eight simultaneous conversion results using two DOUT lines on the AD7609. In this case, a 72 SCLK RD The pin is used to read data from the output conversion transfer is used to access data from the AD7609 and CS is held RD results register. Two pulses are required to read the full low to frame the entire 72 SCLK cycles. Data can also be clocked 18-bit conversion result from each channel. Applying a out using only one D line, in which case D A is recom- OUT OUT RD RD sequence of 16 pulses to the AD7609 pin clocks the mended to access all conversion data, because the channel data conversion results out from each channel onto the parallel is output in ascending order. For the AD7609 to access all eight output bus, DB[15:0], in ascending order. The first RD falling conversion results on one D line, a total of 144 SCLK cycles OUT edge after BUSY goes low clocks out DB[17:2] of the V1 result, are required. These 144 SCLK cycles can be framed by one CS the next RD falling edge updates the bus with DB[1:0] of the V1 signal or each group of 18 SCLK cycles can be individually RD result. It takes 16 pulses to read the eight 18-bit conversion framed by the CS signal. The disadvantage of using only one th RD results from the AD7609. The 16 falling edge of clocks out DOUT line is that the throughput rate is reduced if reading after RD the DB[1:0] conversion result for Channel V8. When the conversion. The unused D line should be left unconnected OUT signal is logic low, it enables the data conversion result from in serial mode. For the AD7609, if D B is to be used as a OUT each channel to be transferred to the digital host (DSP, FPGA). single D line, the channel results are output in the following OUT When there is only one AD7609 in a system/board and it order: V5, V6, V7, V8, V1, V2, V3, V4; however, the FRSTDATA does not share the parallel bus, data can be read using only one indicator returns low after V5 is read on DOUTB. CS RD control signal from the digital host. The and signals can be tied together, as shown in Figure 5. In this case, the data CS RD bus comes out of three-state on the falling edge of / . The CS RD combined and signal allows the data to be clocked out of the AD7609 and to be read by the digital host. In this case, CS is used to frame the data transfer of each data channel and 16 CS pulses are required to read the eight channels of data. Rev. A | Page 26 of 36 09760-040 Data Sheet AD7609 Figure 6 shows the timing diagram for reading one channel of are read on D B, the FRSTDATA output does not go high OUT CS when V1 is being output on this serial data output pin. It only data, framed by the signal, from the AD7609 in serial mode. goes high when V1 is available on D A (and this is when V5 The SCLK input signal provides the clock source for the serial OUT is available on D B). OUT read operation. CS goes low to access the data from the AD7609. The falling edge of CS takes the bus out of three-state and READING DURING CONVERSION clocks out the MSB of the 18-bit conversion result. This MSB Data can be read from the AD7609 while BUSY is high is valid on the first falling edge of the SCLK after the CS falling and conversions are in progress. This has little effect on the edge. The subsequent 17 data bits are clocked out of the performance of the converter and allows a faster throughput AD7609 on the SCLK rising edge. Data is valid on the SCLK rate to be achieved. A parallel or serial read can be performed falling edge. Eighteen clock cycles must be provided to the during conversions and when oversampling may or may not AD7609 to access each conversion result. be in use. Figure 3 shows the timing diagram for reading while The FRSTDATA output signal indicates when the first channel, BUSY is high in parallel or serial mode. Reading during conver- V1, is being read back. When the CS input is high, the FRSTDATA sions allows the full throughput rate to be achieved when using the serial interface with a V of 3.3 V to 5.25 V. output pin is in three-state. In serial mode, the falling edge of DRIVE CS takes FRSTDATA out of three-state and sets the FRSTDATA Data can be read from the AD7609 at any time other than on pin high indicating that the result from V1 is available on the the falling edge of BUSY because this is when the output data D A output data line. The FRSTDATA output returns to a OUT registers are updated with the new conversion data. t6, outlined th logic low following the 18 SCLK falling edge. If all channels in Table 3, should be observed in this condition. CS 72 SCLK D A V1 V2 V3 V4 OUT D B OUT V5 V6 V7 V8 Figure 44. AD7609 Serial Interface with Two D Lines OUT Rev. A | Page 27 of 36 09760-041 AD7609 Data Sheet The CONVST A and CONVST B pins must be tied/driven DIGITAL FILTER together when oversampling is turned on. When the over- The AD7609 contains an optional digital filter. This digital filter sampling function is turned on, the BUSY high time for the is a first-order sinc filter. This digital filter should be used in conversion process extends. The actual BUSY high time applications where slower throughput rates are used or where depends on the oversampling rate selected; the higher the higher signal-to-noise ratio or dynamic range is desirable. The oversampling rate, the longer the BUSY high, or total oversampling ratio of the digital filter is controlled using the conversion time, see Table 9. oversampling pins, OS [2:0] (see Table 9). OS 2 is the MSB Figure 46 shows that the conversion time extends as the over- control bit and OS 0 is the LSB control bit. Table 9 provides sampling rate is increased, and the BUSY signal lengthens for the the oversampling bit decoding to select the different oversample different oversampling rates. For example, a sampling frequency rates. The OS pins are latched on the falling edge of BUSY. of 10 kSPS yields a cycle time of 100 µs. Figure 46 shows OS × 2 This sets the oversampling rate for the next conversion (see and OS × 4; for a 10 kSPS example, there is adequate cycle time Figure 45). In addition to the oversampling function, the output to further increase the oversampling rate and yield greater result is decimated to 18-bit resolution. improvements in SNR performance. In an application where the initial sampling or throughput rate is at 200 kSPS, for If the OS pins are set to select an OS ratio of 8, the next example, and oversampling is turned on, the throughput rate CONVST x rising edge takes the first sample for each channel must be reduced to accommodate the longer conversion time and the remaining seven samples for all channels are taken with and to allow for the read. To achieve the fastest throughput an internally generated sampling signal. These samples are then rate possible when oversampling is turned on, the read can be averaged to yield an improvement in SNR performance. Table 9 performed during the BUSY high time. The falling edge of BUSY shows typical SNR performance for both the ±10 V and the is used to update the output data registers with the new conver- ±5 V ranges. As Table 9 indicates, there is an improvement in sion data; therefore, the reading of conversion data should not SNR as the OS ratio increases. As the OS ratio increases, the occur on this edge. Figure 47 to Figure 53 illustrate the effect of 3 dB frequency is reduced and the allowed sampling frequency oversampling on the code spread in a dc histogram plot. As the is also reduced. In an application where the required sampling oversample rate is increased, the spread of codes is reduced. (In frequency is 10 kSPS, an OS ratio of up to 16 can be used. In Figure 47 to Figure 53, AV = V = 5 V and the sampling CC DRIVE this case, the application sees an improvement in SNR but the rate was scaled with OS ratio.) input −3 dB bandwidth is limited to ~6 kHz. CONVST A, CONVST B OVERSAMPLE RATE LATCHED FOR CONVERSION N + 1 CONVERSION N CONVERSION N + 1 BUSY t OS_HOLD t OS_SETUP OS x Figure 45. OS Pin Timing Table 9. Oversampling Bit Decoding (100 Hz Input Signal) OS OS SNR ±5 V Range SNR ±10 V Range −3 dB BW 5 V Range −3 dB BW 10 V Maximum Throughput [2:0] Ratio (dB) (dB) (kHz) Range (kHz) CONVST x Frequency (kHz) 000 No OS 90.8 91.5 22 33 200 001 2 93.3 93.9 22 28.9 100 010 4 95.5 96.4 18.5 21.5 50 011 8 98 98.9 11.9 12 25 100 16 100.6 101 6 6 12.5 101 32 101.8 102 3 3 6.25 110 64 102.7 102.9 1.5 1.5 3.125 111 Invalid Rev. A | Page 28 of 36 09760-042 Data Sheet AD7609 t CYCLE CONVST A, t CONV CONVST B 19µs 9µs 4µs OS = 0 OS = 2 OS = 4 BUSY t 4 t 4 t 4 CS RD DATA: DB[15:0] Figure 46. AD7609—No Oversampling, Oversampling × 4, and Oversampling × 8 Using Read After Conversion 3000 1600 OVERSAMPLING BY 4 NO OVERSAMPLING 1384 1373 1400 2500 2394 2363 1167 1200 1062 2000 1000 840 1500 800 1340 727 1191 600 1000 492 450 400 422 500 210 219 341 200 83 100 79 27 49 32 10 5 8 2 11 2 1 0 0 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 –5 –4 –3 –2 –1 0 1 2 3 4 CODE CODE Figure 49. Histogram of Codes—OS × 4 (10 Codes) Figure 47. Histogram of Codes—No OS (19 Codes) 4000 2000 OVERSAMPLING BY 2 OVERSAMPLING BY 8 1785 1772 1800 3500 3392 1600 3000 1389 1400 2500 2397 1146 1200 2000 1000 1568 788 800 1500 599 600 1000 400 317 549 214 500 200 229 105 46 41 15 12 15 1 1 2 1 0 0 –4 –3 –2 –1 0 1 2 3 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 CODE CODE Figure 50. Histogram of Codes—OS × 8 (Eight Codes) Figure 48. Histogram Of Codes—OS × 2 (15 Codes) Rev. A | Page 29 of 36 NUMBER OF OCCURRENCES NUMBER OF OCCURRENCES 09760-045 09760-044 NUMBER OF OCCURRENCES NUMBER OF OCCURRENCES 09760-043 09760-047 09760-046 AD7609 Data Sheet 4500 When the oversampling mode is selected, this has the effect OVERSAMPLING BY 16 of adding a digital filter function after the ADC. The different 4000 3833 oversampling rates and the CONVST x sampling frequency 3500 3279 produces different digital filter frequency profiles. 3000 Figure 54 to Figure 59 show the digital filter frequency profiles 2500 for the different oversampling rates. The combination of the analog antialiasing filter and the oversampling digital filter can 2000 be used to eliminate or reduce the complexity of the design of 1500 the filter before the AD7609. The digital filtering combines 1000 steep roll-off and linear phase response. 657 406 385 500 0 AV = 5V CC 14 3 V = 5V 0 DRIVE –10 –3 –2 –1 0 1 2 T = 25°C A 10V RANGE CODE –20 OS BY 2 Figure 51. Histogram of Codes—OS × 16 (Six Codes) –30 6000 –40 OVERSAMPLING BY 32 5090 –50 5000 –60 4000 –70 –80 3000 2716 –90 100 1k 10k 100k 1M 10M 2000 FREQUENCY (Hz) Figure 54. Digital Filter Response for OS × 2 1000 341 0 45 AV = 5V CC 0 V = 5V –10 DRIVE –2 –1 0 1 T = 25°C A CODE 10V RANGE –20 OS BY 4 Figure 52. Histogram of Codes—OS × 32 (Four Codes) –30 7000 –40 OVERSAMPLING BY 64 5871 –50 6000 –60 5000 –70 –80 4000 –90 3000 –100 2245 100 1k 10k 100k 1M 10M 2000 FREQUENCY (Hz) Figure 55. Digital Filter Response for OS × 4 1000 75 1 0 –2 –1 0 1 CODE Figure 53. Histogram of Codes – OS × 64 (Four Codes) Rev. A | Page 30 of 36 NUMBER OF OCCURENCES NUMBER OF OCCURENCES NUMBER OF OCCURENCES 09760-050 09760-049 09760-048 ATTENUATION (dB) ATTENUATION (dB) 09760-052 09760-051 Data Sheet AD7609 0 0 AV = 5V AV = 5V CC CC V = 5V V = 5V –10 DRIVE –10 DRIVE T = 25°C T = 25°C A A 10V RANGE 10V RANGE –20 –20 OS BY 8 OS BY 32 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 56. Digital Filter Response for OS × 8 Figure 58. Digital Filter Response for OS × 32 0 0 AV = 5V AV = 5V CC CC V = 5V V = 5V DRIVE DRIVE –10 –10 T = 25°C T = 25°C A A 10V RANGE 10V RANGE –20 –20 OS BY 16 OS BY 64 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 57. Digital Filter Response for OS × 16 Figure 59. Digital Filter Response for OS × 64 Rev. A | Page 31 of 36 ATTENUATION (dB) ATTENUATION (dB) 09760-054 09760-053 ATTENUATION (dB) ATTENUATION (dB) 09760-056 09760-055 AD7609 Data Sheet LAYOUT GUIDELINES The printed circuit board that houses the AD7609 should be designed so that the analog and digital sections are separated and confined to different areas of the board. Use at least one ground plane. It can be common or split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7609. If the AD7609 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point, a star ground point, which should be established as close as possible to the AD7609. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Individual vias or Figure 60. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and multiple vias to the ground plane should be used for each REGCAP Pins ground pin. Avoid running digital lines under the devices because doing so couples noise onto the die. Allow the analog ground plane to run under the AD7609 to avoid noise coupling. Shield fast- switching signals like CONVST A, CONVST B, or clocks with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Avoid crossover of digital and analog signals. Run traces on layers in close proximity on the board at right angles to each other to reduce the effect of feedthrough through the board. The power supply lines to the AVCC and VDRIVE pins on the AD7609 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes. Good connec- tions should be made between the AD7609 supply pins and the power tracks on the board; this should involve the use of a single Figure 61. Bottom Layer Decoupling via or multiple vias for each supply pin. Good decoupling is also important to lower the supply imped- ance presented to the AD7609 and to reduce the magnitude of the supply spikes. Place the decoupling capacitors close to, ideally right up against, these pins and their corresponding ground pins. Place the decoupling capacitors for the REFIN/ REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7609 pins. Where possible, they should be placed on the same side of the board as the AD7609 device. Figure 60 shows the recommended decoupling on the top layer of the AD7609 board. Figure 61 shows bottom layer decoupling. Bottom layer decoupling is for the four AV pins CC and the V pin. DRIVE Rev. A | Page 32 of 36 09760-058 09760-057 Data Sheet AD7609 To ensure good device-to-device performance matching in a system that contains multiple AD7609 devices, a symmetrical layout between the AD7609 devices is important. Figure 62 shows a layout with two AD7609 devices. The AVCC supply plane runs to the right of both devices. The VDRIVE supply track runs to the left of the two AD7609 devices. The reference chip is positioned between both AD7609 devices and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 to U2. A solid ground plane is used. These symmetrical layout principles can be applied to a system that contains more than two AD7609 devices. The AD7609 devices can be placed in a north-to-south direction with the reference voltage located midway between the AD7609 devices and the reference track running in the north-to-south direction similar to Figure 62. Figure 62. Multiple AD7609 Layout, Top Layer and Supply Plane Layer Rev. A | Page 33 of 36 09760-059 AD7609 Data Sheet OUTLINE DIMENSIONS 12.20 12.00 SQ 0.75 11.80 0.60 1.60 MAX 0.45 64 49 1 48 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 1.45 0.20 1.40 0.09 1.35 7° 3.5° 16 33 0.15 0° SEATING 17 32 0.05 0.08 PLANE COPLANARITY VIEW A 0.27 0.50 0.22 BSC VIEW A LEAD PITCH 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 63. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD7609BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7609BSTZ-RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 EVAL-AD7609EDZ −40°C to +85°C Evaluation Board for the AD7609 CED1Z Converter Evaluation Development 1 Z = RoHS Compliant Part. Rev. A | Page 34 of 36 051706-A Data Sheet AD7609 NOTES Rev. A | Page 35 of 36 AD7609 Data Sheet NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09760-0-2/12(A) Rev. A | Page 36 of 36