ANALOG DEVICES AD7606

8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC Data Sheet AD7606/AD7606-6/AD7606-4 FEATURES APPLICATIONS 8/6/4 simultaneously sampled inputs Power-line monitoring and protection systems True bipolar analog input ranges: ±10 V, ±5 V Multiphase motor control Single 5 V analog supply and 2.3 V to 5 V V Instrumentation and control systems DRIVE Fully integrated data acquisition solution Multiaxis positioning systems Analog input clamp protection Data acquisition systems (DAS) Input buffer with 1 MΩ analog input impedance Table 1. High Resolution, Bipolar Input, Simultaneous Second-order antialiasing analog filter Sampling DAS Solutions On-chip accurate reference and reference buffer Single- True Number of 16-bit ADC with 200 kSPS on all channels Ended Differential Simultaneous Oversampling capability with digital filter Resolution Inputs Inputs Sampling Channels Flexible parallel/serial interface 18 Bits AD7608 AD7609 8 SPI/QSPI™/MICROWIRE™/DSP compatible 16 Bits AD7606 8 Performance AD7606-6 6 7 kV ESD rating on analog input channels AD7606-4 4 95.5 dB SNR, −107 dB THD 14 Bits AD7607 8 ±0.5 LSB INL, ±0.5 LSB DNL Low power: 100 mW Standby mode: 25 mW 64-lead LQFP package FUNCTIONAL BLOCK DIAGRAM AV AV CC CC REGCAP REGCAP REFCAPB REFCAPA 1MΩ R FB V1 CLAMP T/H SECOND- V1GND CLAMP ORDER LPF 2.5V 2.5V R 1MΩ FB LDO LDO 1MΩ R FB REFIN/REFOUT V2 CLAMP T/H SECOND- V2GND CLAMP ORDER LPF R 1MΩ FB REF SELECT 2.5V REF AGND 1MΩ R FB V3 CLAMP T/H OS 2 SECOND- V3GND CLAMP ORDER LPF R 1MΩ FB OS 1 OS 0 1MΩ R FB V4 CLAMP T/H D A SECOND- OUT V4GND CLAMP ORDER LPF SERIAL R 1MΩ FB D B OUT 8:1 MUX PARALLEL/ RD/SCLK 1MΩ R FB 16-BIT DIGITAL SERIAL V5 CLAMP SAR FILTER T/H INTERFACE CS SECOND- V5GND CLAMP ORDER LPF R 1MΩ FB PAR/SER/BYTE SEL V DRIVE 1MΩ R FB V6 CLAMP T/H SECOND- DB[15:0] V6GND CLAMP PARALLEL ORDER LPF R 1MΩ FB AD7606 1MΩ R FB V7 CLAMP T/H SECOND- V7GND CLAMP ORDER LPF CLK OSC R 1MΩ FB 1MΩ R FB BUSY V8 CLAMP CONTROL T/H INPUTS SECOND- FRSTDATA V8GND CLAMP ORDER LPF R 1MΩ FB AGND CONVST A CONVST B RESET RANGE Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved. 08479-001 AD7606/AD7606-6/AD7606-4 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input ............................................................................... 22 Applications ....................................................................................... 1 ADC Transfer Function ............................................................. 23 Functional Block Diagram .............................................................. 1 Internal/External Reference ...................................................... 24 Revision History ............................................................................... 2 Typical Connection Diagram ................................................... 25 General Description ......................................................................... 3 Power-Down Modes .................................................................. 25 Specifications ..................................................................................... 4 Conversion Control ................................................................... 26 Timing Specifications .................................................................. 7 Digital Interface .............................................................................. 27 Absolute Maximum Ratings .......................................................... 11 Parallel Interface (PAR/SER/BYTE SEL = 0) .......................... 27 Thermal Resistance .................................................................... 11 Parallel Byte (PAR/SER/BYTE SEL = 1, DB15 = 1) ............... 27 ESD Caution ................................................................................ 11 Serial Interface (PAR/SER/BYTE SEL = 1) ............................. 27 Pin Configurations and Function Descriptions ......................... 12 Reading During Conversion ..................................................... 28 Typical Performance Characteristics ........................................... 17 Digital Filter ................................................................................ 29 Terminology .................................................................................... 21 Layout Guidelines....................................................................... 32 Theory of Operation ...................................................................... 22 Outline Dimensions ....................................................................... 34 Converter Details........................................................................ 22 Ordering Guide .......................................................................... 34 REVISION HISTORY 1/12—Rev. B to Rev. C Changes to Analog Input Ranges Section ................................... 22 10/11—Rev. A to Rev. B Changes to Input High Voltage (V ) and Input Low Voltage INH (V ) Parameters and Endnote 6, Table 2 ..................................... 4 INL Changes to Table 3 ............................................................................ 7 Changes to Table 4 .......................................................................... 11 Changes to Pin 32 Description, Table 6 ....................................... 13 Changes to Analog Input Clamp Protection Section ................. 22 Changes to Typical Connection Diagram Section ..................... 25 8/10—Rev. 0 to Rev. A Changes to Note 1, Table 2 .............................................................. 6 5/10—Revision 0: Initial Version Rev. C | Page 2 of 36 Data Sheet AD7606/AD7606-6/AD7606-4 GENERAL DESCRIPTION 1 The AD7606 /AD7606-6/AD7606-4 are 16-bit, simultaneous The AD7606/AD7606-6/AD7606-4 operate from a single 5 V sampling, analog-to-digital data acquisition systems (DAS) with supply and can accommodate ±10 V and ±5 V true bipolar input eight, six, and four channels, respectively. Each part contains signals while sampling at throughput rates up to 200 kSPS for analog input clamp protection, a second-order antialiasing filter, all channels. The input clamp protection circuitry can tolerate a track-and-hold amplifier, a 16-bit charge redistribution successive voltages up to ±16.5 V. The AD7606 has 1 MΩ analog input approximation analog-to-digital converter (ADC), a flexible impedance regardless of sampling frequency. The single supply digital filter, a 2.5 V reference and reference buffer, and high operation, on-chip filtering, and high input impedance eliminate speed serial and parallel interfaces. the need for driver op amps and external bipolar supplies. The AD7606/AD7606-6/AD7606-4 antialiasing filter has a 3 dB cutoff frequency of 22 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the 3 dB bandwidth. 1 Patent pending. Rev. C | Page 3 of 36 AD7606/AD7606-6/AD7606-4 Data Sheet SPECIFICATIONS 1 VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE f = 1 kHz sine wave unless otherwise noted IN 2, 3 Signal-to-Noise Ratio (SNR) Oversampling by 16; ±10 V range; f = 130 Hz 94 95.5 dB IN Oversampling by 16; ±5 V range; fIN = 130 Hz 93 94.5 dB No oversampling; ±10 V Range 88.5 90 dB No oversampling; ±5 V range 87.5 89 dB 2 Signal-to-(Noise + Distortion) (SINAD) No oversampling; ±10 V range 88 90 dB No oversampling; ±5 V range 87 89 dB Dynamic Range No oversampling; ±10 V range 90.5 dB No oversampling; ±5 V range 90 dB 2 Total Harmonic Distortion (THD) −107 −95 dB 2 Peak Harmonic or Spurious Noise (SFDR) −108 dB 2 Intermodulation Distortion (IMD) fa = 1 kHz, fb = 1.1 kHz Second-Order Terms −110 dB Third-Order Terms −106 dB 2 Channel-to-Channel Isolation fIN on unselected channels up to 160 kHz −95 dB ANALOG INPUT FILTER Full Power Bandwidth −3 dB, ±10 V range 23 kHz −3 dB, ±5 V range 15 kHz −0.1 dB, ±10 V range 10 kHz −0.1 dB, ±5 V range 5 kHz t ±10 V Range 11 µs GROUP DELAY ±5 V Range 15 µs DC ACCURACY Resolution No missing codes 16 Bits 2 4 Differential Nonlinearity ±0.5 ±0.99 LSB 2 Integral Nonlinearity ±0.5 ±2 LSB Total Unadjusted Error (TUE) ±10 V range ±6 LSB ±5 V range ±12 LSB 2, 5 Positive Full-Scale Error External reference ±8 ±32 LSB Internal reference ±8 LSB Positive Full-Scale Error Drift External reference ±2 ppm/°C Internal reference ±7 ppm/°C 2 Positive Full-Scale Error Matching ±10 V range 5 32 LSB ±5 V range 16 40 LSB 2, 6 Bipolar Zero Code Error ±10 V range ±1 ±6 LSB ± 5 V range ±3 ±12 LSB Bipolar Zero Code Error Drift ±10 V range 10 µV/°C ± 5 V range 5 µV/°C 2 Bipolar Zero Code Error Matching ±10 V range 1 8 LSB ±5 V range 6 22 LSB 2, 5 Negative Full-Scale Error External reference ±8 ±32 LSB Internal reference ±8 LSB Negative Full-Scale Error Drift External reference ±4 ppm/°C Internal reference ±8 ppm/°C 2 Negative Full-Scale Error Matching ±10 V range 5 32 LSB ±5 V range 16 40 LSB Rev. C | Page 4 of 36 Data Sheet AD7606/AD7606-6/AD7606-4 Parameter Test Conditions/Comments Min Typ Max Unit ANALOG INPUT Input Voltage Ranges RANGE = 1 ±10 V RANGE = 0 ±5 V Analog Input Current 10 V; see Figure 31 5.4 µA 5 V; see Figure 31 2.5 µA 7 Input Capacitance 5 pF Input Impedance See the Analog Input section 1 MΩ REFERENCE INPUT/OUTPUT Reference Input Voltage Range See the ADC Transfer Function section 2.475 2.5 2.525 V DC Leakage Current ±1 µA 7 Input Capacitance REF SELECT = 1 7.5 pF Reference Output Voltage REFIN/REFOUT 2.49/ V 2.505 Reference Temperature Coefficient ±10 ppm/°C LOGIC INPUTS Input High Voltage (V ) 0.7 × V V INH DRIVE Input Low Voltage (V ) 0.3 × V V INL DRIVE Input Current (IIN) ±2 µA 7 Input Capacitance (CIN) 5 pF LOGIC OUTPUTS Output High Voltage (VOH) ISOURCE = 100 µA VDRIVE − 0.2 V Output Low Voltage (VOL) ISINK = 100 µA 0.2 V Floating-State Leakage Current ±1 ±20 µA 7 Floating-State Output Capacitance 5 pF Output Coding Twos complement CONVERSION RATE Conversion Time All eight channels included; see Table 3 4 µs Track-and-Hold Acquisition Time 1 µs Throughput Rate Per channel, all eight channels included 200 kSPS POWER REQUIREMENTS AVCC 4.75 5.25 V VDRIVE 2.3 5.25 V ITOTAL Digital inputs = 0 V or VDRIVE Normal Mode (Static) AD7606 16 22 mA AD7606-6 14 20 mA AD7606-4 12 17 mA 8 Normal Mode (Operational) fSAMPLE = 200 kSPS AD7606 20 27 mA AD7606-6 18 24 mA AD7606-4 15 21 mA Standby Mode 5 8 mA Shutdown Mode 2 6 µA Rev. C | Page 5 of 36 AD7606/AD7606-6/AD7606-4 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit Power Dissipation Normal Mode (Static) AD7606 80 115.5 mW 8 Normal Mode (Operational) fSAMPLE = 200 kSPS AD7606 100 142 mW AD7606-6 90 126 mW AD7606-4 75 111 mW Standby Mode 25 42 mW Shutdown Mode 10 31.5 µW 1 Temperature range for the B version is −40°C to +85°C. The AD7606 is operational up to 125°C with throughput rates ≤ 160 kSPS, and the SNR typically reduces by 0.7 dB at 125°C. 2 See the Terminology section. 3 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with V = 5 V, SNR typically reduces by 1.5 dB DRIVE and THD by 3 dB. 4 LSB means least significant bit. With ±5 V input range, 1 LSB = 152.58 µV. With ±10 V input range, 1 LSB = 305.175 µV. 5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section. 7 Sample tested during initial release to ensure compliance. 8 Operational power/current figure includes contribution when running in oversampling mode. Rev. C | Page 6 of 36 Data Sheet AD7606/AD7606-6/AD7606-4 TIMING SPECIFICATIONS 1 AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. Table 3. Limit at T , T Limit at T , T MIN MAX MIN MAX (0.1 × V and (0.3 × V and DRIVE DRIVE 0.9 × VDRIVE 0.7 × VDRIVE Logic Input Levels) Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description PARALLEL/SERIAL/BYTE MODE tCYCLE 1/throughput rate 5 5 µs Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using D A and D B lines OUT OUT 9.4 µs Serial mode reading after a conversion; V = 2.7 V DRIVE 9.7 10.7 µs Serial mode reading after a conversion; VDRIVE = 2.3 V, D A and D B lines OUT OUT 2 tCONV Conversion time 3.45 4 4.15 3.45 4 4.15 µs Oversampling off; AD7606 3 3 µs Oversampling off; AD7606-6 2 2 µs Oversampling off; AD7606-4 7.87 9.1 7.87 9.1 µs Oversampling by 2; AD7606 16.05 18.8 16.05 18.8 µs Oversampling by 4; AD7606 33 39 33 39 µs Oversampling by 8; AD7606 66 78 66 78 µs Oversampling by 16; AD7606 133 158 133 158 µs Oversampling by 32; AD7606 257 315 257 315 µs Oversampling by 64; AD7606 tWAKE-UP STANDBY 100 100 µs STBY rising edge to CONVST x rising edge; power-up time from standby mode t WAKE-UP SHUTDOWN Internal Reference 30 30 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode External Reference 13 13 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode t 50 50 ns RESET high pulse width RESET tOS_SETUP 20 20 ns BUSY to OS x pin setup time t 20 20 ns BUSY to OS x pin hold time OS_HOLD t 40 45 ns CONVST x high to BUSY high 1 t2 25 25 ns Minimum CONVST x low pulse t 25 25 ns Minimum CONVST x high pulse 3 t4 0 0 ns BUSY falling edge to CS falling edge setup time 3 t5 0.5 0.5 ms Maximum delay allowed between CONVST A, CONVST B rising edges t6 25 25 ns Maximum time between last CS rising edge and BUSY falling edge t 25 25 ns Minimum delay between RESET low to CONVST x high 7 PARALLEL/BYTE READ OPERATION t 0 0 ns 8 CS to RD setup time t 0 0 ns CS to RD hold time 9 t10 RD low pulse width 16 19 ns V above 4.75 V DRIVE 21 24 ns VDRIVE above 3.3 V 25 30 ns V above 2.7 V DRIVE 32 37 ns V above 2.3 V DRIVE t11 15 15 ns RD high pulse width t 22 22 ns 12 CS high pulse width (see Figure 5); CS and RD linked Rev. C | Page 7 of 36 AD7606/AD7606-6/AD7606-4 Data Sheet Limit at T , T Limit at T , T MIN MAX MIN MAX (0.1 × V and (0.3 × V and DRIVE DRIVE 0.9 × VDRIVE 0.7 × VDRIVE Logic Input Levels) Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description t Delay from CS until DB[15:0] three-state disabled 13 16 19 ns VDRIVE above 4.75 V 20 24 ns V above 3.3 V DRIVE 25 30 ns VDRIVE above 2.7 V 30 37 ns V above 2.3 V DRIVE 4 t Data access time after RD falling edge 14 16 19 ns VDRIVE above 4.75 V 21 24 ns V above 3.3 V DRIVE 25 30 ns VDRIVE above 2.7 V 32 37 ns VDRIVE above 2.3 V t 6 6 ns RD 15 Data hold time after falling edge t16 6 6 ns CS to DB[15:0] hold time t 22 22 ns 17 Delay from CS rising edge to DB[15:0] three-state enabled SERIAL READ OPERATION fSCLK Frequency of serial read clock 23.5 20 MHz V above 4.75 V DRIVE 17 15 MHz VDRIVE above 3.3 V 14.5 12.5 MHz VDRIVE above 2.7 V 11.5 10 MHz V above 2.3 V DRIVE t18 Delay from CS until D A/D B three-state OUT OUT disabled/delay from CS until MSB valid 15 18 ns V above 4.75 V DRIVE 20 23 ns VDRIVE above 3.3 V 30 35 ns V = 2.3 V to 2.7 V DRIVE 4 t19 Data access time after SCLK rising edge 17 20 ns V above 4.75 V DRIVE 23 26 ns V above 3.3 V DRIVE 27 32 ns VDRIVE above 2.7 V 34 39 ns V above 2.3 V DRIVE t 0.4 t 0.4 t ns SCLK low pulse width 20 SCLK SCLK t21 0.4 tSCLK 0.4 tSCLK ns SCLK high pulse width t 7 7 SCLK rising edge to D A/D B valid hold time 22 OUT OUT t23 22 22 ns CS rising edge to D A/D B three-state enabled OUT OUT FRSTDATA OPERATION t24 Delay from CS falling edge until FRSTDATA three- state disabled 15 18 ns VDRIVE above 4.75 V 20 23 ns V above 3.3 V DRIVE 25 30 ns V above 2.7 V DRIVE 30 35 ns VDRIVE above 2.3 V t25 ns CS Delay from falling edge until FRSTDATA high, serial mode 15 18 ns V above 4.75 V DRIVE 20 23 ns VDRIVE above 3.3 V 25 30 ns V above 2.7 V DRIVE 30 35 ns V above 2.3 V DRIVE t26 Delay from RD falling edge to FRSTDATA high 16 19 ns V above 4.75 V DRIVE 20 23 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 30 35 ns V above 2.3 V DRIVE Rev. C | Page 8 of 36 Data Sheet AD7606/AD7606-6/AD7606-4 Limit at T , T Limit at T , T MIN MAX MIN MAX (0.1 × V and (0.3 × V and DRIVE DRIVE 0.9 × VDRIVE 0.7 × VDRIVE Logic Input Levels) Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description t Delay from RD falling edge to FRSTDATA low 27 19 22 ns VDRIVE = 3.3 V to 5.25V 24 29 ns V = 2.3 V to 2.7V DRIVE th t28 Delay from 16 SCLK falling edge to FRSTDATA low 17 20 ns V = 3.3 V to 5.25V DRIVE 22 27 ns V = 2.3 V to 2.7V DRIVE t29 24 29 ns Delay from CS rising edge until FRSTDATA three- state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. R F DRIVE 2 In oversampling mode, typical tCONV for the AD7606-6 and AD7606-4 can be calculated using ((N × tCONV) + ((N − 1) × 1 µs)). N is the oversampling ratio. For the AD7606-6, tCONV = 3 µs; and for the AD7606-4, tCONV = 2 µs. 3 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets. 4 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins. Timing Diagrams t 5 CONVST A, CONVST B t CYCLE t 2 CONVST A, t CONVST B 3 t CONV t 1 BUSY t 4 CS t 7 t RESET RESET Figure 2. CONVST Timing—Reading After a Conversion t 5 CONVST A, CONVST B t CYCLE t 2 CONVST A, t CONVST B 3 t CONV t 1 BUSY t 6 CS t 7 t RESET RESET Figure 3. CONVST Timing—Reading During a Conversion Rev. C | Page 9 of 36 08479-003 08479-002 AD7606/AD7606-6/AD7606-4 Data Sheet CS t 9 t t 8 11 t 10 t RD 16 t 13 t t 17 14 t 15 DATA: INVALID V1 V2 V3 V4 V7 V8 DB[15:0] t t t 26 27 29 t 24 FRSTDATA Figure 4. Parallel Mode, Separate CS and RD Pulses t 12 CS AND RD t t 16 13 t 17 DATA: V1 V2 V3 V4 V5 V6 V7 V8 DB[15:0] FRSTDATA CS RD Figure 5. and , Linked Parallel Mode CS t t 21 20 SCLK t 19 t 22 t t 23 18 D A, OUT DB15 DB14 DB13 DB1 DB0 D B OUT t t t 29 25 28 FRSTDATA Figure 6. Serial Read Operation (Channel 1) CS t t 8 9 t 10 t 11 t 16 RD t 13 t t 17 t 15 14 HIGH LOW HIGH LOW DATA: DB[7:0] INVALID BYTE V1 BYTE V1 BYTE V8 BYTE V8 t 26 t t 29 27 t 24 FRSTDATA Figure 7. BYTE Mode Read Operation Rev. C | Page 10 of 36 08479-007 08479-005 08479-004 08479-006 Data Sheet AD7606/AD7606-6/AD7606-4 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 4. θ is specified for the worst-case conditions, that is, a device Parameter Rating JA soldered in a circuit board for surface-mount packages. These AV to AGND −0.3 V to +7 V CC V to AGND −0.3 V to AV + 0.3 V specifications apply to a 4-layer board. DRIVE CC 1 Analog Input Voltage to AGND ±16.5 V Table 5. Thermal Resistance Digital Input Voltage to AGND −0.3 V to VDRIVE + 0.3 V Package Type θJA θJC Unit Digital Output Voltage to AGND −0.3 V to V + 0.3 V DRIVE 64-Lead LQFP 45 11 °C/W REFIN to AGND −0.3 V to AV + 0.3 V CC 1 Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range ESD CAUTION B Version −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Pb/SN Temperature, Soldering Reflow (10 sec to 30 sec) 240 (+0)°C Pb-Free Temperature, Soldering Reflow 260 (+0)°C ESD (All Pins Except Analog Inputs) 2 kV ESD (Analog Input Pins Only) 7 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 11 of 36 AD7606/AD7606-6/AD7606-4 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AV 1 48 AV CC CC ANALOG INPUT PIN 1 2 47 AGND AGND DECOUPLING CAP PIN OS 0 3 46 REFGND POWER SUPPLY OS 1 4 45 REFCAPB GROUND PIN OS 2 5 44 REFCAPA 6 43 DATA OUTPUT PAR/SER/BYTE SEL REFGND AD7606 7 42 REFIN/REFOUT DIGITAL OUTPUT STBY TOP VIEW (Not to Scale) 8 41 RANGE AGND DIGITAL INPUT 9 40 CONVST A AGND REFERENCE INPUT/OUTPUT CONVST B 10 39 REGCAP 11 38 AV RESET CC AV RD/SCLK 12 37 CC 13 36 REGCAP CS BUSY 14 35 AGND FRSTDATA 15 34 REF SELECT DB0 16 33 DB15/BYTE SEL 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 8. AD7606 Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 AV AV 48 CC CC ANALOG INPUT PIN 1 2 47 AGND AGND DECOUPLING CAP PIN 3 46 OS 0 REFGND POWER SUPPLY 4 45 OS 1 REFCAPB GROUND PIN OS 2 5 44 REFCAPA 6 43 REFGND DATA OUTPUT PAR/SER/BYTE SEL AD7606-6 7 42 REFIN/REFOUT STBY TOP VIEW DIGITAL OUTPUT (Not to Scale) RANGE 8 41 AGND DIGITAL INPUT 9 40 AGND CONVST A REFERENCE INPUT/OUTPUT 10 39 REGCAP CONVST B 11 38 AV RESET CC 12 37 AV RD/SCLK CC 13 36 CS REGCAP BUSY 14 35 AGND FRSTDATA 15 34 REF SELECT DB0 16 33 DB15/BYTE SEL 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 9. AD7606-6 Pin Configuration Rev. C | Page 12 of 36 DB1 AGND DB1 V8GND DB2 AGND DB2 V8 DB3 V6GND DB3 V7GND DB4 V6 DB4 V7 V5GND V6GND DB5 DB5 V5 V6 DB6 DB6 V4GND V5GND V V DRIVE DRIVE V4 V5 DB7/D A DB7/D A OUT OUT AGND V4GND DB8/D B DB8/D B OUT OUT AGND V4 AGND AGND V3GND V3GND DB9 DB9 V3 V3 DB10 DB10 V2GND V2GND DB11 DB11 V2 V2 DB12 DB12 V1GND V1GND DB13 DB13 V1 V1 DB14/HBEN DB14/HBEN 08479-009 08479-008 Data Sheet AD7606/AD7606-6/AD7606-4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 AV AV 48 CC CC ANALOG INPUT PIN 1 2 47 AGND AGND DECOUPLING CAP PIN 3 46 OS 0 REFGND POWER SUPPLY 4 45 OS 1 REFCAPB GROUND PIN 5 44 OS 2 REFCAPA 6 43 DATA OUTPUT REFGND PAR/SER/BYTE SEL AD7606-4 7 42 REFIN/REFOUT STBY TOP VIEW DIGITAL OUTPUT (Not to Scale) RANGE 8 41 AGND DIGITAL INPUT 9 40 AGND CONVST A REFERENCE INPUT/OUTPUT 10 39 REGCAP CONVST B RESET 11 38 AV CC RD/SCLK 12 37 AV CC 13 36 REGCAP CS BUSY 14 35 AGND FRSTDATA 15 34 REF SELECT DB0 16 33 DB15/BYTE SEL 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 10. AD7606-4 Pin Configuration Table 6. Pin Function Descriptions Mnemonic 1 Pin No. Type AD7606 AD7606-6 AD7606-4 Description 1, 37, 38, P AV AV AV Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to CC CC CC 48 the internal front-end amplifiers and to the ADC core. These supply pins should be decoupled to AGND. 2, 26, 35, P AGND AGND AGND Analog Ground. These pins are the ground reference points for all analog 40, 41, 47 circuitry on the AD7606. All analog input signals and external reference signals should be referred to these pins. All six of these AGND pins should connect to the AGND plane of a system. 5, 4, 3 DI OS [2:0] OS [2:0] OS [2:0] Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2 is the MSB control bit, and OS 0 is the LSB control bit. See the Digital Filter section for more details about the oversampling mode of operation and Table 9 for oversampling bit decoding. 6 DI PAR/SER/ PAR/SER/ PAR/SER/ Parallel/Serial/Byte Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel interface is selected. If this pin is tied to a logic high, BYTE SEL BYTE SEL BYTE SEL the serial interface is selected. Parallel byte interface mode is selected when this pin is logic high and DB15/BYTE SEL is logic high (see Table 8). In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA pin and the DB8/DOUTB pin function as serial data outputs. When the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to ground. In byte mode, DB15, in conjunction with PAR/SER/BYTE SEL, is used to select the parallel byte mode of operation (see Table 8). DB14 is used as the HBEN pin. DB[7:0] transfer the 16-bit conversion results in two RD operations, with DB0 as the LSB of the data transfers. 7 DI STBY STBY STBY Standby Mode Input. This pin is used to place the AD7606/AD7606-6/ AD7606-4 into one of two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin, as shown in Table 7. When in standby mode, all circuitry, except the on- chip reference, regulators, and regulator buffers, is powered down. When in shutdown mode, all circuitry is powered down. Rev. C | Page 13 of 36 DB1 AGND DB2 AGND DB3 AGND DB4 AGND V4GND DB5 V4 DB6 V3GND V DRIVE V3 DB7/D A OUT AGND DB8/D B OUT AGND AGND AGND DB9 AGND DB10 V2GND DB11 V2 DB12 V1GND DB13 V1 DB14/HBEN 08479-010 AD7606/AD7606-6/AD7606-4 Data Sheet Mnemonic 1 Pin No. Type AD7606 AD7606-6 AD7606-4 Description 8 DI RANGE RANGE RANGE Analog Input Range Selection. Logic input. The polarity on this pin deter- mines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic change on this pin has an immediate effect on the analog input range. Changing this pin during a conversion is not recommended for fast throughput rate applications. See the Analog Input section for more information. 9, 10 DI CONVST A, CONVST A, CONVST A, Conversion Start Input A, Conversion Start Input B. Logic inputs. These CONVST B CONVST B CONVST B logic inputs are used to initiate conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A and CONVST B can be shorted together, and a single convert start signal can be applied. Alternatively, CONVST A can be used to initiate simultaneous sampling: V1, V2, V3, and V4 for the AD7606; V1, V2, and V3 for the AD7606-6; and V1 and V2 for the AD7606-4. CONVST B can be used to initiate simultaneous sampling on the other analog inputs: V5, V6, V7, and V8 for the AD7606; V4, V5, and V6 for the AD7606-6; and V3 and V4 for the AD7606-4. This is possible only when oversampling is not switched on. When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold circuitry for the respective analog inputs is set to hold. 11 DI RESET RESET RESET Reset Input. When set to logic high, the rising edge of RESET resets the AD7606/AD7606-6/AD7606-4. The part should receive a RESET pulse after power-up. The RESET high pulse should typically be 50 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers reset to all zeros. 12 DI RD/SCLK RD/SCLK RD/SCLK Parallel Data Read Control Input When the Parallel Interface Is Selected (RD)/ Serial Clock Input When the Serial Interface Is Selected (SCLK). When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the DOUTA and DOUTB data output lines out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the DOUTA and DOUTB serial data outputs. For more information, see the Conversion Control section. 13 DI CS CS CS Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the DB[15:0] output bus is enabled and the conversion result is output on the parallel data bus lines. In serial mode, CS is used to frame the serial read transfer and clock out the MSB of the serial output data. 14 DO BUSY BUSY BUSY Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and indicates that the conversion process has started. The BUSY output remains high until the conversion process for all channels is complete. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and is available to read after a Time t . Any data read while BUSY is high must be completed before the 4 falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high. 15 DO FRSTDATA FRSTDATA FRSTDATA Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on the parallel, byte, or serial interface. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of takes FRSTDATA out of three-state. In parallel mode, the falling CS edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, indicating that the result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low following the next falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS because th this clocks out the MSB of V1 on D A. It returns low on the 16 SCLK OUT falling edge. See the Conversion Control section falling edge after the CS for more details. Rev. C | Page 14 of 36 Data Sheet AD7606/AD7606-6/AD7606-4 Mnemonic 1 Pin No. Type AD7606 AD7606-6 AD7606-4 Description 22 to 16 DO DB[6:0] DB[6:0] DB[6:0] Parallel Output Data Bits, DB6 to DB0. When /SER/BYTE SEL = 0, these PAR pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB6 to DB0 of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to AGND. When operating in parallel byte interface mode, DB[7:0] outputs the 16-bit con- version result in two RD operations. DB7 (Pin 24) is the MSB; DB0 is the LSB. 23 P VDRIVE VDRIVE VDRIVE Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface (that is, DSP and FPGA). 24 DO DB7/D A DB7/D A DB7/D A Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (D A). OUT OUT OUT OUT When PAR/SER/BYTE SEL = 0, this pins acts as a three-state parallel digital input/output pin. When and are low, this pin is used to output DB7 CS RD of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions as DOUTA and outputs serial conversion data (see the Conversion Control section for more details). When operating in parallel byte mode, DB7 is the MSB of the byte. 25 DO DB8/D B DB8/D B DB8/D B Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (D B). OUT OUT OUT OUT When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB8 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions as DOUTB and outputs serial conversion data (see the Conversion Control section for more details). 31 to 27 DO DB[13:9] DB[13:9] DB[13:9] Parallel Output Data Bits, DB13 to DB9. When PAR/SER/BYTE SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB13 to DB9 of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to AGND. 32 DO/DI DB14/ DB14/ DB14/ Parallel Output Data Bit 14 (DB14)/High Byte Enable (HBEN). When PAR/ HBEN HBEN HBEN SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB14 of the conversion result. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606/ AD7606-6/AD7606-4 operate in parallel byte interface mode. In parallel byte mode, the HBEN pin is used to select whether the most significant byte (MSB) or the least significant byte (LSB) of the conversion result is output first. When HBEN = 1, the MSB is output first, followed by the LSB. When HBEN = 0, the LSB is output first, followed by the MSB. In serial mode, this pin should be tied to GND. 33 DO/DI DB15/ DB15/ DB15/ Parallel Output Data Bit 15 (DB15)/Parallel Byte Mode Select (BYTE SEL). BYTE SEL BYTE SEL BYTE SEL When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB15 of the conversion result. When /SER/BYTE SEL = 1, the BYTE SEL pin is used to PAR select between serial interface mode and parallel byte interface mode (see Table 8). When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the AD7606 operates in serial interface mode. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606 operates in parallel byte interface mode. 34 DI REF SELECT REF SELECT REF SELECT Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. 36, 39 P REGCAP REGCAP REGCAP Decoupling Capacitor Pin for Voltage Output from Internal Regulator. These output pins should be decoupled separately to AGND using a 1 μF capacitor. The voltage on these pins is in the range of 2.5 V to 2.7 V. Rev. C | Page 15 of 36 AD7606/AD7606-6/AD7606-4 Data Sheet Mnemonic 1 Pin No. Type AD7606 AD7606-6 AD7606-4 Description 42 REF REFIN/ REFIN/ REFIN/ Reference Input (REFIN)/Reference Output (REFOUT). The on-chip reference REFOUT REFOUT REFOUT of 2.5 V is available on this pin for external use if the REF SELECT pin is set to logic high. Alternatively, the internal reference can be disabled by setting the REF SELECT pin to logic low, and an external reference of 2.5 V can be applied to this input (see the Internal/External Reference section). Decoupling is required on this pin for both the internal and external reference options. A 10 μF capacitor should be applied from this pin to ground close to the REFGND pins. 43, 46 REF REFGND REFGND REFGND Reference Ground Pins. These pins should be connected to AGND. 44, 45 REF REFCAPA, REFCAPA, REFCAPA, Reference Buffer Output Force/Sense Pins. These pins must be connected REFCAPB REFCAPB REFCAPB together and decoupled to AGND using a low ESR, 10 μF ceramic capacitor. The voltage on these pins is typically 4.5 V. 49 AI V1 V1 V1 Analog Input. This pin is a single-ended analog input. The analog input range of this channel is determined by the RANGE pin. 50, 52 AI GND V1GND, V1GND, V1GND, Analog Input Ground Pins. These pins correspond to Analog Input Pin V1 V2GND V2GND V2GND and Analog Input Pin V2. All analog input AGND pins should connect to the AGND plane of a system. 51 AI V2 V2 V2 Analog Input. This pin is a single-ended analog input. The analog input range of this channel is determined by the RANGE pin. 53 AI/GND V3 V3 AGND Analog Input 3. For the AD7606-4, this is an AGND pin. 54 AI GND/ V3GND V3GND AGND Analog Input Ground Pin. For the AD7606-4, this is an AGND pin. GND 55 AI/GND V4 AGND AGND Analog Input 4. For the AD7606-6 and the AD7606-4, this is an AGND pin. 56 AI GND/ V4GND AGND AGND Analog Input Ground Pin. For the AD7606-6 and AD7606-4, this is an GND AGND pin. 57 AI V5 V4 V3 Analog Inputs. These pins are single-ended analog inputs. The analog input range of these channels is determined by the RANGE pin. 58 AI GND V5GND V4GND V3GND Analog Input Ground Pins. All analog input AGND pins should connect to the AGND plane of a system. 59 AI V6 V5 V4 Analog Inputs. These pins are single-ended analog inputs. 60 AI GND V6GND V5GND V4GND Analog Input Ground Pins. All analog input AGND pins should connect to the AGND plane of a system. 61 AI/GND V7 V6 AGND Analog Input Pins. For the AD7606-4, this is an AGND pin. 62 AI GND/ V7GND V6GND AGND Analog Input Ground Pins. For the AD7606-4, this is an AGND pin. GND 63 AI/GND V8 AGND AGND Analog Input Pin. For the AD7606-4 and AD7606-6, this is an AGND pin. 64 AI GND/ V8GND AGND AGND Analog Input Ground Pin. For the AD7606-4 and AD7606-6, this is an GND AGND pin. 1 P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, GND is ground. Rev. C | Page 16 of 36 Data Sheet AD7606/AD7606-6/AD7606-4 TYPICAL PERFORMANCE CHARACTERISTICS 0 2.0 AV , V = 5V AV , V = 5V CC DRIVE CC DRIVE INTERNAL REFERENCE F = 200kSPS SAMPLE –20 1.5 ±10V RANGE T = 25°C A F = 200kSPS INTERNAL REFERENCE SAMPLE –40 F = 1kHz ±10V RANGE IN 1.0 16,384 POINT FFT SNR = 90.17dB –60 THD = –106.25dB 0.5 –80 0 –100 –0.5 –120 –1.0 –140 –1.5 –160 –180 –2.0 0 10k 20k 30k 40k 50k 60k 70k 80k 90k 100k 06 10k 20k 30k 40k 50k0k INPUT FREQUENCY (Hz) CODE Figure 11. AD7606 FFT, ±10 V Range Figure 14. AD7606 Typical INL, ±10 V Range 0 1.0 AV , V = 5V AV , V = 5V CC DRIVE CC DRIVE INTERNAL REFERENCE F = 200kSPS SAMPLE 0.8 –20 ±5V RANGE T = 25°C A F = 200kSPS INTERNAL REFERENCE SAMPLE 0.6 –40 F = 1kHz ±10V RANGE IN 16,384 POINT FFT 0.4 SNR = 89.48dB –60 THD = –108.65dB 0.2 –80 0 –100 –0.2 –120 –0.4 –140 –0.6 –160 –0.8 –180 –1.0 0 10k 20k 30k 40k 50k 60k 70k 80k 90k 100k 06 10k 20k 30k 40k 50k0k INPUT FREQUENCY (Hz) CODE Figure 12. AD7606 FFT Plot, ±5 V Range Figure 15. AD7606 Typical DNL, ±10 V Range 0 2.0 AV , V = 5V AV , V = 5V CC DRIVE CC DRIVE –10 INTERNAL REFERENCE INTERNAL REFERENCE –20 1.5 ±10V RANGE ±5V RANGE –30 F = 11.5kSPS F = 200kSPS SAMPLE SAMPLE –40 T = 25°C T = 25°C A A 1.0 –50 F = 133Hz IN 8192 POINT FFT –60 OS BY 16 0.5 –70 SNR = 96.01dB –80 THD = –108.05dB –90 0 –100 –110 –0.5 –120 –130 –1.0 –140 –150 –1.5 –160 –170 –180 –2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 FREQUENCY (kHz) CODE Figure 13. FFT Plot Oversampling By 16, ±10 V Range Figure 16. AD7606 Typical INL, ±5 V Range Rev. C | Page 17 of 36 AMPLITUDE (dB) AMPLITUDE (dB) AMPLITUDE (dB) 08479-031 08479-012 08479-011 INL (LSB) DNL (LSB) INL (LSB) 08479-013 08479-014 08479-015 AD7606/AD7606-6/AD7606-4 Data Sheet 1.00 10 AV , V = 5V CC DRIVE INTERNAL REFERENCE 8 0.75 ±5V RANGE PFS ERROR F = 200kSPS SAMPLE 6 T = 25°C A 0.50 4 NFS ERROR 0.25 2 0 0 –2 –0.25 –4 –0.50 –6 10V RANGE –0.75 –9 AV , V = 5V CC DRIVE EXTERNAL REFERENCE –1.00 –10 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 –40 –25 –10 5 20 35 50 65 80 CODE TEMPERATURE (°C) Figure 17. AD7606 Typical DNL, ±5 V Range Figure 20. NFS and PFS Error Matching 20 10 15 8 10 ±10V RANGE 6 5 ±5V RANGE 0 4 –5 2 AV , V = 5V CC DRIVE F = 200 kSPS SAMPLE –10 T = 25°C A EXTERNAL REFERENCE 0 –15 200kSPS SOURCE RESISTANCE IS MATCHED ON AV , V = 5V THE VxGND INPUT CC DRIVE EXTERNAL REFERENCE ±10V AND ±5V RANGE –20 –2 –40 –25 –10 5 20 35 50 65 80 0 20k 40k 60k 80k 100k 120k TEMPERATURE (°C) SOURCE RESISTANCE (Ω) Figure 18. NFS Error vs. Temperature Figure 21. PFS and NFS Error vs. Source Resistance 20 1.0 0.8 15 0.6 10 0.4 5 0.2 0 0 ±5V RANGE 5V RANGE –0.2 –5 ±10V RANGE –0.4 –10 10V RANGE –0.6 –15 200kSPS 200kSPS –0.8 AV , V = 5V AV , V = 5V CC DRIVE CC DRIVE EXTERNAL REFERENCE EXTERNAL REFERENCE –20 –1.0 –40 –25 –10 5 20 35 50 65 80 –40 –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 19. PFS Error vs. Temperature Figure 22. Bipolar Zero Code Error vs. Temperature Rev. C | Page 18 of 36 DNL (LSB) PFS ERROR (LSB) NFS ERROR (LSB) 08479-118 08479-017 08479-016 BIPOLAR ZERO CODE ERROR (LSB) PFS/NFS ERROR (%FS) NFS/PFS CHANNEL MATCHING (LSB) 08479-023 08479-019 08479-018 Data Sheet AD7606/AD7606-6/AD7606-4 4 98 96 3 5V RANGE 94 2 92 1 10V RANGE 90 0 88 –1 86 OS BY 64 –2 OS BY 32 AV , V = 5V 84 CC DRIVE OS BY 16 F CHANGES WITH OS RATE SAMPLE OS BY 8 200kSPS –3 T = 25°C OS BY 4 A 82 AV , V = 5V OS BY 2 INTERNAL REFERENCE CC DRIVE EXTERNAL REFERENCE NO OS ±5V RANGE –4 80 –40 –25 –10 5 20 35 50 65 80 10 100 1k 10k 100k TEMPERATURE (°C) INPUT FREQUENCY (Hz) Figure 23. Bipolar Zero Code Error Matching Between Channels Figure 26. SNR vs. Input Frequency for Different Oversampling Rates, ±5 V Range –40 100 ±10V RANGE AV , V = +5V CC DRIVE 98 –50 F = 200kSPS SAMPLE R MATCHED ON Vx AND VxGND INPUTS SOURCE 96 –60 94 –70 92 –80 90 105kΩ 88 –90 48.7kΩ 23.7kΩ 86 OS BY 64 10kΩ –100 OS BY 32 AV , V = 5V 5kΩ CC DRIVE OS BY 16 84 F CHANGES WITH OS RATE 1.2kΩ OS BY 8 SAMPLE T = 25°C –110 100Ω OS BY 4 A 82 51Ω OS BY 2 INTERNAL REFERENCE NO OS 0Ω ±10V RANGE –120 80 1k 10k 100k 10 100 1k 10k 100k INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) Figure 24. THD vs. Input Frequency for Various Source Impedances, Figure 27. SNR vs. Input Frequency for Different Oversampling Rates, ±10 V Range ±10 V Range –40 –50 ±5V RANGE AV , V = 5V CC DRIVE AV , V = +5V INTERNAL REFERENCE CC DRIVE –60 –50 F = 200kSPS AD7606 RECOMMENDED DECOUPLING USED SAMPLE R MATCHED ON Vx AND VxGND INPUTS F = 150kSPS SOURCE SAMPLE –70 T = 25°C A –60 INTERFERER ON ALL UNSELECTED CHANNELS –80 –70 –90 ±10V RANGE –80 –100 105kΩ ±5V RANGE –90 48.7kΩ –110 23.7kΩ 10kΩ –100 –120 5kΩ 1.2kΩ –110 100Ω –130 51Ω 0Ω –120 –140 1k 10k 100k 0 20 40 60 80 100 120 140 160 INPUT FREQUENCY (Hz) NOISE FREQUENCY (kHz) Figure 25. THD vs. Input Frequency for Various Source Impedances, Figure 28. Channel-to-Channel Isolation ±5 V Range Rev. C | Page 19 of 36 THD (dB) THD (dB) BIPOLAR ZERO CODE ERROR MATCHING (LSB) 08479-122 08479-021 08479-024 CHANNEL-TO-CHANNEL ISOLATION (dB) SNR (dB) SNR (dB) 08479-025 08479-121 08479-020 AD7606/AD7606-6/AD7606-4 Data Sheet 100 22 98 ±10V RANGE 20 96 18 94 ±5V RANGE 92 16 90 14 88 86 12 AV , V = 5V AV , V = 5V 84 CC DRIVE CC DRIVE T = 25°C T = 25°C A 10 A INTERNAL REFERENCE INTERNAL REFERENCE 82 F SCALES WITH OS RATIO F VARIES WITH OS RATE SAMPLE SAMPLE 80 8 OFF OS2 OS4 OS8 OS16 OS32 OS64 NO OS OS2 OS4 OS8 OS16 OS32 OS64 OVERSAMPLING RATIO OVERSAMPLING RATIO Figure 29. Dynamic Range vs. Oversampling Rate Figure 32. Supply Current vs. Oversampling Rate 2.5010 140 130 2.5005 AV = 5.25V CC AV = 5V CC 120 ±10V RANGE 2.5000 110 ±5V RANGE 2.4995 100 AV = 4.75V CC 90 2.4990 80 AV , V = 5V CC DRIVE INTERNAL REFERENCE 2.4985 AD7606 RECOMMENDED DECOUPLING USED 70 F = 200kSPS SAMPLE T = 25°C A 2.4980 60 –40 –25 –10 5 20 35 50 65 80 0 100 200 300 400 500 600 700 800 900 1000 1100 TEMPERATURE (°C) AV NOISE FREQUENCY (kHz) CC Figure 30. Reference Output Voltage vs. Temperature for Figure 33. PSRR Different Supply Voltages 8 AV , V = 5V CC DRIVE F = 200kSPS SAMPLE 6 4 2 0 –2 –4 –6 +85°C –8 +25°C –40°C –10 –10 –8 –6 –4 –2 0 2 4 6 8 10 INPUT VOLTAGE (V) Figure 31. Analog Input Current vs. Temperature for Various Supply Voltages Rev. C | Page 20 of 36 REFOUT VOLTAGE (V) INPUT CURRENT (µA) DYNAMIC RANGE (dB) 08479-028 08479-026 08479-029 POWER SUPPLY REJECTION RATIO (dB) AV SUPPLY CURRENT (mA) CC 08479-030 08479-027 Data Sheet AD7606/AD7606-6/AD7606-4 TERMINOLOGY Integral Nonlinearity Total Harmonic Distortion (THD) The maximum deviation from a straight line passing through The ratio of the rms sum of the harmonics to the fundamental. the endpoints of the ADC transfer function. The endpoints of For the AD7606/AD7606-6/AD7606-4, it is defined as the transfer function are zero scale, at ½ LSB below the first THD (dB) = code transition; and full scale, at ½ LSB above the last code 2 2 2 2 2 2 2 2 V  V  V  V  V  V  V  V 2 3 4 5 6 7 8 9 transition. 20log V 1 Differential Nonlinearity The difference between the measured and the ideal 1 LSB where: V1 is the rms amplitude of the fundamental. change between any two adjacent codes in the ADC. V to V are the rms amplitudes of the second through ninth 2 9 Bipolar Zero Code Error harmonics. The deviation of the midscale transition (all 1s to all 0s) from Peak Harmonic or Spurious Noise the ideal, which is 0 V − ½ LSB. The ratio of the rms value of the next largest component in the Bipolar Zero Code Error Match ADC output spectrum (up to fS/2, excluding dc) to the rms value The absolute difference in bipolar zero code error between any of the fundamental. Normally, the value of this specification is two input channels. determined by the largest harmonic in the spectrum, but for Positive Full-Scale Error ADCs where the harmonics are buried in the noise floor, it is The deviation of the actual last code transition from the ideal determined by a noise peak. last code transition (10 V − 1½ LSB (9.99954) and 5 V − 1½ LSB Intermodulation Distortion (4.99977)) after bipolar zero code error is adjusted out. The With inputs consisting of sine waves at two frequencies, fa and fb, positive full-scale error includes the contribution from the any active device with nonlinearities creates distortion products internal reference buffer. at sum and difference frequencies of mfa ± nfb, where m, n = 0, Positive Full-Scale Error Match 1, 2, 3. Intermodulation distortion terms are those for which The absolute difference in positive full-scale error between any neither m nor n is equal to 0. For example, the second-order two input channels. terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). Negative Full-Scale Error The deviation of the first code transition from the ideal first The calculation of the intermodulation distortion is per the code transition (−10 V + ½ LSB (−9.99984) and −5 V + ½ LSB THD specification, where it is the ratio of the rms sum of the (−4.99992)) after the bipolar zero code error is adjusted out. individual distortion products to the rms amplitude of the sum The negative full-scale error includes the contribution from the of the fundamentals expressed in decibels (dB). internal reference buffer. Power Supply Rejection Ratio (PSRR) Negative Full-Scale Error Match Variations in power supply affect the full-scale transition but not The absolute difference in negative full-scale error between any the converter’s linearity. PSR is the maximum change in full- two input channels. scale transition point due to a change in power supply voltage from the nominal value. The PSR ratio (PSRR) is defined as the Signal-to-(Noise + Distortion) Ratio ratio of the power in the ADC output at full-scale frequency, f, The measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the to the power of a 100 mV p-p sine wave applied to the ADC’s fundamental. Noise is the sum of all nonfundamental signals VDD and VSS supplies of Frequency fS. up to half the sampling frequency (f /2, excluding dc). S PSRR (dB) = 10 log (Pf/PfS) The ratio depends on the number of quantization levels in where: the digitization process: the more levels, the smaller the Pf is equal to the power at Frequency f in the ADC output. quantization noise. Pf is equal to the power at Frequency f coupled onto the AV S S CC supply. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Channel-to-Channel Isolation Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Channel-to-channel isolation is a measure of the level of crosstalk between all input channels. It is measured by applying a full-scale Thus, for a 16-bit converter, the signal-to-(noise + distortion) sine wave signal, up to 160 kHz, to all unselected input channels is 98 dB. and then determining the degree to which the signal attenuates in the selected channel with a 1 kHz sine wave signal applied (see Figure 28). Rev. C | Page 21 of 36 AD7606/AD7606-6/AD7606-4 Data Sheet THEORY OF OPERATION Analog Input Clamp Protection CONVERTER DETAILS Figure 34 shows the analog input structure of the AD7606/ The AD7606/AD7606-6/AD7606-4 are data acquisition systems AD7606-6/AD7606-4. Each analog input of the AD7606/ that employ a high speed, low power, charge redistribution, AD7606-6/AD7606-4 contains clamp protection circuitry. successive approximation analog-to-digital converter (ADC) Despite single 5 V supply operation, this analog input clamp and allow the simultaneous sampling of eight/six/four analog input protection allows for an input over voltage of up to ±16.5 V. channels. The analog inputs on the AD7606/AD7606-6/AD7606-4 R can accept true bipolar input signals. The RANGE pin is used to FB select either ±10 V or ±5 V as the input range. The AD7606/ 1MΩ Vx CLAMP AD7606-6/AD7606-4 operate from a single 5 V supply. 1MΩ VxGND CLAMP The AD7606/AD7606-6/AD7606-4 contain input clamp SECOND- ORDER protection, input signal scaling amplifiers, a second-order anti- R LPF FB aliasing filter, track-and-hold amplifiers, an on-chip reference, Figure 34. Analog Input Circuitry reference buffers, a high speed ADC, a digital filter, and high Figure 35 shows the voltage vs. current characteristic of the speed parallel and serial interfaces. Sampling on the AD7606/ clamp circuit. For input voltages of up to ±16.5 V, no current AD7606-6/AD7606-4 is controlled using the CONVST signals. flows in the clamp circuit. For input voltages that are above ±16.5 V, ANALOG INPUT the AD7606/AD7606-6/AD7606-4 clamp circuitry turns on. Analog Input Ranges AV , V = 5V CC DRIVE 30 T = 25°C A The AD7606/AD7606-6/AD7606-4 can handle true bipolar, 20 single-ended input voltages. The logic level on the RANGE pin determines the analog input range of all analog input channels. 10 If this pin is tied to a logic high, the analog input range is ±10 V 0 for all channels. If this pin is tied to a logic low, the analog input –10 range is ±5 V for all channels. A logic change on this pin has an immediate effect on the analog input range; however, there is –20 typically a settling time of approximately 80 µs, in addition to –30 the normal acquisition time requirement. The recommended practice is to hardwire the RANGE pin according to the desired –40 input range for the system signals. –50 –20 –15 –10 –5 0 5 10 15 20 During normal operation, the applied analog input voltage SOURCE VOLTAGE (V) should remain within the analog input range selected via the Figure 35. Input Protection Clamp Profile RANGE pin. A RESET pulse must be applied after power up to A series resistor should be placed on the analog input channels ensure the analog input channels are configured for the range to limit the current to ±10 mA for input voltages above ±16.5 V. selected. In an application where there is a series resistance on an analog When in a power-down mode, it is recommended to tie the input channel, Vx, a corresponding resistance is required on the analog inputs to GND. Per the Analog Input Clamp Protection analog input GND channel, VxGND (see Figure 36). If there is section, the overvoltage clamp protection is recommended for no corresponding resistor on the VxGND channel, an offset use in transient overvoltage conditions and should not remain error occurs on that channel. It is recommended that the input active for extended periods. Stressing the analog inputs outside overvoltage clamp protection circuitry be used to protect the of the conditions mentioned here may degrade the bipolar zero AD7606/AD7606-6/AD7606-4 against transient overvoltage code error and THD performance of the AD7606/AD7606-6/ events. It is not recommended to leave the AD7606/AD7606-6/ AD7606-4. AD7606-4 in a condition where the clamp protection circuitry Analog Input Impedance is active in normal or power-down conditions for extended periods because this may degrade the bipolar zero code error The analog input impedance of the AD7606/AD7606-6/ performance of the AD7606/AD7606-6/AD7606-4. AD7606-4 is 1 MΩ. This is a fixed input impedance that does not vary with the AD7606 sampling frequency. This high analog input impedance eliminates the need for a driver amplifier in front of the AD7606/AD7606-6/AD7606-4, allowing for direct connection to the source or sensor. With the need for a driver amplifier eliminated, bipolar supplies (which are often a source of noise in a system) can be removed from the signal chain. Rev. C | Page 22 of 36 INPUT CLAMP CURRENT (mA) 08479-032 08479-033 Data Sheet AD7606/AD7606-6/AD7606-4 R hold (that is, the delay time between the external CONVST x FB AD7606 signal and the track-and-hold actually going into hold) is well ANALOG R 1MΩ Vx INPUT CLAMP matched, by design, across all eight track-and-holds on one SIGNAL C R 1MΩ VxGND CLAMP device and from device to device. This matching allows more than one AD7606/AD7606-6/AD7606-4 device to be sampled R FB simultaneously in a system. Figure 36. Input Resistance Matching on the Analog Input of the The end of the conversion process across all eight channels is AD7606/AD7606-6/AD7606-4 indicated by the falling edge of BUSY; and it is at this point that the Analog Input Antialiasing Filter track-and-holds return to track mode, and the acquisition time An analog antialiasing filter (a second-order Butterworth) is also for the next set of conversions begins. provided on the AD7606/AD7606-6/AD7606-4. Figure 37 and The conversion clock for the part is internally generated, and Figure 38 show the frequency and phase response, respectively, the conversion time for all channels is 4 μs on the AD7606, of the analog antialiasing filter. In the ±5 V range, the −3 dB 3 μs on the AD7606-6, and 2 μs on the AD7606-4. On the AD7606, frequency is typically 15 kHz. In the ±10 V range, the −3 dB the BUSY signal returns low after all eight conversions to indicate frequency is typically 23 kHz. the end of the conversion process. On the falling edge of BUSY, 5 the track-and-hold amplifiers return to track mode. New data 0 can be read from the output register via the parallel, parallel ±10V RANGE AV , V = 5V byte, or serial interface after BUSY goes low; or, alternatively, CC DRIVE –5 F = 200kSPS SAMPLE ±5V RANGE data from the previous conversion can be read while BUSY is T = 25°C A –10 high. Reading data from the AD7606/AD7606-6/AD7606-4 –15 while a conversion is in progress has little effect on performance and allows a faster throughput to be achieved. In parallel mode –20 ±10V RANGE 0.1dB 3dB –40 10,303 24,365Hz at VDRIVE > 3.3 V, the SNR is reduced by ~1.5 dB when reading –25 +25 9619 23,389Hz during a conversion. +85 9326 22,607Hz –30 ±5V RANGE 0.1dB 3dB ADC TRANSFER FUNCTION –40 5225 16,162Hz –35 +25 5225 15,478Hz The output coding of the AD7606/AD7606-6/AD7606-4 is +85 4932 14,990Hz –40 twos complement. The designed code transitions occur midway 100 1k 10k 100k between successive integer LSB values, that is, 1/2 LSB and 3/2 LSB. INPUT FREQUENCY (Hz) The LSB size is FSR/65,536 for the AD7606. The ideal transfer Figure 37. Analog Antialiasing Filter Frequency Response characteristic for the AD7606/AD7606-6/AD7606-4 is shown in Figure 39. 18 VIN REF ±10V CODE = × 32,768 × 16 10V 2.5V ±5V RANGE 14 VIN REF ±5V CODE = × 32,768 × 5V 2.5V 12 011...111 011...110 ±10V RANGE 10 8 +FS – (–FS) 000...001 LSB = 16 6 2 000...000 111...111 4 2 100...010 0 100...001 100...000 –2 –FS + 1/2LSB 0V – 1/2LSB +FS – 3/2LSB –4 AV , V = 5V CC DRIVE ANALOG INPUT F = 200kSPS SAMPLE –6 T = 25°C A +FS MIDSCALE –FS LSB –8 ±10V RANGE +10V 0V –10V 305µV 10 1k 10k 100k ±5V RANGE +5V 0V –5V 152µV INPUT FREQUENCY (Hz) Figure 39. AD7606/AD7606-6/AD7606-4 Transfer Characteristics Figure 38. Analog Antialias Filter Phase Response The LSB size is dependent on the analog input range selected. Track-and-Hold Amplifiers The track-and-hold amplifiers on the AD7606/AD7606-6/ AD7606-4 allow the ADC to accurately acquire an input sine wave of full-scale amplitude to 16-bit resolution. The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVST x. The aperture time for the track-and- Rev. C | Page 23 of 36 ATTENUATION (dB) PHASE DELAY (µs) 08479-034 08479-036 08479-035 ADC CODE 08479-037 AD7606/AD7606-6/AD7606-4 Data Sheet Internal Reference Mode INTERNAL/EXTERNAL REFERENCE One AD7606/AD7606-6/AD7606-4 device, configured to operate The AD7606/AD7606-6/AD7606-4 contain an on-chip 2.5 V in the internal reference mode, can be used to drive the remaining band gap reference. The REFIN/REFOUT pin allows access to AD7606/AD7606-6/AD7606-4 devices, which are configured to the 2.5 V reference that generates the on-chip 4.5 V reference operate in external reference mode (see Figure 42). The REFIN/ internally, or it allows an external reference of 2.5 V to be applied REFOUT pin of the AD7606/AD7606-6/AD7606-4, configured to the AD7606/AD7606-6/AD7606-4. An externally applied in internal reference mode, should be decoupled using a 10 µF reference of 2.5 V is also gained up to 4.5 V, using the internal ceramic decoupling capacitor. The other AD7606/AD7606-6/ buffer. This 4.5 V buffered reference is the reference used by the AD7606-4 devices, configured in external reference mode, SAR ADC. should use at least a 100 nF decoupling capacitor on their The REF SELECT pin is a logic input pin that allows the user to REFIN/REFOUT pins. select between the internal reference and an external reference. REFIN/REFOUT If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference SAR REFCAPA is disabled and an external reference voltage must be applied BUF to the REFIN/REFOUT pin. The internal reference buffer is 10µF REFCAPB always enabled. After a reset, the AD7606/AD7606-6/AD7606-4 2.5V operate in the reference mode selected by the REF SELECT pin. REF Decoupling is required on the REFIN/REFOUT pin for both the internal and external reference options. A 10 µF ceramic Figure 40. Reference Circuitry capacitor is required on the REFIN/REFOUT pin. The AD7606/AD7606-6/AD7606-4 contain a reference buffer configured to gain the REF voltage up to ~4.5 V, as shown in AD7606 AD7606 AD7606 REF SELECT REF SELECT REF SELECT Figure 40. The REFCAPA and REFCAPB pins must be shorted REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT together externally, and a ceramic capacitor of 10 μF applied to REFGND, to ensure that the reference buffer is in closed-loop 100nF 100nF 100nF operation. The reference voltage available at the REFIN/REFOUT pin is 2.5 V. ADR421 0.1µF When the AD7606/AD7606-6/AD7606-4 are configured in external reference mode, the REFIN/REFOUT pin is a high Figure 41. Single External Reference Driving Multiple AD7606/AD7606-6/ AD7606-4 REFIN Pins input impedance pin. For applications using multiple AD7606 devices, the following configurations are recommended, depending on the application requirements. V DRIVE External Reference Mode AD7606 AD7606 AD7606 REF SELECT REF SELECT REF SELECT One ADR421 external reference can be used to drive the REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT pins of all AD7606 devices (see Figure 41). In this configuration, each REFIN/REFOUT pin of the + 10µF 100nF 100nF AD7606/AD7606-6/AD7606-4 should be decoupled with at least a 100 nF decoupling capacitor. Figure 42. Internal Reference Driving Multiple AD7606/AD7606-6/AD7606-4 REFIN Pins Rev. C | Page 24 of 36 08479-038 08479-039 08479-040 Data Sheet AD7606/AD7606-6/AD7606-4 The power-down mode is selected through the state of the TYPICAL CONNECTION DIAGRAM STBY RANGE pin when the pin is low. Table 7 shows the Figure 43 shows the typical connection diagram for the AD7606/ configurations required to choose the desired power-down mode. AD7606-6/AD7606-4. There are four AVCC supply pins on the When the AD7606/AD7606-6/AD7606-4 are placed in standby part, and each of the four pins should be decoupled using a 100 nF mode, the current consumption is 8 mA maximum and power- capacitor at each supply pin and a 10 µF capacitor at the supply up time is approximately 100 µs because the capacitor on the source. The AD7606/AD7606-6/AD7606-4 can operate with the REFCAPA and REFCAPB pins must charge up. In standby mode, internal reference or an externally applied reference. In this the on-chip reference and regulators remain powered up, and configuration, the AD7606 is configured to operate with the the amplifiers and ADC core are powered down. internal reference. When using a single AD7606/AD7606-6/ AD7606-4 device on the board, the REFIN/REFOUT pin When the AD7606/AD7606-6/AD7606-4 are placed in shutdown should be decoupled with a 10 µF capacitor. Refer to the mode, the current consumption is 6 µA maximum and power-up Internal/External Reference section when using an application time is approximately 13 ms (external reference mode). In shut- with multiple AD7606/AD7606-6/AD7606-4 devices. The down mode, all circuitry is powered down. When the AD7606/ REFCAPA and REFCAPB pins are shorted together and AD7606-6/AD7606-4 are powered up from shutdown mode, decoupled with a 10 µF ceramic capacitor. a RESET signal must be applied to the AD7606/AD7606-6/ AD7606-4 after the required power-up time has elapsed. The VDRIVE supply is connected to the same supply as the processor. The VDRIVE voltage controls the voltage value of the Table 7. Power-Down Mode Selection output logic signals. For layout, decoupling, and grounding STBY Power-Down Mode RANGE hints, see the Layout Guidelines section. Standby 0 1 After supplies are applied to the AD7606/AD7606-6/AD7606-4, Shutdown 0 0 a reset should be applied to the AD7606/AD7606-6/AD7606-4 to ensure that it is configured for the correct mode of operation. POWER-DOWN MODES Two power-down modes are available on the AD7606/AD7606-6/ STBY AD7606-4: standby mode and shutdown mode. The pin controls whether the AD7606/AD7606-6/AD7606-4 are in normal mode or in one of the two power-down modes. ANALOG SUPPLY DIGITAL SUPPLY 1 VOLTAGE 5V VOLTAGE +2.3V TO +5.25V + 1µF 10µF 100nF 100nF 2 AV V REFIN/REFOUT REGCAP CC DRIVE REFCAPA PARALLEL + DB0 TO DB15 INTERFACE 10µF REFCAPB REFGND CONVST A, CONVST B CS V1 RD V1GND BUSY V2 AD7606 V2GND RESET V3 OS 2 V3GND OS 1 OVERSAMPLING V4 EIGHT ANALOG OS 0 INPUTS V1 TO V8 V4GND V5 REF SELECT V DRIVE V5GND PAR/SER SEL V6 V6GND RANGE V7 V DRIVE V7GND STBY V8 AGND V8GND 1 DECOUPLING SHOWN ON THE AV PIN APPLIES TO EACH AV PIN (PIN 1, PIN 37, PIN 38, PIN 48). CC CC DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV PIN 37 AND PIN 38. CC 2 DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). Figure 43. AD7606 Typical Connection Diagram Rev. C | Page 25 of 36 MICROPROCESSOR/ MICROCONVERTER/ DSP 08479-041 AD7606/AD7606-6/AD7606-4 Data Sheet transformers. In a 50 Hz system, this allows for up to 9° of phase CONVERSION CONTROL compensation; and in a 60 Hz system, it allows for up to 10° of Simultaneous Sampling on All Analog Input Channels phase compensation. The AD7606/AD7606-6/AD7606-4 allow simultaneous sampling This is accomplished by pulsing the two CONVST pins of all analog input channels. All channels are sampled simul- independently and is possible only if oversampling is not in use. taneously when both CONVST pins (CONVST A, CONVST B) CONVST A is used to initiate simultaneous sampling of the are tied together. A single CONVST signal is used to control both first set of channels (V1 to V4 for the AD7606, V1 to V3 for the CONVST x inputs. The rising edge of this common CONVST AD7606-6, and V1 and V2 for the AD7606-4); and CONVST B signal initiates simultaneous sampling on all analog input channels is used to initiate simultaneous sampling on the second set of (V1 to V8 for the AD7606, V1 to V6 for the AD7606-6, and V1 analog input channels (V5 to V8 for the AD7606, V4 to V6 for to V4 for the AD7606-4). the AD7606-6, and V3 and V4 for the AD7606-4), as illustrated The AD7606 contains an on-chip oscillator that is used to in Figure 44. On the rising edge of CONVST A, the track-and- perform the conversions. The conversion time for all ADC hold amplifiers for the first set of channels are placed into hold channels is tCONV. The BUSY signal indicates to the user when mode. On the rising edge of CONVST B, the track-and-hold conversions are in progress, so when the rising edge of CONVST amplifiers for the second set of channels are placed into hold is applied, BUSY goes logic high and transitions low at the end mode. The conversion process begins once both rising edges of the entire conversion process. The falling edge of the BUSY of CONVST x have occurred; therefore BUSY goes high on the signal is used to place all eight track-and-hold amplifiers back rising edge of the later CONVST x signal. In Table 3, Time t 5 into track mode. The falling edge of BUSY also indicates that indicates the maximum allowable time between CONVST x the new data can now be read from the parallel bus (DB[15:0]), sampling points. the D A and D B serial data lines, or the parallel byte bus, OUT OUT There is no change to the data read process when using two DB[7:0]. separate CONVST x signals. Simultaneously Sampling Two Sets of Channels Connect all unused analog input channels to AGND. The results The AD7606/AD7606-6/AD7606-4 also allow the analog input for any unused channels are still included in the data read because channels to be sampled simultaneously in two sets. This can be all channels are always converted. used in power-line protection and measurement systems to compensate for phase differences introduced by PT and CT V1 TO V4 TRACK-AND-HOLD ENTER HOLD V5 TO V8 TRACK-AND-HOLD ENTER HOLD t CONVST A 5 CONVST B AD7606 CONVERTS ON ALL 8 CHANNELS BUSY t CONV CS/RD V1 V2 V3 V7 V8 DATA: DB[15:0] FRSTDATA Figure 44. AD7606 Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Mode Rev. C | Page 26 of 36 08479-042 Data Sheet AD7606/AD7606-6/AD7606-4 DIGITAL INTERFACE The AD7606/AD7606-6/AD7606-4 provide three interface When the RD signal is logic low, it enables the data conversion options: a parallel interface, a high speed serial interface, and result from each channel to be transferred to the digital host a parallel byte interface. The required interface mode is selected (DSP, FPGA). PAR via the /SER/BYTE SEL and DB15/BYTE SEL pins. When there is only one AD7606/AD7606-6/AD7606-4 in a system/board and it does not share the parallel bus, data can Table 8. Interface Mode Selection be read using just one control signal from the digital host. The PAR/SER/BYTE SEL DB15 Interface Mode CS RD and signals can be tied together, as shown in Figure 5. 0 0 Parallel interface mode In this case, the data bus comes out of three-state on the falling 1 0 Serial interface mode edge of CS/RD. The combined CS and RD signal allows the data 1 1 Parallel byte interface mode to be clocked out of the AD7606/AD7606-6/AD7606-4 and to Operation of the interface modes is discussed in the following be read by the digital host. In this case, CS is used to frame the sections. data transfer of each data channel. PARALLEL INTERFACE (PAR/SER/BYTE SEL = 0) PARALLEL BYTE (PAR/SER/BYTE SEL = 1, DB15 = 1) Data can be read from the AD7606/AD7606-6/AD7606-4 via Parallel byte interface mode operates much like the parallel the parallel data bus with standard CS and RD signals. To read the interface mode, except that each channel conversion result is read data over the parallel bus, the PAR/SER/BYTE SEL pin should RD out in two 8-bit transfers. Therefore, 16 pulses are required CS and RD input signals are internally gated to be tied low. The to read all eight conversion results from the AD7606. For the enable the conversion result onto the data bus. The data lines, RD AD7606-6, 12 pulses are required; and on the AD7606-4, CS DB15 to DB0, leave their high impedance state when both eight RD pulses are required to read all the channel results. RD and are logic low. To configure the AD7606/AD76706-6/AD7606-4 to operate in parallel byte mode, the PAR/SER/BYTE SEL and BYTE SEL/ AD7606 INTERRUPT BUSY 14 DB15 pins should be tied to logic high (see Table 8). In parallel 13 CS byte mode, DB[7:0] are used to transfer the data to the digital RD/SCLK 12 DIGITAL host. DB0 is the LSB of the data transfer, and DB7 is the MSB of HOST [33:24] DB[15:0] the data transfer. In parallel byte mode, DB14 acts as an HBEN [22:16] pin. When DB14/HBEN is tied to logic high, the most Figure 45. AD7606 Interface Diagram—One AD7606 Using the Parallel Bus, significant byte (MSB) of the conversion result is output first, CS RD with and Shorted Together followed by the LSB of the conversion result. When DB14 is tied CS The rising edge of the input signal three-states the bus, and to logic low, the LSB of the conversion result is output first, CS the falling edge of the input signal takes the bus out of the followed by the MSB of the conversion result. The FRSTDATA CS high impedance state. is the control signal that enables the pin remains high until the entire 16 bits of the conversion result data lines; it is the function that allows multiple AD7606/ from V1 are read from the AD7606/AD7606-6/AD7606-4. AD7606-6/ AD7606-4 devices to share the same parallel SERIAL INTERFACE (PAR/SER/BYTE SEL = 1) data bus. To read data back from the AD7606 over the serial interface, the The CS signal can be permanently tied low, and the RD signal PAR CS /SER/BYTE SEL pin must be tied high. The and SCLK can be used to access the conversion results as shown in Figure 4. signals are used to transfer data from the AD7606. The AD7606/ A read operation of new data can take place after the BUSY AD7606-6/AD7606-4 have two serial data output pins, D A OUT signal goes low (see Figure 2); or, alternatively, a read operation and D B. Data can be read back from the AD7606/AD76706- OUT of data from the previous conversion process can take place 6/AD7606-4 using one or both of these DOUT lines. For the while BUSY is high (see Figure 3). AD7606, conversion results from Channel V1 to Channel V4 The RD pin is used to read data from the output conversion first appear on DOUTA, and conversion results from Channel V5 results register. Applying a sequence of RD pulses to the RD pin to Channel V8 first appear on DOUTB. For the AD7606-6, of the AD7606/AD7606-6/AD7606-4 clocks the conversion conversion results from Channel V1 to Channel V3 first appear results out from each channel onto the Parallel Bus DB[15:0] in on D A, and conversion results from Channel V4 to Channel OUT RD V6 first appear on D B. For the AD7606-4, conversion results ascending order. The first falling edge after BUSY goes low OUT RD from Channel V1 and Channel V2 first appear on DOUTA, and clocks out the conversion result from Channel V1. The next conversion results from Channels V3 and Channel V4 first falling edge updates the bus with the V2 conversion result, and so appear on DOUTB. on. On the AD7606, the eighth falling edge of RD clocks out the conversion result for Channel V8. Rev. C | Page 27 of 36 08479-043 AD7606/AD7606-6/AD7606-4 Data Sheet CS CS The falling edge takes the data output lines, DOUTA and DOUTB, The falling edge of takes the bus out of three-state and clocks out of three-state and clocks out the MSB of the conversion out the MSB of the 16-bit conversion result. This MSB is valid result. The rising edge of SCLK clocks all subsequent data bits CS on the first falling edge of the SCLK after the falling edge. onto the serial data outputs, D A and D B. The CS input OUT OUT The subsequent 15 data bits are clocked out of the AD7606/ can be held low for the entire serial read operation, or it can be AD7606-6/AD7606-4 on the SCLK rising edge. Data is valid on pulsed to frame each channel read of 16 SCLK cycles. Figure 46 the SCLK falling edge. To access each conversion result, 16 clock shows a read of eight simultaneous conversion results using two cycles must be provided to the AD7606/AD7606-6/AD7606-4. D lines on the AD7606. In this case, a 64 SCLK transfer is used OUT The FRSTDATA output signal indicates when the first channel, CS to access data from the AD7606, and is held low to frame the CS V1, is being read back. When the input is high, the FRSTDATA entire 64 SCLK cycles. Data can also be clocked out using just output pin is in three-state. In serial mode, the falling edge of one D line, in which case it is recommended that D A be OUT OUT CS takes FRSTDATA out of three-state and sets the FRSTDATA used to access all conversion data because the channel data is pin high, indicating that the result from V1 is available on the output in ascending order. For the AD7606 to access all eight DOUTA output data line. The FRSTDATA output returns to conversion results on one DOUT line, a total of 128 SCLK cycles th a logic low following the 16 SCLK falling edge. If all channels is required. These 128 SCLK cycles can be framed by one CS are read on DOUTB, the FRSTDATA output does not go high when signal, or each group of 16 SCLK cycles can be individually V1 is being output on this serial data output pin. It goes high CS framed by the signal. The disadvantage of using just one only when V1 is available on D A (and this is when V5 is OUT D line is that the throughput rate is reduced if reading occurs OUT available on D B for the AD7606). OUT after conversion. The unused DOUT line should be left unconnected READING DURING CONVERSION in serial mode. For the AD7606, if DOUTB is to be used as a single Data can be read from the AD7606/AD7606-6/AD7606-4 while DOUT line, the channel results are output in the following order: BUSY is high and the conversions are in progress. This has little V5, V6, V7, V8, V1, V2, V3, and V4; however, the FRSTDATA effect on the performance of the converter, and it allows a faster indicator returns low after V5 is read on DOUTB. For the AD7606-6 and the AD7606-4, if D B is to be used as a single D line, throughput rate to be achieved. A parallel, parallel byte, or serial OUT OUT the channel results are output in the following order: V4, V5, V6, read can be performed during conversions and when oversampling V1, V2, and V3 for the AD7606-6; and V3, V4, V1, and V2 for may or may not be in use. Figure 3 shows the timing diagram for the AD7606-4. reading while BUSY is high in parallel or serial mode. Reading during conversions allows the full throughput rate to be achieved Figure 6 shows the timing diagram for reading one channel of when using the serial interface with V above 4.75 V. DRIVE data, framed by the CS signal, from the AD7606/AD7606-6/ Data can be read from the AD7606 at any time other than on AD7606-4 in serial mode. The SCLK input signal provides the the falling edge of BUSY because this is when the output data CS clock source for the serial read operation. The goes low to registers are updated with the new conversion data. Time t6, as access the data from the AD7606/AD7606-6/AD7606-4. outlined in Table 3, should be observed in this condition. CS 64 SCLK D A V1 V2 V3 V4 OUT D B OUT V5 V6 V7 V8 Figure 46. AD7606 Serial Interface with Two D Lines OUT Rev. C | Page 28 of 36 08479-044 Data Sheet AD7606/AD7606-6/AD7606-4 t CYCLE DIGITAL FILTER CONVST A The AD7606/AD7606-6/AD7606-4 contain an optional digital t CONV AND CONVST B first-order sinc filter that should be used in applications where 19µs slower throughput rates are used or where higher signal-to-noise 9µs ratio or dynamic range is desirable. The oversampling ratio of the 4µs digital filter is controlled using the oversampling pins, OS [2:0] (see OS = 0 OS = 2 OS = 4 BUSY Table 9). OS 2 is the MSB control bit, and OS 0 is the LSB control t 4 t 4 t bit. Table 9 provides the oversampling bit decoding to select the 4 different oversample rates. The OS pins are latched on the falling CS edge of BUSY. This sets the oversampling rate for the next conversion (see Figure 48). In addition to the oversampling RD function, the output result is decimated to 16-bit resolution. DATA: If the OS pins are set to select an OS ratio of eight, the next DB[15:0] CONVST x rising edge takes the first sample for each channel, Figure 47. AD7606—No Oversampling, Oversampling × 2, and and the remaining seven samples for all channels are taken with Oversampling × 4 While Using Read After Conversion an internally generated sampling signal. These samples are then Figure 47 shows that the conversion time extends as the over- averaged to yield an improvement in SNR performance. Table 9 sampling rate is increased, and the BUSY signal lengthens for the shows typical SNR performance for both the ±10 V and the ±5 V different oversampling rates. For example, a sampling frequency range. As Table 9 shows, there is an improvement in SNR as the of 10 kSPS yields a cycle time of 100 µs. Figure 47 shows OS × 2 OS ratio increases. As the OS ratio increases, the 3 dB frequency and OS × 4; for a 10 kSPS example, there is adequate cycle time to is reduced, and the allowed sampling frequency is also reduced. further increase the oversampling rate and yield greater improve- In an application where the required sampling frequency is ments in SNR performance. In an application where the initial 10 kSPS, an OS ratio of up to 16 can be used. In this case, the sampling or throughput rate is at 200 kSPS, for example, and application sees an improvement in SNR, but the input 3 dB oversampling is turned on, the throughput rate must be reduced bandwidth is limited to ~6 kHz. to accommodate the longer conversion time and to allow for the The CONVST A and CONVST B pins must be tied/driven read. To achieve the fastest throughput rate possible when over- together when oversampling is turned on. When the over- sampling is turned on, the read can be performed during the sampling function is turned on, the BUSY high time for the BUSY high time. The falling edge of BUSY is used to update the conversion process extends. The actual BUSY high time output data registers with the new conversion data; therefore, the depends on the oversampling rate that is selected: the higher the reading of conversion data should not occur on this edge. oversampling rate, the longer the BUSY high, or total conversion time (see Table 3). CONVST A AND CONVST B OVERSAMPLE RATE LATCHED FOR CONVERSION N + 1 CONVERSION N CONVERSION N + 1 BUSY t OS_HOLD t OS_SETUP OS x Figure 48. OS x Pin Timing Table 9. Oversample Bit Decoding Maximum Throughput OS SNR 5 V Range SNR 10 V Range 3 dB BW 5 V Range 3 dB BW 10 V Range OS[2:0] Ratio (dB) (dB) (kHz) (kHz) CONVST Frequency (kHz) 000 No OS 89 90 15 22 200 001 2 91.2 92 15 22 100 010 4 92.6 93.6 13.7 18.5 50 011 8 94.2 95 10.3 11.9 25 100 16 95.5 96 6 6 12.5 101 32 96.4 96.7 3 3 6.25 110 64 96.9 97 1.5 1.5 3.125 111 Invalid Rev. C | Page 29 of 36 08479-045 08479-046 AD7606/AD7606-6/AD7606-4 Data Sheet 1400 Figure 49 to Figure 55 illustrate the effect of oversampling on OVERSAMPLING BY 8 1263 F = 25kSPS SAMPLE the code spread in a dc histogram plot. As the oversample rate AV = 5V 1200 CC V = 2.5V DRIVE is increased, the spread of the codes is reduced. 1000 1000 NO OVERSAMPLING 928 887 783 F = 200kSPS SAMPLE 900 800 AV = 5V CC V = 2.5V DRIVE 800 600 700 600 400 500 200 400 0 0 0 0 2 0 300 –3 –2 –1 0 1 2 3 CODE (LSB) 200 131 97 100 Figure 52. Histogram of Codes—OS × 8 (Three Codes) 0 3 2 0 1400 OVERSAMPLING BY 16 –3 –2 –1 0 1 2 3 1453 F = 12.5kSPS SAMPLE CODE (LSB) AV = 5V 1200 CC V = 2.5V DRIVE Figure 49. Histogram of Codes—No OS (Six Codes) 1000 1400 OVERSAMPLING BY 2 800 F = 100kSPS SAMPLE AV = 5V 1200 CC 1148 V = 2.5V DRIVE 600 595 1000 400 804 800 200 600 0 0 0 0 0 0 –3 –2 –1 0 1 2 3 400 CODE (LSB) Figure 53. Histogram of Codes—OS × 16 (Two Codes) 200 80 1600 16 0 0 0 OVERSAMPLING BY 32 0 F = 6.125kSPS 1417 –3 –2 –1 0 1 2 3 SAMPLE 1400 AV = 5V CC CODE (LSB) V = 2.5V DRIVE 1200 Figure 50. Histogram of Codes—OS × 2 (Four Codes) 1000 1400 OVERSAMPLING BY 4 1262 F = 50kSPS 800 SAMPLE AV = 5V 1200 CC 631 V = 2.5V DRIVE 600 1000 400 764 800 200 0 0 0 0 0 600 0 –3 –2 –1 0 1 2 3 CODE (LSB) 400 Figure 54. Histogram of Codes—OS × 32 (Two Codes) 200 1600 OVERSAMPLING BY 64 19 1679 0 0 3 0 F = 3kSPS 0 SAMPLE 1400 AV = 5V –3 –2 –1 0 1 2 3 CC V = 2.5V DRIVE CODE (LSB) 1200 Figure 51. Histogram of Codes—OS × 4 (Four Codes) 1000 800 600 400 369 200 0 0 0 0 0 0 –3 –2 –1 0 1 2 3 CODE (LSB) Figure 55. Histogram of Codes—OS × 64 (Two Codes) Rev. C | Page 30 of 36 NUMBER OF OCCURENCES NUMBER OF OCCURENCES NUMBER OF OCCURENCES 08479-049 08479-048 08479-047 NUMBER OF OCCURENCES NUMBER OF OCCURENCES NUMBER OF OCCURENCES NUMBER OF OCCURENCES 08479-153 08479-152 08479-151 08479-050 Data Sheet AD7606/AD7606-6/AD7606-4 0 When the oversampling mode is selected for the AD7606/ AV = 5V CC V = 5V –10 DRIVE AD7606-6/AD7606-4, it has the effect of adding a digital filter T = 25°C A 10V RANGE function after the ADC. The different oversampling rates and –20 OS BY 16 the CONVST sampling frequency produce different digital filter –30 frequency profiles. –40 –50 Figure 56 to Figure 61 show the digital filter frequency profiles for the different oversampling rates. The combination of the analog –60 antialiasing filter and the oversampling digital filter can be used –70 to eliminate and reduce the complexity of the design of any filter –80 before the AD7606/AD7606-6/AD7606-4. The digital filtering –90 combines steep roll-off and linear phase response. –100 100 1k 10k 100k 1M 10M 0 AV = 5V CC FREQUENCY (Hz) V = 5V DRIVE –10 T = 25°C A Figure 59. Digital Filter Response for OS 16 10V RANGE –20 OS BY 2 0 AV = 5V CC –30 V = 5V –10 DRIVE T = 25°C A 10V RANGE –40 –20 OS BY 32 –30 –50 –40 –60 –50 –70 –60 –80 –70 –90 100 1k 10k 100k 1M 10M –80 FREQUENCY (Hz) –90 Figure 56. Digital Filter Response for OS 2 –100 100 1k 10k 100k 1M 10M 0 AV = 5V CC FREQUENCY (Hz) V = 5V –10 DRIVE T = 25°C A Figure 60. Digital Filter Response for OS 32 10V RANGE –20 OS BY 4 0 –30 AV = 5V CC V = 5V –10 DRIVE T = 25°C –40 A 10V RANGE –20 OS BY 64 –50 –30 –60 –40 –70 –50 –80 –60 –90 –70 –100 100 1k 10k 100k 1M 10M –80 FREQUENCY (Hz) –90 Figure 57. Digital Filter Response for OS 4 –100 100 1k 10k 100k 1M 10M 0 AV = 5V CC FREQUENCY (Hz) V = 5V –10 DRIVE T = 25°C A Figure 61. Digital Filter Response for OS 64 10V RANGE –20 OS BY 8 –30 –40 –50 –60 –70 –80 –90 –100 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 58. Digital Filter Response for OS 8 Rev. C | Page 31 of 36 ATTENUATION (dB) ATTENUATION (dB) ATTENUATION (dB) 08479-053 08479-052 08479-051 ATTENUATION (dB) ATTENUATION (dB) ATTENUATION (dB) 08479-156 08479-155 08479-154 AD7606/AD7606-6/AD7606-4 Data Sheet Figure 62 shows the recommended decoupling on the top layer LAYOUT GUIDELINES of the AD7606 board. Figure 63 shows bottom layer decoupling, The printed circuit board that houses the AD7606/AD7606-6/ which is used for the four AV pins and the V pin decoupling. CC DRIVE AD7606-4 should be designed so that the analog and digital Where the ceramic 100 nF caps for the AVCC pins are placed sections are separated and confined to different areas of the board. close to their respective device pins, a single 100 nF capacitor At least one ground plane should be used. It can be common or can be shared between Pin 37 and Pin 38. split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7606/AD7606-6/AD7606-4. If the AD7606/AD7606-6/AD7606-4 are in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point: a star ground point that should be established as close as possible to the AD7606/AD7606-6/AD7606-4. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Use individual vias or multiple vias to the ground plane for each ground pin. Avoid running digital lines under the devices because doing so couples noise onto the die. The analog ground plane should be allowed to run under the AD7606/AD7606-6/AD7606-4 to Figure 62. Top Layer Decoupling REFIN/REFOUT, avoid noise coupling. Fast switching signals like CONVST A, REFCAPA, REFCAPB, and REGCAP Pins CONVST B, or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Avoid crossover of digital and analog signals. Traces on layers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board. The power supply lines to the AV and V pins on the CC DRIVE AD7606/AD7606-6/AD7606-4 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes and make good connections between the AD7606 supply pins and the power tracks on the board. Use a single via or multiple vias for each supply pin. Good decoupling is also important to lower the supply impedance presented to the AD7606/AD7606-6/AD7606-4 and to reduce the magnitude of the supply spikes. The decoupling capacitors should be placed close to (ideally, right up against) these pins Figure 63. Bottom Layer Decoupling and their corresponding ground pins. Place the decoupling capacitors for the REFIN/REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7606/ AD7606-6/AD7606-4 pins; and, where possible, they should be placed on the same side of the board as the AD7606 device. Rev. C | Page 32 of 36 08479-055 08479-054 Data Sheet AD7606/AD7606-6/AD7606-4 To ensure good device-to-device performance matching in AV AVCC CC a system that contains multiple AD7606/AD7606-6/AD7606-4 devices, a symmetrical layout between the AD7606/AD7606-6/ AD7606-4 devices is important. Figure 64 shows a layout with two AD7606/AD7606-6/AD7606-4 U2 U2 devices. The AVCC supply plane runs to the right of both devices, and the VDRIVE supply track runs to the left of the two devices. The reference chip is positioned between the two devices, and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 of U2. A solid ground plane is used. These symmetrical layout principles can also be applied to a system that contains more than two AD7606/AD7606-6/AD7606-4 devices. The AD7606/AD7606-6/AD7606-4 devices can be placed in a north-south direction, with the reference voltage located midway between the devices and the reference track running in the north-south direction, similar to Figure 64. U1 U1 Figure 64. Layout for Multiple AD7606 Devices—Top Layer and Supply Plane Layer Rev. C | Page 33 of 36 08479-056 AD7606/AD7606-6/AD7606-4 Data Sheet OUTLINE DIMENSIONS 12.20 12.00 SQ 0.75 11.80 0.60 1.60 MAX 0.45 64 49 1 48 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 1.45 0.20 1.40 0.09 1.35 7° 3.5° 16 33 0.15 0° SEATING 17 32 0.05 0.08 PLANE COPLANARITY VIEW A 0.27 0.50 0.22 BSC LEAD PITCH VIEW A 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 65. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimetres ORDERING GUIDE 1, 2, 3 Model Temperature Range Package Description Package Option AD7606BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7606BSTZ-RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7606BSTZ-6 −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7606BSTZ-6RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7606BSTZ-4 −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7606BSTZ-4RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 EVAL-AD7606EDZ Evaluation Board for the AD7606 EVAL-AD7606-6EDZ Evaluation Board for the AD7606-6 EVAL-AD7606-4EDZ Evaluation Board for the AD7606-4 CED1Z Converter Evaluation Development 1 Z = RoHS Compliant Part. 2 The EVAL-AD7606EDZ, EVAL-AD7606-6EDZ, and EVAL-AD7606-4EDZ can be used as standalone evaluation boards or in conjunction with the CED1Z for evaluation/demonstration purposes. 3 The CED1Z allows the PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the EDZ designator. Rev. C | Page 34 of 36 051706-A Data Sheet AD7606/AD7606-6/AD7606-4 NOTES Rev. C | Page 35 of 36 AD7606/AD7606-6/AD7606-4 Data Sheet NOTES ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08479-0-1/12(C) Rev. C | Page 36 of 36