ANALOG DEVICES AD760

16/18-Bit Self-Calibrating a Serial/Byte DACPORT AD760 FUNCTIONAL BLOCK DIAGRAM FEATURES ±0.2 LSB (±0.00031%) Typ Peak DNL and INL MSB/ 18/16 ±0.5 LSB (±0.00076%) Typ Unipolar Offset, Bipolar Zero S LSB SERIAL IN OR OR OR 17-Bit Monotonicity Guaranteed CS DB0 DB1 DB2 DB7 18-Bit Resolution (in Serial Mode) 12 16 14 13 7 UNI/ Complete 16/18-Bit D/A Function BIP CLR AD760 17 16/18-BIT On-Chip Output Amplifier OR LBE 15 S OUT INPUT REGISTER 18 HBE On-Chip Buried Zener Voltage Reference 10k 19 SER SPAN/ 24 Microprocessor Compatible 16/18-BIT DAC LATCH BIP 20 CLR OFF Serial or Byte Input 10k 21 LDAC Double Buffered Latches 25 REF IN MAIN DAC Asynchronous Clear Function 23 V 9.95k OUT Serial Output Pin Facilitates Daisy Chaining 27 MUX OUT RAM Pin Strappable Unipolar or Bipolar Output 28 MUX IN Low THD+N: 0.005% +10V 26 REF OUT CALIBRATION DAC REF 22 MUX Output Control on Power-Up and Supply Glitches AGND CALIBRATION SEQUENCER PRODUCT DESCRIPTION The AD760 is a complete 16/18-bit self-calibrating monolithic 1 2 3 4 5 6 DAC (DACPORT®) with onboard voltage reference, double CALOK CAL –V +V +V DGND EE CC LL buffered latches and output amplifier. It is manufactured on Analog Devices’ BiMOS II process. This process allows the fab- rication of low power CMOS logic functions on the same chip MUX output in a predetermined state by means of a digital and as high precision bipolar linear circuitry. analog power supply detection circuit. This is particularly use- Self-calibration is initiated by simply pulsing the CAL pin low. ful for robotic and industrial control applications. The CALOK pin indicates when calibration has been success- The AD760 is available in a 28-pin, 600 mil cerdip package. fully completed. The output multiplexer (MUX ) can be used OUT The AQ version is specified from –40°C to +85°C. to send the output to the bottom of the output range during calibration. Data can be loaded into the AD760 as straight binary, serial data or as two 8-bit bytes. In serial mode, 16-bit or 18-bit data V = –10V TO +10V OUT 0.75 can be used and the serial mode input format is pin selectable, R = 2kΩ L C = 1000pF L to be MSB or LSB first. This is made possible by three digital input pins which have dual functions (Pins 12, 13, and 14). In 0.25 byte mode the user can similarly define whether the high byte or 0 low byte is loaded first. The serial output (S ) pin allows the OUT –0.25 user to daisy chain several AD760s by shifting the data through the input latch into the next DAC thus minimizing the number of control lines required in a multiple DAC application. The –0.75 double buffered latch structure eliminates data skew errors and provides for simultaneous updating of DACs in a multi-DAC 0 16384 32768 49152 65535 system. INPUT CODE – Decimal The asynchronous CLR function can be configured to clear the output to minus full-scale or midscale depending on the state of Typical Integral Nonlinearity Pin 17 when CLR is strobed. The AD760 also powers up with the REV. A DACPORT is a registered trademark of Analog Devices, Inc. Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1995 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 RELATIVE ACCURACY – LSB CONTROL LOGIC (@ T = +25°C, V = +15 V, V = –15 V, V = + 5 V, unless otherwise noted) AD760–SPECIFICATIONS A CC EE LL AD760AQ Model Min Typ Max Units 1 RESOLUTION 16/18 Bits 2 TRANSFER FUNCTION CHARACTERISTICS 3 With Calibration @ T ; –40°C T +85°C CAL CAL Integral Nonlinearity ±0.2 ±0.75 16-Bit LSB Differential Nonlinearity ±0.2 ±0.5 16-Bit LSB Monotonicity 17 18 Bits Unipolar Offset ±0.5 ±1 16-Bit LSB Bipolar Zero Error ±0.5 ±1 16-Bit LSB Without Calibration Integral Nonlinearity ±2 16-Bit LSB T to T ±4 16-Bit LSB MIN MAX Integral Nonlinearity Drift 0.015 16-Bit LSB/°C Differential Nonlinearity ±2 16-Bit LSB T to T ±4 16-Bit LSB MIN MAX Differential Nonlinearity Drift 0.015 16-Bit LSB/°C Monotonicity Over Temperature 14 Bits Unipolar Offset ±2.5 mV Unipolar Offset Drift (T to T ) 3 ppm/°C MIN MAX Bipolar Zero Error ±10 mV Bipolar Zero Error Drift (T to T ) 5 ppm/°C MIN MAX 4, 5 Gain Error ±0.10 % of FSR 5 Gain Drift (T to T ) 25 ppm/°C MIN MAX 6 DAC Gain Error ±0.05 % of FSR 6 DAC Gain Drift (T to T ) 10 ppm/°C MIN MAX INPUT RESISTANCE REFIN 7 10 13 k SPAN/BIP OFF 7 10 13 k REFERENCE OUTPUT Voltage 9.99 10.00 10.01 V Drift 25 ppm/°C 7 External Current 24 mA Capacitive Load 1000 pF Short Circuit Current 25 mA Long-Term Stability 50 ppm/1000 Hrs 2 OUTPUT CHARACTERISTICS Output Voltage Range Unipolar Configuration 0 +10 V Bipolar Configuration –10 +10 V Output Current 5 mA Capacitive Load 1000 pF Short Circuit Current 25 mA MUX Resistance 0.9 7 k OUT DIGITAL INPUTS (T to T ) MIN MAX V (Logic “1”) 2.0 V V IH LL V (Logic “0”) 0 0.8 V IL I (V = V ) ±10 μA IH IH LL I (V = 0 V) ±10 μA IL IL DIGITAL OUTPUT (T to T ) MIN MAX V (I = –0.6 mA) 2.4 V OH OH V (I = 1.6 mA) 0.4 V OL OL POWER SUPPLIES Voltage 8 V +14.25 +15.75 V CC 8 V –15.75 –14.25 V EE V +4.75 +5.25 V LL Current (No Load) I +18 +21 mA CC I –21 –18 mA EE I LL @ V , V = 5.0 V, 0 V 2 3 mA IH IL @ V , V = 2.4 V, 0.4 V 3 7.5 mA IH IL Power Supply Sensitivity with V = 10 V 1 ppm/% OUT Power Dissipation (Static, No Load) 600 725 mW TEMPERATURE RANGE Specified Performance (A) –40 +85 °C –2– REV. A AD760 NOTES 1 For 18-bit resolution, 1 LSB = 0.00038% of FSR. For 16-bit resolution, 1 LSB = 0.0015% of FSR. For 14-bit resolution, 1 LSB = 0.006% of FSR. FSR stands for full-scale range and is 10 V in unipolar mode and 20 V in bipolar mode. 2 Characteristics are guaranteed at V Pin (23). OUT 3 T is the calibration temperature. CAL 4 Gain Error is measured with a fixed 50 resistor as shown in Figure 5a and Figure 6a. 5 Gain Error and gain drift are measured with the internal reference. The internal reference is the main contributor to the gain drift. If lower drift is required, the AD760 can be used with a precision external reference such as the AD587, AD586 or AD688. 6 DAC Gain Error is measured without the on-chip voltage reference. It represents the performance that can be obtained with an external precision reference. 7 External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD760. 8 Operation on ±12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference section. Specifications subject to change without notice. AC PERFORMANCE CHARACTERISTICS With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested. (T < T MIN A < T , V = +15 V, V = –15 V, V = +5 V, tested at V except where noted.) MAX CC EE LL OUT Parameter Limit Units Test Conditions/Comments Output Settling Time 13 μs max 20 V Step, T = +25°C A (Time to +0.0008% FS, with 8 μs typ 20 V Step, T = +25°C A 2 k , 1000 pF Load) 10 μs typ 20 V Step 6 μs typ 10 V Step, T = +25°C A 8 μs typ 10 V Step 2.5 μs typ 1 LSB Step MUX Recovery Time Recovery time is referenced to the rising edge of CALOK, OUT (Time to +0.0008% FS, with when MUX switches from MUX to V . OUT IN OUT 100 pF Load) MUX = V prior to calibration. IN OUT 2 μs typ MUX , V = –10 V to +10 V IN OUT Total Harmonic Distortion + Noise A, S Grade 0.005 % max 0 dB, 1001 Hz. Sample Rate = 100 kHz. T = +25°C A A, S Grade 0.03 % max –20 dB, 1001 Hz. Sample Rate = 100 kHz. T = +25°C A A, S Grade 3.0 % max –60 dB, 1001 Hz. Sample Rate = 100 kHz. T = +25°C A Signal-to-Noise Ratio 94 dB min T = +25°C, byte load A Digital-to-Analog Glitch Impulse 15 nV-s typ DAC alternately loaded with 8000 and 7FFF H H MUX Glitch Impulse 30 nV-s typ 100 pF Load. MUX = V = negative full scale OUT IN OUT Digital Feedthrough 2 nV-s typ DAC alternately loaded with 0000 and FFFF . CS high H H Output Noise Voltage Density (1 kHz–1 MHz) 120 nV/ Hz typ Measured at V , 20 V span, excludes internal reference OUT Reference Noise (1 kHz–1 MHz) 125 nV/ Hz typ Measured at REF OUT Specifications are subject to change without notice. REV. A –3– AD760 (V = +15 V, V = –15 V, V = +5 V, V = 2.4 V, V = 0.4 V) TIMING CHARACTERISTICS CC EE LL IH IL Limit Limit Parameter +25°C T to T Units Parameter +25°C T to T Units MIN MAX MIN MAX (Figure 1a) (Figure 1c) t 50 60 ns min t 100 120 ns min CLR CS t 50 60 ns min t 100 120 ns min DS SET t 0 10 ns min t 0 0 ns min DH HOLD t 50 60 ns min BES (Figure 1d) t 0 10 ns min BEH t 50 50 ns min CAL t 200 350 ns min LH t 200 200 ms max BUSY t 50 50 ns min LW t 170 220 ns max CD (Figure 1b) t 150 190 ns max CS t 80 100 ns min t 150 190 ns max CLK CV t 40 50 ns min LO Specifications subject to change without notice. t 40 50 ns min HI t 50 60 ns min DS t 0 10 ns min DH t 200 350 ns min LH t 50 50 ns min LW t 70 100 ns max PROP DB0–7 t t DS DH HBE OR LBE t t BES BEH t CS CS t t LW LH LDAC Figure 1a. AD760 Byte Load Timing SIN VALID 1 VALID 16/18 t t DS DH t t HI LO CS t t t LW CLK LH LDAC t PROP S VALID 1 OUT Figure 1b. AD760 Serial Load Timing REV. A –4– AD760 t CLR CLR t t HOLD SET UNI/BIP "1"= BIP, "0"= UNI CLR Figure 1c. Asynchronous Clear to Bipolar or Unipolar Zero t CAL CAL t BUSY CALOK t CD t t CS CV HBE Figure 1d. Calibration Timing ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION V to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17.0 V CC DIP V to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17.0 V EE V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V LL AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V CALOK 1 28 MUX IN Digital Inputs (Pins 2, 7–14, and 16–21) CAL 2 27 MUX OUT to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V 3 –V 26 REF OUT EE REF IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10.5 V +V 4 25 REF IN CC Span/Bipolar Offset to AGND . . . . . . . . . . . . . . . . . . . ±10.5 V +V 5 24 SPAN/BIP OFF REF OUT, V , MUX , MUX . . . . . Indefinite Short to LL OUT OUT IN DGND 6 23 V AGND, DGND, V , V , and V AD760 CC EE LL OUT DB7, 15 22 AGND θ , Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 50°C/W 7 JA TOP VIEW Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C DB6, 14 8 21 LDAC (Not to Scale) Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C DB5, 13 9 20 CLR Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C DB4, 12 10 19 SER * Stresses above those listed under “Absolute Maximum Ratings” may cause 11 11 DB3, 11 18 HBE permanent damage to the device. This is a stress rating only and functional DB2, 10, 18/16 SERIAL 12 17 LBE, UNI/BIP CLR operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute DB1, 9, MSB/LSB 13 16 CS maximum rating conditions for extended periods may affect device reliability. DB0, 8, S 14 S 15 IN OUT ORDERING GUIDE Temperature Package Package Model Range Description Option AD760AQ –40°C to +85°C Cerdip Q-28 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD760 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. A –5– AD760 DEFINITIONS OF SPECIFICATIONS THEORY OF OPERATION INTEGRAL NONLINEARITY: Analog Devices defines inte- The AD760 uses autocalibration circuitry to produce a true gral nonlinearity as the maximum deviation of the actual, ad- 16-bit DAC with typically 0.2 LSB Integral and Differential justed DAC output from the ideal analog output (a straight line Linearity Error and 0.5 LSB Offset Error. The block diagram drawn from 0 to FS – 1 LSB) for any bit combination. This is in Figure 2 shows the circuit components needed for calibration. also referred to as relative accuracy. The MAIN DAC uses an array of bipolar current sources with DIFFERENTIAL NONLINEARITY: Differential nonlinearity MOS current steering switches to develop a current propor- is the measure of the change in the analog output, normalized to tional to the applied digital word, ranging from 0 mA to 2 mA. full scale, associated with a 1 LSB change in the digital input A segmented architecture is used, where the most significant code. Monotonic behavior requires that the differential linearity four data bits are thermometer decoded to drive 15 equal cur- error be greater than or equal to –1 LSB over the temperature rent sources. The lesser bits are scaled using an R-2R ladder, range of interest. then applied together with the segmented sources to the sum- ming node of the output amplifier. An extra LSB is included in MONOTONICITY: A DAC is monotonic if the output either the MAIN DAC, for use during calibration. increases or remains constant for increasing digital inputs with the result that the output will always be a single-valued function The self-calibration architecture of the AD760 attempts to of the input. reduce the linearity errors of its transfer function. The algorithm first checks for bipolar or unipolar operation, calibrates either GAIN ERROR: Gain error is a measure of the output error be- bipolar zero or unipolar offset, and then removes the carry er- tween an ideal DAC and the actual device output with all 1s rors (DNL errors) associated with the upper 6 bits (64 codes). loaded after offset error has been adjusted out. Once calibrated, the top six bits of a code entering the MAIN OFFSET ERROR: Offset error is a combination of the offset DAC simultaneously address the RAM, calling up a correction errors of the voltage-mode DAC and the output amplifier and is code that is then applied to the CALDAC. The output cur- measured with all 0s loaded in the DAC. rents of both the MAIN DAC and CALDAC are combined in BIPOLAR ZERO ERROR: When the AD760 is connected for the summing amplifier to produce the corrected output voltage. bipolar output and 10 . . . 000 is loaded in the DAC, the devia- tion of the analog output from the ideal midscale value of 0 V is MSB/ 18/16 S LSB SERIAL called the bipolar zero error. IN OR OR OR CS DB0 DB1 DB2 DB7 DRIFT: Drift is the change in a parameter (such as gain, offset 12 16 14 13 7 UNI/ and bipolar zero) over a specified temperature range. The drift BIP CLR AD760 17 temperature coefficient, specified in ppm/°C, is calculated by 16/18-BIT OR LBE 15 S OUT INPUT REGISTER 18 HBE measuring the parameter at T , 25°C and T and dividing MIN MAX 10k 19 SER the change in the parameter by the corresponding temperature SPAN/ 24 16/18-BIT DAC LATCH BIP 20 CLR change. OFF 10k 21 LDAC TOTAL HARMONIC DISTORTION + NOISE: Total har- 25 REF IN MAIN DAC 23 V monic distortion + noise (THD+N) is defined as the ratio of the 9.95k OUT square root of the sum of the squares of the values of the har- 27 MUX OUT RAM monics and noise to the value of the fundamental input fre- 28 MUX IN quency. It is usually expressed in percent (%). THD+N is a +10V REF OUT 26 CALIBRATION DAC REF 22 AGND measure of the magnitude and distribution of linearity error, dif- ferential linearity error, quantization error and noise. The distri- bution of these errors may be different, depending upon the TRANSFER STD DAC amplitude of the output signal. Therefore, to be the most useful, CALIBRATION SEQUENCER THD+N should be specified for both large and small signal am- plitudes. 2 3 4 5 6 1 SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is CALOK CAL –V +V +V DGND EE CC LL defined as the ratio of the amplitude of the output when a full- scale signal is present to the output with no signal present. This Figure 2. Functional Block Diagram is measured in dB. In the first step of DNL calibration the output of the MAIN DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the DAC is set to the code just below the code to be calibrated. amount of charge injected from the digital inputs to the analog The extra LSB in the MAIN DAC is turned on to find the ex- output when the inputs change state. This is measured at half trapolated value for the next code. The comparator is then scale when the DAC switches around the MSB and as many as nulled using TRANSFER STD DAC. The voltage at V OUT possible switches change state, i.e., from 011 . . . 111 to has in effect been sampled at the code to be calibrated. 100 . . . 000. Next, the extra LSB is turned off and the MAIN DAC code is DIGITAL FEEDTHROUGH: When the DAC is not selected incremented by one LSB. The comparator is once again (i.e., CS is held high), high frequency logic activity on the digi- nulled, this time with the CALDAC, until the V is adjusted OUT tal inputs is capacitively coupled through the device to show up to equal the previously sampled output. The CALDAC code is as noise on the V pin. This noise is digital feedthrough. OUT stored in RAM and the process is repeated for the next code. REV. A –6– CONTROL LOGIC AD760 CALIBRATED LINEARITY PERFORMANCE UNIPOLAR CONFIGURATION The cumulative probability plots for the AD760 INL and DNL The configuration shown in Figure 5a will provide a unipolar shown in Figures 3 and 4 represent the maximum absolute- 0 V to +10 V output range. In this mode a 50 resistor is tied value (peak) linearity error for each part. Roughly 100 parts between REF OUT (Pin 26) and REF IN (Pin 25). It is pos- from each of 3 wafer lots were used. sible to use the AD760 without any external components by tying Pin 26 directly to Pin 25. Eliminating this resistor will The calibrated DNL and INL performance for the sample increase the gain error by 0.50% of FSR. populations shown also represent the expected performance for a single part calibrated often. There is essentially no difference AD760 between the expected performance of many parts calibrated REFIN 25 once and one part calibrated often. The AD760 calibrated per- formance is guaranteed at any temperature within the operating 50Ω temperature range. The peak nonlinearity for the sample popu- REFOUT +10V REF 26 lations shown are also representative of the expected maximum 9.95kΩ linearity errors of a single part recalibrated at temperature. 10kΩ SPAN/BIP OFF 24 100 10kΩ 40 MAIN DAC V OUT 23 80 30 60 Figure 5a. 0 V to +10 V Unipolar Voltage Output 20 If it is desired to adjust the gain error to zero, this can be ac- 40 complished using the circuit shown in Figure 5b. The adjust- ment procedure is as follows: 10 20 STEP 1 . . . OFFSET ADJUST Initiate calibration sequence. CALOK (Pin 1) must remain high 0 0 throughout Gain Adjust. 0 0.125 0.25 0.375 0.5 0.625 0.75 16-BIT LSB STEP 2 . . . GAIN ADJUST Turn all bits ON and adjust gain trimmer, R1, until the output Figure 3. AD760 Peak INL is 9.999847 volts. (Full scale is adjusted to 1 LSB less than the nominal full scale of 10.000000 volts.) 100 50 AD760 REFIN 25 40 80 R1 100Ω 30 60 REFOUT +10V REF 26 9.95kΩ 10kΩ SPAN/BIP OFF 20 40 24 10kΩ 20 10 MAIN DAC V OUT 23 0 0 0 0.125 0.25 0.375 0.5 16-BIT LSB Figure 5b. 0 V to +10 V Unipolar Voltage Output with Gain Adjust Figure 4. AD760 Peak DNL BIPOLAR CONFIGURATION ANALOG CIRCUIT CONNECTIONS The circuit shown in Figure 6a will provide a bipolar output Internal scaling resistors provided in the AD760 may be con- voltage from –10.000000 V to +9.999694 V with positive full nected to produce a unipolar output range of 0 V to +10 V or a scale occurring with all bits ON. As in the unipolar mode, resis- bipolar output range of –10 V to +10 V. Gain and offset drift tor R1 may be eliminated altogether to provide AD760 bipolar are minimized in the AD760 because of the thermal tracking of operation without any external components. Eliminating this the scaling resistors with other device components. resistor will increase the gain error by 0.50% of FSR in the bipolar mode. REV. A –7– COUNT COUNT CUMULATIVE PROBABILITY – % CUMULATIVE PROBABILITY – % AD760 INTERNAL/EXTERNAL REFERENCE USE AD760 REFIN 25 The AD760 has an internal low noise buried Zener diode refer- R1 ence that is trimmed for absolute accuracy and temperature co- 50Ω efficient. This reference is buffered and optimized for use in a REFOUT high speed DAC and will give long-term stability equal or supe- +10V REF 26 rior to the best discrete Zener diode references. The perfor- 9.95kΩ 10kΩ mance of the AD760 is specified with the internal reference 24 SPAN/ driving the DAC and with the DAC alone (for use with a preci- 10kΩ BIP OFF sion external reference). MAIN DAC The internal reference has sufficient buffering to drive external 23 V OUT circuitry in addition to the reference currents required for the DAC (typically 1 mA to REF IN and 1 mA to BIPOLAR OFF- SET). A minimum of 2 mA is available for driving external Figure 6a. 0 V to ±10 V Bipolar Voltage Output loads. The AD760 reference output should be buffered with an external op amp if it is required to supply more than 4 mA total Gain Error can be adjusted to zero using the circuit shown in current. The reference is tested and guaranteed to ±0.1% max Figure 6b. Note that gain adjustment changes the Bipolar Zero error. by one half of the variation made to the full-scale output value. Therefore, to eliminate iterating between Zero (calibration) and It is also possible to use external references other than 10 volts Gain adjustment the following procedure is recommended. with slightly degraded linearity specifications. The recom- mended range of reference voltages is +5 V to +10.24 V. For STEP 1 . . . ZERO ADJUST example, by using the AD586 5 V reference, outputs of 0 V to Initiate Calibration Sequence. +5 V or ±5 V can be realized. Using the AD586 voltage refer- STEP 2 . . . GAIN ADJUST ence makes it possible to operate the AD760 with ±12 V sup- Insure the CALOK pin remains high throughout the gain ad- plies with 10% tolerances. justment process. Turn all bits on and measure the output error Figure 7 shows the AD760 using the AD586 precision 5 V refer- relative to the full-scale output of 9.99695 V. Adjust R1 until ence in the bipolar configuration. The highest grade AD586MN the output is minus two times the full-scale output error. For is specified with a drift of 2 ppm/°C. This circuit includes an example, if the output error is –1 mV, adjust the output 2 mV optional potentiometer that can be used to adjust the gain error higher than the previous full-scale error. in a manner similar to that described in the Bipolar Configura- STEP 3 . . . ZERO ADJUST tion section. Use +4.999847 V as the full-scale output value. Initiate Calibration Sequence. The AD760 will calibrate Bipolar The AD760 can also be used with the AD587, 10 V reference, Zero and the resulting Gain Error will be very small. Reload the using the same configuration shown in Figure 7 to produce a DAC with all ones to check the full-scale output error. ±10 V output. The highest grade AD587L is specified at 5 ppm/°C. AD760 REFIN 25 R1 AD760 REFIN 100Ω 25 +V CC 100Ω REFOUT 2 +10V REF 26 9.95kΩ AD586 10kΩ +10V REF 26 24 REFOUT 6 SPAN/ 9.95kΩ V OUT 10kΩ BIP OFF 10kΩ 24 SPAN/BIP OFF 4 MAIN DAC 10kΩ 23 V OUT MAIN DAC 23 V OUT Figure 6b. 0 V to ±10 V Bipolar Voltage Output Gain Adjustment Figure 7. Using the AD760 with the AD586 5 V Reference It should be noted that using external resistors will introduce a small temperature drift component beyond that inherent in the OUTPUT SETTLING AND GLITCH AD760. The internal resistors are trimmed to ratio-match and The AD760’s output buffer amplifier typically settles to within temperature-track other resistors on chip, even though their 0.0008% FS (1/2 LSB) of its final value in 8 μs for a full-scale absolute tolerances are ±20% and absolute temperature coeffi- step. Figures 8a and 8b show settling for a full scale and an cients are approximately –50 ppm/°C. In the case that external LSB step, respectively, with a 2 k , 1000 pF load applied. The resistors are used, the temperature coefficient mismatch be- guaranteed maximum settling time at +25°C for a full-scale step tween internal and external resistors, multiplied by the sensitiv- is 13 μs with this load. The typical settling time for a 1 LSB step ity of the circuit to variations in the external resistor value, will is 2.5 μs. be the resultant additional temperature drift. REV. A –8– AD760 The digital-to-analog glitch impulse is specified as 15 nV-s typi- A Power-On-Reset feature senses whenever any power supply cal. Figure 8c shows the typical glitch impulse characteristic at is low enough to jeopardize the integrity of the calibration data the code 011 . . . 111 to 100 . . . 000 transition when loading in the RAM. At power-up or in the event of a power supply the second rank register from the first rank register. transient, CALOK (Pin 1) is low and the MUX pin is OUT switched to MUX . IN Self-Calibration is initiated by strobing the CAL pin low (refer 600 to Figure 1d). The CALOK pin will go low and the MUX OUT +10 400 pin is connected to MUX . During calibration, the second-rank IN latch is transparent to allow the CALIBRATION SEQUENCER 200 to control the MAIN DAC. After successful completion of cali- 0 0 bration, the input to the second-rank latch is switched to the –200 first-rank latch, the DAC is loaded with the contents of the first- rank latch, V settles to the value represented by the data in –10 –400 OUT the first-rank latch, then CALOK will go high, and MUX is OUT –600 switched to V . Therefore the user should program the DAC OUT with the desired data before initiating the calibration. The sec- 0 10 20 µs ond rank latch, controlled by LDAC, is a transparent latch. As long as LDAC remains high, changes in the first rank latch will a. –10 V to +10 V Full-Scale Step Settling be reflected in the DAC output immediately. The status of the calibration may be determined by taking the 600 HBE pin low. CALOK either switches high if the calibration is in progress, or CALOK remains low if a power supply voltage 400 transient has interrupted the calibration and caused the AD760 200 to be set to the uncalibrated state. 0 When CLR is strobed, Pin 17 functions as a control input, UNI/ –200 BIP CLR, that determines how the Asynchronous Clear func- tion works (refer to Figure 1c). If the UNI/BIP CLR pin is a –400 logic low when CLR is strobed the DAC is set to minus full- –600 scale; a logic high sets the DAC to midscale. It should be noted that the clear function clears the DAC Latch but does not clear 0 1 23 4 5 µs the first rank latch. Therefore, the data that remains in the first rank latch can be reloaded by simply bringing LDAC high b. LSB Step Settling again. Alternately, new data can be loaded into the first rank latch if desired. Serial Mode Operation is enabled by bringing the SER (Pin +20 19) low. This changes the function of DB0 (Pin 14) to that of the serial input pin, SIN. The function of DB1 (Pin 13) also changes to a control input, MSB/LSB that determines which bit 0 is to be loaded first. Sixteen or Eighteen-Bit Operation is selected with another –20 dual use pin. DB2 (Pin 12) changes to a control input, 18/16- SERIAL, that selects whether 16-bit or 18-bit serial data is to be used. For 16-bit operation the data inputs, Pins 7–12, should be 0 1 23 4 5 tied low. For 18-bit operation Pin 12 must be tied high. µs Data is clocked into the input shift register on the rising edge of c. D-to-A Glitch Impulse CS as shown in Figure 1b. The data is then resident in the first rank latch and can be loaded into the DAC by taking the LDAC Figure 8. Output Characteristics pin high. This will cause the DAC to change to the appropriate output value. In serial mode the byte controls HBE (Pin 18) DIGITAL CIRCUIT DETAILS and LBE (Pin 17) are disabled. Pin 17 can be tied to a logic The AD760 has several “dual-use” pins that allow flexible op- high or low depending on how the user wants the asynchronous eration while maintaining the lowest possible pin count and con- clear function to work. The Serial Out pin (S ) can be used sequently the smallest package size. The following information OUT to daisy chain several DACs together in multi-DAC applications is useful when applying the AD760. to minimize the number of control lines required. The first rank The AD760 uses an internal Output Multiplexer to discon- latch simply acts as a shift register, and repeated strobing of CS nect the DAC output from MUX (Pin 27) when the device OUT will shift the data out through S and into the next DAC. OUT is uncalibrated or when a calibration sequence is in progress. At Each DAC in the chain will require its own LDAC signal unless those times MUX is switched to MUX (Pin 28) so the OUT IN all of the DACs are to be updated simultaneously. user can force a predetermined output voltage. Refer to the fol- lowing section for using the output multiplexer. REV. A –9– µV mV VOLTS µV AD760 +V CC Byte Mode Operation is enabled by setting SER high, which 4 configures DB0–DB7 as data inputs. In this mode HBE and 1 CALOK LBE are used to identify the data as either the high byte or the +V CC SPAN/ low byte of the 16-bit word. The user can load the data in either 0.1µF BIP OFF AD760 24 order into the first rank latch using the rising edge of the CS signal as shown in Figure 1a. The status of Pin 17 when CLR is 7 2 strobed determines whether the AD760 clears to unipolar or 23 AD707 OUTPUT V OUT OR 6 bipolar zero. (But it cannot be hardwired to the desired state, as AD820 MUX OUT in the serial mode.) 1kΩ 27 3 4 0.1µF MUX IN NOTE: CS is edge triggered. HBE, LBE, CLR, SER, CAL, and 28 100pF LDAC are level triggered. AGND 22 3 –V EE USING THE OUTPUT MULTIPLEXER –V EE The onboard multiplexer allows the user to isolate the load from the voltage variations at V during calibration. To minimize OUT Figure 9. Buffering the AD760 Internal MUX the glitch-impulse at MUX , the multiplexer input, MUX , OUT IN should be tied to a voltage equal to the DAC’s negative USING AN EXTERNAL MULTIPLEXER full-scale voltage. Since the DAC is loaded with the contents of An external multiplexer like the ADG419 allows the user to its first-rank latch before completing calibration, the DAC minimize the glitch impulse when holding the output to any should be programmed to negative full scale before calibrating. predetermined voltage during calibration. The ADG419 can be This will minimize the voltage excursions of MUX at the OUT used with a high speed op amp like the AD829, as shown in Fig- beginning and end of calibration. If the glitch-impulse at the ure 10, to attain the fastest possible settling time while main- beginning of calibration is not important, yet the user wants to taining 16-bit linearity. The settling time to 1/2 LSB for a 20 V minimize the recovery time at MUX , MUX should be set OUT IN step is typically 10 μs. to the voltage that corresponds to the data in the first-rank latch before calibration is initiated. AD760 TO MC68HC11 (SPI* BUS) INTERFACE The multiplexer series on-resistance limits its load-drive capability. The AD760 interface to the Motorola SPI (serial peripheral in- To attain 16-bit linearity, MUX must be buffered with a OUT terface) is shown in Figure 11. The MOSI, SCK, and SS pins of suitable op amp. The amplifier open loop-gain and common- the HC11 are respectively connected to the S , CS and LDAC IN mode rejection contribute to gain error whereas the linearity of pins of the AD760. The majority of the interfacing issues are these parameters affect the relative accuracy (or integral nonlin- taken care of in the software initialization. A typical routine such earity). In general, the amplifier linearity is not specified so its as the one shown below begins by initializing the state of the effects must be determined empirically. Using the AD707, as various SPI data and control registers. shown in Figure 9, the overall linearity error is within 0.5 LSB. The most significant data byte (MSBY) is then retrieved from The AD707C/T initial voltage offset and its temperature coeffi- memory and processed by the SENDAT subroutine. The SS cient will not contribute more than 0.1 LSB to the Bipolar Zero pin is driven low by indexing into the PORTD data register and Error over the entire operating temperature range. The settling clearing Bit 5. The MSBY is then sent to the SPI data time to 1/2 LSB is typically 100 μs for a 20 V step. For applica- register where it is automatically transferred to the AD760. tions that require faster settling, the AD820 can be used to *SPI is a registered trademark of Motorola. attain full-scale settling to within a 1/2 LSB in 20 μs. The addi- tional linearity error from the AD820 will be no more than 0.25 LSB. +V CC +V 4 CC CALOK 1 4 +V CC ADG419 SPAN/ 0.1µF AD760 6 24 BIP OFF 7 2 23 8 V OUT AD829 6 OUT MUX 5 27 OUT 1kΩ 1 3 4 MUX IN 1nF 28 60pF 2 0.1µF AGND 22 7 –V 3 EE –V –V EE EE Figure 10. Using the AD760 with an External MUX REV. A –10– AD760 The HC11 generates the requisite 8 clock pulses with data valid the frequency range of interest. The AD760’s noise spectral on the rising edges. After the most significant byte is transmit- density is shown in Figures 13 and 14. Figure 13 shows the ted, the least significant byte (LSBY) is loaded from memory DAC output noise voltage spectral density for a 20 V span ex- and transmitted in a similar fashion. To complete the transfer, cluding the reference. This figure shows the l/f corner frequency the LDAC pin is driven high latching the complete 16-bit word at 100 Hz and the wideband noise to be below 120 nV/ Hz. into the AD760. Figure 14 shows the reference wideband noise to be below 125 nV/ Hz. INIT LDAA #$2F ;SS = 1; SCK = 0; MOSI = I STAA PORTD ;SEND TO SPI OUTPUTS 1000 LDAA #$38 ;SS, SCK,MOSI = OUTPUTS STAA DDRD ;SEND DATA DIRECTION INFO LDAA #$50 ;DABL INTRPTS,SPI IS MASTER & ON STAA SPCR ;CPOL=0, CPHA=0,1MHZ BAUD RATE 100 NEXTPT LDAA MSBY ;LOAD ACCUM W/UPPER 8 BITS BSR SENDAT ;JUMP TO DAC OUTPUT ROUTINE JMP NEXTPT ;INFINITE LOOP 10 SENDAT LDY #$1000 ;POINT AT ON-CHIP REGISTERS BCLR $08,Y,$20 ;DRIVE SS (LDAC) LOW STAA SPDR ;SEND MS-BYTE TO SPI DATA REG WAIT1 LDAA SPSR ;CHECK STATUE OF SPIE 1 10 100k 1M 10M 1 100 1k 10k BPL WAIT1 ;POLL FOR END OF X-MISSION FREQUENCY – Hz LDAA LSBY ;GET LOW 8 BITS FROM MEMORY STAA SPDR ;SEND LS-BYTE TO SPI DATA REG Figure 13. DAC Output Noise Voltage Spectral Density WAIT2 LDAA SPSR ;CHECK STATUS OF SPIE BPL WAIT2 ;POLL FOR END OF X-MISSION 1000 BSET $08,Y,$20 ;DRIV SS HIGH TO LATCH DATA RTS 100 68HC11 S MOSI IN CS SCK AD760 LDAC SS SER 10 Figure 11. AD760 to 68HC11 (SPI) Interface 1 10 100k 1M 10M 1 100 1k 10k AD760 TO MICROWIRE INTERFACE FREQUENCY – Hz The flexible serial interface of the AD760 is also compatible Figure 14. Reference Noise Voltage Spectral Density with the National Semiconductor MICROWIRE* interface. The MICROWIRE* interface is used on microcontrollers such BOARD LAYOUT as the COP400 and COP800 series of processors. A generic in- Designing with high resolution data converters requires careful terface to the MICROWIRE interface is shown in Figure 12. attention to board layout. Trace impedance is the first issue. A The G1, SK, and SO pins of the MICROWIRE interface are re- 306 μA current through a 0.5 trace will develop a voltage spectively connected to the LDAC, CS and S pins of the IN drop of 153 μV, which is 1 LSB at the 16-bit level for a 10 V AD760. full-scale span. In addition to ground drops, inductive and ca- pacitive coupling need to be considered, especially when high MICROWIRE S IN SO accuracy analog signals share the same board with digital sig- SK CS AD760 nals. Finally, power supplies need to be decoupled in order to G1 LDAC filter out ac noise. SER Analog and digital signals should not share a common path. Each signal should have an appropriate analog or digital return routed close to it. Using this approach, signal loops enclose a Figure 12. AD760 to MICROWIRE Interface small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recom- NOISE mended to provide low impedance signal paths. Separate analog In high resolution systems, noise is often the limiting factor. A and digital ground planes should also be used, with a single in- 16-bit DAC with a 10 volt span has an LSB size of 153 μV terconnection point to minimize ground loops. Analog signals (–96 dB). Therefore, the noise must remain below this level in should be routed as far as possible from digital signals and *MICROWIRE is a registered trademark of National Semiconductor. should cross them at right angles. REV. A –11– NOISE VOLTAGE – nV/ Hz NOISE VOLTAGE – nV/ Hz AD760 One feature that the AD760 incorporates to help the user layout GROUNDING is that the analog pins (V , V , REF OUT, REF IN, SPAN/ CC EE The AD760 has two pins, designated analog ground (AGND) BIP OFFSET, V , MUX , MUX and AGND) are adja- OUT OUT IN and digital ground (DGND.) The analog ground pin is the cent to help isolate analog signals from digital signals. “high quality” ground reference point for the device. Any exter- nal loads on the output of the AD760 should be returned to SUPPLY DECOUPLING analog ground. If an external reference is used, this should also The AD760 power supplies should be well filtered, well regu- be returned to the analog ground. lated, and free from high frequency noise. Switching power sup- If a single AD760 is used with separate analog and digital plies are not recommended due to their tendency to generate ground planes, connect the analog ground plane to AGND and spikes which can induce noise in the analog system. the digital ground plane to DGND keeping lead lengths as short Decoupling capacitors should be used in very close layout prox- as possible. Then connect AGND and DGND together at the imity between all power supply pins and ground. A 10 μF tantalum AD760. If multiple AD760s are used or the AD760 shares ana- capacitor in parallel with a 0.1 μF ceramic capacitor provides ad- log supplies with other components, connect the analog and equate decoupling. V and V should be bypassed to analog CC EE digital returns together once at the power supplies rather than at ground, while V should be decoupled to digital ground. LL each chip. This single interconnection of grounds prevents large ground loops and consequently prevents digital currents from An effort should be made to minimize the trace length between flowing through the analog ground. the capacitor leads and the respective converter power supply and common pins. The circuit layout should attempt to locate the AD760, associated analog circuitry and interconnections as far as possible from logic circuitry. A solid analog ground plane around the AD760 will isolate large switching ground currents. For these reasons, the use of wire wrap circuit construction is not recommended; careful printed circuit construction is preferred. PACKAGE INFORMATION 28-Pin Cerdip Package (Q-28) 1.490 (37.84) MAX 28 15 0.525 (13.33) 0.515 (13.08) 1 0.18 (4.57) 14 0.620 (15.74) MAX 0.590 (14.93) GLASS SEALANT 0.125 (3.175) MIN 0.012 (0.305) 0.008 (0.203) 0.22 (5.59) 0.11 (2.79) MAX 15° 0.099 (2.28) 0° 0.02 (0.5) 0.06 (1.52) 0.016 (0.406) 0.05 (1.27) REV. A –12– PRINTED IN U.S.A. C2023–18–4/95