ANALOG DEVICES AD7568

2 LC MOS a Octal 12-Bit DAC AD7568 FUNCTIONAL BLOCK DIAGRAM FEATURES Eight 12-Bit DACs in One Package V V D V C V B V A R A AGND DGND DD REF REF REF REF FB 4-Quadrant Multiplication Separate References AD7568 Single +5 V Supply I A INPUT DAC A OUT1 12 12 DAC A LATCH A LATCH I A OUT2 Low Power: 1 mW R B FB Versatile Serial Interface I B INPUT DAC B OUT1 12 Simultaneous Update Capability 12 DAC B LATCH B LATCH I B OUT2 Reset Function R C FB 44-Pin PQFP and PLCC I C INPUT OUT1 DAC C 12 12 DAC C LATCH C LATCH I C OUT2 APPLICATIONS R D FB Process Control I D INPUT DAC D OUT1 12 12 DAC D LATCH D LATCH I D Automatic Test Equipment OUT2 R E FB General Purpose Instrumentation INPUT I E DAC E OUT1 12 12 DAC E LATCH E LATCH I E OUT2 GENERAL DESCRIPTION R F FB The AD7568 contains eight 12-bit DACs in one monolithic de- INPUT DAC F I F OUT1 12 12 DAC F LATCH F LATCH I F vice. The DACs are standard current output with separate V , OUT2 REF R G FB I , I and R terminals. OUT1 OUT2 FB I G INPUT DAC G OUT1 12 12 DAC G LATCH G LATCH The AD7568 is a serial input device. Data is loaded using I G OUT2 R H FSIN, CLKIN and SDIN. One address pin, A0, sets up a de- FB INPUT DAC H I H OUT1 vice address, and this feature may be used to simplify device 12 12 DAC H LATCH H LATCH I H OUT2 loading in a multi-DAC environment. All DACs can be simultaneously updated using the asynchro- CONTROL LOGIC FSIN + nous LDAC input and they can be cleared by asserting the CLKIN INPUT SHIFT REGISTER asynchronous CLR input. SDIN 12 The AD7568 is housed in a space-saving 44-pin plastic quad V E V G flatpack and 44-lead PLCC. V F V H A0 SDOUT REF REF REF REF LDAC CLR PIN CONFIGURATIONS Plastic Quad Flatpack Plastic Leaded Chip Carrier 645 3 2 1 44 43 42 41 40 7 39 NC 1 PIN 1 IDENTIFIER 33 NC NC NC V C V F 2 32 REF REF V F 8 38 V C REF REF R F 3 31 R C FB FB R F 9 37 R C FB FB I F 4 30 I C OUT1 OUT1 AD7568 PQFP I F 10 36 I C 29 I F 5 AD7568 I C OUT1 OUT1 OUT2 OUT2 TOP VIEW V G 6 28 V B REF Not to Scale TOP VIEW REF I F 11 35 OUT2 I C AD7568 PLCC OUT2 R G 7 27 R B FB (Not to Scale) FB TOP VIEW V B V G 12 34 REF REF I G 8 26 I B OUT1 OUT1 (Not to Scale) R G 13 33 R B I G 9 25 I B FB FB OUT2 OUT2 V H 10 24 V A I G 14 32 I B REF REF OUT1 OUT1 R H 11 23 R A FB FB I G 15 31 I B OUT2 OUT2 V H 16 30 V A REF REF R H 17 29 R A FB FB 18 19 20 21 22 23 24 25 26 27 28 NC = NO CONNECT REV. C NC = NO CONNECT Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. I H I E OUT1 12 44 OUT2 I H I E 13 43 OUT1 OUT2 SDOUT 14 42 R E FB CLR 15 41 V E REF 16 40 V LDAC DD 17 39 DGND FSIN SDIN 18 38 AGND CLKIN 19 37 V D REF A0 20 36 R D FB I A 21 35 I D OUT2 OUT1 I A 22 34 I D OUT1 OUT2 I H I E OUT1 OUT2 I H I E OUT2 OUT1 SDOUT R E FB CLR V E REF LDAC V DD FSIN DGND SDIN AGND CLKIN V D REF A0 R D FB I A I D OUT2 OUT1 I A I D OUT1 OUT2 (V = +4.75 V to +5.25 V; I = I = O V; V = +5 V; T = T to T , DD OUT1 OUT2 REF A MIN MAX 1 unless otherwise noted) AD7568–SPECIFICATIONS 2 Parameter AD7568B Units Test Conditions/Comments ACCURACY 12 Resolution 12 Bits 1 LSB = V /2 = 1.22 mV when V = 5 V REF REF Relative Accuracy ±0.5 LSB max Differential Nonlinearity ±0.9 LSB max All Grades Guaranteed Monotonic over Temperature Gain Error +25°C ±4 LSBs max T to T ±5 LSBs max MIN MAX Gain Temperature Coefficient 2 ppm FSR/°C typ 5 ppm FSR/°C max Output Leakage Current I OUT1 @ +25°C 10 nA max See Terminology Section T to T 200 nA max MIN MAX REFERENCE INPUT Input Resistance 5 kΩ min Typical Input Resistance = 7 kΩ 9kΩ max Ladder Resistance Mismatch 2 % max Typically 0.6% DIGITAL INPUTS V , Input High Voltage 2.4 V min INH V , Input Low Voltage 0.8 V max INL I , Input Current ±1 μA max INH C , Input Capacitance 10 pF max IN POWER REQUIREMENTS V Range 4.75/5.25 V min/V max DD Power Supply Sensitivity ΔGain/ΔV –75 dB typ DD I 300 μA max V = 4.0 V min, V = 0.4 V max DD INH INL 3.5 mA max V = 2.4 V min, V = 0.8 V max INH INL (These characteristics are included for Design Guidance and are not subject AC PERFORMANCE CHARACTERISTICS to test. DAC output op amp is AD843.) 2 Parameter AD7568B Units Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 500 ns typ To 0.01% of Full-Scale Range. DAC Latch Alternately Loaded with All 0s and All 1s. Digital to Analog Glitch Impulse 40 nV–s typ Measured with V = 0 V. DAC Register Alternately REF Loaded with All 0s and All 1s. Multiplying Feedthrough Error –66 dB max V = 20 V pk-pk, 10 kHz Sine Wave. DAC Latch REF Loaded with All 0s. Output Capacitance 60 pF max All 1s Loaded to DAC. 30 pF max All 0s Loaded to DAC. Channel-to-Channel Isolation –76 dB typ Feedthrough from Any One Reference to the Others with 20 V pk-pk, 10 kHz Sine Wave Applied. Digital Crosstalk 40 nV–s typ Effect of all 0s to all 1s Code Transition on Nonselected DACs. Digital Feedthrough 40 nV–s typ Feedthrough to Any DAC Output with FSIN High and Square Wave Applied to SDIN and SCLK. Total Harmonic Distortion –83 dB typ V = 6 V rms, 1 kHz Sine Wave. REF Output Noise Spectral Density @ 1 kHz 20 nV/√Hz All 1s Loaded to the DAC. V = 0 V. Output Op REF Amp is AD OP07. NOTES 1 Temperature range as follows: B Version: –40°C to +85°C. 2 All specifications also apply for V = +10 V, except relative accuracy which degrades to ±1 LSB. REF Specifications subject to change without notice. REV. C –2– AD7568 TIMING SPECIFICATIONS (V = +5 V 6 5%; I = I = 0 V; T = T to T , unless otherwise noted) DD OUT1 OUT2 A MIN MAX Limit at Limit at Parameter T = +258CT = –408C to +858C Units Description A A t 100 100 ns min CLKIN Cycle Time 1 t 40 40 ns min CLKIN High Time 2 t 40 40 ns min CLKIN Low Time 3 t 30 30 ns min FSIN Setup Time 4 t 30 30 ns min Data Setup Time 5 t 5 5 ns min Data Hold Time 6 t 90 90 ns min FSIN Hold Time 7 2 t 70 70 ns max SDOUT Valid After CLKIN Falling Edge 8 t 40 40 ns min LDAC, CLR Pulse Width 9 NOTES 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 t is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. 8 t 1 CLKIN (I) t 3 t 2 t 4 t 7 FSIN (I) t 5 t 6 DB15 DB0 SDIN (I) t 8 SDOUT (O) DB0 DB15 t 9 LDAC, CLR NOTES 1. AO IS HARDWIRED HIGH OR LOW. Figure 1. Timing Diagram 1.6mA I OL TO OUTPUT PIN +2.1V C L 50pF 200mA I OH Figure 2. Load Circuit for Digital Output Timing Specifications REV. C –3– AD7568 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to DGND −0.3 V to +6 V DD other conditions above those indicated in the operational I to DGND −0.3 V to V +0.3 V OUT1 DD section of this specification is not implied. Exposure to absolute I to DGND −0.3 V to V +0.3 V OUT2 DD maximum rating conditions for extended periods may affect Digital Input Voltage to DGND −0.3 V to VDD +0.3 V device reliability. VRFB, VREF to DGND ±15 V 1 Input Current to Any Pin Except Supplies ±10 mA ESD CAUTION Operating Temperature Range Commercial Plastic (B Versions) −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Power Dissipation (Any Package) to 75°C 250 mW Derates above 75°C by 10 mW/°C 1 Transient currents of up to 100 mA will not cause SCR latch-up. PIN DESCRIPTION Mnemonic Description VDD Positive Power Supply. This is 5 V ± 5%. DGND Digital Ground. AGND Analog Ground V to V DAC Reference Inputs. REFA REFH R to R DAC Feedback Resistor Pins. FBA FBH IOUTA to IOUTH DAC Current Output Terminals. AGND This pin connects to the back gates of the current steering switches. It should be connected to the signal ground of the system. CLKIN Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on the clock line to avoid timing issues. FSIN Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When FSIN goes low, it enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address bit is valid, the 12-bit DAC data is transferred to the appropriate input latch on the sixteenth falling edge after FSIN goes low. SDIN Serial Data Input. The device accepts a 16-bit word. The first bit (DB15) is the DAC MSB, with the remaining bits following. Next comes the device address bit, A0. If this does not correspond to the logic level on Pin A0, the data is ignored. Finally comes the three DAC select bits. These determine which DAC in the device is selected for loading. SDOUT This shift register output allows multiple devices to be connected in a daisy-chain configuration. A0 Device Address Pin. This input gives the device an address. If DB3 of the serial input stream does not correspond to this, the data that follows is ignored and not loaded to any input latch. However, it will appear at SDOUT irrespective of this. LDAC Asynchronous LDAC Input. When this input is taken low, all DAC latches are simultaneously updated with the contents of the input latches. CLR Asynchronous CLR Input. When this input is taken low, all DAC latch outputs go to zero. AD7568 TERMINOLOGY Output Voltage Settling Time Relative Accuracy This is the amount of time it takes for the output to settle to a Relative Accuracy or endpoint linearity is a measure of the specified level for a full-scale input change. For the AD7568, it maximum deviation from a straight line passing through the is specified with the AD843 as the output op amp. endpoints of the DAC transfer function. It is measured after Digital to Analog Glitch Impulse adjusting for zero error and full-scale error and is normally ex- This is the amount of charge injected into the analog output pressed in Least Significant Bits or as a percentage or full-scale when the inputs change state. It is normally specified as the area reading. of the glitch in either pA-secs or nV-secs, depending upon Differential Nonlinearity whether the glitch is measured as a current or voltage signal. It Differential nonlinearity is the difference between the measured is measured with the reference input connected to AGND and change and the ideal 1 LSB change between any two adjacent the digital inputs toggled between all 1s and all 0s. codes. A specified differential nonlinearity of 1 LSB maximum AC Feedthrough Error ensures monotonicity. This is the error due to capacitive feedthrough from the DAC Gain Error reference input to the DAC I terminal, when all 0s are OUT Gain Error is a measure of the output error between an ideal loaded in the DAC. DAC and the actual device output. It is measured with all 1s in Channel-to-Channel Isolation the DAC after offset error has been adjusted out and is Channel-to-channel isolation refers to the proportion of input expressed in Least Significant Bits. Gain error is adjustable to signal from one DAC’s reference input which appears at the zero with an external potentiometer. output of any other DAC in the device and is expressed in dBs. Output Leakage Current Digital Crosstalk Output leakage current is current which flows in the DAC lad- The glitch impulse transferred to the output of one converter der switches when these are turned off. For the I terminal, OUT1 due to a change in digital input code to the other converter is it can be measured by loading all 0s to the DAC and measuring defined as the Digital Crosstalk and is specified in nV-secs. the I current. Minimum current will flow in the I line OUT1 OUT2 Digital Feedthrough when the DAC is loaded with all 1s. This is a combination of When the device is not selected, high frequency logic activity on the switch leakage current and the ladder termination resistor the device digital inputs is capacitively coupled through the de- current. The I leakage current is typically equal to that in OUT2 vice to show up as noise on the I pin and subsequently on OUT I . OUT1 the op amp output. This noise is digital feedthrough. Output Capacitance This is the capacitance from the I pin to AGND. OUT1 Table I. AD7568 Loading Sequence DB15 DB0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A0 DS2 DS1 DS0 Table II. DAC Selection DS2 DS1 DS0 Function 0 0 0 DAC A Selected 0 0 1 DAC B Selected 0 1 0 DAC C Selected 0 1 1 DAC D Selected 1 0 0 DAC E Sclected 1 0 1 DAC F Selected 1 1 0 DAC G Sclected 1 1 1 DAC H Selected REV. C –5– AD7568–Typical Performance Curves 5.5 2 1.0 V = +5V DD 5.0 V = +5V V = +5V 0.9 DD DD T = +25°C A T = +25°C A 4.5 0.8 4.0 0.7 3.5 V = +2.4V IH 0.6 3.0 1 0.5 2.5 0.4 2.0 0.3 1.5 V = +4V 0.2 IH 1.0 0.1 0.5 0.0 0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 –40 –15 10 35 60 85 2.0 4.0 6.0 8.0 10.0 DIGITAL INPUT – Volts TEMPERATURE – °C V – Volts REF Figure 3. Supply Current vs. Logic Figure 4. Supply Current vs. Figure 5. Differential Nonlinearity Input Voltage Temperature Error vs. V REF 1.0 1.0 –50 V = +5V DD 0.9 –55 V = +5V T = +25°C DD A V = +10V REF T = +25°C 0.8 A 0.8 V = +5V –60 DD V = 6V rms IN T = +25°C A 0.7 –65 OP AMP = AD713 0.6 0.6 –70 0.5 –75 0.4 0.4 –80 0.3 –85 0.2 0.2 –90 0.1 –95 0.0 0.0 –100 2 3 4 5 2.0 4.0 6.0 8.0 10.0 0 2048 4095 10 10 10 10 V – Volts REF DIGITAL CODE FREQUENCY – Hz Figure 6. Integral Nonlinearity Error Figure 7. Typical DAC to DAC Figure 8. Total Harmonic Distortion vs. V Linearity Matching vs. Frequency REF 0 0 V C = 20V pk-pk SINE WAVE V B GROUNDED REF REF –10 –10 ALL OTHER REFERENCE INPUTS GROUNDED ALL OTHER REFERENCE INPUTS = DAC C LOADED WITH ALL 1s 20V pk-pk SINE WAVE5V200ns –20 –20 ALL OTHER DACs LOADED WITH ALL 0s DAC B LOADED WITH ALL 0s 100 ALL OTHER DACs LOADED WITH ALL 1sDIGITAL INPUTS –30 –30 90V = +5VDD T = +25°C A –40 –40 V = +10VREF OP AMP = AD713 –50 –50AD713 OUTPUT –60 –60 –70 –70 10 –80 –800% –90 –90 50mV200ns –100 –100 3 3 4 5 6 4 5 6 10 10 10 10 10 10 10 10 FREQUENCY – Hz FREQUENCY – Hz Figure 10. Channel-to-Channel Figure 11. Channel-to-Channel Figure 9. Digital-to-Analog Glitch Isolation (1 DAC to 1 DAC) Isolation (1 DAC to All Other DACs) Impulse REV. C –6– V B/V C – dBs OUT OUT V B/V C – dBs OUT OUT INL – LSBs I – mA DD INL SPREAD – LSBs I – mA DD THD – dBs DNL – LSBs AD7568 0 Interface Section DAC LOADED WITH ALL 1s The AD7568 is a serial input device. Three lines control the se- –10 rial interface, FSIN, CLKIN and SDIN. The timing diagram is –20 V = +5V DD shown in Figure 1. T = +25°C A –30 V = 20V pk-pk IN When the FSIN input goes low, data appearing on the SDIN –40 OP AMP = AD713 line is clocked into the input shift register on each falling edge of –50 CLKIN. When sixteen bits have been received, the register –60 loading is automatically disabled until the next falling edge of –70 DAC LOADED WITH ALL 0s FSIN detected. Also, the received data is clocked out on the –80 next rising edge of CLKIN and appears on the SDOUT pin. –90 This feature allows several devices to be connected together in a –100 daisy chain fashion. 3 4 5 6 7 10 10 10 10 10 When the sixteen bits have been received in the input shift regis- Figure 12. Multiplying Frequency Response vs. ter, DB3 (A0) is checked to see if it corresponds to the state of Digital Code pin A0. If it does, then the word is accepted. Otherwise, it is dis- regarded. This allows the user to address one of two AD7568s GENERAL DESCRIPTION in a very simple fashion. DB0 to DB2 of the 16-bit word deter- D/A Section mine which of the eight DAC input latches is to be loaded. The AD7568 contains eight 12-bit current-output D/A convert- When the LDAC line goes low, all eight DAC latches in the de- ers. A simplified circuit diagram for one of the D/A converters is vice are simultaneously loaded with the contents of their respec- shown in Figure 13. tive input latches, and the outputs change accordingly. A segmented scheme is used whereby the 2 MSBs of the 12-bit Bringing the CLR line low resets the DAC latches to all 0s. The data word are decoded to drive the three switches A, B and C. input latches are not affected, so that the user can revert to the The remaining 10 bits of the data word drive the switches S0 to previous analog output if desired. S9 in a standard R–2R ladder configuration. CLKIN Each of the switches A to C steers 1/4 of the total reference cur- 16-BIT INPUT SHIFT REGISTER FSIN rent with the remaining current passing through the R–2R SDIN SDOUT section. Each DAC in the device has separate V , I , I and REF OUT1 OUT2 Figure 14. Input Logic R pins. This makes the device extremely versatile and allows FB DACs in the same device to be configured differently. When an output amplifier is connected in the standard configu- ration of Figure 15, the output voltage is given by: V = –D•V OUT REF where D is the fractional representation of the digital word loaded to the DAC. Thus, in the AD7568, D can be set from 0 to 4095/4096. V REF R R R 2R 2R 2R 2R 2R 2R 2R CB A S9 S8 S9 R/2 R FB I OUT1 I OUT2 SHOWN FOR ALL 1s ON DAC Figure 13. Simplified D/A Circuit Diagram REV. C –7– AD7568 R4 UNIPOLAR BINARY OPERATION (2-Quadrant Multiplication) R2 10W20kW R5 Figure 15 shows the standard unipolar binary connection dia- R A FB C1 R1 20Wgram for one of the DACs in the AD7568. When V is an ac 20kWIN I A OUT1 V IN R3 signal, the circuit performs 2-quadrant multiplication. Resistors V DAC A A1 OUT 10kWA2 R1 and R2 allow the user to adjust the DAC gain error. Offset V A REF I A OUT2 AD7568 can be removed by adjusting the output amplifier offset voltage. SIGNAL A1 should be chosen to suit the application. For example, the GND NOTES AD OP07 or OP177 are ideal for very low bandwidth applica- 1. ONLY ONE DAC IS SHOWN FOR CLARITY. tions while the AD843 and AD845 offer very fast settling time 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C1 PHASE COMPENSATION (5–15pF) MAY BE in wide bandwidth applications. Appropriate multiple versions REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1. of these amplifiers can be used with the AD7568 to reduce board space requirements. Figure 16. Bipolar Operation (4-Quadrant Multiplication) The code table for Figure 15 is shown in Table III. Table IV. Bipolar (Offset Binary) Code Table R2 10W R A FB Digital Input Analog Output C1 R1 20W I A OUT1 MSB . . . . . LSB (V As Shown in Figure 16) V V OUT IN OUT DAC A A1 V A 1111 1111 1111 +V (2047/2048) REF REF I A OUT2 AD7568 A1: OP-177 1000 0000 0001 +V (1/2048) REF SIGNAL ADOP-07 1000 0000 0000 +V (0/2048) = 0 REF GND AD711 0111 1111 1111 –V (1/2048) AD843 NOTES REF AD845 1. ONLY ONE DAC IS SHOWN FOR CLARITY. 0000 0000 0001 –V (2047/2048) REF 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 0000 0000 0000 –V (2048/2048) = –V REF REF 3. C1 PHASE COMPENSATION (5–15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1. NOTE Nominal LSB size for the circuit of Figure 16 is given by: Figure 15. Unipolar Binary Operation V (1/2048). REF Table III. Unipolar Binary Code Table SINGLE SUPPLY CIRCUITS The AD7568 operates from a single +5 V supply, and this Digital Input Analog Output makes it ideal for single supply systems. When operating in such MSB………LSB (V As Shown in Figure 15) OUT a system, it is not possible to use the standard circuits of Figures 15 and 16 since these invert the analog input, V . There are IN 1111 1111 1111 –V (4095/4096) REF two alternatives. One of these continues to operate the DAC as 1000 0000 0001 –V (2049/4096) REF a current-mode device, while the other uses the voltage switch- 1000 0000 0000 –V (2048/4096) REF ing mode. 0111 1111 1111 –V (2047/4096) REF 0000 0000 0001 –V (1/4096) REF R A FB 0000 0000 0000 –V (0/4096) = 0 REF I A OUT1 V V IN OUT NOTE DAC A A1 V A Nominal LSB size for the circuit of Figure 15 is given by: REF I A OUT2 V (1/4096). AD7568 REF BIPOLAR OPERATION (4-Quadrant Multiplication) V Figure 16 shows the standard connection diagram for bipolar BIAS NOTES operation of any one of the DACs in the AD7568. The coding is 1. ONLY ONE DAC IS SHOWN FOR CLARITY. offset binary as shown in Table IV. When V is an ac signal, IN 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C1 PHASE COMPENSATION (5–15pF) MAY BE the circuit performs 4-quadrant multiplication. To maintain the REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1. gain error specifications, resistors R3, R4 and R5 should be ra- tio matched to 0.01%. Figure 17. Single Supply Current-Mode Operation REV. C –8– AD7568 R1 R2 Current Mode Circuit In the current mode circuit of Figure 17, I , and hence OUT2 R A I , is biased positive by an amount V . For the circuit to FB OUT1 BIAS V OUT V IN I A V A A1 OUT1 operate correctly, the DAC ladder termination resistor must be REF connected internally to I . This is the case with the AD7568. DAC A OUT2 I A OUT2 The output voltage is given by: AD7568 R FB V = D V −V+V OUT () BIAS IN BIAS {} R DAC NOTES 1) ONLY ONE DAC IS SHOWN FOR CLARITY. As D varies from 0 to 4095/4096, the output voltage varies from 2) DIGITAL INPUT CONNECTIONS ARE OMITTED. 3) C1 PHASE COMPENSATION (5–15pF) MAY BE V = V to V = 2 V – V . V should be a low OUT BIAS OUT BIAS IN BIAS REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1. impedance source capable of sinking and sourcing all possible variations in current at the I terminal without any OUT2 Figure 18. Single Supply Voltage Switching problems. Mode Operation Voltage Mode Circuit Figure 18 shows DAC A of the AD7568 operating in the APPLICATIONS voltage-switching mode. The reference voltage, V is applied to IN Programmable State Variable Filter the I pin, I is connected to AGND and the output volt- OUT1 OUT2 The AD7568 with its multiplying capability and fast settling age is available at the V terminal. In this configuration, a REF time is ideal for many types of signal conditioning applications. positive reference voltage results in a positive output voltage The circuit of Figure 19 shows its use in a state variable filter making single supply operation possible. The output from the design. This type of filter has three outputs: low pass, high pass DAC is a voltage at a constant impedance (the DAC ladder re- and bandpass. The particular version shown in Figure 19 uses sistance). Thus, an op amp is necessary to buffer the output one half of an AD7568 to control the critical parameters f , Q 0 voltage. The reference voltage input no longer sees a constant and A . Instead of several fixed resistors, the circuit uses the 0 input impedance, but one which varies with code. So, the volt- DAC equivalent resistances as circuit elements. Thus, R1 in age input should be driven from a low impedance source. Figure 19 is controlled by the 12-bit digital word loaded to DAC A of the AD7568. This is also the case with R2, R3 and It is important to note that V is limited to low voltages be- IN R4. The fixed resistor R5 is the feedback resistor, R B. FB cause the switches in the DAC no longer have the same source- drain voltage. As a result, their on-resistance differs and this DAC Equivalent Resistance, R = (R 3 4096)/N EQ LADDER degrades the integral linearity of the DAC. Also, V must not IN where: go negative by more than 0.3 volts or an internal diode will turn R is the DAC ladder resistance. LADDER on, causing possible damage to the device. This means that the full-range multiplying capability of the DAC is lost. N is the DAC Digital Code in Decimal (0 < N < 4096). C3 10pF C1 1000pF C1 1000pF R8 30kWR7 30kW HIGH LOW A1 PASS A2 A3 PASS R6 OUTPUT OUTPUT 10kW A1 BAND PASS I A I B R B V B V C I C V D I D OUTPUT OUT1 OUT1 FB REF REF OUT1 REF OUT1 V IN DAC A DAC B DAC C DAC D (R1) (R2) (R3) (R4) V A REF 1/2 x AD7568 I A I B I C I D OUT2 OUT2 OUT2 OUT2 NOTES 1. A1, A2, A3, A4: 1/4 x AD713 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C3 IS A COMPENSATION CAPACITOR TO ELIMINATE Q AND GAIN VARIATIONS CAUSED BY AMPLIFIER GAIN BANDWIDTH LIMITATIONS. Figure 19. Programmable 2nd Order State Variable Filter REV. C –9– AD7568 In the circuit of Figure 19: the data word transmitted to the AD7568 corresponds to the loading sequence shown in Table I. When data is to be trans- C1 = C2, R7 = R8, R3 = R4 (i.e., the same code is loaded to mitted to the part, P3.3 is taken low. Data on RXD is valid on each DAC). the falling edge of TXD. The 80C51 transmits its serial data in Resonant frequency, f = 1/(2πR3C1). 0 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7568, P3.3 is left low af- Quality Factor, Q = (R6/R8)•(R2/R5). ter the first eight bits are transferred, and a second byte of data Bandpass Gain, A0 = –R2/R1. is then transferred serially to the AD7568. When the second se- Using the values shown in Figure 19, the Q range is 0.3 to 5, rial transfer is complete, the P3.3 line is taken high. Note that and the f range is 0 to 12 kHz. 0 the 80C51 outputs the serial data byte in a format which has the LSB first. The AD7568 expects the MSB first. The 80C51 APPLICATION HINTS transmit routine should take this into account. Output Offset CMOS D/A converters in circuits such as Figures 15, 16 and 17 80C51* AD7568* exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the ampli- fier. The maximum amplitude of this error, which adds to the P3.5 CLR D/A converter nonlinearity, depends on V , where V is the OS OS P3.4 LDAC amplifier input offset voltage. For the AD7568 to maintain specified accuracy with V at 10 V, it is recommended that REF P3.3 FSIN –6 V be no greater than 500 μV, or (50 3 10 )•(V ), over the OS REF TXD SCLK temperature range of operation. Suitable amplifiers include the RXD SDIN AD OP07, AD OP27, OP177, AD711, AD845 or multiple ver- sions of these. *ADDITIONAL PINS OMITTED FOR CLARITY Temperature Coefficients The gain temperature coefficient of the AD7568 has a maxi- Figure 20. AD7568 to 80C51 Interface mum value of 5 ppm/°C and a typical value of 2 ppm/°C. This LDAC and CLR on the AD7568 are also controlled by 80C51 corresponds to gain shifts of 2 LSBs and 0.8 LSBs respectively port outputs. The user can bring LDAC low after every two over a 100°C temperature range. When trim resistors R1 and bytes have been transmitted to update the DAC which has been R2 are used to adjust full-scale in Figures 15 and 16, their tem- programmed. Alternatively, it is possible to wait until all the in- perature coefficients should be taken into account. For further put registers have been loaded (sixteen byte transmits) and then information see “Gain Error and Gain Temperature Coefficient update the DAC outputs. of CMOS Multiplying DACs,” Application Note, Publication Number E630c–5–3/86, available from Analog Devices. AD7568–68HC11 Interface Figure 21 shows a serial interface between the AD7568 and the High Frequency Considerations 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of The output capacitances of the AD7568 DACs work in con- the AD7568, while the MOSI output drives the serial data line junction with the amplifier feedback resistance to add a pole to of the AD7568. The FSIN signal is derived from a port line the open loop response. This can cause ringing or oscillation. (PC7 shown). Stability can be restored by adding a phase compensation ca- pacitor in parallel with the feedback resistor. This is shown as For correct operation of this interface, the 68HC11 should be C1 in Figures 15, 16 and 17. configured such that its CPOL bit is a 0 and its CPHA bit is a 1. When data is to be transmitted to the part, PC7 is taken low. MICROPROCESSOR INTERFACING When the 68HC11 is configured like this, data on MOSI is valid AD7568–80C51 Interface on the falling edge of SCK. The 68HC11 transmits its serial A serial interface between the AD7568 and the 80C51 micro- data in 8-bit bytes (MSB first), with only eight falling clock controller is shown in Figure 20. TXD of the 80C51 drives edges occurring in the transmit cycle. To load data to the SCLK of the AD7568 while RXD drives the serial data line of AD7568, PC7 is left low after the first eight bits are transferred, the part. The FSIN signal is derived from the port line P3.3. and a second byte of data is then transferred serially to the AD7568. When the second serial transfer is complete, the PC7 The 80C51 provides the LSB of its SBUF register as the first bit line is taken high. in the serial data stream. Therefore, the user will have to ensure that the data in the SBUF register is arranged correctly so that REV. C –10– AD7568 68HC11* AD7568* TMS320C25* AD7568* +5V PC5 CLR CLR PC6 LDAC XF LDAC PC7 FSIN FSX FSIN SCK CLKIN DX SDIN MOSI SDIN CLKX CLKIN *ADDITIONAL PINS OMITTED FOR CLARITY CLOCK GENERATION Figure 21. AD7568 to 68HC11 Interface *ADDITIONAL PINS OMITTED FOR CLARITY In Figure 21, LDAC and CLR are controlled by the PC6 and Figure 23. AD7568 to TMS320C25 Interface PC5 port outputs. As with the 80C51, each DAC of the AD7568 can be updated after each two-byte transfer, or else all with the MSB, is then shifted out to the DX pin on the rising DACs can be simultaneously updated. edge of CLKX. When all bits have been transmitted, the user can update the DAC outputs by bringing the XF output flag low. AD7568–ADSP-2101 Interface Figure 22 shows a serial interface between the AD7568 and the Multiple DAC Systems ADSP-2101 digital signal processor. The ADSP-2101 may be If there are only two AD7568s in a system, there is a simple way set up to operate in the SPORT Transmit Normal Internal of programming each. This is shown in Figure 24. If the user Framing Mode. The following ADSP-2101 conditions are rec- wishes to program one of the DACs in the first AD7568, then ommended: Internal SCLK; Active High Framing Signal; 16-bit DB3 of the serial bit stream should be set to 0, to correspond to word length. Transmission is initiated by writing a word to the the state of the A0 pin on that device. If the user wishes to pro- TX register after the SPORT has been enabled. The data is then gram a DAC in the second AD7568, then DB3 should be set to clocked out on every rising edge of SCLK after TFS goes low. 1, to correspond to A0 on that device. TFS stays low until the next data transfer. ADSP-2101* AD7568* ADSP-2101* AD7568* A0 +5V +5V CLR CLR FO LDAC FO LDAC TFS FSIN TFS FSIN DT SDIN DT SDIN SCLK CLKIN SCLK CLKIN *ADDITIONAL PINS OMITTED FOR CLARITY AD7568* Figure 22. AD7568 to ADSP-2101 Interface LDAC AD7568–TMS320C25 Interface FSIN Figure 23 shows an interface circuit for the TMS320C25 SDIN digital signal processor. The data on the DX pin is clocked out of the processor’s Transmit Shift Register by the CLKX CLKIN signal. Sixteen-bit transmit format should be chosen by setting A0 the FO bit in the ST1 register to 0. The transmit operation be- +5V CLR gins when data is written into the data transmit register of the TMS320C25. This data will be transmitted when the FSX line *ADDITIONAL PINS OMITTED FOR CLARITY goes low while CLKX is high or going high. The data, starting Figure 24. Interfacing ADSP-2101 to Two AD7568s REV. C –11– AD7568 For systems which contain larger numbers of AD7568s and 68HC11* AD7568* where the user also wishes to read back the DAC contents for (DAC 1) diagnostic purposes, the SDOUT pin may be used to daisy MOSI SDIN chain several devices together and provide the necessary serial PC7 FSIN readback. An example with the 68HC11 is shown in Figure 25. SCK SCLK The routine below shows how four AD7568s would be pro- PC6 LDAC grammed in such a system. Data is transmitted at the MOSI pin MISO A0 SDOUT of the 68HC11. It flows through the input shift registers of the AD7568s and finally appears at the SDOUT pin of DAC N. So, the readback routine can be invoked any time after the first four SDIN DECODE LOGIC words have been transmitted (the four input shift registers in the AD7568* chain will now be filled up and further activity on the CLKIN (DAC 2) pin will result in data being read back to the microcomputer FSIN through the MISO pin). System connectivity can be verified in SCLK this manner. For a four-device system (32 DACs) a two-line to LDAC four-line decoder is necessary. A0 SDOUT Note that to program the 32 DACs, 35 transmit operations are needed. In the routine, three words must be retransmitted. The first word for DACs #3, #2 and #1 must be transmitted twice in order to synchronize their arrival at the SDIN pin with A0 going SDIN low. AD7568* (DAC N) Table V. Routine for Loading 4 AD7568s Connected As in FSIN Figure 25 SCLK LDAC A0 SDOUT Bring PC7 (FSIN) low to allow writing to the AD7568s. Enable AD7568 #4 (Bring A0 low). Disable the others. *ADDITIONAL PINS OMITTED FOR CLARITY Transmit 1st 16-bit word: Data for DAC H, #4 . . . . Figure 25. Multi-DAC System . . . . Transmit 9th 16-bit word: Data for DAC H, #3 Transmit 9th 16-bit word again: Data for DAC H, #3 Transmit 10th 16-bit word: Data for DAC G, #3 Transmit 11th 16-bit word: Data for DAC F, #3 Enable AD7568 #3, Disable the others. Transmit 12th 16-bit word: Data for DAC E, #3 . . . . . . . . Transmit 17th 16-bit word: Data for DAC H, #2 Transmit 17th 16-bit word again: Data for DAC H, #2 Transmit 18th 16-bit word: Data for DAC G, #2 Enable AD7568 #2, Disable the others. Transmit 19th 16-bit word: Data for DAC F, #2 . . . . . . . . Transmit 25th word: Data for DAC H, #1 Enable AD7568 #1, Disable the others. Transmit 25th word again: Data for DAC H, #1 Transmit 26th word: Data for DAC G, #1 . . . . . . . . Transmit 32nd word: Data for DAC A, #1 Bring PC7 (FSIN) high to disable writing to the AD7568s. REV. C –12– AD7568 OUTLINE DIMENSIONS 0.180 (4.57) 0.048 (1.22) 0.165 (4.19) 0.042 (1.07) 0.056 (1.42) 0.020 (0.51) 0.042 (1.07) MIN 6 40 0.048 (1.22) 7 39 0.021 (0.53) PIN 1 0.042 (1.07) 0.013 (0.33) IDENTIFIER 0.630 (16.00) BOTTOM VIEW 0.050 TOP VIEW 0.590 (14.99) (PINS UP) (1.27) (PINS DOWN) BSC 0.032 (0.81) 0.026 (0.66) 17 29 18 28 0.045 (1.14) R 0.656 (16.66) 0.025 (0.64) 0.120 (3.05) SQ 0.650 (16.51) 0.090 (2.29) 0.695 (17.65) SQ 0.685 (17.40) COMPLIANT TO JEDEC STANDARDS MO-047-AC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 26. 44-Lead Plastic Leaded Chip Carrier [PLCC] (P-44) Dimensions shown in inches and (millimeters) 14.15 1.03 13.90 SQ 2.45 MAX 0.88 13.65 0.73 44 34 1 33 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 2.20 0.23 2.00 0.11 1.80 23 11 7° 12 22 0.25 MIN 0° 0.10 0.45 COPLANARITY 0.30 0.80 BSC LEAD WIDTH LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MO-112-AA-1 Figure 27. 44-Lead Metric Quad Flat Package [MQFP] (S-44-2) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Linearity Error (LSBs) Package Description Package Option AD7568BP −40°C to +85°C ±0.5 44-Lead Plastic Leaded Chip Carrier [PLCC] P-44 AD7568BP-REEL −40°C to +85°C ±0.5 44-Lead Plastic Leaded Chip Carrier [PLCC] P-44 AD7568BPZ −40°C to +85°C ±0.5 44-Lead Plastic Leaded Chip Carrier [PLCC] P-44 AD7568BPZ-REEL −40°C to +85°C ±0.5 44-Lead Plastic Leaded Chip Carrier [PLCC] P-44 AD7568BSZ −40°C to +85°C ±0.5 44-Lead Metric Quad Flat Package [MQFP] S-44-2 AD7568BSZ-REEL −40°C to +85°C ±0.5 44-Lead Metric Quad Flat Package [MQFP] S-44-2 1 Z = RoHS Compliant Part 1.95 REF SEATING PLANE W VIE A 041807-A AD7568 REVISION HISTORY 2/12—Rev. B to Rev. C Changes to Description, Pin Description Table ................... 4 CLR Updated Outline Dimensions ........................................................ 13 Changes to Ordering Guide ........................................................... 13 Added Revision History Section ................................................... 14 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10541-0-2/12(C)