ANALOG DEVICES AD7564

2 LC MOS a +3.3 V/+5 V, Low Power, Quad 12-Bit DAC AD7564 FEATURES FUNCTIONAL BLOCK DIAGRAM Four 12-Bit DACs in One Package 4-Quadrant Multiplication NC AGND V DGND V D V C V B V A R A DD REF REF REF REF FB Separate References Single Supply Operation I A INPUT DAC A OUT1 Guaranteed Specifications with +3.3 V/+5 V Supply 12 12 DAC A LATCH A LATCH I A OUT2 Low Power R B FB Versatile Serial Interface I B INPUT DAC B OUT1 12 12 DAC B LATCH B LATCH Simultaneous Update Capability I B OUT2 R C Reset Function FB I C INPUT OUT1 DAC C 28-Pin SOIC, SSOP and DIP Packages 12 12 DAC C LATCH C LATCH I C OUT2 R D APPLICATIONS FB I D INPUT DAC D OUT1 Process Control 12 12 DAC D LATCH D LATCH I D OUT2 Portable Instrumentation 12 General Purpose Test Equipment CLR FSIN CONTROL LOGIC + CLKIN LDAC INPUT SHIFT REGISTER SDIN AD7564 A0 A1 SDOUT GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7564 contains four 12-bit DACs in one monolithic 1. The AD7564 contains four 12-bit current output DACs with device. The DACs are standard current output with separate separate V inputs. REF V , I , I and R terminals. These DACs operate from REF OUT1 OUT2 FB 2. The AD7564 can be operated from a single +3.3 V to +5 V a single +3.3 V to +5 V supply. supply. The AD7564 is a serial input device. Data is loaded using 3. Simultaneous update capability and reset function are FSIN, CLKIN and SDIN. Two address pins A0 and A1 set up available. a device address, and this feature may be used to simplify device 4. The AD7564 features a fast, versatile serial interface com- loading in a multi-DAC environment. Alternatively, A0 and A1 patible with modern 3 V and 5 V microprocessors and can be ignored and the serial out capability used to configure a microcomputers. daisy-chained system. 5. Low power, 50 μW at 5 V and 33 μW at 3.3 V. All DACs can be simultaneously updated using the asynchro- nous LDAC input, and they can be cleared by asserting the asynchronous CLR input. The device is packaged in 28-pin SOIC, SSOP and DIP packages. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781/329-4700 Fax: 781/461-3113 AD7564–SPECIFICATIONS (V = +4.75 V to +5.25 V; I A to I D = I A = I D = AGND = 0 V; V = +10 V; T = T to T , DD OUT1 OUT1 OUT2 OUT2 REF A MIN MAX Normal Mode unless otherwise noted) 1 Parameter B Grade Units Test Conditions/Comments ACCURACY 12 Resolution 12 Bits 1 LSB = V /2 = 2.44 mV when V = 10 V REF REF Relative Accuracy ±0.5 LSB max Differential Nonlinearity ±0.5 LSB max All Grades Guaranteed Monotonic Over Temperature Gain Error +25°C ±4 LSBs max T to T ±5 LSBs max MIN MAX 2 Gain Temperature Coefficient 2 ppm FSR/°C typ 5 ppm FSR/°C max Output Leakage Current I OUT1 @ +25°C 10 nA max T to T 50 nA max MIN MAX REFERENCE INPUT Input Resistance 6 kΩ min Typical Input Resistance = 9.5 kΩ 13 kΩ max Ladder Resistance Mismatch 2 % max Typically 0.6% DIGITAL INPUTS V , Input High Voltage 2.4 V min INH V , Input Low Voltage 0.8 V max INL I , Input Current ±1 μA max INH 2 C , Input Capacitance 10 pF max IN DIGITAL OUTPUT (SDOUT) Output Low Voltage (V ) 0.4 V max Load Circuit as in Figure 2. OL Output High Voltage (V ) 4.0 V min OH POWER REQUIREMENTS V Range 4.75/5.25 V min/V max Part Functions from 3.3 V to 5.25 V DD 2 Power Supply Rejection ΔGain/ΔV –75 dB typ DD I 10 μA max V = V , V = 0 V DD INH DD INL At Input Levels of 0.8 V and 2.4 V, I is DD Typically 2 mA. NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Not production tested. Guaranteed by characterization at initial product release. Specifications subject to change without notice. REV. B –2– AD7564 (V = +3 V to +5.5 V; V = V = 1.23 V; AGND = 0 V; V = 0 V to 2.45 V; T = T to DD IOUT1 IOUT2 REF A MIN 1 T , unless otherwise noted) Biased Mode MAX 2 Parameter A Grade Units Test Conditions/Comments ACCURACY 12 Resolution 12 Bits 1 LSB = (V – V )/2 = 300 μV when IOUT2 REF V = 1.23 V and V = 0 V IOUT2 REF Relative Accuracy ±1 LSB max Differential Nonlinearity ±0.9 LSB max All Grades Guaranteed Monotonic Over Temperature Gain Error +25°C ±4 LSBs max T to T ±5 LSBs max MIN MAX 3 Gain Temperature Coefficient 2 ppm FSR/°C typ 5 ppm FSR/°C max Output Leakage Current See Terminology Section I OUT1 @ +25°C 10 nA max T to T 50 nA max MIN MAX Input Resistance @ I Pins 6 kΩ min This Varies with DAC Input Code OUT2 DIGITAL INPUTS V , Input High Voltage @ V = +5 V 2.4 V min INH DD V , Input High Voltage @ V = +3.3 V 2.1 V min INH DD V , Input Low Voltage @ V = +5 V 0.8 V max INL DD V , Input Low Voltage @ V = +3.3 V 0.6 V max INL DD I , Input Current ±1 μA max INH 3 C , Input Capacitance 10 pF max IN DIGITAL OUTPUT (SDOUT) Load Circuit as in Figure 2. Output Low Voltage (V ) 0.4 V max V = +5 V OL DD Output Low Voltage (V ) 0.2 V max V = +3.3 V OL DD Output High Voltage (V ) 4.0 V min V = +5 V OH DD Output High Voltage (V)V – 0.2 V min V = +3.3 V OH DD DD POWER REQUIREMENTS V Range 3/5.5 V min/V max DD 3 Power Supply Sensitivity ΔGain/ΔV –75 dB typ DD I 10 μA max V = V – 0.1 V min, V = 0.1 V max; DD INH DD INL SDOUT Open Circuit I is typically 2 mA with V = +5 V, DD DD V = 2.4 V min, V = 0.8 V max; INH INL SDOUT Open Circuit NOTES 1 These specifications apply with the devices biased up at 1.23 V for single supply applications. The model numbering reflects this by means of a "-B" suffix (for example: AD7564AR-B). Figure 19 is an example of Biased Mode Operation. 2 Temperature ranges is as follows: A Version: –40°C to +85°C. 3 Not production tested. Guaranteed by characterization at initial product release. Specifications subject to change without notice. REV. B –3– AD7564 AC Performance Characteristics (V = +4.75 V to +5.25 V; V = V = AGND = 0 V. V = 6 V rms, 1 kHz sine wave; DAC output op amp is DD IOUT1 IOUT2 REF AD843; T = T to T , unless otherwise noted. These characteristics are included for Design Guidance and are A MIN MAX Normal Mode not subject to test.) Parameter B Grade Units Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 550 ns typ To 0.01% of Full-Scale Range. DAC Latch Alternately Loaded with All 0s and All 1s Digital-to-Analog Glitch Impulse 35 nV-s typ Measured with V = 0 V. DAC Register Alternately Loaded REF with All 0s and All 1s Multiplying Feedthrough Error –70 dB max V = 20 V p-p, 10 kHz Sine Wave. DAC Latch Loaded REF with All 0s Output Capacitance 60 pF max All 1s Loaded to DAC 30 pF max All 0s Loaded to DAC Channel-to-Channel Isolation –76 dB typ Feedthrough from Any One Reference to the Others with 20 V p-p, 10 kHz Sine Wave Applied Digital Crosstalk 5 nV-s typ Effect of All 0s to All 1s Code Transition on Nonselected DACs Digital Feedthrough 5 nV-s typ Feedthrough to Any DAC Output with FSIN High and Square Wave Applied to SDIN and SCLK Total Harmonic Distortion –83 dB typ V = 6 V rms, 1 kHz Sine Wave REF Output Noise Spectral Density @ 1 kHz 30 nV/√Hz typ All 1s Loaded to the DAC. V = 0 V. Output Op Amp Is REF ADOP07 AC Performance Characteristics (V = +3 V to +5.5 V; V = V = 1.23 V; AGND = 0 V. V = 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC DD IOUT1 IOUT2 REF output op amp is AD820; T = T to T , unless otherwise noted. These characteristics are included for Design A MIN MAX Biased Mode Guidance and are not subject to test.) Parameter A Grade Units Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 3.5 μs typ To 0.01% of Full-Scale Range. V = 0 V. DAC Latch Alter- REF nately Loaded with all 0s and all 1s. Digital to Analog Glitch Impulse 35 nV-s typ Measured with V = 0 V and V = 0 V. DAC Register Alter- IOUT2 REF nately Loaded with all 0s and all 1s. Multiplying Feedthrough Error –70 dB max DAC Latch Loaded with all 0s. Output Capacitance 100 pF max All 1s Loaded to DAC 40 pF max All 0s Loaded to DAC Digital Feedthrough 5 nV-s typ Feedthrough to Any DAC Output with FSIN HIGH and a Square Wave Applied to SDIN and CLKIN Total Harmonic Distortion –76 dB typ Output Noise Spectral Density @ 1 kHz 20 nV/√Hz typ All 1s Loaded to DAC. V = 0 V; V = 0 V IOUT2 REF –4– REV. B AD7564 1 Timing Specifications (T = T to T unless otherwise noted) A MIN MAX Limit at Limit at Parameter V = +3 V to +3.6 V V = +4.75 V to +5.25 V Units Description DD DD t 180 100 ns min CLKIN Cycle Time 1 t 80 40 ns min CLKIN High Time 2 t 80 40 ns min CLKIN Low Time 3 t 50 30 ns min FSIN Setup Time 4 t 50 30 ns min Data Setup Time 5 3 t 10 5 ns min Data Hold Time 6 t 125 90 ns min FSIN Hold Time 7 2 t 100 70 ns max SDOUT Valid After CLKIN Falling Edge 8 t 80 40 ns min LDAC, CLR Pulse Width 9 NOTES 1 Not production tested. Guaranteed by characterization at initial product release. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed DD from a voltage level of 1.6 V for a V of 5 V and from a voltage level 1.35 V for a V of 3.3 V. DD DD 2 t is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with a V of 5 V and 0.6 V or 2.1 V for a V 8 DD DD of 3.3 V. t1 CLKIN(I) t 3 t t 2 7 t 4 FSIN(I) t 5 t 6 DB15 DB0 SDIN(I) t 8 DB0 SDOUT(O) DB15 t 9 LDAC, CLR Figure 1. Timing Diagram I 1.6mA OL TO OUTPUT PIN +1.6V C L 50pF I 200µA OH Figure 2. Load Circuit for Digital Output Timing Specifications REV. B –5– AD7564 1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (T = +25°C unless otherwise noted) A DIP, SOIC and SSOP Packages V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V DD I to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V OUT1 DD DGND 1 28 I B I to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V OUT2 OUT2 DD I C 2 27 AGND AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V OUT2 DD Digital Input Voltage to DGND . . . . . . –0.3 V to V + 0.3 V V 3 26 NC DD DD V , V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .±15 V I C 4 25 I B RFB REF OUT1 OUT1 2 Input Current to Any Pin Except Supplies . . . . . . . . ±10 mA R C 5 24 R B FB FB Operating Temperature Range V C 6 23 V B REF REF Commercial Plastic (A, B Versions). . . . . . –40°C to +85°C AD7564 I D 7 22 I A OUT2 OUT2 TOP VIEW Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C I D821 I A OUT1 (Not to Scale) OUT1 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C R D920 R A FB FB DIP Package, Power Dissipation . . . . . . . . . . . . . . . . . 875 mW V D 10 19 V A REF REF θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 75°C/W JA SDOUT 11 11 18 A0 Lead Temperature, Soldering (10 sec) . . . . . . . . . . 260°C CLR 12 17 A1 SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 875 mW LDAC 13 16 O CLKIN θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 75°C/W JA Lead Temperature, Soldering (10 sec) . . . . . . . . . . 260°C FSIN 14 15 SDIN Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C NC = NO CONNECT Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220°C SSOP Package, Power Dissipation . . . . . . . . . . . . . . . . 900 mW θ Thermal Impedance . . . . . . . . . . . . . . . . . . . 100°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. WARNING! Although the AD7564 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –6– REV. B AD7564 PIN DESCRIPTIONS Pin Number Mnemonic Description 1 DGND Digital Ground. 2 IOUT2C IOUT2 terminal for DAC C. This should normally connect to the signal ground of the system. 3 VDD Positive power supply. This is +5 V ± 5%. 4 I C I terminal for DAC C. OUT1 OUT1 5 R C Feedback resistor for DAC C. FB 6 V C DAC C reference input. REF 7 IOUT2D IOUT2 terminal for DAC D. This should normally connect to the signal ground of the system. 8 IOUT1D IOUT1 terminal for DAC D. 9 RFBD Feedback resistor for DAC D. 10 V D DAC D reference input. REF 11 SDOUT This shift register output allows multiple devices to be connected in a daisy chain configuration. 12 CLR Asynchronous CLR input. When this input is taken low, all DAC latches are loaded with all 0s. 13 LDAC Asynchronous LDAC input. When this input is taken low, all DAC latches are simultaneously updated with the contents of the input latches. 14 FSIN Level-triggered control input (active low). This is the frame synchronization signal for the input data. When FSIN goes low, it enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address bits are valid, the 12-bit DAC data is transferred to the appropriate input latch on the sixteenth falling edge after FSIN goes low. 15 SDIN Serial data input. The device accepts a 16-bit word. DB0 and DB1 are DAC select bits. DB2 and DB3 are device address bits. DB4 to DB15 contain the 12-bit data to be loaded to the selected DAC. 16 CLKIN Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on the clock line to avoid timing issues. 17 A1 Device address pin. This input in association with A0 gives the device an address. If DB2 and DB3 of the serial input stream do not correspond to this address, the data which follows is ignored and not loaded to any input latch. However, it will appear at SDOUT irrespective of this. 18 A0 Device address pin. This input in association with A1 gives the device an address. 19 V A DAC A reference input. REF 20 R A Feedback resistor for DAC A. FB 21 IOUT1A IOUT1 terminal for DAC A. 22 IOUT2A IOUT2 terminal for DAC A. This should normally connect to the signal ground of the system. 23 VREFB DAC B reference input. 24 R B Feedback resistor for DAC B. FB 25 I B I terminal for DAC B. OUT1 OUT1 26 N/C No Connect pin. 27 AGND This pin connects to the back gates of the current steering switches. It should be connected to the signal ground of the system. 28 IOUT2B IOUT2 terminal for DAC B. This should normally connect to the signal ground of the system. REV. B –7– AD7564 Output Voltage Settling Time TERMINOLOGY This is the amount of time it takes for the output to settle to a Relative Accuracy specified level for a full-scale input change. For the AD7564, it Relative accuracy or endpoint linearity is a measure of the is specified with the AD843 as the output op amp. maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after ad- Digital to Analog Glitch Impulse justing for zero error and full-scale error and is normally ex- This is the amount of charge injected into the analog output pressed in Least Significant Bits or as a percentage of full-scale when the inputs change state. It is normally specified as the reading. area of the glitch in either pA-secs or nV-secs, depending upon whether the glitch is measured as a current or voltage signal. It Differential Nonlinearity is measured with the reference input connected to AGND and Differential nonlinearity is the difference between the measured the digital inputs toggled between all 1s and all 0s. change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum AC Feedthrough Error ensures monotonicity. This is the error due to capacitive feedthrough from the DAC reference input to the DAC I terminal, when all 0s are Gain Error OUT loaded in the DAC. Gain error is a measure of the output error between an ideal DAC and the actual device output. It is measured with all 1s Channel-to-Channel Isolation in the DAC after offset error has been adjusted out and is ex- Channel-to-channel isolation refers to the proportion of input pressed in Least Significant Bits. Gain error is adjustable to signal from one DAC’s reference input which appears at the zero with an external potentiometer. output of any other DAC in the device and is expressed in dBs. Output Leakage Current Digital Crosstalk Output leakage current is current which flows in the DAC The glitch impulse transferred to the output of one converter ladder switches when these are turned off. For the I OUT1 due to a change in digital input code to the other converter is terminal, it can be measured by loading all 0s to the DAC and defined as the Digital Crosstalk and is specified in nV-secs. be measured by loading all 0s to the DAC and measuring the I OUT1 Digital Feedthrough current. Minimum current will flow in the I line when the OUT2 When the device is not selected, high frequency logic activity on DAC is loaded with all 1s. This is a combination of the switch the device digital inputs is capacitively coupled through the de- leakage current and the ladder termination resistor current. vice to show up at on the I pin and subsequently on the op OUT The I leakage current is typically equal to that in I . OUT2 OUT1 amp output. This noise is digital feedthrough. Output Capacitance This is the capacitance from the I pin to AGND. OUT1 Table I. AD7564 Loading Sequence DB15 DB0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A1 A0 DS1 DS0 Table II. DAC Selection DS1 DS0 Function 0 0 DAC A Selected 0 1 DAC B Selected 1 0 DAC C Selected 1 1 DAC D Selected –8– REV. B Typical Performance Curves–AD7564 0.5 0.5 NORMAL MODE OF OPERATION NORMAL MODE OF OPERATION V = +5V V = +5V DD DD T = +25°C T = +25°C A A 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0.0 0.0 2 4 6 8 10 2 4 6 8 10 V – Volts V – Volts REF REF Figure 3. Differential Nonlinearity Error vs. V Figure 6. Integral Nonlinearity Error vs. V REF REF (Normal Mode) (Normal Mode) 0 0 V B = 0V V C = 20V p-p SINE WAVE REF REF –10 –10 ALL OTHER REFERENCE INPUTS = 20V p-p SINE WAVE ALL OTHER REFERENCE INPUTS = 0V DAC B LOADED WITH ALL 0s DAC C LOADED WITH ALL 1s ALL OTHER DACs LOADED WITH ALL 1s ALL OTHER DACs LOADED WITH ALL 0s –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 3 4 5 6 3 4 5 6 10 10 10 10 10 10 10 10 FREQUENCY – Hz FREQUENCY – Hz Figure 4. Channel-to-Channel Isolation (1 DAC to 1 DAC) Figure 7. Channel-to-Channel Isolation (1 DAC to All Other DACs) 0 –50 NORMAL MODE OF OPERATION V = +5V DD –10 V = +5V DD T = +25°C A DAC LOADED WITH ALL 1s V = +6V rms IN V = 20V p-p –20 IN –60 OP AMP = AD713 OP AMP = AD711 T = +25°C A –30 –40 –70 –50 DAC LOADED WITH ALL 0s –60 –80 –70 –80 –90 –90 –100 –100 1k 10k 100k 1M 10M 2 3 4 5 10 10 10 10 FREQUENCY – Hz FREQUENCY – Hz Figure 5. Total Harmonic Distortion vs. Frequency Figure 8. Multiplying Frequency Response vs. Digital (Normal Mode) Code (Normal Mode) REV. B –9– THD – dBs V B/V C – dBs OUT OUT DNL – LSBs V B/V C – dBs INL – LSBs OUT OUT GAIN – dB AD7564 2.0 2.0 V = +3.3V V = +3.3V 1.8 DD 1.8 DD T = +25°C T = +25°C A A OP AMP = AD820 OP AMP = AD820 1.6 1.6 V = +1.23V (AD589) V = +1.23V (AD589) REF REF 1.4 1.4 1.2 1.2 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0.2 0.4 0.6 0.8 1.0 1.2 1.4 |V – V | – Volts |V – V | – Volts REF BIAS REF BIAS Figure 9. Integral Nonlinearity Error vs. V Figure 12. Differential Nonlinearity Error vs. V REF REF (Biased Mode) (Biased Mode) 2.0 2.0 V = +5V V = +5V 1.8 DD 1.8 DD T = +25°C T = +25°C A A OP AMP = AD820 OP AMP = AD820 1.6 1.6 V = +1.23V (AD589) V = +1.23V (AD589) BIAS BIAS 1.4 1.4 1.2 1.2 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0.2 0.4 0.6 0.8 1.0 1.2 1.4 |V – V | – Volts |V – V | – Volts REF BIAS REF BIAS Figure 13. Differential Nonlinearity Error vs. V Figure 10. Integral Nonlinearity Error vs. V REF REF (Biased Mode) (Biased Mode) 0.4 0.2 NORMAL MODE V = +5V DD T = +25°C A 0.1 0.3 V = 10V REF 0.0 0.2 –0.1 –0.2 0.1 –0.3 V = +3.3V DD 0.0 T = +25°C A –0.4 V = 1.23V BIAS V = 0V REF –0.1 –0.5 0 1024 2048 3072 4095 0 1024 2048 3072 4095 CODE – LSBs CODE – LSBs Figure 14. All Codes Linearity Plot (Normal Mode) Figure 11. All Codes Linearity Plot (Biased Mode) –10– REV. B LINEARITY ERROR – LSBs INL – LSBs INL – LSBs LINEARITY ERROR – LSBs DNL – LSBs DNL – LSBs AD7564 GENERAL DESCRIPTION Bringing the CLR line low resets the DAC latches to all 0s. The D/A Section input latches are not affected so that the user can revert to the The AD7564 contains four 12-bit current output D/A convert- previous analog output if desired. ers. A simplified circuit diagram for one of the D/A converters CLKIN is shown in Figure 15. 16-BIT INPUT FSIN SHIFT REGISTER VREF SDOUT R R SDIN R Figure 16. Input Logic 2R 2R 2R 2R 2R 2R 2R 3 UNIPOLAR BINARY OPERATION CB A S9 S8 S0 R/2 R FB (2-Quadrant Multiplication) I Figure 17 shows the standard unipolar binary connection dia- OUT1 I OUT2 gram for one of the DACs in the AD7564. When V is an ac IN SHOWN FOR ALL 1s ON DAC signal, the circuit performs 2-quadrant multiplication. Resistors R1 and R2 allow the user to adjust the DAC gain error. Offset Figure 15. Simplified D/A Circuit Diagram can be removed by adjusting the output amplifier offset voltage. A segmented scheme is used whereby the 2 MSBs of the 12-bit R2 10Ω R A data word are decoded to drive the three switches A, B and C. FB C1 R1 20Ω The remaining 10 bits of the data word drive the switches S0 to I A OUT1 S9 in a standard R-2R ladder configuration. V A1 V IN DAC A I A OUT OUT2 V A Each of the switches A to C steers 1/4 of the total reference REF AD7564 A1: AD707 current with the remaining current passing through the R-2R AD711 SIGNAL section. AD843 GND AD845 NOTES All DACs have separate V , I , I and R pins. REF OUT1 OUT2 FB 1. ONLY ONE DAC IS SHOWN FOR CLARITY. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. When an output amplifier is connected in the standard configu- 3. C1 PHASE COMPENSATION (5–15pF) MAY BE ration of Figure 17, the output voltage is given by: REQUIRED WHEN USING HIGH SPEED AMPLIFIER. Figure 17. Unipolar Binary Operation V = D ×V OUT REF A1 should be chosen to suit the application. For example, the where D is the fractional representation of the digital word AD707 is ideal for very low bandwidth applications while the loaded to the DAC. Thus, in the AD7564, D can be set from 0 AD843 and AD845 offer very fast settling time in wide band- to 4095/4096. width applications. Appropriate multiple versions of these am- Interface Section plifiers can be used with the AD7564 to reduce board space The AD7564 is a serial input device. Three input signals con- requirements. trol the serial interface. These are FSIN, CLKIN and SDIN. The code table for Figure 17 is shown in Table III. The timing diagram is shown in Figure 1. Data applied to the SDIN pin is clocked into the input shift reg- Table III. Unipolar Binary Code Table ister on each falling edge of CLKIN. SDOUT is the shift regis- ter output. It allows multiple devices to be connected in a daisy Digital Input Analog Output chain fashion with the SDOUT pin of one device connected to MSB . . . LSB (V as Shown in Figure 17) OUT the SDIN of the next device. FSIN is the frame synchronization 1111 1111 1111 –V (4095/4096) for the device. REF 1000 0000 0001 –V (2049/4096) REF When the sixteen bits have been received in the input shift regis- 1000 0000 0000 –V (2048/4096) REF ter, DB2 and DB3 (A0 and A1) are checked to see if they corre- 0111 1111 1111 –V (2047/4096) REF spond to the state on pins A0 and A1. If it does, then the word 0000 0000 0001 –V (1/4096) REF is accepted. Otherwise, it is disregarded. This allows the user 0000 0000 0000 –V (0/4096) = 0 REF to address a number of AD7564s in a very simple fashion. DB1 and DB0 of the 16-bit word determine which of the four DAC NOTE Nominal LSB size for the circuit of Figure 17 is given by: V (1/4096). input latches is to be loaded. When the LDAC line goes low, all REF four DAC latches in the device are simultaneously loaded with the contents of their respective input latches and the outputs change accordingly. REV. B –11– AD7564 BIPOLAR OPERATION In the current mode circuit of Figure 19, I and hence I , OUT2 OUT1 4-Quadrant Multiplication) is biased positive by an amount V . For the circuit to operate BIAS Figure 18 shows the standard connection diagram for bipolar correctly, the DAC ladder termination resistor must be con- operation of any one of the DACs in the AD7564. The coding nected internally to I . This is the case with the AD7564. OUT2 is offset binary as shown in Table IV. When V is an ac signal, IN The output voltage is given by: the circuit performs 4-quadrant multiplication. To maintain the gain error specifications, resistors R3, R4 and R5 should be  R  FB V = D × × (V ±V ) +V   OUT BIAS IN BIAS ratio matched to 0.01%. R  DAC  R4 20kΩ As D varies from 0 to 4095/4096, the output voltage varies 20kΩ R2 10Ω R5 from V = V to V = 2 V – V . V should be a OUT BIAS OUT BIAS IN BIAS R A FB low impedance source capable of sinking and sourcing all pos- C1 R1 20Ω I A R4 20Ω OUT1 sible variations in current at the I terminal without any OUT2 V IN A1 problems. DAC A I A OUT2 R3 V A REF 10kΩ Voltage Mode Circuit A2 AD7564 Figure 20 shows DAC A of the AD7564 operating in the SIGNAL V OUT GND voltage-switching mode. The reference voltage, V is applied NOTES: IN 1. ONLY ONE DAC IS SHOWN FOR CLARITY. to the I pin, I is connected to AGND and the output OUT1 OUT2 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. voltage is available at the V terminal. In this configuration, a 3. C1 PHASE COMPENSATION (5–15pF) MAY BE REF REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1. positive reference voltage results in a positive output voltage; making single supply operation possible. The output from the Figure 18. Bipolar Operation (4-Quadrant Multiplication) DAC is a voltage at a constant impedance (the DAC ladder re- sistance). Thus, an op amp is necessary to buffer the output Table IV. Bipolar (Offset Binary) Code Table voltage. The reference voltage input no longer sees a constant Digital Input Analog Output input impedance, but one which varies with code. So, the volt- MSB . . . LSB (V as Shown in Figure 18) age input should be driven from a low impedance source. OUT It is important to note that V is limited to low voltages be- IN 1111 1111 1111 –V (2047/2048) REF cause the switches in the DAC no longer have the same source- 1000 0000 0001 –V (1/2048) REF drain voltage. As a result, their on-resistance differs and this 1000 0000 0000 –V (0/2048 = 0) REF degrades the integral linearity of the DAC. Also, V must not IN 0111 1111 1111 –V (1/2048) REF go negative by more than 0.3 volts or an internal diode will turn 0000 0000 0001 –V (2047/2048) REF on, causing possible damage to the device. This means that the 0000 0000 0000 –V (2048/2048) = –V REF REF full-range multiplying capability of the DAC is lost. NOTE R1 R2 Nominal LSB size for the circuit of Figure 18 is given by: V (1/2048). REF R A FB SINGLE SUPPLY APPLICATIONS I A OUT1 The “–B” versions of the AD7564 are specified and tested for V IN A1 V OUT DAC A I A single supply applications. Figure 19 shows a typical circuit for OUT2 V A REF operation with a single +3.3 V to +5 V supply. AD7564 R A FB NOTES I A OUT1 1. ONLY ONE DAC IS SHOWN FOR CLARITY. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. V A1 V IN DAC A OUT 3. C1 PHASE COMPENSATION (5–15pF) MAY BE V A REF REQUIRED WHEN USING HIGH SPEED AMPLIFIER. I A OUT2 AD7564 Figure 20. Single Supply Voltage Switching Mode Operation V BIAS NOTES: 1. ONLY ONE DAC IS SHOWN FOR CLARITY. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C1 PHASE COMPENSATION (5–15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1. Figure 19. Single Supply Current Mode Operation –12– REV. B AD7564 MICROPROCESSOR INTERFACING AD7564 to 68HC11 Interface AD7564 to 80C51 Interface Figure 22 shows a serial interface between the AD7564 and the A serial interface between the AD7564 and the 80C51 micro- 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of controller is shown in Figure 21. TXD of the 80C51 drives the AD7564 while the MOSI output drives the serial data line of SCLK of the AD7564 while RXD drives the serial data line of the AD7564. The FSIN signal is derived from a port line the part. The FSIN signal is derived from the port line P3.3. (PC7 shown). The 80C51 provides the LSB of its SBUF register as the first bit For correct operation of this interface, the 68HC11 should be in the serial data stream. Therefore, the user will have to ensure configured such that its CPOL bit is a 0 and its CPHA bit is a 1. that the data in the SBUF register is arranged correctly so that When data is to be transmitted to the part, PC7 is taken low. the data word transmitted to the AD7564 corresponds to the When the 68HC11 is configured like this, data on MOSI is valid 3 loading sequence shown in Table I. When data is to be trans- on the falling edge of SCK. The 68HC11 transmits its serial mitted to the part, P3.3 is taken low. Data on RXD is valid on data in 8-bit bytes (MSB first), with only eight falling clock the falling edge of TXD. The 80C51 transmits its serial data in edges occurring in the transmit cycle. To load data to the 8-bit bytes with only eight falling clock edges occurring in the AD7564 , PC7 is left low after the first eight bits are transferred transmit cycle. To load data to the AD7564, P3.3 is left low and a second byte of data is then transferred serially to the after the first eight bits are transferred and a second byte of data AD7564. When the second serial transfer is complete, the PC7 is then transferred serially to the AD7564. When the second line is taken high. serial transfer is complete, the P3.3 line is taken high. Note that the 80C51 outputs the serial data byte in a format which has the LSB first. The AD7564 expects the MSB first. The 80C51 AD7564* transmit routine should take this into account. 64HC11* PC5 CLR PC6 LDAC AD7564* 80C51* PC7 FSIN SCLK SCK P3.5 CLR MOSI SDIN P3.4 LDAC P3.3 FSIN TXD SCLK *ADDITIONAL PINS OMMITTED FOR CLARITY SDIN RXD Figure 22. AD7564 to 64HC11 Interface In Figure 22, LDAC and CLR are controlled by the PC6 *ADDITIONAL PINS OMMITTED FOR CLARITY and PC5 port outputs. As with the 80C51, each DAC of the AD7564 can be updated after each two-byte transfer, or else Figure 21. AD7564 to 80C51 Interface all DACs can be simultaneously updated. This interface LDAC and CLR on the AD7564 are also controlled by 80C51 is suitable for both 3 V and 5 V versions of the 68HC11 port outputs. The user can bring LDAC low after every two microcontroller. bytes have been transmitted to update the DAC which has been programmed. Alternatively, it is possible to wait until all the in- put registers have been loaded (sixteen byte transmits) and then update the DAC outputs. REV. B –13– AD7564 AD7564 to ADSP-2101/ADSP-2103 Interface Figure 23 shows a serial interface between the AD7564 and the AD7564* ADSP-2101/ADSP-2103 digital signal processors. The ADSP- TMS320C25* +5V 2101 operates from 5 V while the ADSP-2103 operates from 3 V supplies. These processors are set up to operate in the CLR SPORT Transmit Alternate Framing Mode. XF LDAC The following DSP conditions are recommended: Internal SCLK; Active low Framing Signal; 16-bit word length. Trans- FSX FSIN mission is initiated by writing a word to the TX register after the SDIN DX SPORT has been enabled. The data is then clocked out on ev- CLKX CLKIN ery rising edge of SCLK after TFS goes low. TFS stays low un- til the next data transfer. CLOCK GENERATION *ADDITIONAL PINS OMMITTED FOR CLARITY AD7564* ADSP-2101/ +5V Figure 24. AD7564 to TMS320C25 Interface ADSP-2103 APPLICATION HINTS CLR Output Offset FO LDAC CMOS D/A converters in circuits such as Figures 17, 18 and 19 TFS FSIN exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the ampli- SDIN DT fier. The maximum amplitude of this error, which adds to the SCLK CLKIN D/A converter nonlinearity, depends on V , where V is the OS OS amplifier input offset voltage. For the AD7564 to maintain specified accuracy with V at 10 V, it is recommended that REF *ADDITIONAL PINS OMMITTED FOR CLARITY –6 V be no greater than 500 μV, or (50 × 10 ) × (V ), over OS REF Figure 23. AD7564 to ADSP-2101/ADSP-2103 Interface the temperature range of operation. Suitable amplifiers include the ADOP-07, ADOP-27, AD711, AD845 or multiple versions AD7564 to TMS320C25 Interface of these. Figure 24 shows an interface circuit for the TMS320C25 digital signal processor. The data on the DX pin is clocked out of Temperature Coefficients the processor’s Transmit Shift Register by the CLKX signal. The gain temperature coefficient of the AD7564 has a maxi- Sixteen-bit transmit format should be chosen by setting the FO mum value of 5 ppm/°C and a typical value of 2 ppm/°C. This bit in the ST1 register to 0. The transmit operation begins corresponds to gain shifts of 2 LSBs and 0.8 LSBs respectively when data is written into the data transmit register of the over a 100°C temperature range. When trim resistors R1 and TMS320C25. This data will be transmitted when the FSX line R2 are used to adjust full scale in Figures 17 and 18, their tem- goes low while CLKX is high or going high. The data, starting perature coefficients should be taken into account. For further with the MSB, is then shifted out to the DX pin on the rising information see “Gain Error and Gain Temperature Coefficient edge of CLKX. When all bits have been transmitted, the user of CMOS Multiplying DACs,” Application Note, Publication can update the DAC outputs by bringing the XF output flag Number E630c-5-3/86, available from Analog Devices. low. High Frequency Considerations The output capacitances of the AD7564 DACs work in con- junction with the amplifier feedback resistance to add a pole to the open loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compensation ca- pacitor in parallel with the feedback resistor. This is shown as C1 in Figures 17 and 18. –14– REV. B AD7564 APPLICATIONS In the circuit of Figure 25: Programmable State Variable Filter C1 = C2, R7 = R8, R3 = R4 (i.e., the same code is loaded to The AD7564 with its multiplying capability and fast settling each DAC). time is ideal for many types of signal conditioning applications. Resonant Frequency, f = 1/(2 π R3C1) O The circuit of Figure 25 shows its use in a state variable filter design. This type of filter has three outputs: low pass, high pass Quality Factor, Q = (R6/R8) × (R2/R5) and bandpass. The particular version shown in Figure 25 uses Bandpass Gain, A = –R2/R1 O the AD7564 to control the critical parameters f , Q and A . In- O O Using the values shown in Figure 25, the Q range is 0.3 to 5 and stead of several fixed resistors, the circuit uses the DAC equiva- the f range is 0 to 12 kHz. lent resistances as circuit elements. O 3 Thus, R1 in Figure 25 is controlled by the 12-bit digital word loaded to DAC A of the AD7564. This is also the case with R2, R3 and R4. The fixed resistor R5 is the feedback resistor, R B. FB DAC Equivalent Resistance, R = (R × 4096)/N EQ LADDER where: R is the DAC ladder resistance LADDER N is the DAC Digital Code in Decimal (0 < N < 4096) C3 10pF R7 C1 1000pF C2 1000pF 30kΩ R8 30kΩ A2 HIGH A3 A4 LOW R6 PASS PASS 10kΩ OUTPUT OUTPUT A1 BAND IAI BRBV V B CI CVDI D PASS OUT1 OUT1 FB REF REF OUT1 REF OUT1 OUTPUT R5 DAC A DAC B DAC C DAC D V IN (R1) (R2) (R3) (R4) V A REF AD7564 IAIBI AGND CI D OUT2 OUT2 OUT2 OUT2 NOTES 1. A1, A2, A3, A4, : 1/4 X AD713. 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. 3. C3 IS A COMPENSATION CAPACITOR TO ELIMINATE Q AND GAIN VARIATIONS CAUSED BY AMPLIFIER GAIN AND BANDWIDTH LIMITATIONS. Figure 25. Programmable 2nd Order State Variable Filter REV. B –15– AD7564 OUTLINE DIMENSIONS 1.565 (39.75) 1.380 (35.05) 28 15 0.580 (14.73) 0.485 (12.31) 114 0.625 (15.88) 0.600 (15.24) 0.100 (2.54) BSC 0.195 (4.95) 0.250 (6.35) 0.015 (0.38) 0.125 (3.17) MAX GAUGE PLANE 0.015 (0.38) 0.200 (5.08) MIN 0.115 (2.92) 0.015 (0.38) SEATING PLANE 0.008 (0.20) 0.700 (17.78) 0.022 (0.56) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.070 (1.78) 0.050 (1.27) COMPLIANT TO JEDEC STANDARDS MS-011 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS. Figure 26. 28-Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-28-2) Dimensions shown in inches and (millimeters) 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 14 10.00 (0.3937) 45° 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 1.27 (0.0500) 0.51 (0.0201) 1.27 (0.0500) 0.33 (0.0130) PLANE BSC 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 27. 28-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-28) Dimensions shown in millimeters and (inches) –16– REV. B 0.75 (0.0295) 0.25 (0.0098) 06-07-2006-A 071006-A AD7564 10.50 10.20 9.90 28 15 5.60 5.30 8.20 5.00 7.80 1 7.40 14 0.25 1.85 0.09 2.00 MAX 1.75 1.65 8° 0.95 0.38 0.05 MIN SEATING 4° 0.75 0.22 PLANE COPLANARITY 0° 0.65 BSC 0.55 0.10 COMPLIANT TO JEDEC STANDARDS MO-150-AH Figure 28. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD7564AR-B −40°C to +85°C 28-Lead SOIC_W RW-28 AD7564ARS-B −40°C to +85°C 28-Lead SSOP RS-28 AD7564ARS-BREEL −40°C to +85°C 28-Lead SSOP RS-28 AD7564ARSZ-B −40°C to +85°C 28-Lead SSOP RS-28 AD7564ARSZ-BREEL −40°C to +85°C 28-Lead SSOP RS-28 AD7564ARZ-B −40°C to +85°C 28-Lead SOIC_W RW-28 AD7564ARZ-BREEL −40°C to +85°C 28-Lead SOIC_W RW-28 AD7564BN −40°C to +85°C 28-Lead PDIP N-28-2 AD7564BNZ −40°C to +85°C 28-Lead PDIP N-28-2 AD7564BR −40°C to +85°C 28-Lead SOIC_W RW-28 AD7564BR-REEL −40°C to +85°C 28-Lead SOIC_W RW-28 AD7564BRS −40°C to +85°C 28-Lead SSOP RS-28 AD7564BRS-REEL −40°C to +85°C 28-Lead SSOP RS-28 AD7564BRSZ −40°C to +85°C 28-Lead SSOP RS-28 AD7564BRSZ-REEL −40°C to +85°C 28-Lead SSOP RS-28 AD7564BRZ −40°C to +85°C 28-Lead SOIC_W RW-28 AD7564BRZ-REEL −40°C to +85°C 28-Lead SOIC_W RW-28 REVISION HISTORY 2/12—Rev. A to Rev. B Changes to Pin 16 Description ....................................................... 7 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10540-0-2/12(B) REV. B –17– 060106-A