ANALOG DEVICES AD7538

2 LC MOS Microprocessor-Compatible 14-Bit DAC AD7538 FEATURES FUNCTIONAL BLOCK DIAGRAM V DD All grades 14-bit monotonic over the full temperature range 23 Low cost, 14-bit upgrade for 12-bit systems AD7538 2 R FB 14-bit parallel load with double buffered inputs 1 14-BIT DAC V 3 Small 24-pin, 0.30” DIP and SOIC REF I OUT Low output leakage (<20 nA) over the full temperature range 4 AGND APPLICATIONS DAC REGISTER 20 LDAC Microprocessor-based control systems Digital audio 21 CS INPUT REGISTER Precision servo control 22 WR 14 Control and measurement in high temperature environments 619 5 24 DB13 TO DB0 DGND V SS Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7538 is a 14-bit monolithic CMOS digital-to-analog 1. Guaranteed Monotonicity. converter (DAC) that uses laser trimmed thin-film resistors to The AD7538 is guaranteed monotonic to 14-bits over the achieve excellent linearity. full temperature range for all grades. 2. Low Cost. The DAC is loaded by a single 14-bit wide word using standard The AD7538, with its 14-bit dynamic range, affords a low chip select and memory write logic. Double buffering, which is cost solution for 12-bit system upgrades. optional using LDAC, allows simultaneous updates in a system 3. Small Package Size. containing multiple AD7538s. The AD7538 is packaged in a small 24-pin, 0.3" DIP and a A novel low leakage configuration enables the AD7538 to 24-pin SOIC. exhibit excellent output leakage current characteristics over 4. Low Output Leakage. the specified temperature range. By tying V (Pin 24) to a negative voltage, it is possible to SS The AD7538 is manufactured using the linear-compatible achieve a low output leakage current at high temperatures. 2 5. Wide Power Supply Tolerance. CMOS (LC MOS) process. It is speed compatible with most The device operates on a +12 V to +15 V VDD, with a ±5% microprocessors and accepts TTL or CMOS logic level inputs. tolerance on this nominal figure. All specifications are guaranteed over this range. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 01139-001 AD7538 TABLE OF CONTENTS Features .............................................................................................. 1 Equivalent Circuit Analysis ...................................................... 10 Applications ....................................................................................... 1 Digital Section ............................................................................ 10 Functional Block Diagram .............................................................. 1 Unipolar Binary Operation (2-Quadrant Multiplication) .... 10 General Description ......................................................................... 1 Bipolar Operation (4-Quadrant Multiplication) .................... 11 Product Highlights ........................................................................... 1 Low Leakage Configuration ...................................................... 11 Revision History ............................................................................... 2 Programmable Gain Amplifier ................................................. 12 Specif ica t ions ..................................................................................... 3 Application Hints ........................................................................... 13 AC Performance Characteristics ................................................ 4 Output Offset .............................................................................. 13 Timing Characteristics ................................................................ 4 General Ground Management .................................................. 13 Timing Diagram ........................................................................... 5 Microprocessor Interfacing ....................................................... 13 Absolute Maximum Ratings ............................................................ 6 AD7538-to-8086 Interface ........................................................ 13 ESD Caution .................................................................................. 6 AD7538-to-MC68000 Interface ............................................... 13 Pin Configuration and Function Descriptions ............................. 7 Digital Feedthrough ................................................................... 14 Terminology ...................................................................................... 8 Outline Dimensions ....................................................................... 15 DAC Section ...................................................................................... 9 Ordering Guide .......................................................................... 16 Circuit Information ........................................................................ 10 REVISION HISTORY 1/09—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Table 1 ............................................................................ 3 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 5/87—Rev. 0 to Rev. A Rev. B | Page 2 of 16 AD7538 SPECIFICATIONS 1 VDD = 11.4 V to 15.75 V , VREF = 10 V; VPIN3 = VPIN4 = 0 V, VSS = −300 mV; all specifications TMIN to TMAX, unless otherwise noted. Table 1. A, J B, K 2 Parameter Versions Versions S Version T Version Unit Test Conditions/Comments ACCURACY Resolution 14 14 14 14 Bits Relative Accuracy ±2 ±1 ±2 ±1 LSB max All grades guaranteed monotonic Differential Nonlinearity ±1 ±1 ±1 ±1 LSB max Over temperature Full-Scale Error Measured using internal RFB DAC +25°C ±4 ±4 ±4 ±4 LSB max Registers loaded with all 1s T to T ±8 ±5 ±10 ±6 LSB max MIN MAX 3 Gain Temperature Coefficient ; ±2 ±2 ±2 ±2 ppm/°C typ ΔGain/ΔTemperature Output Leakage Current IOUT (Pin 3) 25°C ±5 ±5 ±5 ±5 nA max All digital inputs 0 V TMIN to TMAX ±10 ±10 ±20 ±20 nA max VSS = –300 mV T to T ±25 ±25 ±150 ±150 nA max V = 0 V MIN MAX SS REFERENCE INPUT Input Resistance (Pin 1) 3.5 3.5 3.5 3.5 kΩ min Typical input resistance = 6 kΩ 10 10 10 10 kΩ max DIGITAL INPUTS VIH (Input High Voltage) 2.4 2.4 2.4 2.4 V min V (Input Low Voltage) 0.8 0.8 0.8 0.8 V max IL I (Input Current) IN 25°C ±1 ±1 ±1 ±1 μA max VIN = 0 V or VDD TMIN to TMAX ±10 ±10 ±10 ±10 μA max 3 CIN (Input Capacitance) 7 7 7 7 pF max POWER SUPPLY VDD Range 11.4/15.75 11.4/15.75 11.4/15.75 11.4/15.75 V min/V max Specification guaranteed over this range V Range −200/−500 −200/−500 −200/−500 −200/−500 mV min/ Specification guaranteed over SS mV max this range I 4 4 4 4 mA max All digital inputs are V or V DD IL IH 500 500 500 500 μA max All digital inputs are 0 V or VDD 1 Specifications are guaranteed for a VDD of 11.4 V to 15.75 V. At VDD = 5 V, the device is fully functional with degraded specifications. 2 Temperature range as follows: J, K Versions: 0°C to +70°C A, B Versions: −25°C to +85°C S, T Versions: −55°C to +125°C 3 Sample tested to ensure compliance. Rev. B | Page 3 of 16 AD7538 AC PERFORMANCE CHARACTERISTICS These characteristics are included for design guidance only and are not subject to test. VDD = 11.4 V to 15.75 V, VREF = 10 V, VPIN3 = VPIN4 = 0 V, VSS = 0 V or −300 mV, output amplifier is AD711 except where noted. Table 2. T = 25°C A Parameter TA = TMIN, TMAX Unit Test Conditions/Comments Output Current Settling Time 1.5 μs max To 0.003% of full-scale range IOUT load= 100 Ω, CEXT = 13 pF DAC register alternately loaded with all 1s and all 0s; typical value of settling time is 0.8 μs Digital-to-Analog Glitch Impulse 20 nV-sec typ Measured with VREF = 0 V. IOUT load = 100 Ω, CEXT = 13 pF; DAC register alternately loaded with all 1s and all 0s Multiplying Feedthrough Error 3 5 mV p-p typ V = ±10 V, 10 kHz sine wave DAC REF Register loaded with all 0s Power Supply Rejection ΔGain/ΔVDD ±0.01 ±0.02 % per % max ΔVDD = ±5% Output Capacitance C (Pin 3) 260 260 pF max DAC register loaded with all 1s OUT C (Pin 3) 130 130 pF max DAC register loaded with all 0s OUT Output Noise Voltage Density (10 Hz to 100 kHz) 15 nV√Hz typ Measured between RFB and IOUT TIMING CHARACTERISTICS V = 11.4 V to 15.75 V, V = 10 V, V = V = 0 V, V = 0 V or −300 mV. All specifications T to T unless otherwise noted. See DD REF PIN3 PIN4 SS MIN MAX Figure 2 for a timing diagram. Table 3. Limit at Limit at T = 0°C to +70°C Limit at A 1 Parameter TA = +25°C TA = −25°C to +85°C TA = −55°C to +125°C Unit Test Conditions/Comments 0 0 0 ns min CS to WR setup time t 1 0 0 0 ns min CS to WR hold time t 2 170 200 240 ns min LDAC pulse width t3 t4 170 200 240 ns min Write pulse width t5 140 160 180 ns min Data setup time t 20 20 30 ns min Data hold time 6 1 Temperature range as follows: J, K Versions: 0°C to +70°C A, B Versions: −25°C to +85°C S, T Versions: −55°C to +125°C Rev. B | Page 4 of 16 AD7538 TIMING DIAGRAM t t 1 2 5V CS 0V t 3 5V LDAC 0V t 4 5V WR 0V t 6 t 5 5V DATA 0V NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURES FROM 10% TO 90% OF 5V, t = t = 20ns. R F V + V IH IL 2. TIMING MEASUREMENT REFERENCE LEVEL IS . 2 3. IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR, THEN IT MUST STAY LOW FOR t OR LONGER AFTER WR GOES HIGH. 3 Figure 2. Timing Diagram Rev. B | Page 5 of 16 01139-002 AD7538 ABSOLUTE MAXIMUM RATINGS TA = +25°C unless, otherwise stated. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V (Pin 23) to DGND −0.3 V, +17 V DD section of this specification is not implied. Exposure to absolute V (Pin 24) to AGND −15 V, +0.3 V SS maximum rating conditions for extended periods may affect VREF (Pin 1) to AGND ±25 V device reliability. VRFB (Pin 2) to AGND ±25 V Digital Input Voltage (Pins 6 to 22) to DGND −0.3 V, V +0.3 V ESD CAUTION DD V to DGND −0.3 V, V +0.3 V PIN3 DD AGND to DGND −0.3 V, V +0.3 V DD Power Dissipation (Any Package) To 75°C 1000 mW Derates Above 75°C 10 mW/°C Operating Temperature Range Commercial (J, K Versions) 0°C to +70°C Industrial (A, B Versions) −25°C to +85°C Extended (S, T Versions) −55°C to +125°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Rev. B | Page 6 of 16 AD7538 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 24 V REF SS R 2 23 V FB DD I 3 22 WR OUT AGND 4 21 CS AD7538 DGND 5 20 LDAC TOP VIEW (MSB) DB13 6 19 DB0 (LSB) (Not to Scale) DB12 7 18 DB1 DB11 8 17 DB2 DB10 9 16 DB3 DB9 10 15 DB4 DB8 11 14 DB5 DB7 12 13 DB6 Figure 3. Pin Configuration Table 5. Pin Function Description Pin No. Mnemonic Description 1 V Voltage Reference. REF 2 RFB Feedback Resistor. Used to close the loop around an external op amp. 3 IOUT Current Output Terminal. 4 AGND Analog Ground 5 DGND Digital Ground. 6 to 19 DB13 to DB0 Data Inputs. Bit DB13 (MSB) to Bit DB0 (LSB). 20 Chip Select Input. Active low. LDAC 21 CS Asynchronous Load DAC Input. Active low. WR 22 Write Input. Active low. CS LDAC WR Operation 0 1 0 Load input register. 1 1 0 X Load DAC register from input register. 0 0 0 Input and DAC registers are transparent. 1 1 1 X No operation. 1 XX 1 1 No operation. 23 VDD +12 V to +15 V Supply Input. 24 VSS Bias pin for high temperature low leakage configuration. To implement low leakage system, the pin should be at a negative voltage. See Figure 6 and Figure 8 for recommended circuitry. 1 X = don’t care. Rev. B | Page 7 of 16 01139-003 AD7538 TERMINOLOGY Digital-To-Analog Glitch Impulse Relative Accuracy The amount of charge injected from the digital inputs to the Relative accuracy or endpoint nonlinearity is a measure of the analog output when the inputs change state is called digital-to- maximum deviation from a straight line passing through the analog glitch impulse. This is normally specified as the area of endpoints of the DAC transfer function. It is measured after the glitch in either pA-secs or nV-secs depending upon whether adjusting for zero error and full-scale error and is normally the glitch is measured as a current or voltage. It is measured expressed in least significant bits or as a percentage of full- with V = AGND. REF scale reading. Output Capacitance Differential Nonlinearity This is the capacitance from IOUT to AGND. Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent Output Leakage Current codes. A specified differential nonlinearity of ±1 LSB maximum Output leakage current is current which appears at IOUT with the over the operating temperature range ensures monotonicity. DAC register loaded to all 0s. Gain Error Multiplying Feedthrough Error Gain error is a measure of the output error between an ideal This is the ac error due to capacitive feedthrough from the V REF DAC and the actual device output. It is measured with all 1s terminal to I with the DAC register loaded to all zeros. OUT in the DAC after the offset error has been adjusted out and is expressed in least significant bits. Gain error is adjustable to zero with an external potentiometer. Rev. B | Page 8 of 16 AD7538 DAC SECTION Figure 4 shows a simplified circuit diagram for the AD7538 Switch A to Switch G steer equally weighted currents between DAC section. The three MSBs of the 14-bit data word are IOUT and AGND. decoded to drive the seven switches (A to G). The 11 LSBs Because the input resistance at VREF is constant, it may be driven of the data word consist of an R-2R ladder operated in a by a voltage source or a current source of positive or negative current steering configuration. polarity. The R-2R ladder current is ⅛ of the total reference input current. ⅞ current flows in the parallel ladder structure. RR R V REF 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R R/4 R FB G F E D C B A S10 S9 S0 I OUT AGND Figure 4. Simplified Circuit Diagram for the AD7538 DAC Section Rev. B | Page 9 of 16 01139-004 AD7538 CIRCUIT INFORMATION R1 V R2 DD EQUIVALENT CIRCUIT ANALYSIS 20Ω 10Ω V IN Figure 5 shows an equivalent circuit for the analog section 1 23 2 C1 V V R of the AD7538 DAC. The current source I is composed LEAKAGE REF DD FB 33pF of surface and junction leakages. The R resistor denotes the 20 O LDAC LDAC I 3 OUT equivalent output resistance of the DAC, which varies with 21 AD7538 CS CS A1 input code. COUT is the capacitance due to the current steering 4 AGND AD711 22 V WR WR O switches and varies from about 90 pF to 180 pF (typical values) V depending upon the digital input. g(VREF, N) is the Thevenin DB13 TO DB0 DGND SS C2 619 5 24 4.7µF equivalent voltage generator due to the reference input voltage, ANALOG + GND V , and the transfer function of the DAC ladder, N. R3 REF DIGITAL 1kΩ INPUT DATA GND R/4 R4 R FB 47kΩ R O –15V I OUT Figure 6. Unipolar Binary Operation g (V , N) I C LEAKAGE OUT REF AGND Table 6. Unipolar Binary Code Table Figure 5. AD7538 Equivalent Analog Output Circuit Binary Number In DAC Register DIGITAL SECTION MSB LSB Analog Output, VOUT The digital inputs are designed to be both TTL and 5 V CMOS 11 1111 1111 1111 −VIN(16,383/16,384) compatible. All logic inputs are static protected MOS gates with 10 0000 0000 0000 −VIN(8192/16,384) = −½VIN typical input currents of less than 1 nA. To minimize power supply 00 0000 0000 0001 −VIN(1/16,384) currents, it is recommended that the digital input voltages be 00 0000 0000 0000 0 V driven as close as possible to 0 V and 5 V logic levels. UNIPOLAR BINARY OPERATION (2-QUADRANT For zero offset adjustment, the DAC register is loaded with MULTIPLICATION) all 0s and amplifier offset (VOS) adjusted so that VOUT is 0 V. Adjusting VOUT to 0 V is not necessary in many applications, Figure 6 shows the circuit diagram for unipolar binary −6 but it is recommended that V be no greater than (25 × 10 ) OS operation. With an ac input, the circuit performs 2-quadrant (V ) to maintain specified DAC accuracy (see the Application REF multiplication. The code table for Figure 6 is given in Table 6. Hints section). Capacitor C1 provides phase compensation and helps prevent Full-scale trimming is accomplished by loading the DAC overshoot and ringing when high-speed op amps are used. register with all 1s and adjusting R1 so that VOUTA = −VIN (16,383/16,384). For high temperature operation, resistors and potentiometers should have a low temperature coefficient. In many applications, because of the excellent gain TC and gain error specifications of the AD7538, gain error trimming is not necessary. In fixed reference applications, full scale can also be adjusted by omitting R1 and R2 and trimming the reference voltage magnitude. Rev. B | Page 10 of 16 01139-005 01139-006 AD7538 BIPOLAR OPERATION (4-QUADRANT Table 7. Bipolar Code Table for the Offset Binary Circuit MULTIPLICATION) of Figure 8 The recommended circuit diagram for bipolar operation is Binary Number In shown in Figure 8. Offset binary coding is used. The code table DAC Register for Figure 8 is given in Table 7. MSB LSB Analog Output V OUT 11 1111 1111 1111 +VIN(8191/8192) With the DAC loaded to 10 0000 0000 0000, adjust R1 for VO = 10 0000 0000 0001 +V (1/8192) IN 0 V. Alternatively, one can omit R1 and R2 and adjust the ratio 10 0000 0000 0000 0 V of R5 and R6 for V = 0 V. Full-scale trimming can be accom- O 01 1111 1111 1111 −VIN(1/8192) plished by adjusting the amplitude of V or by varying the IN 00 0000 0000 0000 −VIN(8191/8192) value of R7. The values given for R1, R2 are the minimum necessary to calibrate the system for Resistors R5, R6, R7 ratio matched to V = 15V DD 0.1%. System linearity error is independent of resistor ratio 60 V = 10V REF matching and is affected by DAC linearity error only. 50 When operating over a wide temperature range, it is important 40 that the resistors be of the same type so that their temperature V = 0V 30 SS coefficients match. 20 LOW LEAKAGE CONFIGURATION V = –0.3V SS 10 For CMOS multiplying DAC, as the device is operated at higher 0 temperatures, the output leakage current increases. For a 14-bit resolution system, this can be a significant source of error. The 30 40 50 60 70 80 90 100 110 120 AD7538 features a leakage reduction configuration to keep the TEMPERATURE (°C) leakage current low over an extended temperature range. One Figure 7. Graph of Typical Leakage Current vs. Temperature for AD7538 may operate the device with or without this configuration. If VSS (Pin 24) is tied to AGND then the DAC exhibits normal output leakage currents at high temperatures. To use the low leakage facility, VSS should be tied to a voltage of approximately −0.3 V as in Figure 6 and Figure 8. A simple resistor divider (R3, R4) produces approximately −300 mV from −15 V. The C2 capacitor in parallel with R3 is an integral part of the low leakage configuration and must be 4.7 μF or greater. Figure 7 is a plot of leakage current vs. temperature for both conditions. It clearly shows the improvement gained by using the low leakage configuration. V IN V R2 DD R6 R1 22Ω 20kΩ 50Ω 1 23 2 C1 R7 V V R REF DD FB 33pF 20kΩ LDAC 20 LDAC R5 I 3 OUT 10kΩ 21 AD7538 CS CS A1 AGND 4 A2 AD711 22 WR WR AD711 V O R8 V DB13 TO DB0 DGND SS C2 5kΩ, 10% 619 5 24 4.7µF + R3 ANALOG DIGITAL 1kΩ GND INPUT DATA GND R4 47kΩ –15V Figure 8. Bipolar Operation Rev. B | Page 11 of 16 LEAKAGE CURRENT (nA) 01139-007 01139-008 AD7538 Substituting this expression into Equation 1 and assuming PROGRAMMABLE GAIN AMPLIFIER zero gain error for the DAC (R = R ), the transfer function IN FB The circuit shown in Figure 9 provides a programmable gain simplifies to amplifier (PGA). In it the DAC behaves as a programmable n resistance and thus allows the circuit gain to be digitally V 2 OUT =− (3) controlled. V N IN DIGITAL n INPUT The ratio N/2 is commonly represented by the term, D, and, as N such, is the fractional representation of the digital input word. V DD n I OUT V − 2 −1 OUT AD7538 =− = (4) V N D IN GND V REF A Equation 4 indicates that the gain of the circuit can be varied V DD R FB from 16,384 down to unity (actually 16,384/16,383) in 16,383 V IN V OUT steps. The all 0s code is never applied. This avoids an open-loop condition thereby saturating the amplifier. With the all 0s code A V SS n NOTES excluded there remains (2 – 1) possible input codes allowing a 1. RESISTOR R IS ACTUALLY FB n choice of (2 – 1) output levels. In decibels the dynamic range is INCLUDED ON THE DICE. Figure 9. Programmable Gain Amplifier (PGA) V OUT n 20 log = 20 log (2 − 1)= 84 dB 10 10 V The transfer function of Figure 9 is: IN R V EQ OUT Gain= =− (1) V R IN FB R is the equivalent transfer impedance of the DAC from the EQ V pin to the I pin and can be expressed as REF OUT n 2 R IN R = (2) EQ N where: n is the resolution of the DAC. N is the DAC input code in decimal. R is the constant input impedance of the DAC (R = R ). IN IN LAD Rev. B | Page 12 of 16 01139-009 AD7538 APPLICATION HINTS In a multiple DAC system, the double buffering of the AD7538 OUTPUT OFFSET allows the user to simultaneously update all DACs. In Figure 11, CMOS DACs in circuits such as Figure 6 and Figure 8 exhibit a 14-bit word is loaded to the input registers of each of the DACs a code dependent output resistance, which in turn can cause a in sequence. Then, with one instruction to the appropriate code dependent error voltage at the output of the amplifier. LDAC address, CS4 (that is, ) is brought low, updating all the The maximum amplitude of this error, which adds to the DAC DACs simultaneously. nonlinearity, depends on VOS, where VOS is the amplifier input ADDRESS BUS offset voltage. To maintain specified accuracy with VREF at 10 V, it is recommended that VOS be no greater than 0.25 mV, or (25 × −6 16-BIT ADDRESS CS1 10 ) (V ), over the temperature range of operation. The AD711 is REF ALE CS LATCH DECODE 1 AD7538 a suitable op amp. The op amp has a wide bandwidth and high CS4 CS3 CS2 8096 LDAC slew rate and is recommended for ac and other applications WR WR requiring fast settling. DB0 TO DB13 AD0 TO AD15 DATA BUS GENERAL GROUND MANAGEMENT Because the AD7538 is specified for high accuracy, it is impor- tant to use a proper grounding technique. AC or transient CS voltages between AGND and DGND can cause noise injection 1 AD7538 into the analog output. The simplest method of ensuring that LDAC voltages at AGND and DGND are equal is to tie AGND and WR DGND together at the AD7538. In more complex systems DB0 TO DB13 where the AGND and DGND intertie on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7538 AGND and DGND pins (1N914 or equivalent). CS 1 AD7538 MICROPROCESSOR INTERFACING LDAC The AD7538 is designed for easy interfacing to 16-bit micro- WR processors and can be treated as a memory mapped peripheral. DB0 TO DB13 This reduces the amount of external logic needed for interfacing 1 to a minimal. LINEAR CIRCUITRY OMITTED FOR CLARITY. Figure 11. AD7538-to-8086 Interface: Multiple DAC System AD7538-TO-8086 INTERFACE AD7538-TO-MC68000 INTERFACE Figure 10 shows the 8086 processor interface to a single device. LDAC In this setup, the double buffering feature (using ) of the Figure 12 shows the MC68000 processor interface to a single device. In this setup, the double buffering feature of the DAC DAC is not used. The 14-bit word is written to the DAC in one is not used and the appropriate data is written into the DAC in MOVE instruction and the analog output responds one MOVE instruction. immediately. ADDRESS BUS A1 TO A23 ADDRESS BUS 16-BIT ADDRESS MC68000 ALE CS LATCH DECODE ADDRESS CS LDAC AS DECODE 8096 1 LDAC AD7538 DTACK 1 WR AD7538 WR AD13 WR R/W AD0 TO AD15 DATA BUS DB0 TO DB13 AD0 D0 TO D15 DATA BUS DB0 TO DB13 1 LINEAR CIRCUITRY OMITTED FOR CLARITY. Figure 10. AD7538-to-8086 Interface Circuit 1 LINEAR CIRCUITRY OMITTED FOR CLARITY. Figure 12. AD7538-to-MC68000 Interface Rev. B | Page 13 of 16 01139-010 01139-012 01139-011 AD7538 DIGITAL FEEDTHROUGH ADDRESS A0 TO A15 DECODE 1 AD7538 The digital inputs to the AD7538 are directly connected to the MICRO- CS microprocessor bus in the preceding interface configurations. PROCESSOR LDAC SYSTEM These inputs are constantly changing even when the device is EN WR WR not selected. The high frequency logic activity on the bus can 16-BIT feed through the DAC package capacitance to show up as noise LATCH DB0 TO DB13 D0 TO D15 on the analog output. To minimize this digital feedthrough 1 isolate the DAC from the noise source. Figure 13 shows an LINEAR CIRCUITRY OMITTED FOR CLARITY. interface circuit, which uses this technique. All data inputs are Figure 13. AD7538 Interface Circuit Using Latches to Minimize Digital Feedthrough latched from the bus by the CS signal. One may also use other means, such as peripheral interface devices, to reduce the digital feedthrough. Rev. B | Page 14 of 16 01139-013 AD7538 OUTLINE DIMENSIONS 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 0.280 (7.11) 0.250 (6.35) 1 0.240 (6.10) 12 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) MAX 0.210 (5.33) 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) MIN 0.130 (3.30) GAUGE 0.014 (0.36) PLANE 0.115 (2.92) SEATING 0.010 (0.25) PLANE 0.008 (0.20) 0.022 (0.56) 0.430 (10.92) 0.005 (0.13) 0.018 (0.46) MAX MIN 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 14. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 0.098 (2.49) 0.005 (0.13) MIN MAX 0.310 (7.87) 0.220 (5.59) 24 13 112 PIN 1 0.060 (1.52) 0.320 (8.13) 0.200 (5.08) 1.280 (32.51) MAX 0.015 (0.38) MAX 0.290 (7.37) 0.150 (3.81) MIN 0.015 (0.38) 0.008 (0.20) 0.200 (5.08) 15° 0.125 (3.18) SEATING 0° 0.100 0.070 (1.78) PLANE (2.54) 0.030 (0.76) 0.023 (0.58) BSC 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 15. 24-Lead Ceramic Dual In-Line Package [CERDIP] (Q-24-1) Dimensions shown in inches and (millimeters) Rev. B | Page 15 of 16 100808-A 071006-A AD7538 15.60 (0.6142) 15.20 (0.5984) 24 13 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 12 10.00 (0.3937) 45° 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 1.27 (0.0500) 0.51 (0.0201) 1.27 (0.0500) 0.33 (0.0130) PLANE BSC 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 16. 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Relative Accuracy Full-Scale Error Package Description Package Option AD7538JN 0°C to +70°C ±2 LSB ±8 LSB 24-Lead PDIP N-24-1 1 AD7538JNZ 0°C to +70°C ±2 LSB ±8 LSB 24-Lead PDIP N-24-1 AD7538KN 0°C to +70°C ±1 LSB ±5 LSB 24-Lead PDIP N-24-1 1 AD7538KNZ 0°C to +70°C ±1 LSB ±5 LSB 24-Lead PDIP N-24-1 AD7538JR 0°C to +70°C ±2 LSB ±8 LSB 24-Lead SOIC_W RW-24 AD7538JR-REEL 0°C to +70°C ±2 LSB ±8 LSB 24-Lead SOIC_W RW-24 1 AD7538JRZ 0°C to +70°C ±2 LSB ±8 LSB 24-Lead SOIC_W RW-24 1 AD7538JRZ-REEL 0°C to +70°C ±2 LSB ±8 LSB 24-Lead SOIC_W RW-24 AD7538KR 0°C to +70°C ±1 LSB ±5 LSB 24-Lead SOIC_W RW-24 AD7538KR-REEL 0°C to +70°C ±1 LSB ±5 LSB 24-Lead SOIC_W RW-24 1 AD7538KRZ 0°C to +70°C ±1 LSB ±5 LSB 24-Lead SOIC_W RW-24 1 AD7538KRZ-REEL 0°C to +70°C ±1 LSB ±5 LSB 24-Lead SOIC_W RW-24 AD7538AQ −25°C to +85°C ±2 LSB ±8 LSB 24-Lead CERDIP Q-24-1 AD7538BQ −25°C to +85°C ±1 LSB ±5 LSB 24-Lead CERDIP Q-24-1 AD7538SQ −55°C to +125°C ±2 LSB ±10 LSB 24-Lead CERDIP Q-24-1 AD7538TQ −55°C to +125°C ±1 LSB ±6 LSB 24-Lead CERDIP Q-24-1 1 Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01139-0-1/09(B) Rev. B | Page 16 of 16 0.75 (0.0295) 0.25 (0.0098) 060706-A