ANALOG DEVICES AD7528

CMOS Dual 8-Bit a Buffered Multiplying DAC AD7528 FEATURES FUNCTIONAL BLOCK DIAGRAM On-Chip Latches for Both DACs V A REF +5 V to +15 V Operation DACs Matched to 1% R A V FB DD Four Quadrant Multiplication DB0 OUT A TTL/CMOS Compatible DATA INPUT LATCH DAC A INPUTS BUFFER Latch Free (Protection Schottkys not Required) DB7 AGND APPLICATIONS Digital Control of: AD7528 DAC A/ DAC B Gain/Attenuation R B FB CONTROL CS Filter Parameters LOGIC OUT B WR Stereo Audio Circuits LATCH DAC B X-Y Graphics DGND V B REF 1 GENERAL DESCRIPTION ORDERING GUIDE The AD7528 is a monolithic dual 8-bit digital/analog converter Temperature Relative Gain Package featuring excellent DAC-to-DAC matching. It is available in 2 3 Model Ranges Accuracy Error Options skinny 0.3" wide 20-lead DIPs and in 20-lead surface mount packages. AD7528JN –40°C to +85°C–1 LSB–4 LSB N-20 AD7528KN –40°C to +85°C–1/2 LSB–2 LSB N-20 Separate on-chip latches are provided for each DAC to allow AD7528LN –40°C to +85°C–1/2 LSB–1 LSB N-20 easy microprocessor interface. AD7528JP –40°C to +85°C–1 LSB–4 LSB P-20A Data is transferred into either of the two DAC data latches via a AD7528KP –40°C to +85°C–1/2 LSB–2 LSB P-20A AD7528LP –40°C to +85°C–1/2 LSB–1 LSB P-20A common 8-bit TTL/CMOS compatible input port. Control AD7528JR –40°C to +85°C–1 LSB–4 LSB R-20 input DAC A/DAC B determines which DAC is to be loaded. AD7528KR –40°C to +85°C–1/2 LSB–2 LSB R-20 The AD7528’s load cycle is similar to the write cycle of a ran- AD7528LR –40°C to +85°C–1/2 LSB–1 LSB R-20 dom access memory and the device is bus compatible with most AD7528AQ –40°C to +85°C–1 LSB–4 LSB Q-20 8-bit microprocessors, including 6800, 8080, 8085, Z80. AD7528BQ –40°C to +85°C–1/2 LSB–2 LSB Q-20 The device operates from a +5 V to +15 V power supply, dis- AD7528CQ –40°C to +85°C–1/2 LSB–1 LSB Q-20 AD7528SQ –55°C to +125°C–1 LSB–4 LSB Q-20 sipating only 20 mW of power. AD7528TQ –55°C to +125°C–1/2 LSB–2 LSB Q-20 Both DACs offer excellent four quadrant multiplication charac- AD7528UQ –55°C to +125°C–1/2 LSB–1 LSB Q-20 teristics with a separate reference input and feedback resistor for NOTES each DAC. 1 Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts will be marked with cerdip designator “Q.” 2 PRODUCT HIGHLIGHTS Processing to MIL-STD-883C, Class B is available. To order, add suffix “/883B” to part number. For further information, see Analog Devices’ 1990 Military Products 1. DAC-to-DAC matching: since both of the AD7528 DACs are Databook. fabricated at the same time on the same chip, precise match- 3 N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. ing and tracking between DAC A and DAC B is inherent. The AD7528’s matched CMOS DACs make a whole new range of applications circuits possible, particularly in the audio, graphics and process control areas. 2. Small package size: combining the inputs to the on-chip DAC latches into a common data bus and adding a DAC A/DAC B select line has allowed the AD7528 to be packaged in either a small 20-lead DIP, SOIC or PLCC. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998 (V A = V B = +10 V; OUT A = OUT B = O V unless otherwise noted) AD7528–SPECIFICATIONS REF REF V = +5 V V = +15 V DD DD 1 Parameter Version T = +25°CT , T T = +25°CT , T Units Test Conditions/Comments A MIN MAX A MIN MAX 2 STATIC PERFORMANCE Resolution All 8 8 8 8 Bits Relative Accuracy J, A, S–1–1–1–1 LSB max This is an Endpoint Linearity Specification K, B, T–1/2–1/2–1/2–1/2 LSB max L, C, U–1/2–1/2–1/2–1/2 LSB max Differential Nonlinearity All–1–1–1–1 LSB max All Grades Guaranteed Monotonic Over Full Operating Temperature Range Gain Error J, A, S–4–6–4–5 LSB max Measured Using Internal R A and R B FB FB K, B, T–2–4–2–3 LSB max Both DAC Latches Loaded with 11111111 L, C, U–1–3–1–1 LSB max Gain Error is Adjustable Using Circuits of Figures 4 and 5 3 Gain Temperature Coefficient DGain/DTemperature All–0.007–0.007–0.0035–0.0035 %/°C max Output Leakage Current OUT A (Pin 2) All–50–400–50–200 nA max DAC Latches Loaded with 00000000 OUT B (Pin 20) All–50–400–50–200 nA max Input Resistance (V A, V B) All 8 8 8 8 kW min Input Resistance TC = –300 ppm/°C, Typical REF REF 15 15 15 15 kW max Input Resistance is 11 kW V A/V B Input Resistance REF REF Match All–1–1–1–1% max 4 DIGITAL INPUTS Input High Voltage V All 2.4 2.4 13.5 13.5 V min IH Input Low Voltage V All 0.8 0.8 1.5 1.5 V max IL Input Current I All–1–10–1–10mA max V = 0 or V IN IN DD Input Capacitance DB0–DB7 All 10 10 10 10 pF max WR, CS, DAC A/DAC B All 15 15 15 15 pF max 3 SWITCHING CHARACTERISTICS See Timing Diagram Chip Select to Write Set Up Time All 90 100 60 80 ns min tCS Chip Select to Write Hold Time All 0 0 10 15 ns min tCH DAC Select to Write Set Up Time All 90 100 60 80 ns min tAS DAC Select to Write Hold Time All 0 0 10 15 ns min t AH Data Valid to Write Set Up Time All 80 90 30 40 ns min t DS Data Valid to Write Hold Time All 0 0 0 0 ns min t DH Write Pulsewidth t All 90 100 60 80 ns min WR POWER SUPPLY See Figure 3 I All 2 2 2 2 mA max All Digital Inputs V or V DD IL IH All 100 500 100 500mA max All Digital Inputs 0 V or V DD (Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as 5 AC PERFORMANCE CHARACTERISTICS Output Amplifiers) V = +5 V V = +15 V DD DD 1 Parameter Version T = +25°CT , T T = +25°CT , T Units Test Conditions/Comments A MIN MAX A MIN MAX DC SUPPLY REJECTION (DGAIN/DV ) All 0.02 0.04 0.01 0.02 % per % maxDV = –5% DD DD 2 CURRENT SETTLING TIME All 350 400 180 200 ns max To 1/2 LSB. OUT A/OUT B Load = 100 W. WR = CS = 0 V. DB0–DB7 = 0 V to V or DD V to 0 V DD PROPAGATION DELAY (From Digital In- V A = V B = +10 V REF REF put to 90% of Final Analog Output Current) All 220 270 80 100 ns max OUT A, OUT B Load = 100 W C = 13 pF EXT WR = CS = 0 V DB0–DB7 = 0 V to V or DD V to 0 V DD DIGITAL-TO-ANALOG GLITCH IMPULSE All 160 440 nV sec typ For Code Transition 00000000 to 11111111 OUTPUT CAPACITANCE C A All 50 50 50 50 pF max DAC Latches Loaded with 00000000 OUT C B 50 505050pF max OUT C A 120 120 120 120 pF max DAC Latches Loaded with 11111111 OUT C B 120 120 120 120 pF max OUT 6 AC FEEDTHROUGH V A to OUT A All –70 –65 –70 –65 dB max V A, V B = 20 V p-p Sine Wave REF REF REF V B to OUT B –70 –65 –70 –65 dB max @ 100 kHz REF –2– REV. B AD7528 V = +5 V V = +15 V DD DD 1 Parameter Version T = +25°CT , T T = +25°CT , T Units Test Conditions/Comments A MIN MAX A MIN MAX CHANNEL-TO-CHANNEL ISOLATION Both DAC Latches Loaded with 11111111. V A to OUT B All –77 –77 dB typ V A = 20 V p-p Sine Wave @ 100 kHz REF REF V B = 0 V see Figure 6. REF V B to OUT A –77 –77 dB typ V A = 20 V p-p Sine Wave @ 100 kHz REF REF V A = 0 V see Figure 6. REF DIGITAL CROSSTALK All 30 60 nV sec typ Measured for Code Transition 00000000 to 11111111 HARMONIC DISTORTlON All –85 –85 dB typ V = 6 V rms @ 1 kHz IN NOTES 1 Temperature Ranges are J, K, L Versions: –40°C to +85°C A, B, C Versions: –40°C to +85°C AD7528, ideal maximum output is V – 1 LSB. Gain error of REF S, T, U Versions: –55°C to +125°C 2 both DACs is adjustable to zero with external resistance. Specifications applies to both DACs in AD7528. 3 Guaranteed by design but not production tested. Output Capacitance 4 Logic inputs are MOS Gates. Typical input current (+25°C) is less than 1 nA. 5 Capacitance from OUT A or OUT B to AGND. These characteristics are for design guidance only and are not subject to test. 6 Feedthrough can be further reduced by connecting the metal lid on the ceramic package Digital to Analog Glitch lmpulse (suffix D) to DGND. The amount of charge injected from the digital inputs to the Specifications subject to change without notice. analog output when the inputs change state. This is normally ABSOLUTE MAXIMUM RATINGS specified as the area of the glitch in either pA-secs or nV-secs (T = +25°C unless otherwise noted) A depending upon whether the glitch is measured as a current or V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V DD A, voltage signal. Glitch impulse is measured with V REF V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V DD B = AGND. V REF AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . V + 0.3 V DD Propagation Delay DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . V + 0.3 V DD This is a measure of the internal delays of the circuit and is Digital Input Voltage to DGND . . . . . . . –0.3 V, V + 0.3 V DD defined as the time from a digital input change to the analog V , V to AGND . . . . . . . . . . . . . . –0.3 V, V + 0.3 V PIN2 PIN20 DD output current reaching 90% of its final value. V A, V B to AGND . . . . . . . . . . . . . . . . . . . . . . .–25 V REF REF V A, V B to AGND . . . . . . . . . . . . . . . . . . . . . . .–25 V Channel-to-Channel Isolation RFB RFB Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW The proportion of input signal from one DAC’s reference input Derates above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C which appears at the output of the other DAC, expressed as a Operating Temperature Range ratio in dB. Commercial (J, K, L) Grades . . . . . . . . . . . –40°C to +85°C Digital Crosstalk Industrial (A, B, C) Grades . . . . . . . . . . . . –40°C to +85°C The glitch energy transferred to the output of one converter due Extended (S, T, U) Grades . . . . . . . . . . . –55°C to +125°C to a change in digital input code to the other converter. Speci- Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C fied in nV secs. Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C PIN CONFIGURATIONS CAUTION: PLCC 1. ESD sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on uncon- nected devices subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. 3 2 1 20 19 2. Do not insert this device into powered sockets. Remove PIN 1 V A 4 18 V B REF REF IDENTIFIER power before insertion or removal. DGND 5 17 V DD AD7528 6 16 DAC A/DAC B WR TOP VIEW TERMINOLOGY (Not to Scale) (MSB) DB7 7 15 CS Relative Accuracy 8 14 DB6 DB0 (LSB) Relative accuracy or endpoint nonlinearity is a measure of the 9 10 11 12 13 maximum deviation from a straight line passing through the DIP, SOIC endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in 1 20 OUT B AGND LSBs or as a percentage of full scale reading. 2 19 R B OUT A FB Differential Nonlinearity R A 3 18 V B FB REF Differential nonlinearity is the difference between the measured V A 4 17 V REF DD change and the ideal 1 LSB change between any two adjacent 5 16 DGND WR AD7528 codes. A specified differential nonlinearity of –1 LSB max over TOP VIEW 6 15 DAC A/DAC B CS (Not to Scale) the operating temperature range ensures monotonicity. (MSB) DB7 7 14 DB0 (LSB) Gain Error DB6 8 13 DB1 Gain error or full-scale error is a measure of the output error 9 12 DB5 DB2 between an ideal DAC and the actual device output. For the 10 11 DB4 DB3 REV. B –3– R A DB5 FB OUT A DB4 DB3 AGND OUT B DB2 R B DB1 FB AD7528 INTERFACE LOGIC INFORMATION Figure 1. An inverted R-2R ladder structure is used, that is, bi- DAC Selection: nary weighted currents are switched between the DAC output Both DAC latches share a common 8-bit input port. The con- and AGND thus maintaining fixed currents in each ladder leg trol input DAC A/DAC B selects which DAC can accept data independent of switch state. from the input port. EQUIVALENT CIRCUIT ANALYSIS Mode Selection: Figure 2 shows an approximate equivalent circuit for one of the Inputs CS and WR control the operating mode of the selected AD7528’s D/A converters, in this case DAC A. A similar DAC. See Mode Selection Table below. equivalent circuit can be drawn for DAC B. Note that AGND Write Mode: (Pin 1) is common for both DAC A and DAC B. When CS and WR are both low the selected DAC is in the write The current source I is composed of surface and junc- LEAKAGE mode. The input data latches of the selected DAC are transpar- tion leakages and, as with most semiconductor devices, approxi- ent and its analog output responds to activity on DB0–DB7. mately doubles every 10°C. The resistor R as shown in Figure O Hold Mode: 2 is the equivalent output resistance of the device which varies The selected DAC latch retains the data which was present on with input code (excluding all 0s code) from 0.8 R to 2 R. R is DB0–DB7 just prior to CS or WR assuming a high state. Both typically 11 kW. C is the capacitance due to the N-channel OUT analog outputs remain at the values corresponding to the data in switches and varies from about 50 pF to 120 pF depending their respective latches. upon the digital input. g(V A, N) is the Thevenin equivalent REF Mode Selection Table voltage generator due to the reference input voltage V A and REF the transfer function of the R-2R ladder. DAC A/DAC B CS WR DAC A DAC B L L L WRITE HOLD R H L L HOLD WRITE R R A O FB OUT A X H X HOLD HOLD g(V A, N) C I X X H HOLD HOLD REF LKG OUT AGND L = Low State; H = High State; X = Don’t Care. Figure 2. Equivalent Analog Output Circuit of DAC A WRITE CYCLE TIMING DIAGRAM CIRCUIT INFORMATION–DIGITAL SECTION t CH V t The input buffers are simple CMOS inverters designed such CS DD CHIP SELECT that when the AD7528 is operated with V = 5 V, the buffer 0 DD t converts TTL input levels (2.4 V and 0.8 V) into CMOS logic AH V t DD AS levels. When V is in the region of 2.0 volts to 3.5 volts the IN DAC A/DAC B 0 input buffers operate in their linear region and pass a quiescent t V WR DD current, see Figure 3. To minimize power supply currents it is WRITE 0 recommended that the digital input voltages be as close to the t DS t DH supply rails (V and DGND) as is practically possible. DD V DD V DATA IN IH DATA IN STABLE V The AD7528 may be operated with any supply voltage in the (DB0 – DB7) IL 0 NOTES: range 5 £ V £ 15 volts. With V = +15 V the input logic DD DD 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED levels are CMOS compatible only, i.e., 1.5 V and 13.5 V. FROM 10% TO 90% OF V . DD V = +5V, t = t = 20ns; DD r f V = +15V, t = t = 40ns; DD r f V + V 9 IH IL 2. TIMING MEASUREMENT REFERENCE LEVEL IS 2 800 V = +15V 8 T = +258C DD A ALL DIGITAL INPUTS 700 7 CIRCUIT INFORMATION—D/A SECTION TIED TOGETHER The AD7528 contains two identical 8-bit multiplying D/A con- 600 6 verters, DAC A and DAC B. Each DAC consists of a highly 500 5 stable thin film R-2R ladder and eight N-channel current steer- 400 4 ing switches. A simplified D/A circuit for DAC A is shown in 300 V = +5V 3 DD 200 2 R R R V A REF 100 1 2R 2R 2R 2R 2R S1 S2 S3 S8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 R R A V – Volts FB IN OUT A AGND Figure 3. Typical Plots of Supply Current, I vs. Logic DD DAC A DATA LATCHES Input Voltage V , for V = +5 V and +15 V IN DD AND DRIVERS Figure 1. Simplified Functional Circuit for DAC A –4– REV. B I mA (V = +5V) DD DD I mA (V = +15V) DD DD AD7528 V A IN (± 10V) Table I. Unipolar Binary Code Table 1 R1 DAC Latch Contents Analog Output 1 R2 MSB LSB (DAC A or DAC B) V DD 2 R A C1 FB  255  DB0 ±V   1 1 1 1 1 1 1 1 IN DATA INPUT DAC A OUT A V AŁ256łLATCH OUT INPUTS BUFFER DB7  129  AGND AGND ±V   1 0 0 0 0 0 0 1 IN Ł256ł AD7528 1 V R4  128  DAC A/ IN ±V   =- DAC B 1 0 0 0 0 0 0 0 IN Ł256ł2 CONTROL 2 R B C2 FB CS LOGIC  127  WR ±V   LATCH OUT B DAC B V B 0 1 1 1 1 1 1 1 IN OUT Ł256ł DGND  1  AGND ±V   0 0 0 0 0 0 0 1 IN Ł256ł 1 R3  0  V B ±V   = 0 IN 0 0 0 0 0 0 0 0 IN Ł256ł(± 10V) NOTES: 1 R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 1-8 Note: 1 LSB = 2 V = V () () SEE TABLE III FOR RECOMMENDED VALUES. () IN IN 256 2 C1, C2 PHASE COMPENSATION (10pF–15pF) IS REQUIRED WHEN USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION. Figure 4. Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication); See Table I V A IN Table II. Bipolar (Offset Binary) Code Table (± 10V) R5 20kV DAC Latch Contents Analog Output 2 R6 1 R1 20kV MSB LSB (DAC A or DAC B) 2 R7 A2 V A OUT 1 R2 10kV  127  +V   1 1 1 1 1 1 1 1 IN V DD 3Ł128łR A C1 R11 FB 5kV DB0 DATA INPUT A1 AGND LATCH DAC A OUT A 1 0 0 0 0 0 0 1 INPUTS BUFFER DB7 AGND 1 0 0 0 0 0 0 0 0 AGND AD7528 1 R4 DAC A/  1  DAC B 3 ±V CONTROL   R B C2 0 1 1 1 1 1 1 1 IN FB CSŁ128łLOGIC WR R8 LATCH DAC B OUT B A3  127  20kV ±V   0 0 0 0 0 0 0 1 IN 2 DGND R9Ł128ł AGND 10kV 128  2 A4 V B ±V R10   OUT 0 0 0 0 0 0 0 0 IN 1 R3Ł128ł20kV R12 -7 1 5kV 2 V = V V B Note: 1 LSB = () () () IN IN IN 128 (± 10V) AGND NOTES: 1 R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. SEE TABLE III FOR RECOMMENDED VALUES. ADJUST R1 FOR V A = 0V WITH CODE 10000000 IN DAC A LATCH. OUT ADJUST R3 FOR V B = 0V WITH CODE 10000000 IN DAC B LATCH. OUT 2 MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS Table III. Recommended Trim Resistor R6, R7 AND R9, R10. Values vs. Grade 3 C1, C2 PHASE COMPENSATION (10pF–15pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER. Trim Figure 5. Dual DAC Bipolar Operation Resistor J/A/S K/B/T L/C/U (4 Quadrant Multiplication); See Table II R1; R3 1 k 500 200 R2; R4 330 150 82 REV. B –5– AD7528 APPLICATIONS INFORMATION ship between input frequency and channel to channel isolation. Application Hints Figure 7 shows a printed circuit layout for the AD7528 and the To ensure system performance consistent with AD7528 specifi- AD644 dual op amp which minimizes feedthrough and crosstalk. cations, careful attention must be given to the following points: SINGLE SUPPLY APPLICATIONS 1. GENERAL GROUND MANAGEMENT: AC or transient The AD7528 DAC R-2R ladder termination resistors are con- voltages between the AD7528 AGND and DGND can cause nected to AGND within the device. This arrangement is par- noise injection into the analog output. The simplest method ticularly convenient for single supply operation because AGND of ensuring that voltages at AGND and DGND are equal is may be biased at any voltage between DGND and V . Figure DD to tie AGND and DGND together at the AD7528. In more 8 shows a circuit which provides two +5 V to +8 V analog out- complex systems where the AGND–DGND intertie is on the puts by biasing AGND +5 V up from DGND. The two DAC backplane, it is recommended that diodes be connected in reference inputs are tied together and a reference input voltage inverse parallel between the AD7528 AGND and DGND is obtained without a buffer amplifier by making use of the pins (1N914 or equivalent). constant and matched impedances of the DAC A and DAC B reference inputs. Current flows through the two DAC R-2R 2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a ladders into R1 and R1 is adjusted until the V A and V B code-dependent output resistance which in turn causes a REF REF inputs are at +2 V. The two analog output voltages range from code-dependent amplifier noise gain. The effect is a code- +5 V to +8 V for DAC codes 00000000 to 11111111. dependent differential nonlinearity term at the amplifier output which depends on V (V is amplifier input offset OS OS V = +15V DD voltage). This differential nonlinearity term adds to the R/2R differential nonlinearity. To maintain monotonic operation, it DAC A V A = +5V TO +8V is recommended that amplifier V be no greater than 10% of OS OUT DB0 DATA 1 LSB over the temperature range of interest. INPUTS DB7 SUGGESTED OP AMP: 3. HIGH FREQUENCY CONSIDERATIONS: The output CS AD7528 AD644 WR capacitance of a CMOS DAC works in conjunction with the DAC A/DAC B amplifier feedback resistance to add a pole to the open loop V B = +5V TO +8V DAC B OUT 2 VOLTS response. This can cause ringing or oscillation. Stability can R1 be restored by adding a phase compensation capacitor in 10kV AD584J V R2 DD parallel with the feedback resistor. 1kV GND DYNAMIC PERFORMANCE The dynamic performance of the two DACs in the AD7528 will Figure 8. AD7528 Single Supply Operation depend upon the gain and phase characteristics of the output Figure 9 shows DAC A of the AD7528 connected in a positive amplifiers together with the optimum choice of the PC board reference, voltage switching mode. This configuration is useful layout and decoupling components. Figure 6 shows the relation in that V is the same polarity as V allowing single supply OUT IN operation. However, to retain specified linearity, V must be in IN –100 the range 0 V to +2.5 V and the output buffered or loaded with T = +258C A a high impedance, see Figure 10. Note that the input voltage is V = +15V –90 DD V = 20V PEAK TO PEAK connected to the DAC OUT A and the output voltage is taken IN –80 from the DAC V A pin. REF –70 V OUT V (0V TO +2.5V) IN V A REF –60 –50 V DD DAC A OUT A +15V AD7528 20k 50k 100k 200k 500k 1M INPUT FREQUENCY – Hz Figure 9. AD7528 in Single Supply, Voltage Switching Mode Figure 6. Channel-to-Channel Isolation 3 PIN 8 OF TO-5 CAN (AD644) AD644 V+ T = +258C A V = +15V DD 2 V– NONLINEARITY AGND AD7528 PIN 1 C1 LOCATION *NOTE 1 C2 LOCATION V B* REF INPUT SCREENS V TO REDUCE V A* DIFFERENTIAL DD REF FEEDTHROUGH. NONLINEARITY WR DGND LAYOUT SHOWS CS DAC A/DAC B COPPER SIDE AD7528 (i.e., BOTTOM VIEW). LSB MSB 2.53456 3.5 4.5 5.5 6.57 7.5 V A – Volts IN Figure 7. Suggested PC Board Layout for AD7528 with Figure 10. Typical AD7528 Performance in Single Supply AD644 Dual Op Amp Voltage Switching Mode (K/B/T, L/C/U Grades) –6– REV. B ISOLATION – dB ERROR – LSB AD7528 MICROPROCESSOR INTERFACE A8–A15 ADDRESS BUS A** A0–A15 ADDRESS BUS DAC A/DAC B ADDRESS CPU DECODE 8085 CS A** LOGIC DAC A DAC A/DAC B ADDRESS A + 1** V MA DECODE WR WR AD7528* CS LOGIC DAC A CPU DB0 LATCH A + 1** DAC B ALE 6800 8212 AD7528* DB7 WR f2 DB0 DAC B AD0–AD7 ADDR/DATA BUS DB7 *ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY D0–D7 **A = DECODED 7528 ADDR DAC A DATA BUS A + 1 = DECODED 7528 ADDR DAC B *ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY NOTE: **A = DECODED 7528 ADDR DAC A 8085 INSTRUCTION SHLD (STORE H & L DIRECT) CAN UPDATE A + 1 = DECODED 7528 ADDR DAC B BOTH DACs WITH DATA FROM H AND L REGISTERS Figure 11. AD7528 Dual DAC to 6800 CPU Interface Figure 12. AD7528 Dual DAC to 8085 CPU Interface PROGRAMMABLE WINDOW COMPARATOR In the circuit of Figure 13 the AD7528 is used to implement a V DD TEST INPUT V 0 TO –V programmable window comparator. DACs A and B are loaded CC REF R A FB with the required upper and lower voltage limits for the test, 1kV OUT A V A REF 3 7 respectively. If the test input is not within the programmed DAC A 2 DB0 DATA limits, the pass/fail output will indicate a fail (logic zero). INPUTS DB7 AD311 COMPARATOR CS AD7528 PASS/ FAIL OUTPUT WR OUT B 2 DAC A/DAC B 7 3 DAC B +V REF V B REF AD311 COMPARATOR R B FB Figure 13. Digitally Programmable Window Comparator (Upper and Lower Limit Detector) PROGRAMMABLE STATE VARIABLE FILTER In this state variable or universal filter configuration (Figure 14) The filter provides low pass, high pass and band pass outputs DACs A1 and B1 control the gain and Q of the filter character- and is ideally suited for applications where microprocessor istic while DACs A2 and B2 control the cutoff frequency, f . control of filter parameters is required, e.g., equalizer, tone C DACs A2 and B2 must track accurately for the simple expres- controls, etc. sion for f to hold. This is readily accomplished by the AD7528. C Programmable range for component values shown is f = 0 kHz C Op amps are 2 · AD644. C3 compensates for the effects of op to 15 kHz and Q = 0.3 to 4.5. amp gain bandwidth limitations. R5 CIRCUIT EQUATIONS 30kV CC 12==,, R12R R4=R5 C1 C2 R4 1000pF 1000pF C3 30kV R3 47pF 10kV 1 A1 HIGH LOW f = C A2 PASS A3 A4 PASS 21pRC1 OUTPUT OUTPUT BAND R3 R F PASS Q=· V OUTPUT V DD DD R4 R FBB1 AD7528 R F A = – O DAC A1 DAC B1 DAC A2 DAC B2 V IN AD7528 R R R R1 R2 S F S NOTE DAC Equivalent Resistance DB0–DB7 DB0–DB7 Equals CS WR DAC A/DAC B CS WR DAC A/DAC B DATA 1 DATA 2 256·() DAC Ladder Resistance Figure 14. Digitally Controlled State Variable Filter DAC Digital Code REV. B –7– AD7528 DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR Table IV. Attenuation vs. DAC A, DAC B Code for the Circuit In this configuration the AD7528 functions as a 2-channel digi- of Figure 15 tally controlled attenuator. Ideal for stereo audio and telephone signal level control applications. Table IV gives input codes vs. Attn. DAC Input Code In Attn. DAC Input Code In attenuation for a 0 dB to 15.5 dB range. dB Code Decimal dB Code Decimal 0.0 1 1 1 1 1 1 1 1 255 88.0 0 1 1 0 0 1 1 0 102   Attenuation, dB -0.5 1 1 1 1 0 0 1 0 242 88.5 0 1 1 0 0 0 0 0 96 Input Code = 256 3 10 exp   20Łł 1.0 1 1 1 0 0 1 0 0 228 89.0 0 1 0 1 1 0 1 1 91 1.5 1 1 0 1 0 1 1 1 215 89.5 0 1 0 1 0 1 1 0 86 2.0 1 1 0 0 1 0 1 1 203 10.0 0 1 0 1 0 0 0 1 81 V DD 2.5 1 1 0 0 0 0 0 0 192 10.5 0 1 0 0 1 1 0 0 76 V A IN DAC A A1 V A 3.0 1 0 1 1 0 1 0 1 181 11.0 0 1 0 0 1 0 0 0 72 OUT 3.5 1 0 1 0 1 0 1 1 171 11.5 0 1 0 0 0 1 0 0 68 4.0 1 0 1 0 0 0 1 0 162 12.0 0 1 0 0 0 0 0 0 64 DB0 DATA BUS 4.5 1 0 0 1 1 0 0 0 152 12.5 0 0 1 1 1 1 0 1 61 DB7 CS 5.0 1 0 0 1 0 0 0 0 144 13.0 0 0 1 1 1 0 0 1 57 AD7528 WR 5.5 1 0 0 0 1 0 0 0 136 13.5 0 0 1 1 0 1 1 0 54 DAC A/DAC B 6.0 1 0 0 0 0 0 0 0 128 14.0 0 0 1 1 0 0 1 1 51 V B 6.5 0 1 1 1 1 0 0 1 121 14.5 0 0 1 1 0 0 0 0 48 IN DAC B V B A2 OUT 7.0 0 1 1 1 0 0 1 0 114 15.0 0 0 1 0 1 1 1 0 46 7.5 0 1 1 0 1 1 0 0 108 15.5 0 0 1 0 1 0 1 1 43 SUGGESTED OP AMP: AD644 For further applications information the reader is referred to Figure 15. Digitally Controlled Dual Telephone Attenuator Analog Devices Application Note on the AD7528. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Cerdip (Q-20) 20-Lead Plastic DIP (N-20) 11 1.07 (27.18) MAX 20 0.28 (7.11) 20 11 PIN 1 0.24 (6.1) 0.255 (6.477) 110 0.245 (6.223) 110 0.32 (8.128) 0.32 (8.128) 0.97 (24.64) 0.30 (7.62) 0.29 (7.366) PIN 1 0.935 (23.75) 0.135 (3.429) 0.14 (3.56) 0.145 (3.683) 0.20 (5.0) 0.125 (3.17) MIN 0.125 (3.17) 0.14 (3.56) 0.125 (3.175) 0.15 (3.8) MIN SEATING SEATING 0.011 (0.28) 0.125 (3.18) PLANE PLANE 0.011 (0.28) 0.11 (2.79) 0.065 (1.66) 0.021 (0.533) 158 0.009 (0.23) 0.07 (1.78) 0.02 (0.5) 0.11 (2.79) 158 0.009 (0.23) 0.09 (2.28) 0.045 (1.15) 0.015 (0.381) 08 0.05 (1.27) 0.016 (0.41) 0.09 (2.28) 08 LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42 LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42 20-Lead SOIC (R-20) 20-Lead Plastic Leaded Chip Carrier (P-20A) 0.5118 (13.00) 0.180 (4.47) 0.4961 (12.60) 0.165 (4.19) 0.395 (10.02) SQ 0.385 (9.78) 0.12 (3.05) 20 11 0.356 (9.04) 0.09 (2.29) SQ 0.350 (8.89) 0.2992 (7.60) 0.020 (0.51) MIN 0.048 (1.21) 0.2914 (7.40) 3 19 0.021 (0.53) 0.042 (1.07) 4 PIN 1 18 0.4193 (10.65) IDENTIFIER 0.013 (0.33) 0.050 1 10 0.3937 (10.00) (1.27) TOP VIEW BSC 0.032 (0.81) (PINS DOWN) 0.026 (0.66) 8 14 0.02 PIN 1 9 13 0.1043 (2.65) (0.51) 0.0291 (0.74) MAX 0.0926 (2.35) 3 458 0.025 (0.64) 0.0098 (0.25) 0.02 (0.51) MIN MAX 0.060 (1.53) MIN 88 0.0118 (0.30) 0.0500 0.0192 (0.49) 08 0.0500 (1.27) SEATING 0.0125 (0.32) (1.27) 0.0138 (0.35) 0.0040 (0.10) PLANE 0.0157 (0.40) BSC 0.0091 (0.23) –8– REV. B PRINTED IN U.S.A. C681e–0–9/98