ANALOG DEVICES AD7524

CMOS a 8-Bit Buffered Multiplying DAC AD7524 FEATURES FUNCTIONAL BLOCK DIAGRAM Microprocessor Compatible (6800, 8085, Z80, Etc.) TTL/CMOS Compatible Inputs On-Chip Data Latches Endpoint Linearity Low Power Consumption Monotonicity Guaranteed (Full Temperature Range) Latch Free (No Protection Schottky Required) APPLICATIONS Microprocessor Controlled Gain Circuits Microprocessor Controlled Attenuator Circuits Microprocessor Controlled Function Generation Precision AGC Circuits Bus Structured Instruments GENERAL DESCRIPTION The AD7524 is a low cost, 8-bit monolithic CMOS DAC designed for direct interface to most microprocessors. ORDERING GUIDE Basically an 8-bit DAC with input latches, the AD7524’s load Temperature Nonlinearity Package cycle is similar to the “write” cycle of a random access 1 2 Model Range (V = +15 V) Option DD memory. Using an advanced thin-film on CMOS fabrication process, the AD7524 provides accuracy to 1/8 LSB with a typi- AD7524JN –40°C to +85°C ±1/2 LSB N-16 cal power dissipation of less than 10 milliwatts. AD7524KN –40°C to +85°C ±1/4 LSB N-16 AD7524LN –40°C to +85°C ±1/8 LSB N-16 A newly improved design eliminates the protection Schottky AD7524JP –40°C to +85°C ±1/2 LSB P-20A previously required and guarantees TTL compatibility when AD7524KP –40°C to +85°C ±1/4 LSB P-20A using a +5 V supply. Loading speed has been increased for AD7524LP –40°C to +85°C ±1/8 LSB P-20A compatibility with most microprocessors. AD7524JR –40°C to +85°C ±1/2 LSB R-16A Featuring operation from +5 V to +15 V, the AD7524 inter- AD7524AQ –40°C to +85°C ±1/2 LSB Q-16 faces directly to most microprocessor buses or output ports. AD7524BQ –40°C to +85°C ±1/4 LSB Q-16 Excellent multiplying characteristics (2- or 4-quadrant) make AD7524CQ –40°C to +85°C ±1/8 LSB Q-16 the AD7524 an ideal choice for many microprocessor con- AD7524SQ –55°C to +125°C ±1/2 LSB Q-16 trolled gain setting and signal control applications. AD7524TQ –55°C to +125°C ±1/4 LSB Q-16 AD7524UQ –55°C to +125°C ±1/8 LSB Q-16 AD7524SE –55°C to +125°C ±1/2 LSB E-20A AD7524TE –55°C to +125°C ±1/4 LSB E-20A AD7524UE –55°C to +125°C ±1/8 LSB E-20A NOTES 1 To order MIL-STD-883, Class B processed parts, add/883B to part number. Contact your local sales office for military data sheet. For U.S. Standard Military Drawing (SMD) see DESC drawing #5962-87700. 2 E = Leadless Ceramic Chip Carrier: N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 (V = +10 V, V = V = 0 V, unless otherwise noted) REF OUT1 OUT2 AD7524–SPECIFICATIONS 1 Limit, T = +258C Limit, T , T A MIN MAX Parameter V = +5 V V = +15 V V = 5 V V = +15 V Units Test Conditions/Comments DD DD DD DD STATIC PERFORMANCE Resolution 8 8 8 8 Bits Relative Accuracy J, A, S Versions ±1/2 ±1/2 ±1/2 ±1/2 LSB max K, B, T Versions ±1/2 ±1/4 ±1/2 ±1/4 LSB max L, C, U Versions ±1/2 ±1/8 ±1/2 ±1/8 LSB max Monotonicity Guaranteed Guaranteed Guaranteed Guaranteed 2 Gain Error ±2 1/2 ±1 1/4 ±3 1/2 ±1 1/2 LSB max 3 Average Gain TC ±40 ±10 ±40 ±10 ppm/°C Gain TC Measured from +25°C to T or from +25°C to T MIN MAX 3 DC Supply Rejection, ΔGain/ΔV 0.08 0.02 0.16 0.04 % FSR/% max ΔV = ±10% DD DD 0.002 0.001 0.01 0.005 % FSR/% typ Output Leakage Current I (Pin 1) ±50 ±50 ±400 ±200 nA max DB0–DB7 = 0 V; WR, CS = 0 V; V = ±10 V OUT1 REF I (Pin 2) ±50 ±50 ±400 ±200 nA max DB0–DB7 = V ; WR, CS = 0 V; V = ±10 V OUT2 DD REF DYNAMIC PERFORMANCE 3 Output Current Settling Time (to 1/2 LSB) 400 250 500 350 ns max OUT1 Load = 100 Ω, C = 13 pF; WR, CS = EXT 0 V; DB0–DB7 = 0 V to V to 0 V. DD 3 AC Feedthrough at OUT1 0.25 0.25 0.5 0.5 % FSR max V = ±10 V, 100 kHz Sine Wave; DB0–DB7 = REF at OUT2 0.25 0.25 0.5 0.5 % FSR max 0 V; WR, CS = 0 V REFERENCE INPUT 4 R (Pin 15 to GND) 5 555 kΩ min IN 20 20 20 20 kΩ max ANALOG OUTPUTS 3 Output Capacitance C (Pin 1) 120 120 120 120 pF max DB0–DB7 = V ; WR, CS = 0 V OUT1 DD C (Pin 2) 30 30 30 30 pF max OUT2 C (Pin 1) 30 30 30 30 pF max DB0–DB7 = 0 V; WR, CS = 0 V OUT1 C (Pin 2) 120 120 120 120 pF max OUT2 DIGITAL INPUTS Input HIGH Voltage Requirement V +2.4 +13.5 +2.4 +13.5 V min IH Input LOW Voltage Requirement V +0.8 +1.5 +0.5 +1.5 V max IL Input Current I ±1 ±1 ±10 ±10 μA max V = 0 V or V IN IN DD 3 Input Capacitance DB0–DB7 5 5 5 5 pF max V = 0 V IN WR, CS 20 20 20 20 pF max V = 0 V IN SWITCHING CHARACTERISTICS 5 Chip Select to Write Setup Time See Timing Diagram t t = t CS WR CS AD7524J, K, L, A, B, C 170 100 220 130 ns min AD7524S, T, U 170 100 240 150 ns min Chip Select to Write Hold Time t CH All Grades 0 0 0 0 ns min Write Pulse Width t t ≥ t , t ≥ 0 WR CS WR CH AD7524J, K, L, A, B, C 170 100 220 130 ns min AD7524S, T, U 170 100 240 150 ns min Data Setup Time t DS AD7524J, K, L, A, B, C 135 60 170 80 ns min AD7524S, T, U 135 60 170 100 ns min Data Hold Time t DH All Grades 10 10 10 10 ns min POWER SUPPLY I 1 2 2 2 mA max All Digital Inputs V or V DD IL IH 100 100 500 500 μA max All Digital Inputs 0 V or V DD NOTES 1 Temperature ranges as follows: J, K, L versions: –40°C to +85°C A, B, C versions: –40°C to +85°C S, T, U versions: –55°C to +125°C 2 Gain error is measured using internal feedback resistor. Full-Scale Range (FSR) = V . REF 3 Guaranteed not tested. 4 DAC thin-film resistor temperature coefficient is approximately –300 ppm/°C. 5 AC parameter, sample tested @ +25°C to ensure conformance to specification. Specifications subject to change without notice. –2– REV. B AD7524 ABSOLUTE MAXIMUM RATINGS* Power Dissipation (Any Package) (T = +25°C, unless otherwise noted) A To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Derates above 75°C by . . . . . . . . . . . . . . . . . . . . 6 mW/°C V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V DD Operating Temperature V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V RFB Commercial (J, K, L) . . . . . . . . . . . . . . . . . –40°C to +85°C V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V REF Industrial (A, B, C) . . . . . . . . . . . . . . . . . . –40°C to +85°C Digital Input Voltage to GND . . . . . . . . –0.3 V to V +0.3 V DD Extended (S, T, U) . . . . . . . . . . . . . . . . . –55°C to +125°C OUT1, OUT2 to GND . . . . . . . . . . . . . –0.3 V to V +0.3 V DD Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C *Stresses above those listed under “Absolute Maximum Ratings” may cause Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7524 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. TERMINOLOGY with all 1s in the DAC after offset error has been adjusted out and is expressed in LSBs. Gain Error is adjustable to zero with RELATIVE ACCURACY: A measure of the deviation from a an external potentiometer. straight line through the end points of the DAC transfer function. Normally expressed as a percentage of full scale range. For the FEEDTHROUGH ERROR: Error caused by capacitive cou- AD7524 DAC, this holds true over the entire V range. REF pling from V to output with all switches OFF. REF RESOLUTION: Value of the LSB. For example, a unipolar con- OUTPUT CAPACITANCE: Capacity from OUT1 and –n verter with n bits has a resolution of (2 ) (V ). A bipolar con- REF OUT2 terminals to ground. –(n–1) verter of n bits has a resolution of [2 ] [V ]. Resolution in no REF OUTPUT LEAKAGE CURRENT: Current which appears way implies linearity. on OUT1 terminal with all digital inputs LOW or on OUT2 GAIN ERROR: Gain Error is a measure of the output error be- terminal when all inputs are HIGH. This is an error current tween an ideal DAC and the actual device output. It is measured which contributes an offset voltage at the amplifier output. PIN CONFIGURATIONS DIP, SOIC PLCC LCCC REV. B –3– AD7524 WRITE MODE CIRCUIT DESCRIPTION When CS and WR are both LOW, the AD7524 is in the CIRCUIT INFORMATION WRITE mode, and the AD7524 analog output responds to data The AD7524, an 8-bit multiplying D/A converter, consists of a activity at the DB0–DB7 data bus inputs. In this mode, the highly stable thin film R-2R ladder and eight N-channel current AD7524 acts like a nonlatched input D/A converter. switches on a monolithic chip. Most applications require the addition of only an output operational amplifier and a voltage HOLD MODE or current reference. When either CS or WR is HIGH, the AD7524 is in the HOLD The simplified D/A circuit is shown in Figure 1. An inverted mode. The AD7524 analog output holds the value correspond- R-2R ladder structure is used—that is, the binarily weighted ing to the last digital input present at DB0–DB7 prior to WR or currents are switched between the OUT1 and OUT2 bus lines, CS assuming the HIGH state. thus maintaining a constant current in each ladder leg indepen- dent of the switch state. MODE SELECTION TABLE CS WR Mode DAC Response L L Write DAC responds to data bus (DB0–DB7) inputs. H X Hold Data bus (DB0–DB7) is Locked Out: X H Hold DAC holds last data present when WR or CS assumed HIGH state. L = Low State, H = High State, X = Don't Care. WRITE CYCLE TIMING DIAGRAM Figure 1. Functional Diagram EQUIVALENT CIRCUIT ANALYSIS The equivalent circuit for all digital inputs LOW is shown in Figures 2. In Figure 2 with all digital inputs LOW, the refer- ence current is switched to OUT2. The current source I LEAKAGE is composed of surface and junction leakages to the substrate 1 while the current source represents a constant 1-bit cur- 256 rent drain through the termination resistor on the R-2R ladder. The “ON” capacitance of the output N-channel switches is 120 pF, as shown on the OUT2 terminal. The “OFF” switch capacitance is 30 pF, as shown on the OUT1 terminal. Analysis of the circuit for all digital inputs high is similar to Figure 2 however, the “ON” switches are now on terminal OUT1, hence the 120 pF appears at that terminal. Figure 2. AD7524 DAC Equivalent Circuit—All Digital Inputs Low INTERFACE LOGIC INFORMATION Figure 3. Supply Current vs. Logic Level MODE SELECTION Typical plots of supply current, I , versus logic input voltage, DD AD7524 mode selection is controlled by the CS and WR inputs. V , for V = +5 V and V = +15 V are shown above. IN DD DD –4– REV. B AD7524 ANALOG CIRCUIT CONNECTIONS AD7524 AD7524 Figure 5. Bipolar (4-Quadrant) Operation Figure 4. Unipolar Binary Operation (2-Quadrant Multiplication) Table II. Bipolar (Offset Binary) Code Table Table I. Unipolar Binary Code Table Digital Input Digital Input MSB LSB Analog Output MSB LSB Analog Output 1111 1111 –V (255/256) 1111 1111 +V (127/128) REF REF 1000 0001 –V (129/256) 1000 0001 +V (1/128 ) REF REF 1000 0000 –V (128/256) = –V /2 1000 0000 0 REF REF 0111 1111 –V (127/256) 0111 1111 –V (1/128) REF REF 0000 0001 –V (1/256) 0000 0001 –V (127/128) REF REF 0000 0000 –V (0/256) = 0 0000 0000 –V (128/128) REF REF –8 –7 Note: 1 LSB = (2 )(V ) = 1/256 (V ) Note: 1 LSB = (2 )(V ) = 1/128 (V ) REF REF REF REF MICROPROCESSOR INTERFACE Figure 6. AD7524/8085A Interface Figure 7. AD7524/MC6800 Interface REV. B –5– AD7524 POWER GENERATION Figure 8. –6– REV. B AD7524 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Terminal Ceramic Leadless Chip Carrier 20-Lead Plastic Leadless Chip Carrier (PLCC) (E-20A) (P-20A) 0.200 (5.08) 0.180 (4.57) 0.075 BSC 0.165 (4.19) 0.100 (2.54) 0.048 (1.21) (1.91) 0.064 (1.63) 0.100 (2.54) BSC 0.056 (1.42) REF 0.042 (1.07) 0.025 (0.63) 0.042 (1.07) 0.015 (0.38) 0.015 (0.38) 0.095 (2.41) 0.048 (1.21) 19 3 MIN 3 19 20 0.075 (1.90) 18 4 0.042 (1.07) 0.021 (0.53) 0.028 (0.71) 4 PIN 1 18 0.358 0.358 (9.09) 1 0.050 IDENTIFIER 0.013 (0.33) 0.011 (0.28) 0.330 (8.38) (9.09) 0.022 (0.56) BOTTOM (1.27) 0.342 (8.69) 0.007 (0.18) MAX TOP VIEW 0.032 (0.81) VIEW 0.290 (7.37) BSC SQ 0.050 (1.27) (PINS DOWN) SQ R TYP 0.026 (0.66) 14 8 BSC 8 14 0.075 (1.91) 13 9 9 13 REF 0.020 0.040 (1.01) 45° TYP (0.50) 0.356 (9.04) 0.025 (0.64) 0.088 (2.24) 0.055 (1.40) SQ 0.150 (3.81) R 0.350 (8.89) BSC 0.054 (1.37) 0.045 (1.14) 0.110 (2.79) 0.395 (10.02) SQ 0.085 (2.16) 0.385 (9.78) 16-Lead Plastic DIP (Narrow) 16-Lead Cerdip (N-16) (Q-16) 0.840 (21.33) 0.005 (0.13) MIN 0.080 (2.03) MAX 0.745 (18.93) 16 9 16 9 0.310 (7.87) 0.280 (7.11) 0.220 (5.59) 0.240 (6.10) 18 1 8 0.325 (8.25) 0.320 (8.13) 0.195 (4.95) PIN 1 0.060 (1.52) 0.300 (7.62) 0.290 (7.37) PIN 1 0.115 (2.93) 0.015 (0.38) 0.840 (21.34) MAX 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) 0.200 (5.08) MAX MAX 0.130 0.150 (3.30) (3.81) 0.160 (4.06) 0.200 (5.08) MIN MIN 0.115 (2.93) 0.125 (3.18) 0.015 (0.381) 0.015 (0.38) SEATING 0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.023 (0.58) 0.100 0.070 (1.78) 0.008 (0.204) 15° PLANE 0.008 (0.20) PLANE (2.54) (2.54) 0.045 (1.15) 0.014 (0.36) 0.014 (0.356) 0.030 (0.76) 0° BSC BSC 16-Lead Narrow-Body (SOIC) (R-16A) 0.3937 (10.00) 0.3859 (9.80) 16 9 0.1574 (4.00) 0.2550 (6.20) 1 8 0.1497 (5.80) 0.2284 (5.80) 0.0688 (1.75) PIN 1 0.0196 (0.50) x 45° 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25) 0.0040 (0.10) 8° 0.0500 0.0192 (0.49) 0° SEATING 0.0500 (1.27) 0.0099 (0.25) (1.27) 0.0138 (0.35) PLANE BSC 0.0160 (0.41) 0.0075 (0.19) REV. B –7– –8– PRINTED IN U.S.A. C542e–5–11/86