ANALOG DEVICES AD7495

1 MSPS,12-Bit ADCs AD7475/AD7495 FUNCTIONAL BLOCK DIAGRAMS FEATURES AND APPLICATIONS Fast throughput rate: 1 MSPS V DD Specified for V of 2.7 V to 5.25 V DD 12-BIT Low power: T/H V IN SUCCESSIVE APPROXIMATION 4.5 mW max at 1 MSPS with 3 V supplies REF IN ADC 10.5 mW max at 1 MSPS with 5 V supplies Wide input bandwidth: SCLK 68 dB SNR at 300 kHz input frequency CONTROL SDATA LOGIC Flexible power/serial clock speed management CS No pipeline delays V DRIVE High speed serial interface: AD7475 SPI™-/QSPI™-/MICROWIRE™-/DSP-compatible GND On-board reference: 2.5 V (AD7495 only) V DD Standby mode: 1 μA max 8-lead MSOP and SOIC packages 12-BIT T/H V IN SUCCESSIVE APPROXIMATION ADC Battery-powered systems REF OUT Personal digital assistants BUF Medical instruments SCLK CONTROL SDATA Mobile communications LOGIC 2.5V REFERENCE CS Instrumentation and control systems Data acquisition systems V DRIVE AD7495 Optical sensors GND GENERAL DESCRIPTION Figure 1. 1 The AD7475/AD7495 are 12-bit, high speed, low power, PRODUCT HIGHLIGHTS successive-approximation ADCs that operate from a single 2.7 V to 5.25 V power supply with throughput rates up to 1. The AD7475 offers 1 MSPS throughput rates with 4.5 mW 1 MSPS. They contain a low noise, wide bandwidth track-and- power consumption. hold amplifier that can handle input frequencies above 1 MHz. 2. Single-supply operation with V function. The DRIVE The conversion process and data acquisition are controlled AD7475/AD7495 operate from a single 2.7 V to 5.25 V using and the serial clock, allowing the devices to interface CS supply. The V function allows the serial interface DRIVE with microprocessors or DSPs. The input signal is sampled on to connect directly to either 3 V or 5 V processor systems the falling edge of CS and conversion is initiated at this point. independent of VDD. The conversion time is determined by the SCLK frequency. 3. Flexible power/serial clock speed management. The con- There are no pipeline delays associated with the part. version rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock The AD7475/AD7495 use advanced design techniques to speed increase. The parts also feature shutdown modes to achieve very low power dissipation at high throughput rates. maximize power efficiency at lower throughput rates. This With 3 V supplies and a 1 MSPS throughput rate, the AD7475 allows the average power consumption to be reduced while consumes just 1.5 mA, while the AD7495 consumes 2 mA. not converting. Power consumption is 1 μA when in full With 5 V supplies and 1 MSPS, the current consumption is shutdown. 2.1 mA for the AD7475 and 2.6 mA for the AD7495. 4. No pipeline delay. The parts feature a standard successive The analog input range for the parts is 0 V to REF IN. The 2.5 V approximation ADC with accurate control of the sampling reference for the AD7475 is applied externally to the REF IN instant via a CS input and once-off conversion control. pin, while the AD7495 has an on-board 2.5 V reference. 1 Protected by U.S. Patent No. 6,681,332 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. 01684-B-001 AD7475/AD7495 TABLE OF CONTENTS AD7475 Specifications..................................................................... 3 Operating Modes............................................................................ 16 AD7495 Specifications..................................................................... 5 Normal Mode.............................................................................. 16 Timing Specifications....................................................................... 7 Partial Power-Down Mode ....................................................... 16 Timing Example 1 ........................................................................ 8 Full Power-Down Mode ............................................................ 17 Timing Example 2 ........................................................................ 8 Power vs. Throughput Rate....................................................... 19 Absolute Maximum Ratings............................................................ 9 Serial Interface ................................................................................ 20 ESD Caution.................................................................................. 9 Microprocessor Interfacing........................................................... 21 Pin Configuration and Function Descriptions........................... 10 AD7475/AD7495 to TMS320C5X/C54X................................. 21 Terminology .................................................................................... 11 AD7475/AD7495 to ADSP-21XX ............................................. 21 Typical Performance Curves ......................................................... 12 AD7475/AD7495 to DSP56XXX ............................................... 22 Theory of Operation ...................................................................... 13 AD7475/AD7495 to MC68HC16............................................. 22 Converter Operation.................................................................. 13 Outline Dimensions ....................................................................... 23 ADC Transfer Function............................................................. 13 Ordering Guide .......................................................................... 24 Typical Connection Diagram ................................................... 14 REVISION HISTORY 5/05—Rev. A to Rev. B Updated Format..................................................................Universal Added Patent Information .............................................................. 1 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 24 Rev. B | Page 2 of 24 AD7475/AD7495 AD7475 SPECIFICATIONS VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. 1 1 Parameter A Version B VersionUnit Test Conditions/Comments DYNAMIC PERFORMANCE 68 68 dB min f = 300 kHz sine wave, f = 1 MSPS Signal-to-Noise and Distortion IN SAMPLE Ratio (SINAD) Total Harmonic Distortion (THD) −75 −75 dB max fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS Peak Harmonic or Spurious Noise −76 −76 dB max fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS (SFDR) Intermodulation Distortion (IMD) Second-Order Terms −78 −78 dB typ Third-Order Terms −78 −78 dB typ Aperture Delay 10 10 ns typ Aperture Jitter 50 50 ps typ Full Power Bandwidth 8.3 8.3 MHz typ @ 3 dB Full Power Bandwidth 1.3 1.3 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 12 Bits Integral Nonlinearity ±1.5 ±1 LSB max @ 5 V (typ @ 3 V) ±0.5 ±0.5 LSB typ @ 25°C Differential Nonlinearity +1.5/−0.9 +1.5/−0.9 LSB max @ 5 V guaranteed no missed codes to 12 bits (typ @ 3 V) ±0.5 ±0.5 LSB typ @ 25°C Offset Error ±8 ±8 LSB max Typically ±2.5 LSB Gain Error ±3 ±3 LSB max ANALOG INPUT Input Voltage Ranges 0 to REF IN V DC Leakage Current ±1 ±1 μA max Input Capacitance 20 20 pF typ REFERENCE INPUT REF IN Input Voltage Range 2.5 2.5 V ±1% for specified performance DC Leakage Current ±1 ±1 μA max Input Capacitance 20 20 pF typ LOGIC INPUTS Input High Voltage, VINH VDRIVE − 1 VDRIVE − 1 V min Input Low Voltage, VINL 0.4 0.4 V max Input Current, I ±1 ±1 μA max Typically 10 nA, V = 0 V or V IN IN DRIVE 2 Input Capacitance, C 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 μA; V = 2.7 V to 5.25 V OH DRIVE SOURCE DRIVE Output Low Voltage, V 0.4 0.4 V max I = 200 μA OL SINK Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance10 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 800 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 300 ns max Sine wave input 325 325 ns max Full-scale step input Throughput Rate 1 1 MSPS max See the Serial Interface section Rev. B | Page 3 of 24 AD7475/AD7495 1 1 Parameter A Version B VersionUnit Test Conditions/Comments POWER REQUIREMENTS VDD 2.7/5.25 2.7/5.25 V min/max VDRIVE 2.7/5.25 2.7/5.25 V min/max 3 I Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 750 750 μA typ V = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.1 2.1 mA max V = 4.75 V to 5.25 V, f = 1 MSPS DD SAMPLE 1.5 1.5 mA max VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS Partial Power-Down Mode 450 450 μA typ fSAMPLE = 100 kSPS Partial Power-Down Mode 100 100 μA max Static Full Power-Down Mode 1 1 μA max SCLK on or off Power Dissipation Normal Mode (Operational) 10.5 10.5 mW max VDD = 5 V, fSAMPLE = 1 MSPS 4.5 4.5 mW max VDD = 3 V, fSAMPLE = 1 MSPS Partial Power-Down (Static) 500 500 μW max VDD = 5 V 300 300 μW max V = 3 V DD Full Power-Down 5 5 μW max V = 5 V DD 3 3 μW max V = 3 V DD 1 Temperature ranges for A, B versions: −40°C to +85°C. 2 Guaranteed by initial characterization. 3 See the Power vs. Throughput Rate section. Rev. B | Page 4 of 24 AD7475/AD7495 AD7495 SPECIFICATIONS VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 2. 1 1 Parameter A Version B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE Signal-to-Noise and Distortion (SINAD) 68 68 dB min f = 300 kHz sine wave, f = 1 MSPS IN SAMPLE Total Harmonic Distortion (THD) −75 −75 dB max fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS Peak Harmonic or Spurious Noise −76 −76 dB max fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS (SFDR) Intermodulation Distortion (IMD) Second-Order Terms −78 −78 dB typ Third-Order Terms −78 −78 dB typ Aperture Delay 10 10 ns typ Aperture Jitter 50 50 ps typ Full Power Bandwidth 8.3 8.3 MHz typ @ 3 dB Full Power Bandwidth 1.3 1.3 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 12 Bits Integral Nonlinearity ±1.5 ±1 LSB max @ 5 V (typ @ 3 V) ±0.5 ±0.5 LSB typ @ 25°C Differential Nonlinearity +1.5/−0.9 +1.5/−0.9 LSB max @ 5 V guaranteed no missed codes to 12 bits (typ @ 3 V) ±0.6 ±0.6 LSB typ @ 25°C Offset Error ±8 ±8 LSB max Typically ±2.5 LSB Gain Error ±7 ±7 LSB max Typically ±2.5 LSB ANALOG INPUT Input Voltage Ranges 0 to 2.5 0 to 2.5 V DC Leakage Current ±1 ±1 μA max Input Capacitance 20 20 pF typ REFERENCE OUTPUT REF OUT Output Voltage 2.4625/2.5375 2.4625/2.5375 V min/max REF OUT Impedance 10 10 Ω typ REF OUT Temperature Coefficient 50 50 ppm/°C typ LOGIC INPUTS Input High Voltage, VINH VDRIVE − 1 VDRIVE − 1 V min Input Low Voltage, VINL 0.4 0.4 V max Input Current, IIN ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDRIVE 2 Input Capacitance, C 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min ISOURCE = 200 μA; VDD = 2.7 V to 5.25 V Output Low Voltage, V 0.4 0.4 V max I = 200 μA OL SINK Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance10 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 800 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 300 ns max Sine wave input 325 325 ns max Full-scale step input Throughput Rate 1 1 MSPS max See the Serial Interface section Rev. B | Page 5 of 24 AD7475/AD7495 1 1 Parameter A Version B Version Unit Test Conditions/Comments POWER REQUIREMENTS VDD 2.7/5.25 2.7/5.25 V min/max VDRIVE 2.7/5.25 2.7/5.25 V min/max I Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 1 1 mA typ V = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.6 2.6 mA max V = 4.75 V to 5.25 V, f = 1 MSPS DD SAMPLE 2 2 mA max VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS Partial Power-Down Mode 650 650 μA typ fSAMPLE = 100 kSPS Partial Power-Down Mode 230 230 μA max Static Full Power-Down Mode 1 1 μA max Static, SCLK on or off 3 Power Dissipation Normal Mode (Operational) 13 13 mW max VDD = 5 V, fSAMPLE = 1 MSPS 6 6 mW max VDD = 3 V, fSAMPLE = 1 MSPS Partial Power-Down (Static) 1.15 1.15 mW max VDD = 5 V 690 690 μW max V = 3 V DD Full Power-Down 5 5 μW max V = 5 V DD 3 3 μW max V = 3 V DD 1 Temperature ranges for A, B versions: −40°C to +85°C. 2 Guaranteed by initial characterization. 3 See the Power vs. Throughput Rate section. Rev. B | Page 6 of 24 AD7475/AD7495 1 TIMING SPECIFICATIONS VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475), TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter Limit at TMIN, TMAX Unit Description 2 f 10 kHz min SCLK 20 MHz max tCONVERT 16 × tSCLK tSCLK = 1/fSCLK 800 ns max fSCLK = 20 MHz tQUIET 100 ns min Minimum quiet time required between conversions t 10 ns min CS to SCLK setup time 2 3 t 22 ns max Delay from CS until SDATA three-state disabled 3 t4 40 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK low pulse width t6 0.4 tSCLK ns min SCLK high pulse width t 10 ns min SCLK to data valid hold time 7 4 t 10 ns min SCLK falling edge to SDATA high impedance 8 45 ns max SCLK falling edge to SDATA high impedance t9 20 ns max CS rising edge to SDATA high impedance tPOWER-UP 20 μs max Power-up time from full power-down (AD7475) 650 μs max Power-up time from full power-down (AD7495) 1 Guaranteed by initial characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t and t are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is 8 9 extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are the true bus relinquish times of the part and are independent of the bus loading. Rev. B | Page 7 of 24 AD7475/AD7495 TIMING EXAMPLE 1 TIMING EXAMPLE 2 With fSCLK = 20 MHz and a throughput of 1 MSPS, the cycle With fSCLK = 5 MHz and a throughput of 315 KSPS, the cycle time is t2 + 12.5(1/fSCLK) + tACQ = 1 μs. With t2 = 10 ns min, tACQ time is t2 + 12.5(1/fSCLK) + tACQ = 3.174 μs. With t2 = 10 ns min, is 365 ns. The 365 ns satisfies the requirement of 300 ns for tACQ. tACQ is 664 ns. The 664 ns satisfies the requirement of 300 ns for In Figure 3, t comprises 2.5(1/f ) + t + t , where t = t . In Figure 3, t comprises 2.5(1/f ) + t8 + t , where ACQ SCLK 8 QUIET 8 ACQ ACQ SCLK QUIET 45 ns. This allows a value of 195 ns for t , satisfying the t8 = 45 ns. This allows a value of 119 ns for t , satisfying the QUIET QUIET minimum requirement of 100 ns. minimum requirement of 100 ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 100 ns minimum tQUIET between conversions. In Example 2, the signal should be fully acquired at approximately Point C in Figure 3. CS t CONVERT t t 6 B 2 4 1 2 3 5 13 14 15 16 SCLK t 5 t 7 t t 8 QUIET t t 4 3 0 0 SDATA 0 0 DB11 DB10 DB2 DB1 DB0 THREE-STATE THREE-STATE FOUR LEADING ZEROS Figure 2. Serial Interface Timing Diagram CS t CONVERT t t 6 B C 2 1 2 3 4 5 13 14 15 16 SCLK t 5 t t 8 QUIET 45ns 12.5 (1/f ) SCLK t ACQUISITION 10ns 1/THROUGHPUT Figure 3. Serial Interface Timing Example 200μA I OL TO OUTPUT 1.6V PIN C L 50pF 200μA I OH Figure 4. Load Circuit for Digital Output Timing Specifications Rev. B | Page 8 of 24 01684-B-004 01684-B-003 01684-B-002 AD7475/AD7495 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Table 4. Stresses above those listed under Absolute Maximum Ratings Parameters Ratings may cause permanent damage to the device. This is a stress V to GND −0.3 V to +7 V DD rating only; functional operation of the device at these or any VDRIVE to GND −0.3 V to +7 V other conditions above those listed in the operational sections Analog Input Voltage to GND −0.3 V to VDD + 0.3 V of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to +7 V maximum rating conditions for extended periods may affect V to V −0.3 V to V + 0.3 V DRIVE DD DD device reliability. Digital Output Voltage to GND −0.3 V to V + 0.3 V DRIVE REF IN to GND −0.3 V to V + 0.3 V DD Input Current to Any Pin Except ±10 mA 1 Supplies Operating Temperature Range Commercial (A, B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C SOIC, MSOP Package, Power Dissipation 450 mW θJA Thermal Impedance 157°C/W (SOIC) 205.9°C/W (MSOP) θ Thermal Impedance 56°C/W (SOIC) JC 43.74°C/W (MSOP) Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 4 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 9 of 24 AD7475/AD7495 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF IN 1 8 V DD AD7475 V 2 7 CS IN TOP VIEW GND 3 6 V DRIVE (Not to Scale) SCLK 4 5 SDATA Figure 5. AD7475 SOIC/MSOP Pin Configuration REF OUT 1 8 V DD AD7495 V 2 7 CS IN TOP VIEW GND 3 6 V (Not to Scale) DRIVE SCLK 4 5 SDATA Figure 6. AD7495 SOIC/MSOP Pin Configuration Table 5. Pin Descriptions Pin No. Mnemonic Function 1 (AD7475) REF IN Reference Input for the AD7475. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. A cap of a least 0.1 μF should be placed on the REF IN pin. 1 (AD7495) REF OUT Reference Output for the AD7495. A minimum 100 nF capacitance is required from this pin to GND. The internal reference can be taken from this pin, but buffering is required before it is applied elsewhere in a system. 2 V Analog Input. Single-ended analog input channel. The input range is 0 to REF IN. IN 3 GND Analog Ground. Ground reference point for all circuitry on the AD7475/AD7495. All analog input signals and any external reference signal should be referred to this GND voltage. 4 SCLK Serial Clock, Logic Input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7475/AD7495 conversion process. 5 SDATA Data Out, Logic Output. The conversion result from the AD7475/AD7495 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. 6 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage for the serial interface of the AD7475/AD7495. 7 CS Chip Select, Active Low Logic Input. This input provides the dual function of initiating conversions on the AD7475/AD7495 and also frames the serial data transfer. 8 V Power Supply Input. The V range for the AD7475/AD7495 is from 2.7 V to 5.25 V. DD DD Rev. B | Page 10 of 24 01684-B-005 01684-B-006 AD7475/AD7495 TERMINOLOGY Integral Nonlinearity Total Harmonic Distortion (THD) The maximum deviation from a straight line passing through The ratio of the rms sum of harmonics to the fundamental. For the endpoints of the ADC transfer function. The endpoints of the AD7475/AD7495, THD is defined as the transfer function are zero scale, a point ½ LSB below the 2 2 2 2 2 first code transition, and full scale, a point ½ LSB above the last V +V +V +V +V 2 3 4 5 6 THD() dB = 20 log code transition. V 1 Differential Nonlinearity where V1 is the rms amplitude of the fundamental and V2, V3, The difference between the measured and the ideal 1 LSB V4, V5, and V6 are the rms amplitudes of the second through the change between any two adjacent codes in the ADC. sixth harmonics. Offset Error Peak Harmonic or Spurious Noise The deviation of the first code transition (00 . . . 000) to The ratio of the rms value of the next largest component in (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. the ADC output spectrum (up to f /2 and excluding dc) to S the rms value of the fundamental. Normally, the value of this Gain Error specification is determined by the largest harmonic in the This is the deviation of the last code transition (111. . . 110) to spectrum, but for ADCs where the harmonics are buried in (111. . . 111) from the ideal (that is, V − 1.5 LSB) after the REF the noise floor, it is a noise peak. offset error has been adjusted out. Intermodulation Distortion Track-and-Hold Acquisition Time With inputs consisting of sine waves at two frequencies, fa and The track-and-hold amplifier returns into track mode on the fb, any active device with nonlinearities creates distortion th 13 SCLK rising edge (see the Serial Interface section). The products at sum and difference frequencies of mfa ± nfb where track-and-hold acquisition time is the minimum time required m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for the track-and-hold amplifier to remain in track mode for its for which neither m nor n is equal to zero. For example, the output to reach and settle to within 0.5 LSB of the applied input second-order terms include (fa + fb) and (fa − fb), while the signal, given a step change to the input signal. third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). Signal-to-Noise and Distortion Ratio (SINAD) The measured ratio of signal-to-noise and distortion at the The AD7475/AD7495 are tested using the CCIF standard where output of the analog-to-digital converter (ADC). The signal is two input frequencies near the top end of the input bandwidth the rms amplitude of the fundamental. Noise is the sum of all are used. In this case, the second-order terms are usually nonfundamental signals up to half the sampling frequency distanced in frequency from the original sine waves while the (f /2), excluding dc. The ratio is dependent on the number of S third order terms are usually at a frequency close to the input quantization levels in the digitization process; the more levels, frequencies. As a result, the second- and third-order terms are the smaller the quantization noise. The theoretical SINAD ratio specified separately. Like THD, intermodulation distortion is for an ideal N-bit converter with a sine wave input is given by calculated as the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed Signal to() Noise+ Distortion =(6.02 N+ 1.76) dB in dBs. For a 12-bit converter, the SINAD is 74 dB. Rev. B | Page 11 of 24 AD7475/AD7495 TYPICAL PERFORMANCE CURVES Figure 7 shows a typical FFT plot for the AD7475 at a 1 MHz Figure 9 shows the SINAD performance vs. input frequency for sample rate and a 100 kHz input frequency. various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz. 8192 POINT FFT 71.0 f = 1MSPS SAMPLE –15 f = 100kHz IN SINAD = 70.46dB THD = –87.7dB V = V = 4.75V 70.5 DD DRIVE SFDR = –89.5dB –35 V = V = 3.60V DD DRIVE –55 70.0 –75 V = V = 2.70V DD DRIVE 69.5 V = V = 5.25V DD DRIVE –95 69.0 –115 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (kHz) 68.5 10 100 1000 Figure 7. AD7475 Dynamic Performance INPUT FREQUENCY (kHz) Figure 9. AD7495 SINAD vs. Input Frequency at 1 MSPS Figure 8 shows a typical FFT plot for the AD7495 at a 1 MHz sample rate and a 100 kHz input frequency. 8192 POINT FFT f = 1MSPS SAMPLE –15 f = 100kHz IN SINAD = 69.95dB THD = –89.2dB –35 SFDR = –91.2dB –55 –75 –95 –115 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (kHz) Figure 8. AD7495 Dynamic Performance Rev. B | Page 12 of 24 SINAD (dB) SINAD (dB) 01684-B-008 01684-B-007 SINAD (dB) 01684-B-009 AD7475/AD7495 THEORY OF OPERATION The AD7475/AD7495 are fast, micropower, 12-bit, single- When the ADC starts a conversion (see Figure 11), SW2 opens supply analog-to-digital converters (ADCs). The parts can be and SW1 moves to Position B causing the comparator to operated from a 2.7 V to 5.25 V supply. When operated from become unbalanced. The control logic and the capacitive DAC either a 5 V supply or a 3 V supply, the AD7475/AD7495 are are used to add and subtract fixed amounts of charge from the capable of throughput rates of 1 MSPS when provided with a sampling capacitor to bring the comparator back into a 20 MHz clock. balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC The AD7475/AD7495 ADCs have an on-chip track-and-hold output code. with a serial interface housed in either an 8-lead SOIC_N or MINI_SO package, features that offer the user considerable CAPACITIVE space-saving advantages over alternative solutions. The AD7495 DAC also has an on-chip 2.5 V reference. The serial clock input accesses data from the part but also provides the clock source 4kΩ A V IN for the successive-approximation ADC. The analog input range SW1 B CONTROL LOGIC SW2 is 0 V to REF IN for the AD7475 and 0 V to REF OUT for the COMPARATOR AGND AD7495. Figure 11. ADC Conversion Phase The AD7475/AD7495 also feature power-down options to allow power saving between conversions. The power-down feature is ADC TRANSFER FUNCTION implemented across the standard serial interface, as described The output coding of the AD7475/AD7495 is straight binary. in the Operating Modes section. The designed code transitions occur midway between 3 CONVERTER OPERATION successive LSB integer values (that is, ½ LSB, /2 LSBs, etc.). The LSB size is = VREF/4096. The ideal transfer characteristic for the The AD7475/AD7495 are 12-bit, successive approximation AD7475/AD7495 is shown in Figure 12. analog-to-digital converters based around a capacitive DAC. The AD7475/AD7495 can convert analog input signals in the range 0 V to 2.5 V. Figure 10 and Figure 12 show simplified schematics of the ADC. The ADC comprises control logic, SAR, and a capacitive DAC, which are used to add and subtract fixed 111...111 111...110 amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. Figure 10 shows the 111...000 1LSB = V /4096 REF ADC during its acquisition phase. SW2 is closed and SW1 is in 011...111 Position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on VIN. 000...010 000...001 000...000 CAPACITIVE 0.5LSB 0V V –1.5LSB REF DAC ANALOG INPUT 4kΩ A Figure 12. AD7475/AD7495 Transfer Characteristic V IN B SW1 CONTROL LOGIC SW2 COMPARATOR AGND Figure 10. ADC Acquisition Phase Rev. B | Page 13 of 24 01684-B-010 ADC CODE 01684-B-012 01684-B-011 AD7475/AD7495 Analog Input TYPICAL CONNECTION DIAGRAM Figure 14 shows an equivalent circuit of the analog input Figure 13 and Figure 15 show typical connection diagrams for structure of the AD7475/AD7495. The D1 and D2 diodes the AD7475 and AD7495, respectively. In both setups the GND provide ESD protection for the analog inputs. Care must be pin is connected to the analog ground plane of the system. In taken to ensure that the analog input signal never exceeds the Figure 13, REF IN is connected to a decoupled 2.5 V supply supply rails by more than 200 mV. This causes these diodes to from a reference source, the AD780, to provide an analog input become forward-biased and start conducting current into the range of 0 V to 2.5 V. Although the AD7475 is connected to a substrate. The maximum current these diodes can conduct VDD of 5 V, the serial interface is connected to a 3 V micro- without causing irreversible damage to the part is 20 mA. processor. The VDRIVE pin of the AD7475 is connected to the The capacitor C1 in Figure 14 is typically about 4 pF and can same 3 V supply of the microprocessor to allow a 3 V logic primarily be attributed to pin capacitance. The resistor R1 is a interface (see the Digital Inputs section.) In Figure 15, the REF lumped component made up of the on resistance of a switch. OUT pin of the AD7495 is connected to a buffer and then This resistor is typically about 100 Ω. The capacitor C2 is applied to a level-shifting circuit used on the analog input to the ADC sampling capacitor and has a capacitance of 16 pF, allow a bipolar signal to be applied to the AD7495. A minimum typically. For ac applications, it is recommended to remove 100 nF capacitance is required on the REF OUT pin to GND. high frequency components from the analog input signal The conversion result from both ADCs is output in a 16-bit using an RC low-pass filter on the relevant analog input pin. In word with four leading zeros followed by the MSB of the 12-bit applications where harmonic distortion and signal-to-noise result. For applications where power consumption is of concern, ratio are critical, the analog input should be driven from a low the power-down modes should be used between conversions or impedance source. Large source impedances significantly affect bursts of several conversions to improve power performance. the ac performance of the ADC. This may necessitate the use of See the Operating Modes section for more information. an input buffer amplifier. The choice of the op amp is a function 5V SERIAL SUPPLY of the particular application. INTERFACE 0.1μF 10μF V DD V DD SCLK C2 0V TO D1 16pF 2.5V V IN SDATA R1 AD7475 INPUT μC/μP V IN C1 D2 CS 4pF GND CONVERSION PHASE: SWITCH OPEN V DRIVE TRACK PHASE: SWITCH CLOSED REF IN 0.1μF 10μF 2.5V Figure 14. Equivalent Analog Input Circuit 0.1μF AD780 (MIN) 3V SUPPLY Figure 13. AD7475 Typical Connection Diagram 5V SERIAL SUPPLY INTERFACE 0.1μF 10μF V V 0V TO DD R SCLK R 2.5V 0V V INPUT V IN SDATA 3R AD7495 μC/μP R CS GND V DRIVE REF OUT 0.1μF 10μF 0.1μF (MIN) 3V SUPPLY Figure 15. AD7495 Typical Connection Diagram Rev. B | Page 14 of 24 01684-B-013 01684-B-015 01684-B-014 AD7475/AD7495 V DRIVE When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum The AD7475/AD7495 also has the VDRIVE feature. This feature source impedance depends on the amount of total harmonic controls the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V distortion (THD) that can be tolerated. The THD increases as processors. the source impedance increases and performance degrades. Figure 16 shows a graph of the total harmonic distortion vs. For example, if the AD7475/AD7495 were operated with a V DD source impedance for various analog input frequencies. of 5 V, the V pin could be powered from a 3 V supply. The DRIVE –10 AD7475/AD7495 have better dynamic performance with a V DD of 5 V, while still being able to interface to 3 V digital parts. –20 Care should be taken to ensure VDRIVE does not exceed VDD by –30 f = 10kHz IN more than 0.3 V. (See the Absolute Maximum Ratings section.) –40 f = 500kHz IN Reference Section –50 f = 200kHz An external reference source should be used to supply the 2.5 V IN –60 reference to the AD7475. Errors in the reference source result in gain errors in the AD7475 transfer function and add the –70 specified full-scale errors on the part. The AD7475 voltage f = 100kHz IN –80 reference input, REF IN, has a dynamic input impedance. A small dynamic current is required to charge the capacitors in –90 1 10 100 1000 10000 the capacitive DAC during the bit trials. This current is typically SOURCE IMPEDANCE (Ω) 50 μA for a 2.5 V reference. A capacitor of at least 0.1 μF should be placed on the REF IN pin. Suitable reference sources for the Figure 16. THD vs. Source Impedance for Various Analog Input Frequencies AD7475 are the AD780, AD680, AD1582, ADR391, ADR381, Figure 17 shows a graph of total harmonic distortion vs. analog ADR431, and ADR03. input frequency for various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz. The AD7495 contains an on-chip 2.5 V reference. As shown in Figure 18, the voltage that appears at the REF OUT pin is –75 internally buffered before being applied to the ADC; the output V = V = 5.25V –77 DD DRIVE V = V = 2.70V DD DRIVE impedance of this buffer is typically 10 Ω. The reference is –79 capable of sourcing up to 2 mA. The REF OUT pin should be –81 decoupled to AGND using a 100 nF or greater capacitor. –83 If the 2.5 V internal reference is used to drive another device V = V = 3.60V –85 DD DRIVE that is capable of glitching the reference at critical times, then –87 V = V = 4.75V DD DRIVE the reference has to be buffered before driving the device. To –89 ensure optimum performance of the AD7495, it is recom- –91 mended that the internal reference not be over driven. If an –93 ADC with external reference capability is required, the AD7475 –95 should be used. 10 100 1000 INPUT FREQUENCY (kHz) V Figure 17. THD vs. Analog Input Frequency for Various Supply Voltages REF OUT 25Ω Digital Inputs 40kΩ 160kΩ The digital inputs applied to the AD7475/AD7495 are not limited by the maximum ratings, which limit the analog inputs. Figure 18. AD7495 Reference Circuit Instead, the digital inputs applied can go to 7 V and are not restricted by the VDD + 0.3 V limit as on the analog inputs. Another advantage of SCLK and CS not being restricted by the V + 0.3 V limit is that power supply sequencing issues are DD avoided. If or SCLK are applied before V , there is no risk CS DD of latch-up as there would be on the analog inputs if a signal greater than 0.3 V were applied prior to V . DD Rev. B | Page 15 of 24 THD (dB) THD (dB) 01684-B-017 01684-B-016 01684-B-018 AD7475/AD7495 OPERATING MODES The AD7475/AD7495 operating mode is selected by controlling may idle high until the next conversion or may idle low until the logic state of the CS signal during a conversion. There are sometime prior to the next conversion (effectively idling CS three possible modes of operation: normal mode, partial power- low). down mode, and full power-down mode. The point at which CS Once a data transfer is complete (SDATA has returned to three- is pulled high after the conversion has been initiated determines state), another conversion can be initiated after the quiet time, which power-down mode, if any, the device enters. Similarly, if t , has elapsed, by bringing low again. QUIET CS already in a power-down mode, CS can control whether the device returns to normal operation or remains in power-down. PARTIAL POWER-DOWN MODE These modes of operation are designed to provide flexible This mode is intended for use in applications where slower power management options. These options can be chosen to throughput rates are required; either the ADC is powered down optimize the power dissipation/throughput rate ratio for between each conversion, or a series of conversions may be differing application requirements. performed at a high throughput rate and then the ADC is powered down for a relatively long duration between these NORMAL MODE bursts of several conversions. When the AD7475 is in partial This mode is intended for fastest throughput rate performance, power-down, all analog circuitry is powered down except for because the user does not have to worry about any power-up the bias current generator; and, in the case of the AD7495, all times with the AD7475/AD7495 remaining fully powered all analog circuitry is powered down except for the on-chip the time. Figure 19 shows the general diagram of the AD7475/ reference and reference buffer. AD7495 operating in this mode. To enter partial power-down, the conversion process must be The conversion is initiated on the falling edge of , as CS interrupted by bringing CS high anywhere after the second described in the Serial Interface section. To ensure the part falling edge of SCLK and before the tenth falling edge of SCLK, remains fully powered-up at all times, CS must remain low until as shown in Figure 20. Once CS has been brought high in this at least 10 SCLK falling edges have elapsed after the falling edge window of SCLKs, the part enters partial power-down, the th of CS. If CS is brought high any time after the 10 SCLK falling conversion that was initiated by the falling edge of is CS th edge, but before the 16 SCLK falling edge, the part remains terminated, and SDATA goes back into three-state. If CS is powered up but the conversion is terminated and SDATA goes brought high before the second SCLK falling edge, the part back into three-state. Sixteen serial clock cycles are required to remains in normal mode and does not power down. This avoids complete the conversion and access the conversion result. CS accidental power-down due to glitches on the CS line. CS 1 10 16 SCLK SDATA FOUR LEADING ZEROS + CONVERSION RESULT Figure 19. Normal Mode CS 1 2 10 16 SCLK Figure 20. Entering Partial Power-Down Mode Rev. B | Page 16 of 24 01684-B-020 01684-B-019 AD7475/AD7495 To exit this operating mode and power up the AD7475/AD7495 When powering up from the power-down mode with a dummy again, a dummy conversion is performed. On the falling edge of cycle, as in Figure 21, the track-and-hold that was in hold mode , the device begins to power up and continues to power up as while the part was powered down returns to track mode after CS the first SCLK edge the part receives after the falling edge of . CS long as CS is held low until after the falling edge of the tenth This is shown as Point A in Figure 21. Although at any SCLK SCLK. The device is fully powered up once 16 SCLKs have frequency one dummy cycle is sufficient to power up the device elapsed, and valid data results from the next conversion, as and acquire V , it does not necessarily mean that a full dummy IN shown in Figure 21. If CS is brought high before the second cycle of 16 SCLKs must always elapse to power up the device falling edge of SCLK, the AD7475/AD7495 go back into partial and fully acquire VIN; 1 μs is sufficient to power up the device power-down again. This avoids accidental power-up due to and acquire the input signal. If, for example, a 5 MHz SCLK glitches on the line; although the device may begin to power CS frequency were applied to the ADC, the cycle time would be up on the falling edge of CS, it powers down again on the rising 3.2 μs. In one dummy cycle, 3.2 μs, the part would be powered edge of . If in partial power-down and is brought high CS CS up and V fully acquired. However, after 1 μs with a 5 MHz IN between the second and tenth falling edges of SCLK, the device SCLK, only 5 SCLK cycles would have elapsed. At this stage, enters full power-down mode. the ADC would be fully powered up and the signal acquired. Power-Up Time In this case, the can be brought high after the tenth SCLK CS The power-up time of the AD7475/AD7495 from partial falling edge and brought low again after a time, tQUIET, to initiate the conversion. power-down is typically 1 μs, which means that with any frequency of SCLK up to 20 MHz, one dummy cycle is FULL POWER-DOWN MODE sufficient to allow the device to power up from partial power- Full power-down mode is intended for use in applications down. Once the dummy cycle is complete, the ADC is fully where slower throughput rates are required than that in the powered up and the input signal is acquired properly. The quiet partial power-down mode, because power up from a full power- time, t must still be allowed from the point where the bus QUIET, down would not be complete in just one dummy conversion. goes back into three-state after the dummy conversion to the This mode is more suited to applications where a series of next falling edge of . When running at a 1 MSPS throughput CS conversions performed at a relatively high throughput rate are rate, the AD7475/AD7495 power up and acquire a signal within followed by a long period of inactivity and therefore power ±0.5 LSB in one dummy cycle, 1 μs. down. When the AD7475/AD7495 are in full power-down, all analog circuitry is powered down. THE PART BEGINS THE PART IS FULLY TO POWER UP POWERED UP CS A1 16 1 16 10 SCLK SDATA INVALID DATA VALID DATA Figure 21. Exiting Partial Power-Down Mode THE PART ENTERS THE PART BEGINS THE PART ENTERS PARTIAL POWER-DOWN TO POWER UP FULL POWER-DOWN CS 1 2 16 1 2 16 10 10 SCLK THREE-STATE THREE-STATE SDATA INVALID DATA INVALID DATA Figure 22. Entering Full Power-Down Mode Rev. B | Page 17 of 24 01684-B-021 01684-B-023 AD7475/AD7495 Full power-down is entered in a way similar to partial power- SCLK falling edge, as shown in Figure 19. In the second cycle, down, except the timing sequence shown in Figure 20 must be must be brought high before the tenth SCLK edge, but CS executed twice. The conversion process must be interrupted in a after the second SCLK falling edge, as shown in Figure 20. similar fashion by bringing high anywhere after the second CS Alternatively, if the intent is to place the part in full power- falling edge of SCLK and before the tenth falling edge of SCLK. down mode when the supplies have been applied, then three The device enters partial power-down at this point. To reach dummy cycles must be initiated. The first dummy cycle must full power-down, the next conversion cycle must be interrupted hold low until after the tenth SCLK edge, as shown in CS in the same way, as shown in Figure 22. Once has been CS Figure 19; the second and third dummy cycle place the part in brought high in this window of SCLKs, then the part powers full power-down, as shown in Figure 22. (See the Operating down completely. Modes section.) Once supplies are applied to the AD7475, enough time must be allowed for the external reference to Note that it is not necessary to complete the 16 SCLKs once CS power up and charge the reference capacitor to its final value. has been brought high to enter a power-down mode. For the AD7495, enough time should be allowed for the internal reference buffer to charge the reference capacitor. Then, To exit full power-down, and power up the AD7475/AD7495 to place the AD7475/ AD7495 in normal mode, a dummy cycle, again, a dummy conversion is performed as when powering up 1 μs, should be initiated. If the first valid conversion is then from partial power-down. On the falling edge of CS, the device performed directly after the dummy conversion, ensure that begins to power up and continues to power up as long as is CS adequate acquisition time has been allowed. As mentioned held low until after the falling edge of the tenth SCLK. The earlier, when powering up from the power-down mode, the part power-up time is longer than one dummy conversion cycle returns to track upon the first SCLK edge applied after the however, and this time, t must elapse before a POWER-UP, falling edge of . However, when the ADC powers up initially CS conversion can be initiated, as shown in Figure 23. See the after supplies are applied, the track-and-hold is already in track. Timing Specifications section for more information. This means (assuming one has the facility to monitor the ADC When power supplies are first applied to the AD7475/AD7495, supply current) if the ADC powers up in the desired mode of the ADC may power up in either of the power-down modes operation, and a dummy cycle is not required to change mode, or normal mode. Because of this, it is best to allow a dummy then neither is a dummy cycle required to place the track-and- cycle to elapse to ensure the part is fully powered up before hold into track. If no current monitoring facility is available, the attempting a valid conversion. Likewise, if the intent is to keep relevant dummy cycle(s) should be performed to ensure the the part in partial power-down mode immediately after the part is in the required mode. supplies are applied, then two dummy cycles must be initiated. The first dummy cycle must hold CS low until after the tenth THE PART BEGINS THE PART IS FULLY POWERED UP TO POWER UP t POWER-UP CS 1 16 1 16 10 SCLK SDATA INVALID DATA VALID DATA Figure 23. Exiting Full Power-Down Mode Rev. B | Page 18 of 24 01684-B-022 AD7475/AD7495 POWER VS. THROUGHPUT RATE By using the partial power-down mode on the AD7475/ The AD7495 dissipates 6 mW for 2 μs during each conversion AD7495 when not converting, the average power consumption cycle and 0.69 mW for the remaining 8 μs where the part is in of the ADC decreases at lower throughput rates. Figure 24 partial power-down. With a throughput rate of 100 kSPS, the shows how, as the throughput rate is reduced, the part remains average power dissipated during each conversion cycle is (2/10) in its partial power-down state longer and the average power × (6 mW) + (8/10) × (0.69 mW) = 1.752 mW. Figure 24 shows consumption over time drops accordingly. the power vs. throughput rate when using partial power-down mode between conversions with both 5 V and 3 V supplies for 100 both the AD7475 and AD7495. For the AD7475, partial power- AD7495 5V SCLK = 20MHz down current is lower than that of the AD7495. AD7475 5V 10 SCLK = 20MHz Full power-down mode is intended for use in applications with slower throughput rates than required for partial power-down 1 AD7495 3V mode. It is necessary to leave 650 μs for the AD7495 to be fully SCLK = 20MHz AD7475 3V powered up from full power-down before initiating a conver- SCLK = 20MHz 0.1 sion. Current consumptions between conversions is typically less than 1 μA. 0.01 Figure 25 shows a typical graph of current vs. throughput for the AD7495 while operating in different modes. At slower 0.001 throughput rates, for example, 10 SPS to 1 kSPS, the AD7495 0 50 100 150 200 250 300 350 was operated in full power-down mode. As the throughput rate THROUGHPUT (kSPS) increased, up to 100 kSPS, the AD7495 was operated in partial Figure 24. Power vs. Throughput for Partial Power Down power-down mode, with the part being powered down between For example, if the AD7495 is operated in a continuous conversions. With throughput rates from 100 kSPS to 1 MSPS, sampling mode with a throughput rate of 100 kSPS and an the part operated in normal mode, remaining fully powered up SCLK of 20 MHz (V = 5 V), and the device is placed in partial DD at all times. power-down mode between conversions, then the power 2.0 consumption is calculated as follows. The maximum power V = 5V DD 1.8 dissipation during normal operation is 13 mW (V = 5 V). If DD 1.6 the power-up time from partial power-down is one dummy cycle, that is, 1 μs, and the remaining conversion time is another 1.4 cycle, that is, 1 μs, then the AD7495 can be said to dissipate 1.2 13 mW for 2 μs during each conversion cycle. For the 1.0 remainder of the conversion cycle, 8 μs, the part remains in 0.8 FULL PARTIAL partial power-down mode. The AD7495 dissipates 1.15 mW for POWER-DOWN NORMAL POWER-DOWN 0.6 the remaining 8 μs of the conversion cycle. If the throughput rate is 100 kSPS, and the cycle time is 10 μs, the average power 0.4 dissipated during each cycle is (2/10) × (13 mW) + (8/10) × 0.2 (1.15 mW) = 3.52 mW. If VDD = 3 V, SCLK = 20 MHz and the 0 10 100 1k 10k 100k 1M device is again in partial power-down mode between conver- THROUGHPUT (SPS) sions, the power dissipated during normal operation is 6 mW. Figure 25. Typical AD7495 Current vs. Throughput Rev. B | Page 19 of 24 POWER (mW) 01684-B-025 CURRENT (mA) 01684-B-026 AD7475/AD7495 SERIAL INTERFACE Figure 26 shows the detailed timing diagram for serial inter- Sixteen serial clock cycles are required to perform the con- facing to the AD7475/AD7495. The serial clock provides the version process and to access data from the AD7475/AD7495. conversion clock and also controls the transfer of information CS going low provides the first leading zero to be read in by the from the AD7475/AD7495 during conversion. microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges beginning with the second CS initiates the data transfer and conversion process. The falling leading zero; thus the first falling clock edge on the serial clock edge of puts the track-and-hold into hold mode and takes CS has the second leading zero provided. The final bit in the data th the bus out of three-state. The analog input is sampled at this transfer is valid on the 16 falling edge, having been clocked out th point. on the previous (15 ) falling edge. The conversion is also initiated at this point and requires In applications with a slower SCLK, it may be possible to read in 16 SCLK cycles to complete. Once 13 SCLK falling edges have data on each SCLK rising edge, although the first leading zero elapsed, the track-and-hold goes back into track on the next still has to be read on the first SCLK falling edge after the CS SCLK rising edge, as shown in Figure 26 at Point B. On the 16th falling edge. Therefore, the first rising edge of SCLK after the SCLK falling edge, the SDATA line goes back into three-state. CS falling edge provides the second leading zero and the 15th If the rising edge of CS occurs before 16 SCLKs have elapsed, rising SCLK edge has DB0 provided. This method may not the conversion is terminated and the SDATA line goes back work with most microprocessors/DSPs, but could possibly be into three-state, as shown in Figure 27; otherwise SDATA used with FPGAs and ASICs. returns to three-state on the 16th SCLK falling edge, as shown in Figure 26. CS t CONVERT t t 6 B 2 1 2 3 4 5 13 15 16 SCLK 14 t 5 t 7 t t 8 QUIET t t 4 3 0 SDATA 0 0 0 DB11 DB10 DB2 DB1 DB0 THREE-STATE THREE-STATE FOUR LEADING ZEROS Figure 26. Serial Interface Timing Diagram CS t CONVERT t t 6 B 2 1 2 3 4 5 13 14 15 16 SCLK t t 9 7 t QUIET t t 4 3 0 SDATA 0 0 0 DB11 DB10 DB2 THREE-STATE THREE-STATE FOUR LEADING ZEROS Figure 27. Serial Interface Timing Diagram — Conversion Termination Rev. B | Page 20 of 24 01684-B-028 01684-B-027 AD7475/AD7495 MICROPROCESSOR INTERFACING The serial interface on the AD7475/AD7495 allows the parts AD7475/AD7495 TO ADSP-21XX to be directly connected to a range of many different micro- The ADSP-21xx family of DSPs is interfaced directly to the processors. This section explains how to interface the AD7475/ AD7475/AD7495 without any glue logic required. The V DRIVE AD7495 with some of the more common microcontroller and pin of the AD7475/AD7495 takes the same supply voltage as DSP serial interface protocols. that of the ADSP-21xx. This allows the ADC to operate at a higher voltage than the serial interface, that is, ADSP-21xx, if AD7475/AD7495 TO TMS320C5X/C54X necessary. The serial interface on the TMS320C5x/C54x uses a continuous serial clock and frame synchronization signals to synchronize The SPORT control register should be set up as shown in Table 6. the data transfer operations with peripheral devices like the Table 6. AD7475/AD7495. The input allows easy interfacing CS SPORT Control Register Bits Function between the TMS320C5x/C54x and the AD7475/AD7495 TFSW = RFSW = 1 Alternate framing without any glue logic required. The serial port of the INVRFS = INVTFS = 1 Active low frame signal TMS320C5x/C54x is set up to operate in burst mode with DTYPE = 00 Right-justify data internal CLKX (Tx serial clock) and FSX (Tx frame sync). SLEN = 1111 16-bit data words The serial port control register (SPC) must have the following ISCLK = 1 Internal serial clock setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The format TFSR = RFSR = 1 Frame every word bit, FO, may be set to 1 to set the word length to 8 bits, in order IRFS = 0 to implement the power-down modes on the AD7475/AD7495. ITFS = 1 The connection diagram is shown in Figure 28. Note that for signal processing applications, it is imperative that the frame To implement the power-down modes, SLEN should be set to synchronization signal from the TMS320C5x/C54x provide 1001 to issue an 8-bit SCLK burst. equidistant sampling. The V pin of the AD7475/AD7495 DRIVE The connection diagram is shown in Figure 29. The ADSP-21xx takes the same supply voltage as that of the TMS320C5x/C54x. has the TFS and RFS of the SPORT tied together, with TFS set This allows the ADC to operate at a higher voltage than the as an output and RFS set as an input. The DSP operates in serial interface, that is, TMS320C5x/C54x, if necessary. alternate framing mode and the SPORT control register is set up as described. The frame synchronization signal generated TMS320C5x/C54x* AD7475/AD7495* on the TFS is tied to and, as with all signal processing CS SCLK CLKX applications, equidistant sampling is necessary. However, in this CLKR example, the timer interrupt is used to control the sampling rate SDATA DR of the ADC and, under certain conditions, equidistant sampling CS FBX may not be achieved. V DRIVE FSR ADSP-21xx* AD7475/AD7495* V DD *ADDITIONAL PINS OMITTED FOR CLARITY SCLK SCLK Figure 28. Interfacing to the TMS320C5x/54x SDATA DR CS RFS V DRIVE TFS V DD *ADDITIONAL PINS OMITTED FOR CLARITY Figure 29. Interfacing to the ADSP-21xx Rev. B | Page 21 of 24 01684-B-029 01684-B-030 AD7475/AD7495 The timer registers are loaded with a value that provides an AD7475/AD7495 TO MC68HC16 interrupt at the required sample interval. When an interrupt is The serial peripheral interface (SPI) on the MC68HC16 is received, a value is transmitted with TFS/DT (ADC control configured for master mode (MSTR) = 1, clock polarity bit word). The TFS is used to control the RFS, and therefore, the (CPOL) = 1, and the clock phase bit (CPHA) = 0. The SPI is reading of data. The frequency of the serial clock is set in the configured by writing to the SPI control register (SPCR), as SCLKDIV register. When the instruction to transmit with TFS described in the 68HC16 User Manual. The serial transfer takes is given, (that is, AX0 = TX0), the state of the SCLK is checked. place as a 16-bit operation when the size bit in the SPCR The DSP waits until the SCLK has gone high, low, and high register is set to size = 1. To implement the power-down modes before transmission starts. If the timer and SCLK values are with an 8-bit transfer, set size = 0. (A connection diagram is chosen such that the instruction to transmit occurs on or near shown in Figure 31.) The VDRIVE pin of the AD7475/AD7495 the rising edge of SCLK, the data can be transmitted or it can takes the same supply voltage as that of the MC68HC16. This wait until the next clock edge. allows the ADC to operate at a higher voltage than the serial interface, that is, the MC68HC16, if necessary. For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, an MC68HC16* AD7475/AD7495* SCLK of 2 MHz is obtained, and eight master clock periods SCLK SCLK/PCM2 elapse for every one SCLK period. If the timer registers are SDATA MISO/PMC0 loaded with the value 803, 100.5 SCLKs occur between CS SS/PMC3 interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling because the V DRIVE transmit instruction is occurring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure V DD *ADDITIONAL PINS OMITTED FOR CLARITY of N, equidistant sampling is implemented by the DSP. Figure 31. Interfacing to the MC68HC16 AD7475/AD7495 TO DSP56XXX The connection diagram in Figure 30 shows how the AD7475/ AD7495 can be connected to the synchronous serial interface (SSI) of the DSP56xxx family of devices from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB = 1) with internally generated 1-bit clock period frame sync for both Tx and Rx (Bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word length to 16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To implement the power-down modes on the AD7475/AD7495, the word length can be changed to 8 bits by setting Bit WL1 = 0 and Bit WL0 = 0 in CRA. For signal processing applications, it is imperative that the frame synchronization signal from the DSP56xxx provide equidistant sampling. The V pin of the DRIVE AD7475/AD7495 takes the same supply voltage as that of the DSP56xxx. This allows the ADC to operate at a voltage higher than the serial interface, that is, DSP56xxx, if necessary. DSP56xxx* AD7475/AD7495* SCLK SCLK SDATA SRD CS SC2 V DRIVE V DD *ADDITIONAL PINS OMITTED FOR CLARITY Figure 30. Interfacing to the DSP56xxx Rev. B | Page 22 of 24 01684-B-031 01684-B-032 AD7475/AD7495 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2440) 4.00 (0.1574) 5.80 (0.2284) 3.80 (0.1497) 1 4 1.27 (0.0500) 0.50 (0.0196) × 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 0.10 (0.0040) 8° 0.51 (0.0201) 0° 1.27 (0.0500) COPLANARITY 0.25 (0.0098) 0.31 (0.0122) SEATING 0.10 0.40 (0.0157) 0.17 (0.0067) PLANE COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 32. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.00 BSC 8 5 4.90 3.00 BSC BSC 1 4 PIN 1 0.65 BSC 1.10 MAX 0.15 0.00 0.80 8° 0.60 0.38 0.23 0° 0.40 0.22 0.08 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 33. 8-Lead Mini Small Outline Package [MINI_SO] (RM-8) Dimensions shown in millimeters Rev. B | Page 23 of 24 AD7475/AD7495 ORDERING GUIDE 1 2 Model Range Linearity Error (LSB) Package Option Branding Information AD7475AR −40°C to +85°C ±1.5 SO-8 AD7475AR-REEL −40°C to +85°C ±1.5 SO-8 AD7475AR-REEL7 −40°C to +85°C ±1.5 SO-8 AD7475BR −40°C to +85°C ±1 SO-8 AD7475BR-REEL −40°C to +85°C ±1 SO-8 AD7475BR-REEL7 −40°C to +85°C ±1 SO-8 AD7475ARM −40°C to +85°C ±1.5 RM-8 C9A AD7475ARM-REEL −40°C to +85°C ±1.5 RM-8 C9A AD7475ARM-REEL7 −40°C to +85°C ±1.5 RM-8 C9A AD7475BRM −40°C to +85°C ±1 RM-8 C9B AD7475BRM-REEL −40°C to +85°C ±1 RM-8 C9B AD7475BRM-REEL7 −40°C to +85°C ±1 RM-8 C9B 3 AD7475BRMZ −40°C to +85°C ±1 RM-8 C3C 3 AD7475BRMZ-REEL −40°C to +85°C ±1 RM-8 C3C 3 AD7475BRMZ-REEL7 −40°C to +85°C ±1 RM-8 C3C AD7495AR −40°C to +85°C ±1.5 SO-8 AD7495AR-REEL −40°C to +85°C ±1.5 SO-8 AD7495AR-REEL7 −40°C to +85°C ±1.5 SO-8 AD7495BR −40°C to +85°C ±1 SO-8 AD7495BR-REEL −40°C to +85°C ±1 SO-8 AD7495BR-REEL7 −40°C to +85°C ±1 SO-8 3 AD7495BRZ −40°C to +85°C ±1 SO-8 3 AD7495BRZ-REEL −40°C to +85°C ±1 SO-8 3 AD7495BRZ-REEL7 −40°C to +85°C ±1 SO-8 AD7495ARM −40°C to +85°C ±1.5 RM-8 CCA AD7495ARM-REEL −40°C to +85°C ±1.5 RM-8 CCA AD7495ARM-REEL7 −40°C to +85°C ±1.5 RM-8 CCA 3 AD7495ARMZ −40°C to +85°C ±1.5 RM-8 C3B 3 AD7495ARMZ-REEL −40°C to +85°C ±1.5 RM-8 C3B 3 AD7495ARMZ-REEL7 −40°C to +85°C ±1.5 RM-8 C3B AD7495BRM −40°C to +85°C ±1 RM-8 CCB AD7495BRM-REEL −40°C to +85°C ±1 RM-8 CCB AD7495BRM-REEL7 −40°C to +85°C ±1 RM-8 CCB 4 EVAL-AD7495CB Evaluation Board EVAL-AD7475CB Evaluation Board 5 EVAL-CONTROL BRD2 Controller Board 1 Linearity error here refers to integral linearity error. 2 SO = SOIC; RM = MSOP. 3 Z = Pb-free part. 4 This can be used as a standalone evaluation board or in conjunction with the evaluation controller board for evaluation/demonstration purposes. 5 The evaluation board controller is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01684–0–5/05(B) Rev. B | Page 24 of 24