ANALOG DEVICES AD7485

a 1 MSPS, Serial 14-Bit SAR ADC AD7485 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast Throughput Rate: 1 MSPS AV AGND C DV V DGND DD BIAS DD DRIVE Wide Input Bandwidth: 40 MHz Excellent DC Accuracy Performance Flexible Serial Interface 2.5 V Low Power: REFOUT BUF REFERENCE 80 mW (Full Power) and 3 mW (NAP Mode) REFSEL REFIN STANDBY Mode: 2 �A Max Single 5 V Supply Operation 14-BIT Internal 2.5 V Reference ALGORITHMIC SAR VIN T/H Full-Scale Overrange Indication AD7485 GENERAL DESCRIPTION MCLK NAP The AD7485 is a 14-bit, high speed, low power, successive- TFS approximation ADC. The part features a serial interface with CONTROL STBY LOGIC AND I/O SCO throughput rates up to 1 MSPS. The part contains a low noise, REGISTERS RESET SDO wide bandwidth track-and-hold that can handle input frequencies CONVST in excess of 40 MHz. SMODE The conversion process is a proprietary algorithmic successive- approximation technique. The input signal is sampled and a conversion is initiated on the falling edge of the CONVST signal. The AD7485 features an on-board 2.5 V reference, but the part can The conversion process is controlled by an external master also accommodate an externally provided 2.5 V reference source. clock. Interfacing is via standard serial signal lines, making the The nominal analog input range is 0 V to 2.5 V. part directly compatible with microcontrollers and DSPs. The AD7485 also provides the user with overrange indication via a The AD7485 provides excellent ac and dc performance specifi- fifteenth bit. If the analog input range strays outside the 0 V to cations. Factory trimming ensures high dc accuracy resulting in 2.5 V input range, the fifteenth data bit is set to a logic high. very low INL, DNL, offset, and gain errors. The AD7485 is powered from a 4.75 V to 5.25 V supply. The The part uses advanced design techniques to achieve very low part also provides a V pin that allows the user to set the power dissipation at high throughput rates. Power consumption DRIVE voltage levels for the digital interface lines. The range for this in the normal mode of operation is 80 mW. There are two power- V pin is from 2.7 V to 5.25 V. The part is housed in a saving modes: a NAP mode keeps reference circuitry alive for DRIVE 48-lead LQFP package and is specified over a –40°C to +85°C quick power-up and consumes 3 mW, while a STANDBY mode temperature range. reduces power consumption to a mere 10 µW. REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise Fax: © Analog Devices, Inc., under any patent or patent rights of Analog Devices. (V = 5 V � 5%, AGND = DGND = 0 V, V = External, f = 1 MSPS; all specifica- 1 DD REF SAMPLE AD7485–SPECIFICATIONS tions T to T and valid for V = 2.7 V to 5.25 V, unless otherwise noted.) MIN MAX DRIVE Parameter Specification Unit Test Conditions/Comments 2, 3 DYNAMIC PERFORMANCE f = 500 kHz Sine Wave IN 4 Signal to Noise + Distortion (SINAD) 76.5 dB min 78 dB typ 77 dB typ Internal Reference 4 Total Harmonic Distortion (THD) –90 dB max –95 dB typ –92 dB typ Internal Reference 4 Peak Harmonic or Spurious Noise (SFDR) –88 dB max 4 Intermodulation Distortion (IMD) Second-Order Terms –96 dB typ f = 95.053 kHz, f = 105.329 kHz IN1 IN2 Third-Order Terms –94 dB typ Aperture Delay 10 ns typ Full Power Bandwidth 40 MHz typ @ 3 dB 3.5 MHz typ @ 0.1 dB DC ACCURACY Resolution 14 Bits 4 Integral Nonlinearity ±1LSB max ±0.5 LSB typ 4 Differential Nonlinearity ±0.75 LSB max Guaranteed No Missed Codes to 14 Bits ±0.25 LSB typ 4 Offset Error ±6LSB max 0.036 %FSR max 4 Gain Error ±6LSB max 0.036 %FSR max ANALOG INPUT Input Voltage 0 V min 2.5 V max DC Leakage Current ±1 µA max 5 Input Capacitance 35 pF typ REFERENCE INPUT/OUTPUT V Input Voltage 2.5 V ±1% for Specified Performance REFIN V Input DC Leakage Current ±1 µA max REFIN 5 V Input Capacitance 25 pF typ REFIN 6 V Input Current 220 �A typ External Reference REFIN V Output Voltage 2.5 V typ REFOUT V Error @ 25°C ±50 mV typ REFOUT V Error T to T ±100 mV max REFOUT MIN MAX V Output Impedance 1 Ω typ REFOUT LOGIC INPUTS Input High Voltage, V V –1V min INH DRIVE Input Low Voltage, V 0.4 V max INL Input Current, I ±1 µA max IN 5 Input Capacitance, C 10 pF typ IN LOGIC OUTPUTS 7 Output High Voltage, V 0.7 × V V min OH DRIVE 7 Output Low Voltage, V 0.3 × V V max OL DRIVE Floating-State Leakage Current ±10 µA max 5 Floating-State Output Capacitance 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 24 MCLKs Track/Hold Acquisition Time 100 ns max Sine Wave Input 70 ns max Full-Scale Step Input Throughput Rate 1 MSPS max –2– REV. AD7485 Parameter Specification Unit Test Conditions/Comments POWER REQUIREMENTS V 5V ±5% DD V 2.7 V min DRIVE 5.25 V max I DD Normal Mode (Static) 13 mA max Normal Mode (Operational) 17 mA max NAP Mode 0.6 mA max 8 STANDBY Mode 2 µA max 0.5 µA typ Power Dissipation Normal Mode (Operational) 85 mW max NAP Mode 3 mW max 8 STANDBY Mode 10 µW max NOTES 1 Temperature ranges as follows: –40°C to +85°C. 2 SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB. 3 See Typical Performance Characteristics section for analog input circuits used. 4 See Terminology. 5 Sample tested @ 25°C to ensure compliance. 6 Current drawn from external reference during conversion. 7 I = 200 µA. LOAD 8 Digital input levels at GND or V . DRIVE Specifications subject to change without notice. (V = 5 V � 5%, AGND = DGND = 0 V, V = External; all specifications T to T and DD REF MIN MAX 1 TIMING CHARACTERISTICS valid for V = 2.7 V to 5.25 V, unless otherwise noted.) DRIVE Parameter Symbol Min Typ Max Unit Master Clock Frequency f 0.01 25 MHz MCLK MCLK Period t 40 100000 ns 1 Conversion Time t t � 24 ns 2 1 2 CONVST Low Period (Mode 1) t t � 22 ns 3 1 2 CONVST High Period (Mode 1) t 10 ns 4 MCLK High Period t 0.4 � t 0.6 � t ns 5 1 1 MCLK Low Period t 0.4 � t 0.6 � t ns 6 1 1 CONVST Falling Edge to MCLK Rising Edge t7ns 7 MCLK Rising Edge to MSB Valid t 15 ns 8 Data Valid before SCO Falling Edge t 10 ns 9 Data Valid after SCO Falling Edge t 20 ns 10 CONVST Rising Edge to SDO Three-State t 6ns 11 2 CONVST Low Period (Mode 2) t 10 t � 2ns 12 1 3 CONVST High Period (Mode 2) t 10 ns 13 CONVST Falling Edge to TFS Falling Edge t 10 ns 14 TFS Falling Edge to MSB Valid t 30 ns 15 TFS Rising Edge to SDO Three-State t 8ns 16 4 TFS Low Period t t � 22 ns 17 1 4 TFS High Period t 10 ns 18 MCLK Fall Time t 525ns 19 MCLK Rise Time t 525ns 20 MCLK – SCO Delay t 625ns 21 NOTES 1 All timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. 2 CONVST idling high. See Serial Interface section for further details. 3 CONVST idling low. See Serial Interface section for further details. 4 TFS can also be tied low in this mode. Specifications subject to change without notice. REV. –3– AD7485 ABSOLUTE MAXIMUM RATINGS* � Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 50°C/W JA (T = 25°C, unless otherwise noted.) � Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 10°C/W A JC Lead Temperature, Soldering V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C V to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DRIVE Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Analog Input Voltage to GND . . . . . . –0.3 V to AV + 0.3 V DD ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV Digital Input Voltage to GND . . . . . –0.3 V to V + 0.3 V DRIVE *Stresses above those listed under Absolute Maximum Ratings may cause perma- REFIN to GND . . . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V DD nent damage to the device. This is a stress rating only; functional operation of the Input Current to Any Pin except Supplies . . . . . . . . . ±10 mA device at these or any other conditions above those listed in the operational sections Operating Temperature Range of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. Commercial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate WARNING! on the human body and test equipment and can discharge without detection. Although the AD7485 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid ESD SENSITIVE DEVICE performance degradation or loss of functionality. PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 1 AV 36 SMODE DD PIN 1 2 C IDENTIFIER BIAS 35 TFS 3 AGND 34 DGND 4 AGND 33 DGND AV 5 32 V DD DRIVE AD7485 AGND 6 31 DGND TOP VIEW 7 VIN 30 DGND (Not to Scale) 8 REFOUT 29 DV DD 9 REFIN 28 DGND 10 REFSEL 27 DGND 11 AGND 26 DGND AGND 12 25 DGND 13 14 15 16 17 18 19 20 21 22 23 24 –4– REV. AV AGND DD AGND AGND AGND AV DD STBY DV DD NAP DGND MCLK DGND DGND RESET DGND CONVST SCO SDO DGND DGND DGND DGND DGND DGND AD7485 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1, 5, 13, 46 AV Positive Power Supply for Analog Circuitry DD 2C Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin BIAS and AGND. 3, 4, 6, 11, 12, AGND Power Supply Ground for Analog Circuitry 14, 15, 47, 48 7VIN Analog Input. Single-ended analog input channel. 8 REFOUT Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF capacitor must be placed between this pin and AGND. 9 REFIN Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an external voltage reference source, the reference voltage should be applied to this pin. 10 REFSEL Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected from this pin to AGND. When using an external reference source, this pin should be connected directly to AGND. 16 STBY Standby Logic Input. When this pin is logic high, the device will be placed in STANDBY mode. See the Power Saving section for further details. 17 NAP Nap Logic Input. When this pin is logic high, the device will be placed in a very low power mode. See the Power Saving section for further details. 18 MCLK Master Clock Input. This is the input for the master clock, which controls the conversion cycle. The fre- quency of this clock may be up to 25 MHz. Twenty-four clock cycles are required for each conversion. 19, 20, 22–28 DGND Ground Reference for Digital Circuitry 30, 31, 33, 34 37–39, 43, 44 21 SDO Serial Data Output. The conversion data is latched out on this pin on the rising edge of SCO. It should be latched into the receiving serial port of the DSP on the falling edge of SCO. The over- range bit is latched out first, then 14 bits of data (MSB first) followed by a trailing zero. 29, 45 DV Positive Power Supply for Digital Circuitry DD 32 V Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface DRIVE logic of the AD7485 will operate. 35 TFS Transmit Frame Sync Input. In Serial Mode 2, this pin acts as a framing signal for the serial data being clocked out on SDO. A falling edge on TFS brings SDO out of three-state and the data starts to get clocked out on the next rising edge of SCO. 36 SMODE Serial Mode Input. A logic low on this pin selects Serial Mode 1 and a logic high selects Serial Mode 2. See the Serial Interface section for further details. 40 SCO Serial Clock Output. This clock is derived from MCLK and is used to latch conversion data from the device. See the Serial Interface section for further details. 41 CONVST Convert Start Logic Input. A conversion is initiated on the falling edge of the CONVST signal. The input track/hold amplifier goes from track mode to hold mode and the conversion process commences. 42 RESET Reset Logic Input. A falling edge on this pin resets the internal state machine and terminates a conversion that may be in progress. Holding this pin low keeps the part in a reset state. REV. –5– AD7485 TERMINOLOGY Total Harmonic Distortion Integral Nonlinearity Total harmonic distortion (THD) is the ratio of the rms sum This is the maximum deviation from a straight line passing of the harmonics to the fundamental. For the AD7485, it is through the endpoints of the ADC transfer function. The end- defined as: 2 2 2 2 2 points of the transfer function are zero scale, a point 1/2 LSB VVV ++ +V+V 2 3 4 5 6 THD dB = 20 log () below the first code transition, and full scale, a point 1/2 LSB V 1 above the last code transition. where V is the rms amplitude of the fundamental and V , V , 1 2 3 V , V , and V are the rms amplitudes of the second through Differential Nonlinearity 4 5 6 sixth harmonics. This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the Offset Error rms value of the next largest component in the ADC output This is the deviation of the first code transition (00 . . . 000) to spectrum (up to f /2 and excluding dc) to the rms value of the (00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB. S fundamental. Normally, the value of this specification is deter- Gain Error mined by the largest harmonic in the spectrum, but for ADCs This is the deviation of the last code transition (111 . . . 110) to where the harmonics are buried in the noise floor, it will be a (111 . . . 111) from the ideal (i.e., V – 1.5 LSB) after the REF noise peak. offset error has been adjusted out. Intermodulation Distortion Track/Hold Acquisition Time With inputs consisting of sine waves at two frequencies, fa and fb, Track/hold acquisition time is the time required for the output any active device with nonlinearities will create distortion products of the track/hold amplifier to reach its final value, within ±1/2 LSB, at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, after the end of conversion (the point at which the track/hold 3, and so on. Intermodulation distortion terms are those for which returns to track mode). neither m nor n is equal to zero. For example, the second-order Signal to (Noise + Distortion) Ratio terms include (fa + fb) and (fa – fb), while the third-order terms This is the measured ratio of signal to (noise + distortion) at include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). the output of the A/D converter. The signal is the rms amplitude The AD7485 is tested using the CCIF standard where two of the fundamental. Noise is the sum of all nonfundamental input frequencies near the top end of the input bandwidth are signals up to half the sampling frequency (f /2), excluding dc. S used. In this case, the second-order terms are usually distanced The ratio is dependent on the number of quantization levels in in frequency from the original sine waves while the third-order the digitization process; the more levels, the smaller the quanti- terms are usually at a frequency close to the input frequencies. zation noise. The theoretical signal to (noise + distortion) ratio As a result, the second- and third-order terms are specified for an ideal N-bit converter with a sine wave input is given by: separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms Signal to() Noise+= Distortion 60. 2 N+17. 6 dB () sum of the individual distortion products to the rms amplitude Thus, for a 14-bit converter this is 86.04 dB. of the sum of the fundamentals expressed in dBs. –6– REV. Typical Performance Characteristics–AD7485 1.0 –40 0.8 –50 0.6 100� 0.4 –60 51� 0.2 –70 0 –0.2 10� –80 –0.4 0� –0.6 –90 –0.8 –100 –1.0 100 1000 10000 0 4096 8192 12288 16384 ADC CODE INPUT FREQUENCY – kHz TPC 1. Typical DNL TPC 4. THD vs. Input Tone for Different Input Resistances 1.0 0 100mV p-p SINE WAVE ON SUPPLY PINS 0.8 –10 0.6 –20 0.4 –30 0.2 0 –40 –0.2 –50 –0.4 –60 –0.6 –70 –0.8 –1.0 –80 0 4096 8192 12288 16384 10 100 1000 ADC CODE FREQUENCY – kHz TPC 5. PSRR without Decoupling TPC 2. Typical INL 80 0.0004 0 75 –0.0004 –0.0008 70 –0.0012 –0.0016 65 –0.0020 10 100 1000 10000 –55 –25 5 35 65 95 125 INPUT FREQUENCY – kHz TEMPERATURE – �C TPC 3. SINAD vs. Input Tone (AD8021 Input Circuit) TPC 6. Reference Error REV. –7– INL – LSB DNL – LSB SINAD – dB REFOUT – V THD – dB PSRR – dB AD7485 0 0 f = 10.7kHz f = 507.3kHz IN IN SNR = 78.76dB SNR = 78.35dB –20 –20 SNR + D = 78.70dB SNR + D = 78.33dB THD = –97.10dB THD = –100.33dB –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 100 200 300 400 500 0 100 200 300 400 500 FREQUENCY – kHz FREQUENCY – kHz TPC 8. 64k FFT Plot with 500 kHz Input Tone TPC 7. 64k FFT Plot with 10 kHz Input Tone +V S Figure 1 shows the analog input circuit used to obtain the data 8 1k� 100� for the FFT plot shown in TPC 7. The circuit uses an Analog AC 7 3 + SIGNAL Devices AD829 op amp as the input buffer. A bipolar analog 1k� 6 V IN AD829 BIAS signal is applied as shown and biased up with a stable, low noise VOLTAGE 4 2 – dc voltage connected to the labeled terminal shown. A 220 pF 5 1 –V S compensation capacitor is connected between Pin 5 of the AD829 220pF and the analog ground plane. The AD829 is supplied with +12 V 150� and –12 V supplies. The supply pins are decoupled as close to the device as possible, with both a 0.1 µF and 10 µF capacitor Figure 1. Analog Input Circuit Used for 10 kHz Input Tone connected to each pin. In each case, the 0.1 µF capacitor should be the closer of the two capacitors to the device. More information on the AD829 is available on the Analog Devices website. For higher input bandwidth applications, Analog Devices’ AD8021 op amp (also available as a dual AD8022) is the recommended +V S choice to drive the AD7485. Figure 2 shows the analog input circuit used to obtain the data for the FFT plot shown in TPC 8. 8 50� AC A bipolar analog signal is applied to the terminal shown and 7 2 + SIGNAL biased with a stable, low noise dc voltage connected as shown. A V 6 IN AD8021 220� 10 pF compensation capacitor is connected between Pin 5 of the BIAS 4 – 3 VOLTAGE 5 AD8021 and the negative supply. As with the previous circuit, 1 the AD8021 is supplied with +12 V and –12 V supplies. The 10pF supply pins are decoupled as close to the device as possible with –V S both a 0.1 µF and 10 µF capacitor connected to each pin. In each 220� case, the 0.1 µF capacitor should be the closer of the two capaci- tors to the device. The AD8021 Logic Reference pin is tied to 10pF analog ground and the DISABLE pin is tied to the positive sup- Figure 2. Analog Input Circuit Used for 500 kHz Input Tone ply as shown. Detailed information on the AD8021 is available on the Analog Devices website. –8– REV. dB dB AD7485 CIRCUIT DESCRIPTION CAPACITIVE CONVERTER OPERATION DAC The AD7485 is a 14-bit algorithmic successive-approximation analog-to-digital converter based around a capacitive DAC. It pro- vides the user with track-and-hold, reference, an A/D converter, A V IN + and versatile interface logic functions on a single chip. The analog SW1 CONTROL LOGIC B input signal range that the AD7485 can convert is 0 V to 2.5 V. – SW2 The part requires a 2.5 V reference that can be provided from COMPARATOR the part’s own internal reference or an external reference source. Figure 3 shows a very simplified schematic of the ADC. The AGND Control Logic, SAR, and Capacitive DAC are used to add and Figure 5. ADC Acquisition Phase subtract fixed amounts of charge from the sampling capacitor to bring the comparator back to a balanced condition. ADC TRANSFER FUNCTION The output coding of the AD7485 is straight binary. The designed COMPARATOR code transitions occur midway between successive integer LSB CAPACITIVE DAC values (i.e., 1/2 LSB, 3/2 LSB, and so on). The LSB size is V /16384. The nominal transfer characteristic for the REF AD7485 is shown in Figure 6. V IN SWITCHES V REF 111...111 SAR 111...110 111...000 CONTROL CONTROL 1LSB = V /16384 REF LOGIC INPUTS OUTPUT DATA 011...111 14-BIT SERIAL 000...010 Figure 3. Simplified Block Diagram 000...001 000...000 Conversion is initiated on the AD7485 by pulsing the CONVST 0.5LSB +V –1.5LSB REF 0V input. On the falling edge of CONVST, the track/hold goes from ANALOG INPUT track to hold mode and the conversion sequence is started. Figure 6. Transfer Characteristic Conversion time for the part is 24 MCLK periods. Figure 4 shows the ADC during conversion. When conversion starts, SW2 will POWER SAVING open and SW1 will move to position B causing the comparator to The AD7485 uses advanced design techniques to achieve very become unbalanced. The ADC then runs through its successive low power dissipation at high throughput rates. In addition to approximation routine and brings the comparator back into a this, the AD7485 features two power saving modes, NAP mode balanced condition. When the comparator is rebalanced, the and STANDBY mode. These modes are selected by bringing conversion result is available in the SAR register. either the NAP or STBY pin to a logic high. When operating the AD7485 with a 25 MHz MCLK in normal, CAPACITIVE fully powered mode, the current consumption is 16 mA during DAC conversion and the quiescent current is 12 mA. Operating at a throughput rate of 500 kSPS, the conversion time of 960 ns A contributes 38.4 mW to the overall power dissipation. V IN + SW1 CONTROL LOGIC 960 ns/. 2 �s×× 5V 16 mA = 38 4 mW B ()() – SW2 COMPARATOR For the remaining 1.04 µs of the cycle, the AD7485 dissipates 31.2 mW of power. AGND 10./ 4�� ss 2 ×× 5V 12mA = 312.mW ()() Figure 4. ADC Conversion Phase Thus the power dissipated during each cycle is: At the end of conversion, track-and-hold returns to tracking mode and the acquisition time begins. The track/hold acquisition 38.. 4 mW+= 31 2 mW 69.6 mW time is 70 ns. Figure 5 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on V . IN REV. –9– ADC CODE AD7485 Figure 7 shows the AD7485 conversion sequence operating in Figures 9 and 10 show a typical graphical representation of normal mode. power versus throughput for the AD7485 when in normal and NAP modes, respectively. 2�s 80 CONVST 78 76 READ DATA CONVERSION TFS 74 FINISHED 72 960ns 1.04�s 70 Figure 7. Normal Mode Power Dissipation 68 In NAP mode, all the internal circuitry except for the internal reference is powered down. In this mode, the power dissipation 66 of the AD7485 is reduced to 3 mW. When exiting NAP mode, 64 a minimum of 300 ns when using an external reference must be 62 waited before initiating a conversion. This is necessary to allow the internal circuitry to settle after power-up and for the track/hold 60 0 100 200 300 400 500 600 700 800 900 1000 to properly acquire the analog input signal. THROUGHPUT – kSPS If the AD7485 is put into NAP mode after each conversion, the Figure 9. Normal Mode, Power vs. Throughput average power dissipation will be reduced but the throughput rate will be limited by the power-up time. Using the AD7485 with 50 a throughput rate of 100 kSPS while placing the part in NAP 45 mode after each conversion would result in average power dissi- 40 pation as follows: 35 The power-up phase contributes: 30 300 ns/. 10 �s×× 5V 12 mA = 1 8 mW ()() 25 The conversion phase contributes: 20 960 ns/. 10 �s×× 5V 16 mA = 7 68 mW ()() 15 While in NAP mode for the rest of the cycle, the AD7485 dissipates 10 only 2.185 mW of power. 5 87./ 4�� ssV 10 ×× 5 06.mA =26. 22mW ()() 0 050 100 150 200 250 300 350 400 450 500 THROUGHPUT – kSPS Thus the power dissipated during each cycle is: Figure 10. NAP Mode, Power vs. Throughput 18.. mW++ 768 mW 2.622 mW+ 12.1mW In STANDBY mode, all the internal circuitry is powered down Figure 8 shows the AD7485 conversion sequence if putting the and the power consumption of the AD7485 is reduced to 10 µW. part into NAP mode after each conversion. Because the internal reference has been powered down, the power-up time necessary before a conversion can be initiated is 1.26�s 8.74�s longer. If using the internal reference of the AD7485, the ADC must be brought out of STANDBY mode 500 ms before a conver- NAP sion is initiated. Initiating a conversion before the required 300ns power-up time has elapsed will result in incorrect conversion data. If an external reference source is used and kept powered up CONVST while the AD7485 is in STANDBY mode, the power-up time required will be reduced to 80 µs. TFS 10�s Figure 8. NAP Mode Power Dissipation –10– REV. POWER – mW POWER – mW AD7485 DIGITAL ANALOG SERIAL INTERFACE SUPPLY SUPPLY The AD7485 has two serial interface modes, selected by the state 4.75V–5.25V 4.75V–5.25V of the SMODE pin. In both these modes, the MCLK pin must be + + 10�F 1nF 0.1�F 0.1�F 47�F supplied with a clock signal of between 10 kHz and 25 MHz. This MCLK signal controls the internal conversion process and is also 0.1�F used to derive the SCO signal. As the AD7485 uses an algorithmic V DV AV DRIVE DD DD successive-approximation technique, 24 MCLK cycles are ADM809 RESET C BIAS required to complete a conversion. Due to the error-correcting SMODE 1nF operation of this ADC, all bit trials must be completed before the NAP REFSEL conversion result is calculated. This results in a single sample STBY delay in the result that is clocked out. AD780 2.5V REFIN REFERENCE 0.47�F In Serial Mode 1 (Figure 13), the CONVST pin is used to AD7485 initiate the conversion and also frame the serial data. When CONVST is brought low, the SDO line is taken out of three- �C/�P CONVST REFOUT state, the overrange bit will be clocked out on the next rising TFS 0.47�F SCO edge of SCO followed by the 14 data bits (MSB first) and a SDO trailing zero. CONVST must remain low for 22 SCO pulses to V 0V TO 2.5V IN allow all the data to be clocked out and the conversion in 25MHz MCLK XO progress to be completed. When CONVST returns to a logic high, the SDO line returns to three-state. TFS should be tied to Figure 11. Typical Connection Diagram ground in this mode. Driving the CONVST Pin In Serial Mode 2 (Figure 14), the CONVST pin is used to To achieve the specified performance from the AD7485, the initiate the conversion, but the TFS signal is used to frame the CONVST pin must be driven from a low jitter source. Since the serial data. The CONVST signal can idle high or low in this falling edge on the CONVST pin determines the sampling instant, mode. Idling high, the CONVST pulsewidth must be between any jitter that may exist on this edge will appear as noise when 10 ns and two MCLK periods. Idling low, the CONVST the analog input signal contains high frequency components. pulsewidth must be at least 10 ns. TFS must remain low for a The relationship between the analog input frequency (f ), timing IN minimum of 22 SCO cycles in this mode but can also be tied jitter (t ), and resulting SNR is given by the equation below. j permanently low. If TFS is tied low, the SDO line will always 1 be driven. SNR () dB = 10 log JITTER 2 () 2π××ft The relationship between the MCLK and SCO signals is shown IN j in Figure 15. As an example, if the desired SNR due to jitter was 100 dB with Figure 11 shows a typical connection diagram for the AD7485. a maximum full-scale analog input frequency of 500 kHz, ignor- In this case, the MCLK signal is provided by a 25 MHz crystal ing all other noise sources we get an allowable jitter of 3.18 ps oscillator module. It could also be provided by the second serial on the CONVST falling edge. For a 14-bit converter (ideal port of a DSP (e.g., ADSP-2189M) if one were available. SNR = 86.04 dB), the allowable jitter will be greater than the figure given above; but due consideration needs to be given to the In Figure 11 the V pin is tied to DV , which results in logic DRIVE DD design of the CONVST circuitry to achieve 14-bit performance output levels being either 0 V or DV . The voltage applied to DD with large analog input frequencies. V controls the voltage value of the output logic signals. For DRIVE example, if DV is supplied by a 5 V supply and V by a 3 V DD DRIVE supply, the logic output levels would be either 0 V or 3 V. This feature allows the AD7485 to interface to 3 V devices while still enabling the A/D to process signals at 5 V supply. The maximum slew rate at the input of the ADC should be limited to 500 V/µs while the conversion is taking place. This will prevent corruption of the current conversion. In any multi- plexed application, the channel switching should occur as early as possible after the first MCLK period. REV. –11– AD7485 Board Layout and Grounding To obtain optimum performance from the AD7485, it is recom- mended that a printed circuit board with a minimum of three layers is used. One of these layers, preferably the middle layer, should be as complete a ground plane as possible to give the best shielding. The board should be designed in such a way that the analog and digital circuitry are separated and confined to certain areas of the board. This practice, along with avoiding running digital and analog lines close together, should help to avoid coupling digital noise onto analog lines. The power supply lines to the AD7485 should be approximately Figure 12a Figure 12b 3 mm wide to provide a low impedance path and reduce the effects of glitches on the power supply lines. It is vital that good decoupling is also present. A combination of ferrites and decoupling capacitors should be used as shown in Figure 11. The decoupling capacitors should be as close to the supply pins as possible. This is made easier by the use of multilayer boards. The signal traces from the AD7485 pins can be run on the top layer while the decoupling capacitors and ferrites mounted on the bottom layer where the power traces exist. The ground plane between the top and bottom planes provides excellent shielding. Figures 12a–12e show a sample layout of the board area imme- Figure 12c Figure 12d diately surrounding the AD7485. Pin 1 is the bottom left corner of the device. Figure 12a shows the top layer where the AD7485 is mounted with vias to the bottom routing layer highlighted. Figure 12b shows the bottom layer where the power routing is with the same vias highlighted. Figure 12c shows the bottom layer silkscreen where the decoupling components are soldered directly beneath the device. Figure 12d shows the silkscreen overlaid on the solder pads for the decoupling components, and Figure 12e shows the top and bottom routing layers overlaid. The black area in each figure indicates the ground plane present on the middle layer. Figure 12e C1-6 : 100 nF, C7–8: 470 nF, C9: 1 nF L1-4: Meggit-Sigma Chip Ferrite Beads (BMB2A0600RS2) –12– REV. AD7485 t 2 t 4 t 3 CONVST t t t 7 1 5 MCLK t 6 SCO t t t t 8 9 10 11 SDO D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 13. Serial Mode 1 (SMODE = 0) Read Cycle t 2 t t 12 13 CONVST t t t 7 1 5 MCLK t t 6 14 SCO t t 9 10 SDO D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 t t 15 16 TFS t t 17 18 Figure 14. Serial Mode 2 (SMODE = 1) Read Cycle t 1 t 6 MCLK t t 19 20 t 5 SCO t 21 Figure 15. Serial Clock Timing REV. –13– AD7485 OUTLINE DIMENSIONS 9.20 0.75 9.00 SQ 1.60 0.60 8.80 MAX 0.45 48 37 1 36 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 (PINS DOWN) 0.20 6.80 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 1. 48-Lead Low Profile Quad Flatpack [LQFP] 7 mm × 7 mm, Very Thin Quad (ST-48) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD7485BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flatpack [LQFP] ST-48 1 Z = RoHS Compliant Part. REVISION HISTORY 4/10—Rev. 0 to Rev. A Changes to Specifications Table ............................................................. 3 ©2002-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02758-0-4/10(A) Rev. A | Page 14 051706-A