ANALOG DEVICES AD7400A

Isolated Sigma-Delta Modulator AD7400A FEATURES GENERAL DESCRIPTION 1 10 MHz clock rate The AD7400A is a second-order, Σ-Δ modulator that converts Second-order modulator an analog input signal into a high speed, 1-bit data stream with 16 bits, no missing codes on-chip digital isolation based on Analog Devices, Inc., iCoupler® ±2 LSB INL typical at 16 bits technology. The AD7400A operates from a 5 V power supply 1.5 μV/°C typical offset drift and accepts a differential input signal of ±250 mV (±320 mV On-board digital isolator full scale). The analog input is sampled continuously by the On-board reference analog modulator, eliminating the need for external sample- ±250 mV analog input range and-hold circuitry. The input information is contained in the Low power operation: 15.5 mA typical at 5.5 V output stream as a density of ones with a data rate of 10 MHz. −40°C to +125°C operating range The original information can be reconstructed with an appropriate 8-lead surface-mount PDIP package with gull wing leads and digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). 16-lead SOIC package The serial interface is digitally isolated. High speed CMOS, AD7401A, external clock version in 16-lead SOIC combined with monolithic air core transformer technology, Safety and regulatory approvals means the on-chip isolation provides outstanding performance UL recognition characteristics superior to alternatives such as optocoupler 5000 V rms for 1 minute per UL 1577 devices. The part contains an on-chip reference and has an CSA Component Acceptance Notice #5A operating temperature range of −40°C to +125°C. The AD7400A is VDE Certificate of Conformity offered in an 8-lead surface-mount PDIP with gull wing leads and DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 a 16-lead SOIC package. V = 891 V peak IORM 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents APPLICATIONS are pending. AC motor controls Shunt current monitoring Data acquisition systems Analog-to-digital and opto-isolator replacements FUNCTIONAL BLOCK DIAGRAM V V DD1 DD2 AD7400A V + IN Σ-∆ ADC V – IN UPDATE WATCHDOG ENCODE DECODE MDAT REF CONTROL LOGIC UPDATE WATCHDOG ENCODE MCLKOUT DECODE GND GND 1 2 Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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T/H BUF 07077-001 AD7400A TABLE OF CONTENTS Features .............................................................................................. 1  Terminology.................................................................................... 12  Applications....................................................................................... 1  Theory of Operation ...................................................................... 13  General Description ......................................................................... 1  Circuit Information.................................................................... 13  Functional Block Diagram .............................................................. 1  Analog Input ............................................................................... 13  Revision History ............................................................................... 2  Differential Inputs...................................................................... 14  Specifications..................................................................................... 3  Current Sensing Applications................................................... 14  Timing Specifications .................................................................. 4  Voltage Sensing Applications.................................................... 14  Insulation and Safety-Related Specifications............................ 5  Digital Filter ................................................................................ 15  Regulatory Information............................................................... 5  Applications Information .............................................................. 17  DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Grounding and Layout .............................................................. 17  Characteristics .............................................................................. 6  Evaluating the AD7400A Performance ................................... 17  Absolute Maximum Ratings............................................................ 7  Insulation Lifetime..................................................................... 17  ESD Caution.................................................................................. 7  Outline Dimensions....................................................................... 18  Pin Configuration and Function Descriptions............................. 8  Ordering Guide .......................................................................... 18  Typical Performance Characteristics ............................................. 9  REVISION HISTORY 7/11—Rev. B to Rev. C 9/08—Rev. 0 to Rev. A Changes to Minimum External Air Gap (Clearance) Parameter, Added 16-Lead SOIC.........................................................Universal Table 3 and Minimum External Tracking (Creepage) Parameter, Changes to General Description Section .......................................1 Table 3 ................................................................................................ 5 Changes to Table 1, Test Conditions/Comments Column ..........3 Changes to Figure 6; Pin 1 Description, Table 8; and Pin 7 Changes to Timing Specifications Table Summary ......................4 Description, Table 8.......................................................................... 8 Changes to Table 4, Note 2...............................................................5 Added Figure 6; Renumbered Sequentially ...................................8 1/11—Rev. A to Rev. B Changes to Terminology Section ................................................. 12 Changed UL Recognition from 3750 V rms to 5000 V rms....... 1 Updated Outline Dimensions....................................................... 18 Changes to Input-to-Output Momentary Withstand Voltage Changes to Ordering Guide .......................................................... 18 Value (Table 3) .................................................................................. 5 Changed UL Recognition from 3750 V rms to 5000 V rms 5/08—Revision 0: Initial Version (Table 4) ............................................................................................. 5 Changes to Note 1 (Table 4) ............................................................ 5 Rev. C | Page 2 of 20 AD7400A SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −200 mV to +200 mV, except where specified, and VIN− = 0 V (single-ended); 3 TA = −40°C to +125°C, except where specified; fMCLK = 10 MHz, tested with Sinc filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. Table 1. 1 Y Version Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 Bits Filter output truncated to 16 bits 2 Integral Nonlinearity ±2 ±12 LSB V + = ±200 mV, T = −40°C to +125°C IN A ±4 ±16 LSB V + = ±250 mV, T = −40°C to +85°C IN A ±4 ±22 LSB VIN+ = ±250 mV, TA = −40°C to +125°C 2 Differential Nonlinearity ±0.9 LSB Guaranteed no missing codes to 16 bits 2 Offset Error ±50 ±500 μV Offset Drift vs. Temperature 1.5 4 μV/°C −40°C to +125°C Offset Drift vs. V 120 μV/V DD1 2 Gain Error ±1.5 mV −40°C to +85°C ±2 mV −40°C to +125°C Gain Error Drift vs. Temperature 23 μV/°C −40°C to +125°C Gain Error Drift vs. VDD1 110 μV/V ANALOG INPUT Input Voltage Range −250 +250 mV For specified performance, full range = ±320 mV Dynamic Input Current ±7 ±8 μA VIN+ = 400 mV, VIN− = 0 V ±9 ±10 μA V + = 500 mV, V − = 0 V IN IN ±0.5 μA V + = V − = 0 V IN IN Input Capacitance 10 pF DYNAMIC SPECIFICATIONS V + = 35 Hz IN 2 Signal-to-Noise and Distortion (SINAD) Ratio 70 78 dB V + = ±200 mV IN 68 78 dB VIN+ = ±250 mV Signal-to-Noise Ratio (SNR) 73 80 dB VIN+ = ±200 mV 72 80 dB VIN+ = ±250 mV 2 Total Harmonic Distortion (THD) −84 dB V + = ±200 mV IN −82 dB V + = ±250 mV IN 2 Peak Harmonic or Spurious Noise (SFDR) −86 dB V + = ±200 mV IN −84 dB VIN+ = ±250 mV 2 Effective Number of Bits (ENOB) 11.5 12.5 Bits VIN+ = ±200 mV 11 12.5 Bits VIN+ = ±250 mV 2 Isolation Transient Immunity 25 30 kV/μs LOGIC OUTPUTS Output High Voltage, V V − 0.1 V I = −200 μA OH DD2 O Output Low Voltage, V 0.4 V I = +200 μA OL O POWER REQUIREMENTS V 4.5 5.5 V DD1 V 3 5.5 V DD2 3 I 11 13 mA V = 5.5 V DD1 DD1 4 IDD2 4.5 6 mA VDD2 = 5.5 V 3 3.5 mA VDD2 = 3.3 V 1 All voltages are relative to their respective ground. 2 See the Terminology section. 3 See Figure 15. 4 See Figure 16. Rev. C | Page 3 of 20 AD7400A TIMING SPECIFICATIONS 1 VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +125°C, except where specified. Table 2. Parameter Limit at tMIN, tMAX Unit Description 2 f 10 MHz typ Master clock output frequency MCLKOUT 9/11 MHz min/MHz max Master clock output frequency 3 t1 40 ns max Data access time after MCLK rising edge 3 t2 10 ns min Data hold time after MCLK rising edge t 0.4 × t ns min Master clock low time 3 MCLKOUT t 0.4 × t ns min Master clock high time 4 MCLKOUT 1 Sample tested during initial release to ensure compliance. 2 Mark space ratio for clock output is 40/60 to 60/40. 3 Measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 200µA I OL TO OUTPUT +1.6V PIN C L 25pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Specifications t 4 MCLKOUT t t 1 2 t 3 MDAT Figure 3. Data Timing Rev. C | Page 4 of 20 07077-002 07077-003 AD7400A INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 3. Parameter Symbol Value Unit Conditions Input-to-Output Momentary Withstand Voltage V 5000 min V rms 1-minute duration ISO Minimum External Air Gap (Clearance) L(I01) 8.1 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 7.46 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material group (DIN VDE 0110, 1/89, Table 1) REGULATORY INFORMATION Table 4. 1 2 UL CSA VDE Recognized Under 1577 Approved under CSA Component Certified according to DIN V VDE V 0884-10 1 2 Component Recognition Program Acceptance Notice #5A (VDE V 0884-10):2006-12 5000 V rms isolation voltage Reinforced insulation per CSA 60950-1-03 and Reinforced insulation per DIN V VDE V 0884-10 IEC 60950-1, 630 V rms maximum working voltage (VDE V 0884-10):2006-12, 891 V peak File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each AD7400A is proof tested by applying an insulation test voltage ≥6000 V rms for 1 sec (current leakage detection limit = 15 μA). 2 In accordance with DIN V VDE V 0884-10, each AD7400A is proof tested by applying an insulation test voltage ≥1671 V peak for 1 sec (partial discharge detection limit = 5 pC). Rev. C | Page 5 of 20 AD7400A DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 5. Parameter Symbol Characteristic Unit INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage ≤ 300 V rms I to IV For Rated Mains Voltage ≤ 450 V rms I to II For Rated Mains Voltage ≤ 600 V rms I to II CLIMATIC CLASSIFICATION 40/105/21 POLLUTION DEGREE (DIN VDE 0110, Table 1) 2 MAXIMUM WORKING INSULATION VOLTAGE V 891 V peak IORM INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1 VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC VPR 1671 V peak INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A VPR After Environmental Test Subgroup 1 1426 V peak V × 1.6 = V , t = 60 sec, Partial Discharge < 5 pC IORM PR m After Input and/or Safety Test Subgroup 2/Safety Test Subgroup 3 1069 V peak V × 1.2 = V , t = 60 sec, Partial Discharge < 5 pC IORM PR m HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, t = 10 sec) V 6000 V peak TR TR SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, ALSO SEE Figure 4) Case Temperature TS 150 °C Side 1 Current I 265 mA S1 Side 2 Current I 335 mA S2 9 INSULATION RESISTANCE AT TS, VIO = 500 V RS >10 Ω 350 300 250 SIDE 2 200 150 SIDE 1 100 50 0 0 50 100 150 200 CASE TEMPERATURE (°C) Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. C | Page 6 of 20 SAFETY-LIMITING CURRENT (mA) 07077-026 AD7400A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to Stresses above those listed under Absolute Maximum Ratings their respective ground. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 6. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to GND −0.3 V to +6.5 V DD1 1 maximum rating conditions for extended periods may affect VDD2 to GND2 −0.3 V to +6.5 V device reliability. Analog Input Voltage to GND1 −0.3 V to VDD1 + 0.3 V 1 Output Voltage to GND2 −0.3 V to VDD2 + 0.3 V Table 7. Maximum Continuous Working Voltage 1 Input Current to Any Pin Except Supplies ±10 mA Parameter Max Unit Constraint Operating Temperature Range −40°C to +125°C AC Voltage, 565 V peak 50-year minimum Storage Temperature Range −65°C to +150°C Bipolar Waveform lifetime Junction Temperature 150°C AC Voltage, 891 V peak Maximum CSA/VDE PDIP Package Unipolar Waveform approved working 2 voltage θJA Thermal Impedance 116.8°C/W 2 DC Voltage 891 V Maximum CSA/VDE θ Thermal Impedance 38.9°C/W JC approved working SOIC Package voltage 2 θJA Thermal Impedance 89.2°C/W 1 2 Refers to continuous voltage magnitude imposed across the isolation θJC Thermal Impedance 55.6°C/W barrier. See the Insulation Lifetime section for more details. 12 Resistance (Input-to-Output), RI-O 10 Ω 3 Capacitance (Input-to-Output), C 1.7 pF typ I-O RoHS-Compliant Temperature, Soldering ESD CAUTION Reflow 260 (+0)°C ESD 2.5 kV 1 Transient currents of up to 100 mA do not cause SCR to latch-up. 2 JEDEC 2S2P standard board. 3 f = 1 MHz. Rev. C | Page 7 of 20 AD7400A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 16 GND V 2 DD1 V + 2 15 IN NC AD7400A V – 3 14 V IN DD2 TOP VIEW NC 4 13 MCLKOUT (Not to Scale) 5 12 NC NC 6 11 V 1 8 V NC MDAT DD1 DD2 AD7400A V + 2 7 MCLKOUT V /NC 7 10 NC IN DD1 TOP VIEW V – 3 6 MDAT GND 8 9 GND IN 1 2 (Not to Scale) GND 4 5 GND 1 2 NC = NO CONNECT Figure 5. 8-Lead PDIP Pin Configuration Figure 6. 16-Lead SOIC Pin Configuration Table 8. Pin Function Descriptions Pin No. PDIP SOIC Mnemonic Description 1 1 V Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7400A and DD1 is relative to GND1. 2 2 VIN+ Positive Analog Input. Specified range of ±250 mV. 3 3 VIN− Negative Analog Input. Normally connected to GND1. 1 N/A 4 to 6, 10, 12, 15 NC No Connect. 1 N/A 7 V /NC Supply Voltage. 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7400A and is DD1 1 relative to GND . No Connect (NC). If desired, Pin 7 of the SOIC device may be allowed to float. It should not be tied to ground. The AD7400A will operate normally provided that the supply voltage is applied to Pin 1. 4 8 GND Ground 1. This is the ground reference point for all circuitry on the isolated side. 1 5 9, 16 GND Ground 2. This is the ground reference point for all circuitry on the nonisolated side. 2 6 11 MDAT Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are clocked out on the rising edge of the MCLKOUT output and are valid on the following MCLKOUT rising edge. 7 13 MCLKOUT Master Clock Logic Output (10 MHz Typical). The bit stream from the modulator is valid on the rising edge of MCLKOUT. 8 14 V Supply Voltage, 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND . DD2 2 1 N/A = not applicable. Rev. C | Page 8 of 20 07077-004 07077-104 AD7400A TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, using 20 kHz brickwall filter, unless otherwise noted. 110 –85 100 90 –80 80 70 –75 60 50 –70 40 30 –65 20 V = V = 5V DD1 DD2 NO DECOUPLING CAPACITOR V = V = 5V 10 DD1 DD2 V = 200mV SINE WAVE ON V RIPPLE DD1 T = 25°C A 0 –60 100 1k 10k 100k 1M 10M 50 100 150 200 250 300 350 SUPPLY RIPPLE FREQUENCY (Hz) INPUT AMPLITUDE (mV) Figure 10. SINAD vs. V Figure 7. PSRR vs. Supply Ripple Frequency Without Supply Decoupling IN (1 MHz Filter Used) 0.5 –90 V + = –200mV TO +200mV IN V – = 0V –80 0.4 IN –70 0.3 V = V = 4.5V DD1 DD2 –60 0.2 –50 0.1 –40 0 V = V = 5.5V DD1 DD2 V = V = 5V DD1 DD2 –30 –0.1 –20 –0.2 –10 –0.3 0 –0.4 0 500 1000 1500 2000 2500 3000 3500 4000 0 10,000 20,000 30,000 40,000 50,000 60,000 INPUT FREQUENCY (Hz) CODE Figure 8. SINAD vs. Analog Input Frequency for Various Supply Voltages Figure 11. Typical DNL, ±200 mV Range 3 (Using Sinc Filter, 256 Decimation Rate) 0 0.8 V + = –200mV TO +200mV 8192 POINT FFT IN V –= 0V f = 35Hz –20 IN IN 0.6 SINAD = 79.6991dB THD = –92.6722dB –40 DECIMATION BY 256 0.4 –60 0.2 –80 –100 0 –120 –0.2 –140 –0.4 –160 –180 –0.6 02 2 4 6 8 10 12 14 16 180 0 10,000 20,000 30,000 40,000 50,000 60,000 FREQUENCY (kHz) CODE Figure 9. Typical FFT, ±200 mV Range Figure 12. Typical INL, ±200 mV Range 3 3 (Using Sinc Filter, 256 Decimation Rate) (Using Sinc Filter, 256 Decimation Rate) Rev. C | Page 9 of 20 (dB) PSRR (dB) SINAD (dB) 07077-006 07077-007 07077-005 DNL ERROR (LSB) INL ERROR (LSB) SINAD (dB) 07077-010 07077-008 07077-009 AD7400A 500 3.9 +125°C 450 +85°C 3.7 400 3.5 350 300 +25°C 3.3 250 –40°C 3.1 200 150 2.9 100 2.7 50 V = V = 5V DD1 DD2 V = V = 5V DD2 DD1 T = 25°C A 0 2.5 –60 –40 –20 0 20 40 60 80 100 120 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 TEMPERATURE (°C) V DC INPUT VOLTAGE (V) IN Figure 13. Offset Drift vs. Temperature Figure 16. IDD2 vs. VIN at Various Temperatures 0.20 –30 0.15 –40 0.10 –50 V = V = 4.5V DD1 DD2 0.05 V = V = 5V DD1 DD2 –60 0 –70 –0.05 –80 –0.10 V = V = 5.5V –90 DD1 DD2 –0.15 –0.20 –100 –45–35–25–15 –5 5 152535455565758595 105 100 1k 10k 100k 1M 10M TEMPERATURE (°C) COMMON-MODE RIPPLE FREQUENCY (Hz) Figure 14 . Gain Error Drift vs. Temperature for Various Supply Voltages Figure 17. CMRR vs. Common-Mode Ripple Frequency 11.0 1.0 +125°C BANDWIDTH = 100kHz +85°C 10.5 0.8 +25°C 10.0 0.6 –40°C 9.5 0.4 9.0 0.2 V = V = 5V DD2 DD1 8.5 0 –0.33 –0.21 –0.09 0.03 0.15 0.27 0.39 V DC INPUT VOLTAGE (V) IN V DC INPUT (V) IN Figure 18. RMS Noise Voltage vs. V DC Input IN Figure 15. IDD1 vs. VIN at Various Temperatures Rev. C | Page 10 of 20 I (mA) DD1 GAIN (%) OFFSET (µV) 07077-032 07077-012 07077-013 CMRR (dB) I (mA) NOISE (mV) DD2 –0.30 –0.25 –0.20 –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 07077-017 07077-014 07077-015 AD7400A 11.0 10.8 10.6 10.4 V = V = 4.5V DD1 DD2 10.2 10.0 9.8 V = V = 5.25V 9.6 DD1 DD2 9.4 V = V = 5V DD1 DD2 9.2 9.0 TEMPERATURE (°C) Figure 19. MCLKOUT vs. Temperature for Various Supplies Rev. C | Page 11 of 20 MCLKOUT (MHz) –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 07077-024 AD7400A TERMINOLOGY Differential Nonlinearity Total Harmonic Distortion (THD) Differential nonlinearity is the difference between the measured THD is the ratio of the rms sum of harmonics to the and the ideal 1 LSB change between any two adjacent codes in fundamental. For the AD7400A, it is defined as the ADC. 2 2 2 2 2 V +V +V +V +V 2 3 4 5 6 THD(dB)= 20 log Integral Nonlinearity V 1 Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. where: The endpoints of the transfer function are specified negative V1 is the rms amplitude of the fundamental. full scale, −250 mV (VIN+ − VIN−), Code 7169, and specified V , V , V , V , and V are the rms amplitudes of the second 2 3 4 5 6 positive full scale, +250 mV (VIN+ − VIN−), Code 58,366 for through the sixth harmonics. the 16-bit level. Peak Harmonic or Spurious Noise Offset Error Peak harmonic or spurious noise is defined as the ratio of the rms Offset is the deviation of the midscale code (Code 32,768 for value of the next largest component in the ADC output spectrum the 16-bit level) from the ideal V + − V − (that is, 0 V). IN IN (up to fS/2, excluding dc) to the rms value of the fundamental. Gain Error Normally, the value of this specification is determined by the Gain error includes both positive full-scale gain error and largest harmonic in the spectrum, but for ADCs where the negative full-scale gain error. Positive full-scale gain error is the harmonics are buried in the noise floor, it is a noise peak. deviation of the specified positive full-scale code (58,366 for the Common-Mode Rejection Ratio (CMRR) 16-bit level) from the ideal VIN+ − VIN− (+250 mV) after the CMRR is defined as the ratio of the power in the ADC output at offset error is adjusted out. Negative full-scale gain error is the ±250 mV frequency, f, to the power of a 250 mV p-p sine wave deviation of the specified negative full-scale code (7169 for the applied to the common-mode voltage of VIN+ and VIN− of 16-bit level) from the ideal V + − V − (−250 mV) after the IN IN frequency fS as offset error is adjusted out. Gain error includes reference error. CMRR (dB) = 10 log(Pf/PfS) Signal-to-Noise and Distortion (SINAD) Ratio where: This ratio is the measured ratio of signal-to-noise and distortion at the output of the ADC. The signal is the rms amplitude of the Pf is the power at frequency f in the ADC output. fundamental. Noise is the sum of all nonfundamental signals up Pf is the power at frequency f in the ADC output. S S to half the sampling frequency (f /2), excluding dc. The ratio is S dependent on the number of quantization levels in the digitization Power Supply Rejection Ratio (PSRR) process; the more levels, the smaller the quantization noise. The Variations in power supply affect the full-scale transition but theoretical signal-to-noise and distortion ratio for an ideal N-bit not the converter linearity. PSRR is the maximum change in the specified full-scale (±250 mV) transition point due to a change converter with a sine wave input is given by in power supply voltage from the nominal value (see Figure 7). Signal-to-Noise and Distortion = (6.02N + 1.76) dB Isolation Transient Immunity Therefore, for a 12-bit converter, SINAD is 74 dB. The isolation transient immunity specifies the rate of rise/fall of Effective Number of Bits (ENOB) a transient pulse applied across the isolation boundary beyond The ENOB is defined by which clock or data is corrupted. (The AD7400A was tested using ENOB = (SINAD − 1.76)/6.02 a transient pulse frequency of 100 kHz.) Rev. C | Page 12 of 20 AD7400A THEORY OF OPERATION A differential input of 320 mV ideally results in a stream of all CIRCUIT INFORMATION 1s. This is the absolute full-scale range of the AD7400A, while The AD7400A isolated Σ-Δ modulator converts an analog input 250 mV is the specified full-scale range, as shown in Table 9. signal into a high speed (10 MHz typical), single-bit data stream; the time average of the single-bit data from the modulator is Table 9. Analog Input Range directly proportional to the input signal. Figure 22 shows a Analog Input Voltage Input typical application circuit where the AD7400A is used to provide Full-Scale Range +640 mV isolation between the analog input, a current sensing resistor, Positive Full Scale +320 mV and the digital output, which is then processed by a digital filter Positive Typical Input Range +250 mV to provide an N-bit word. Positive Specified Input Range +200 mV ANALOG INPUT Zero 0 mV Negative Specified Input Range −200 mV The differential analog input of the AD7400A is implemented Negative Typical Input Range −250 mV with a switched capacitor circuit. This circuit implements a Negative Full Scale −320 mV second-order modulator stage that digitizes the input signal into a 1-bit output stream. The sample clock (MCLKOUT) To reconstruct the original information, this output needs provides the clock signal for the conversion process as well as 3 to be digitally filtered and decimated. A Sinc filter is recom- the output data-framing clock. This clock source is internal on mended because this is one order higher than that of the the AD7400A. The analog input signal is continuously sampled AD7400A modulator. If a 256 decimation rate is used, the by the modulator and compared to an internal voltage reference. A resulting 16-bit word rate is 39 kHz, assuming a 10 MHz digital stream that accurately represents the analog input over internal clock frequency. Figure 21 shows the transfer function time appears at the output of the converter (see Figure 20). of the AD7400A relative to the 16-bit output. MODULATOR OUTPUT +FS ANALOG INPUT 65535 –FS ANALOG INPUT 53248 ANALOG INPUT Figure 20. Analog Input vs. Modulator Output SPECIFIED RANGE A differential signal of 0 V ideally results in a stream of 1s and 0s at the MDAT output pin. This output is high 50% of the time 12288 and low 50% of the time. A differential input of 200 mV produces a stream of 1s and 0s that are high 81.25% of the time (for a +250 mV input, the output stream is high 89.06% of the time). A differential input of −200 mV produces a stream of 1s and 0s that are high 18.75% of the time (for a −250 mV input, the output 0 stream is high 10.94% of the time). –320mV –200mV +200mV +320mV ANALOG INPUT Figure 21. Filtered and Decimated 16-Bit Transfer Characteristic ISOLATED NONISOLATED 5V 5V/3V AD7400A V V V DD1 DD2 DD 3 SINC FILTER* Σ-∆ CS MOD/ V + MDAT MDAT IN ENCODER DECODER + SCLK INPUT CURRENT MCLKOUT MCLK V – IN SDAT R SHUNT DECODER ENCODER GND GND GND 1 2 *THIS FILTER IS IMPLEMENTED WITH AN FPGA OR DSP. Figure 22. Typical Application Circuit Rev. C | Page 13 of 20 07077-019 ADC CODE 07077-018 07077-020 AD7400A DIFFERENTIAL INPUTS CURRENT SENSING APPLICATIONS The analog input to the modulator is a switched capacitor The AD7400A is ideally suited for current sensing applications design. The analog signal is converted into charge by highly where the voltage across a shunt resistor is monitored. The load linear sampling capacitors. A simplified equivalent circuit current flowing through an external shunt resistor produces a diagram of the analog input is shown in Figure 23. A signal voltage at the input terminals of the AD7400A. The AD7400A source driving the analog input must be able to provide the provides isolation between the analog input from the current charge onto the sampling capacitors every half MCLKOUT cycle sensing resistor and the digital outputs. By selecting the appropriate and settle to the required accuracy within the next half cycle. shunt resistor value, a variety of current ranges can be monitored. Choosing R SENSE φA 1kΩ The shunt resistor values used in conjunction with the AD7400A φB V + IN 2pF are determined by the specific application requirements in terms of voltage, current, and power. Small resistors minimize power 2pF φA dissipation, while low inductance resistors prevent any induced 1kΩ φB V – IN voltage spikes, and good tolerance devices reduce current variations. The final values chosen are a compromise between φA φB φA φB low power dissipation and good accuracy. Low value resistors MCLKOUT have less power dissipated in them, but higher value resistors Figure 23. Analog Input Equivalent Circuit may be required to use the full input range of the ADC, thus Because the AD7400A samples the differential voltage across its achieving maximum SNR performance. analog inputs, low noise performance is attained with an input When the peak sense current is known, the voltage range of the circuit that provides low common-mode noise at each input. AD7400A (±200 mV) is divided by the maximum sense current The amplifiers used to drive the analog inputs play a critical to yield a suitable shunt value. If the power dissipation in the shunt role in attaining the high performance available from the resistor is too large, the shunt resistor can be reduced, in which AD7400A. case, less of the ADC input range is used. Using less of the ADC When a capacitive load is switched onto the output of an op input range results in performance that is more susceptible to noise amp, the amplitude drops momentarily. The op amp tries to and offset errors because offset errors are fixed and are thus more correct the situation and, in the process, hits its slew rate limit. significant when smaller input ranges are used. This nonlinear response, which can cause excessive ringing, can R must be able to dissipate the I2R power losses. If the power SENSE lead to distortion. To remedy the situation, a low-pass RC filter dissipation rating of the resistor is exceeded, its value may drift can be connected between the amplifier and the input to the or the resistor may be damaged, resulting in an open circuit. AD7400A. The external capacitor at each input aids in supplying This can result in a differential voltage across the terminals of the current spikes created during the sampling process, and the the AD400A in excess of the absolute maximum ratings (see resistor isolates the op amp from the transient nature of the load. Table 6.). If I has a large high frequency component, take SENSE The recommended circuit configuration for driving the differential care to choose a resistor with low inductance. inputs to achieve best performance is shown in Figure 24. A VOLTAGE SENSING APPLICATIONS capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by one input to be The AD7400A can also be used for isolated voltage monitoring. effectively supplied by the other input. The series resistor again For example, in motor control applications, it can be used to isolates any op amp from the current spikes created during the sense bus voltage. In applications where the voltage being sampling process. Recommended values for the resistors and monitored exceeds the specified analog input range of the capacitor are 22 Ω and 47 pF, respectively. AD7400A, a voltage divider network can be used to reduce R the voltage being monitored to the required range. V + IN C AD7400A R V – IN Figure 24. Differential Input RC Network Rev. C | Page 14 of 20 07077-028 07077-027 AD7400A reg [23:0] diff2; DIGITAL FILTER reg [23:0] diff3; The overall system resolution and throughput rate is deter- reg [23:0] diff1_d; mined by the filter selected and the decimation rate used. The higher the decimation rate, the greater the system accuracy, as reg [23:0] diff2_d; illustrated in Figure 25. However, there is a tradeoff between reg [15:0] DATA; accuracy and throughput rate and, therefore, higher decimal- reg [7:0] word_count; tion rates result in lower throughput solutions. reg word_clk; 3 A Sinc filter is recommended for use with the AD7400A. This reg init; filter can be implemented on an FPGA or a DSP. 3 DR /*Perform the Sinc ACTION*/ ⎛(1− Z )⎞ H(z)=⎜ ⎟ −1 ⎜ ⎟ always @ (mdata1) () 1− Z ⎝ ⎠ if(mdata1==0) ip_data1 <= 0; /* change from a 0 where DR is the decimation rate. to a -1 for 2's comp */ 90 3 SINC else 80 ip_data1 <= 1; /*ACCUMULATOR (INTEGRATOR) 70 2 SINC Perform the accumulation (IIR) at the speed 60 of the modulator. MCLKOUT 50 ACC1+ ACC2+ 40 ACC3+ IP_DATA1 Z Z Z 1 SINC + + + 30 Figure 26. Accumulator 20 Z = one sample delay 10 MCLKOUT = modulators conversion bit rate 0 */ 1 10 100 1k always @ (negedge mclk1 or posedge reset) DECIMATION RATE if (reset) Figure 25. SNR vs. Decimation Rate for Different Filter Types begin 3 The following Verilog code provides an example of a Sinc filter /*initialize acc registers on reset*/ acc1 <= 0; implementation on a Xilinx® Spartan-II 2.5 V FPGA. This code acc2 <= 0; can possibly be compiled for another FPGA, such as an Altera® acc3 <= 0; device. Note that the data is read on the negative clock edge in end this case, although it can be read on the positive edge, if preferred. else Figure 25 shows the effect of using different decimation rates begin /*perform accumulation process*/ with various filter types. acc1 <= acc1 + ip_data1; /*`Data is read on negative clk edge*/ acc2 <= acc2 + acc1; module DEC256SINC24B(mdata1, mclk1, reset, acc3 <= acc3 + acc2; DATA); end input mclk1; /*used to clk filter*/ input reset; /*used to reset filter*/ /*DECIMATION STAGE (MCLKOUT/ WORD_CLK) input mdata1; /*ip data to be */ filtered*/ always @ (posedge mclk1 or posedge reset) output [15:0] DATA; /*filtered op*/ if (reset) integer location; word_count <= 0; integer info_file; else word_count <= word_count + 1; reg [23:0] ip_data1; always @ (word_count) reg [23:0] acc1; word_clk <= word_count[7]; reg [23:0] acc2; reg [23:0] acc3; reg [23:0] acc3_d1; reg [23:0] acc3_d2; reg [23:0] diff1; Rev. C | Page 15 of 20 SNR (dB) 07077-025 07077-021 AD7400A /*DIFFERENTIATOR (including decimation diff2_d <= diff2; stage) end Perform the differentiation stage (FIR) at a /* Clock the Sinc output into an output lower speed. register DIFF1 DIFF2 DIFF3 + + + WORD_CLK ACC3 – – – – –1 –1 –1 Z Z Z DIFF3 DATA Figure 28. Clocking Sinc Output into an Output Register WORD_CLK WORD_CLK = output word rate Figure 27. Differentiator */ Z = one sample delay always @ (posedge word_clk) WORD_CLK = output word rate begin */ DATA[15] <= diff3[23]; DATA[14] <= diff3[22]; always @ (posedge word_clk or posedge reset) DATA[13] <= diff3[21]; if(reset) DATA[12] <= diff3[20]; begin DATA[11] <= diff3[19]; acc3_d2 <= 0; DATA[10] <= diff3[18]; diff1_d <= 0; DATA[9] <= diff3[17]; diff2_d <= 0; DATA[8] <= diff3[16]; diff1 <= 0; DATA[7] <= diff3[15]; diff2 <= 0; DATA[6] <= diff3[14]; diff3 <= 0; DATA[5] <= diff3[13]; end DATA[4] <= diff3[12]; DATA[3] <= diff3[11]; else DATA[2] <= diff3[10]; DATA[1] <= diff3[9]; begin DATA[0] <= diff3[8]; diff1 <= acc3 - acc3_d2; diff2 <= diff1 - diff1_d; end diff3 <= diff2 - diff2_d; endmodule acc3_d2 <= acc3; diff1_d <= diff1; Rev. C | Page 16 of 20 07077-022 07077-023 AD7400A APPLICATIONS INFORMATION INSULATION LIFETIME GROUNDING AND LAYOUT All insulation structures subjected to sufficient time and/or Supply decoupling with a value of 100 nF is strongly recom- voltage are vulnerable to breakdown. In addition to the testing mended on both V and V . Decoupling on one or DD1 DD2 performed by the regulatory agencies, Analog Devices has carried both V pins does not significantly affect performance. In DDx out an extensive set of evaluations to determine the lifetime of applications involving high common-mode transients, ensure the insulation structure within the AD7400A. that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed so that These tests subjected populations of devices to continuous any coupling that occurs equally affects all pins on a given cross-isolation voltages. To accelerate the occurrence of failures, component side. Failure to ensure this may cause voltage the selected test voltages were values exceeding those of normal differentials between pins to exceed the absolute maximum use. The time to failure values of these units were recorded and ratings of the device, thereby leading to latch-up or permanent used to calculate acceleration factors. These factors were then damage. Any decoupling used should be placed as close to the used to calculate the time to failure under normal operating supply pins as possible. conditions. The values shown in Table 7 are the lesser of the following two values: Series resistance in the analog inputs should be minimized to avoid any distortion effects, especially at high temperatures. If • The value that ensures at least a 50-year lifetime of possible, equalize the source impedance on each analog input to continuous use. minimize offset. Beware of mismatch and thermocouple effects • The maximum CSA/VDE approved working voltage. on the analog input PCB tracks to reduce offset drift. Note that the lifetime of the AD7400A varies according to EVALUATING THE AD7400A PERFORMANCE the waveform type imposed across the isolation barrier. The An AD7400A evaluation board is available with split ground iCoupler insulation structure is stressed differently depending planes and a board split beneath the AD7400A package to on whether the waveform is bipolar ac, unipolar ac, or dc. ensure isolation. This board allows access to each pin on the Figure 29, Figure 30, and Figure 31 illustrate the different device for evaluation purposes. isolation voltage waveforms. RATED PEAK VOLTAGE The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for 0V controlling the board from the PC via the EVAL-CED1Z. The 3 software also includes a SINC filter implemented on an FPGA. Figure 29. Bipolar AC Waveform The evaluation board is used in conjunction with the EVAL-CED1Z board and can be used as a standalone board. The software RATED PEAK VOLTAGE allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7400A. The software and documentation are on a CD that ships with the evaluation board. 0V Figure 30. Unipolar AC Waveform RATED PEAK VOLTAGE 0V Figure 31. DC Waveform Rev. C | Page 17 of 20 07077-031 07077-030 07077-029 AD7400A OUTLINE DIMENSIONS 0.379 (9.63) 0.375 (9.53) 0.371 (9.43) 0.388 (9.86) 8 5 0.254 (6.45) 0.380 (9.65) 0.250 (6.35) 0.372 (9.45) 0.246 (6.25) 1 4 0.300 (7.62) REF 0.065 (1.651) 0.135 (3.43) 0.134 (3.40) REF REF 0.130 (3.30) 0.126 (3.20) 0.012 (0.305) 0.010 (0.245) 0.008 (0.203) 0.012 (0.303) 0.037 (0.94) 0.008 (0.203) 0.035 (0.89) 0.100 (2.54) 0.004 (0.103) REF 0.044 (1.118) 0.033 (0.84) 0.040 (1.016) 0.053 (1.35) 0.036 (0.915) 0.051 (1.30) 0.049 (1.25) NOTE TH AT THIS IS A PDIP CONVERTED TO SMD. CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCHES EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 32. 8-Lead DIP Style Surface Mount Package, With Gull Wing Leads [PDIP_SMD] (NS-8) Dimensions shown in inches and (millimeters) 10.50 (0.4134) 10.10 (0.3976) 16 9 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 8 10.00 (0.3937) 1.27 (0.0500) 45° BSC 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.51 (0.0201) 0.10 1.27 (0.0500) 0.33 (0.0130) PLANE 0.31 (0.0122) 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 33. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Package 1 Model Temperature Range Package Description Option AD7400AYNSZ −40°C to +125°C 8-Lead DIP Style Surface Mount Package, With Gull Wing Leads (PDIP_SMD) NS-8 AD7400AYRWZ −40°C to +125°C 16-Lead Standard Small Outline Package (SOIC_W) RW-16 AD7400AYRWZ-RL −40°C to +125°C 16-Lead Standard Small Outline Package (SOIC_W) RW-16 EVAL-AD7400AEDZ Standalone Evaluation Board EVAL-CED1Z Development Board 1 Z = RoHS Compliant Part. Rev. C | Page 18 of 20 0.75 (0.0295) 0.25 (0.0098) 03-27-2007-B 090507-A AD7400A NOTES Rev. C | Page 19 of 20 AD7400A NOTES ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07077-0-7/11(C) Rev. C | Page 20 of 20