ANALOG DEVICES AD7366-5

True Bipolar Input, 12-/14-Bit, 2-Channel, Simultaneous Sampling SAR ADCs AD7366-5/AD7367-5 FEATURES FUNCTIONAL BLOCK DIAGRAM V D A AV DV Dual 12-bit/14-bit, 2-channel ADCs DD CAP CC CC True bipolar analog inputs Programmable input ranges REF BUF AD7366-5/AD7367-5 ±10 V, ±5 V, 0 V to +10 V ±12 V with +3 V external reference V A1 Throughput rate: 500 kSPS 12-/14-BIT SUCCESSIVE OUTPUT Simultaneous conversion with read in less than 2 μs MUX T/H D A OUT APPROXIMATION DRIVERS ADC High analog input impedance V A2 Low current consumption SCLK CNVST 5.1 mA typical in normal mode CS 320 nA typical in shutdown mode CONTROL BUSY LOGIC ADDR AD7366-5 RANGE0 72 dB SNR at 50 kHz input frequency RANGE1 REFSEL 12-bit no missing codes V B1 V DRIVE AD7367-5 76 dB SNR at 50 kHz input frequency MUX T/H 12-/14-BIT SUCCESSIVE OUTPUT 14-bit no missing codes D B OUT APPROXIMATION DRIVERS ADC Accurate on-chip reference: 2.5 V ± 0.2% V B2 –40°C to +85°C operation BUF High speed serial interface SPI-/QSPI-/MICROWIRE-/DSP-compatible AGND AGND V D B DGND SS CAP iCMOS process technology Figure 1. Available in a 24-lead TSSOP GENERAL DESCRIPTION The devices have an on-chip 2.5 V reference that can be disabled to 1 allow the use of an external reference. If a 3 V reference is applied The AD7366-5/AD7367-5 are dual, 12-/14-bit, low power, to the DCAPA and DCAPB pins, the AD7366-5/AD7367-5 can successive approximation analog-to-digital converters (ADCs) accept a true bipolar ±12 V analog input. Minimum ±12 V VDD that feature throughput rates up to 500 kSPS. Each device contains and VSS supplies are required for the ±12 V input range. two ADCs, which are both preceded by a 2-channel multiplexer, and a low noise, wide bandwidth, track-and-hold amplifier. PRODUCT HIGHLIGHTS The AD7366-5/AD7367-5 are fabricated on the Analog 1. True bipolar analog input signals can be accepted, as well 2 Devices, Inc., industrial CMOS process (iCMOS®) , which is as ±10 V, ±5 V, ±12 V (with external reference), and 0 V to a technology platform combining the advantages of low and +10 V unipolar signals. high voltage CMOS. The process allows the parts to accept 2. Two complete ADC functions allow simultaneous high voltage bipolar signals in addition to reducing power sampling and conversion of two channels. consumption and package size. The AD7366-5/AD7367-5 can accept true bipolar analog input signals in the ±10 V range, 3. A 500 kSPS serial interface is SPI-/QSPI™-/MICROWIRE™-/ ±5 V range, and 0 V to +10 V range. DSP-compatible. Table 1. Related Products Device Resolution Throughput Rate No. of Channels AD7366 12-Bit 1 MSPS Dual, 2-channel 1 Protected by U.S. Patent No. 6,731,232. 2 AD7366-5 12-Bit 500 kSPS Dual, 2-channel For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS is a AD7367 14-Bit 1 MSPS Dual, 2-channel technology platform that enables the development of analog ICs capable of AD7367-5 14-Bit 500 kSPS Dual, 2-channel +30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06842-001 AD7366-5/AD7367-5 TABLE OF CONTENTS Features .............................................................................................. 1  Typical Connection Diagram ................................................... 18  Functional Block Diagram .............................................................. 1  Driver Amplifier Choice ........................................................... 19  General Description ......................................................................... 1  Reference ..................................................................................... 19  Product Highlights ........................................................................... 1  Modes of Operation ....................................................................... 20  Revision History ............................................................................... 2  Normal Mode .............................................................................. 20  Specif ica t ions ..................................................................................... 3  Shutdown Mode ......................................................................... 21  AD7366-5 Specifications ............................................................. 3  Power-Up Times ......................................................................... 21  AD7367-5 Specifications ............................................................. 5  Serial Interface ................................................................................ 22  Timing Specifications .................................................................. 7  Microprocessor Interfacing ........................................................... 24  Absolute Maximum Ratings ............................................................ 8  AD7366-5/AD7367-5 to ADSP-218x ...................................... 24  ESD Caution .................................................................................. 8  AD7366-5/AD7367-5 to ADSP-BF53x ................................... 25  Pin Configuration and Function Descriptions ............................. 9  AD7366-5/AD7367-5 to TMS320VC5506 ............................. 25  Typical Performance Characteristics ........................................... 11  AD7366-5/AD7367-5 to DSP563xx......................................... 26  Terminology .................................................................................... 14  Application Hints ........................................................................... 27  Theory of Operation ...................................................................... 16  Layout and Grounding .............................................................. 27  Circuit Information .................................................................... 16  Evaluating the AD7366-5/AD7367-5 ...................................... 27  Converter Operation .................................................................. 16  Outline Dimensions ....................................................................... 28  Analog Inputs .............................................................................. 17  Ordering Guide .......................................................................... 28  Transfer Function ....................................................................... 17  REVISION HISTORY 8/09—Rev. 0 to Rev. A Changes to Table 2 ............................................................................ 4 Changes to Table 3 ............................................................................ 6 7/07—Revision 0: Initial Version Rev. A | Page 2 of 28 AD7366-5/AD7367-5 SPECIFICATIONS AD7366-5 SPECIFICATIONS AV = DV = 4.75 V to 5.25 V; V = 5 V to 16.5 V; V = −16.5 V to −5 V; V = 2.7 V to 5.25 V; f = 500 kSPS; f = 20 MHz; CC CC DD SS DRIVE SAMPLE SCLK V = 2.5 V internal/external; T = −40°C to +85°C, unless otherwise noted. REF A Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave 1 Signal-to-Noise Ratio (SNR) 70 72 dB 1 Signal-to-Noise (+ Distortion) Ratio (SINAD)70 71 dB 1 Total Harmonic Distortion (THD) −85 −78 dB 1 Spurious-Free Dynamic Range (SFDR) −87 −78 dB 1 Intermodulation Distortion (IMD) fa = 49 kHz, fb = 51 kHz Second-Order Terms −88 dB Third-Order Terms −88 dB 1 Channel-to-Channel Isolation −90 dB SAMPLE AND HOLD 2 Aperture Delay 10 ns 2 Aperture Jitter 40 ps 2 Aperture Delay Matching ±100 ps Full Power Bandwidth 35 MHz @ 3 dB, ±10 V range 8 MHz @ 0.1 dB, ±10 V range DC ACCURACY Resolution 12 Bits 1 Integral Nonlinearity (INL) ±0.5 ±1 LSB 1 Differential Nonlinearity (DNL) ±0.25 ±0.5 LSB Guaranteed no missed codes to 12 bits 1 Positive Full-Scale Error ±1 ±7 LSB ±5 V and ±10 V analog input range ±1 ±6 LSB 0 V to 10 V analog input range 1 Positive Full-Scale Error Match ±1.5 LSB Matching from ADC A to ADC B ±0.1 LSB Channel-to-channel matching for ADC A and ADC B 1 Zero Code Error ±0.5 ±3 LSB ±5 V and ±10 V analog input range ±1 ±6 LSB 0 V to 10 V analog input range 1 Zero Code Error Match ±1.5 LSB Matching from ADC A to ADC B ±0.1 LSB Channel-to-channel matching for ADC A and ADC B 1 Negative Full-Scale Error ±1 ±7 LSB ±5 V and ±10 V analog input range ±1 ±6 LSB 0 V to 10 V analog input range 1 Negative Full-Scale Error Match ±1.5 LSB Matching from ADC A to ADC B ±0.1 LSB Channel-to-channel matching for ADC A and ADC B ANALOG INPUT Input Voltage Ranges ±10 V (Programmed via RANGE Pins) ±5 V 0 to 10 V DC Leakage Current ±0.01 ±1 μA Input Capacitance 9 pF When in track, ±10 V range 13 pF When in track, ±5 V or 0 V to +10 V range Input Impedance 500 kΩ For ±10 V @ 500 kSPS 2.5 MΩ For ±10 V @ 100 kSPS 250 kΩ For ±5 V/0 V to +10 V @ 500 kSPS 1.2 MΩ For ±5 V/0 V to +10 V @ 100 kSPS Rev. A | Page 3 of 28 AD7366-5/AD7367-5 Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT 3 Reference Output Voltage 2.494 2.5 2.506 V ±0.2% maximum @ 25°C Long-Term Stability 150 ppm For 1000 hours 1 Output Voltage Hysteresis 50 ppm Reference Input Voltage Range 2.5 3.0 V DC Leakage Current ±0.01 ±1 μA External reference applied to Pin D A/Pin D B CAP CAP Input Capacitance 25 pF ±5 V and ±10 V analog input range 17 pF 0 V to 10 V analog input range D A, D B Output Impedance 7 Ω CAP CAP Reference Temperature Coefficient 6 25 ppm/°C V Noise 20 μV rms Bandwidth = 3 kHz REF LOGIC INPUTS Input High Voltage, V 0.7 × V V INH DRIVE Input Low Voltage, V +0.8 V INL Input Current, IIN ±0.01 ±1 μA VIN = 0 V or VDRIVE 2 Input Capacitance, CIN 6 pF LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V Output Low Voltage, VOL 0.4 V Floating State Leakage Current ±0.01 ±1 μA 2 Floating State Output Capacitance 8 pF CONVERSION RATE Conversion Time 1.25 μs 2 Track/Hold Acquisition Time 140 ns Full-scale step input Throughput Rate 500 kSPS For 2.7 V ≤ V ≤ 5.25 V, f = 20 MHz DRIVE SCLK POWER REQUIREMENTS Digital inputs = 0 V or V DRIVE V 4.75 5.25 V See Table 7 CC V 5 16.5 V See Table 7 DD VSS −16.5 −5 V See Table 7 VDRIVE 2.7 5.25 V Normal Mode (Static) I 370 550 μA V = 16.5 V DD DD I 40 60 μA V = −16.5 V SS SS ICC 1.5 2.25 mA VCC = 5.5 V Normal Mode (Operational) fS = 500 kSPS IDD 1 1.2 mA VDD = 16.5 V I 0.7 0.82 mA V = −16.5 V SS SS I 3.4 4 mA V = 5.25 V, internal reference enabled CC CC Shutdown Mode IDD 0.01 1 μA VDD = 16.5 V ISS 0.01 1 μA VSS = −16.5 V ICC 0.3 3 μA VCC = 5.25 V Power Dissipation Normal Mode (Operational) 46 54.5 mW V = +16.5 V, V = −16.5 V, V = +5.25 V, DD SS CC fS = 500 kSPS 15 mW ±10 V input range, fS = 100 kSPS 20 mW ±5 V and 0 V to +10 V input range, fS = 100 kSPS Shutdown Mode 1.9 48.75 μW VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V 1 See the Terminology section. 2 Sample tested during initial release to ensure compliance. 3 o Refers to Pin D A or Pin D B specified for 25 C. CAP CAP Rev. A | Page 4 of 28 AD7366-5/AD7367-5 AD7367-5 SPECIFICATIONS AVCC = DVCC = 4.75 V to 5.25 V; VDD = 5 V to 16.5 V; VSS = −16.5 V to −5 V; VDRIVE = 2.7 V to 5.25 V; fSAMPLE = 500 kSPS; fSCLK = 20 MHz; VREF = 2.5 V internal/external; TA = −40°C to +85°C, unless otherwise noted. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave 1 Signal-to-Noise Ratio (SNR) 74 76 dB 1 Signal-to-Noise (+ Distortion) Ratio (SINAD) 73 75 dB 1 Total Harmonic Distortion (THD) −84 −78 dB 1 Spurious-Free Dynamic Range (SFDR) −87 −79 dB 1 Intermodulation Distortion (IMD) fa = 49 kHz, fb = 51 kHz Second-Order Terms −91 dB Third-Order Terms −89 dB 1 Channel-to-Channel Isolation −90 dB SAMPLE AND HOLD 2 Aperture Delay 10 ns 2 Aperture Jitter 40 ps 2 Aperture Delay Matching ±100 ps Full Power Bandwidth 35 MHz @ 3 dB, ±10 V range 8 MHz @ 0.1 dB, ±10 V range DC ACCURACY Resolution 14 Bits 1 Integral Nonlinearity (INL) ±2 ±3.5 LSB 1 Differential Nonlinearity (DNL) ±0.5 ±0.90 LSB Guaranteed no missed codes to 14 bits 1 Positive Full-Scale Error ±4 ±25 LSB ±5 V and ±10 V analog input range ±5 ±25 LSB 0 V to 10 V analog input range 1 Positive Full-Scale Error Match ±3 LSB Matching from ADC A to ADC B ±0.2 LSB Channel-to-channel matching for ADC A and ADC B 1 Zero Code Error ±1 ±10 LSB ±5 V and ±10 V analog input range ±5 ±25 LSB 0 V to 10 V analog input range 1 Zero Code Error Match ±3 LSB Matching from ADC A to ADC B ±0.2 LSB Channel-to-channel matching for ADC A and ADC B 1 Negative Full-Scale Error ±4 ±25 LSB ±5 V and ±10 V analog input range ±5 ±25 LSB 0 V to 10 V analog input range 1 Negative Full-Scale Error Match ±3 LSB Matching from ADC A to ADC B ±0.2 LSB Channel-to-channel matching for ADC A and ADC B ANALOG INPUT Input Voltage Ranges ±10 V (Programmed via RANGE Pins) ±5 V 0 to 10 V See Table 7 DC Leakage Current ±0.01 ±1 μA Input Capacitance 9 pF When in track, ±10 V range 13 pF When in track, ±5 V or 0 V to +10 V range Input Impedance 500 kΩ For ±10 V @ 500 kSPS 2.5 MΩ For ±10 V @ 100 kSPS 250 kΩ For ±5 V/0 V to +10 V @ 500 kSPS 1.2 MΩ For ±5 V/0 V to +10 V @ 100 kSPS Rev. A | Page 5 of 28 AD7366-5/AD7367-5 Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT 3 Reference Output Voltage 2.494 2.5 2.506 V ±0.2% maximum @ 25°C Long-Term Stability 150 ppm For 1000 hours 1 Output Voltage Hysteresis 50 ppm Reference Input Voltage Range 2.5 3.0 V DC Leakage Current ±0.01 ±1 μA External reference applied to D A/Pin D B CAP CAP Input Capacitance 25 pF ±5 V and ±10 V analog input range 17 pF 0 V to 10 V analog input range D A, D B Output Impedance 7 Ω CAP CAP Reference Temperature Coefficient 6 25 ppm/°C V Noise 20 μV rms Bandwidth = 3 kHz REF LOGIC INPUTS Input High Voltage, V 0.7 × V V INH DRIVE Input Low Voltage, V 0.8 V INL Input Current, IIN ±0.01 ±1 μA VIN = 0 V or VDRIVE 2 Input Capacitance, CIN 6 pF LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V Output Low Voltage, VOL 0.4 V Floating State Leakage Current ±0.01 ±1 μA 2 Floating State Output Capacitance 8 pF CONVERSION RATE Conversion Time 1.25 ns 2 Track/Hold Acquisition Time 140 ns Full-scale step input Throughput Rate 500 kSPS For 2.7 V ≤ V ≤ 5.25 V, f = 20 MHz DRIVE SCLK POWER REQUIREMENTS Digital inputs = 0 V or V DRIVE V 4.75 5.25 V See Table 7 CC V 5 16.5 V See Table 7 DD VSS −16.5 −5 V See Table 7 VDRIVE 2.7 5.25 V Normal Mode (Static) I 370 550 μA V = 16.5 V DD DD I 40 60 μA V = −16.5 V SS SS ICC 1.5 2.25 mA VCC = 5.5 V Normal Mode (Operational) fS = 500 kSPS IDD 1 1.2 mA VDD = 16.5 V I 0.7 0.82 mA V = −16.5 V SS SS I 3.4 4 mA V = 5.25 V, internal reference enabled CC CC Shutdown Mode IDD 0.01 1 μA VDD = 16.5 V ISS 0.01 1 μA VSS = −16.5 V ICC 0.3 3 μA VCC = 5.25 V Power Dissipation Normal Mode (Operational) 46 54.5 mW V = +16.5 V, V = −16.5 V, V = +5.25 V DD SS CC 15 mW ±10 V input range, f = 100 kSPS S 20 mW ±5 V and 0 V to +10 V input range, fS = 100 kSPS Shutdown Mode 1.9 48.75 μW VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V 1 See the Terminology section. 2 Sample tested during initial release to ensure compliance. 3 Refers to Pin D A or Pin D B. CAP CAP Rev. A | Page 6 of 28 AD7366-5/AD7367-5 TIMING SPECIFICATIONS 1 AVCC = DVCC = 4.75 V to 5.25 V; VDD = 5 V to 16.5 V; VSS = −16.5 V to −5 V; VDRIVE = 2.7 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted. Table 4. Parameter 2.7 V ≤ VDRIVE ≤ 5.25 V Unit Test Conditions/Comments t CONVERT Conversion time, internal clock. CONVST falling edge to BUSY falling edge. 1.25 μs max For the AD7367-5. 1.25 μs max For the AD7366-5. fSCLK 10 kHz min Frequency of serial read clock. 20 MHz max t 50 ns min Minimum quiet time required between the end of serial read and the start of the next QUIET conversion. t1 10 ns min Minimum CONVST low pulse. t2 40 ns min CONVST falling edge to BUSY rising edge. t 0 ns min BUSY falling edge to MSB valid once CS is low for t prior to BUSY going low. 3 4 t 10 ns max Delay from CS falling edge until Pin 1 (D A) and Pin 23 (D B) are three-state disabled. 4 OUT OUT 2 t 20 ns max Data access time after SCLK falling edge. 5 t6 7 ns min SCLK to data valid hold time. t7 0.3 × tSCLK ns min SCLK low pulse width. t8 0.3 × tSCLK ns min SCLK high pulse width. t 10 ns max CS rising edge to D A, D B, high impedance. 9 OUT OUT t 70 μs max Power up time from shutdown mode; time required between CONVST rising edge and POWER-UP CONVST falling edge. 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. R F DRIVE All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Terminology section and Figure 25. 2 The time required for the output to cross is 0.4 V or 2.4 V. Rev. A | Page 7 of 28 AD7366-5/AD7367-5 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 5. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to AGND, DGND −0.3 V to +16.5 V DD other conditions above those indicated in the operational V to AGND, DGND −16.5 V to +0.3 V SS section of this specification is not implied. Exposure to absolute V to DGND −0.3 V to DV DRIVE CC maximum rating conditions for extended periods may affect VDD to AVCC (VCC − 0.3 V) to +16.5 V device reliability. AVCC to AGND, DGND −0.3 V to +7 V DVCC to AVCC −0.3 V to +0.3 V DV to DGND −0.3 V to +7 V CC ESD CAUTION V to AGND −0.3 V to DV DRIVE CC AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND VSS − 0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to VDRIVE + 0.3 V Digital Output Voltage to GND −0.3 V to V + 0.3 V DRIVE D B, D B Input to AGND −0.3 V to AV + 0.3 V CAP CAP CC 1 Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package θ Thermal Impedance 128°C/W JA θJC Thermal Impedance 42°C/W Pb-free Temperature, Soldering Reflow 260(+0)°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause latch-up. Rev. A | Page 8 of 28 AD7366-5/AD7367-5 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D A 1 24 DGND OUT V 2 23 D B DRIVE OUT DV 3 22 BUSY CC AD7366-5/ RANGE1 4 21 CNVST AD7367-5 RANGE0 5 20 SCLK TOP VIEW ADDR 6 19 CS (Not to Scale) AGND 7 18 REFSEL AV 8 17 AGND CC DAD 16 B 9 CAP CAP V 10 15 V SS DD V 11 14 A1 V B1 V 12 V 13 A2 B2 Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1, 23 DOUTA, DOUTB Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input and 12 SCLK cycles are required to access the data from the AD7366-5 while 14 SCLK cycle are required for the AD7367-5. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366-5 and 14 bits for the AD7367-5 and is provided MSB first. If CS is held low for a further 12 SCLK cycles for the AD7366-5 or 14 SCLK cycles for the AD7367-5, on either DOUTA or DOUTB, the data from the other ADC follows on that DOUT pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or D B using only one serial port. See the Serial Interface section for more information. OUT 2 V Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. DRIVE This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different than the voltage at AVCC and DVCC, but should never exceed either by more than 0.3 V. 3 DVCC Digital Supply Voltage, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the voltage difference between them never exceeds 0.3 V, even on a transient basis. This supply should be decoupled to DGND. Place 10 μF and 100 nF decoupling capacitors on the DV pin. CC 4, 5 RANGE1, Analog Input Range Selection, Logic Inputs. The polarity on these pins determines the input range of the analog RANGE0 input channels. See the Analog Inputs section and Table 8 for details. 6 ADDR Multiplexer Select, Logic Input. This input is used to select the pair of channels to be simultaneously converted, either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B. The logic state on this pin is latched on the rising edge of BUSY to set up the multiplexer for the next conversion. 7, 17 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7366-5/AD7367-5. All analog input signals and any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 8 AV Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AV and DV voltages CC CC CC should ideally be at the same potential. For best performance, it is recommended that the DV and AV pins be CC CC shorted together to ensure that the voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled to AGND. Place 10 μF and 100 nF decoupling capacitors on the AVCC pin. 9, 16 DCAPA, DCAPB Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective ADC. For best performance, it is recommended to use a 680 nF decoupling capacitor on these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. 10 VSS Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure of the AD7366-5/AD7367-5. The supply must be less than or equal to −5 V (see Table 7 for further details). Place 10 μF and 100 nF decoupling capacitors on the VSS pin. 11, 12 V , V Analog Inputs of ADC A. These are both single-ended analog inputs. The analog input range on these channels is A1 A2 determined by the RANGE0 and RANGE1 pins. 13, 14 V , V B2 B1 Analog Inputs of ADC B. These are both single-ended analog inputs. The analog input range on these channels is determined by the RANGE0 and RANGE1 pins. 15 VDD Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure of the AD7366-5/AD7367-5. The supply must be greater than or equal to 5 V (see Table 7 for further details). Place 10 μF and 100 nF decoupling capacitors on the V pin. DD Rev. A | Page 9 of 28 06842-002 AD7366-5/AD7367-5 Pin No. Mnemonic Description 18 REFSEL Internal/External Reference Selection, Logic Input. If this pin is tied to logic high, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to decoupling capacitors. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7366-5/ AD7367-5 through the D A and/or D B pins. CAP CAP 19 CS Chip Select, Active Low Logic Input. This input frames the serial data transfer. When CS is logic low, the output bus is enabled, and the conversion result is output on DOUTA and DOUTB. 20 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7366-5/AD7367-5. 21 CNVST Conversion Start, Logic Input. This pin is edge triggered. On the falling edge of this input, the track/hold goes into hold mode and the conversion is initiated. If CNVST is low at the end of a conversion, the part goes into power- down mode. In this case, the rising edge of CNVST instructs the part to power up again. 22 BUSY Busy Output. BUSY transitions high when a conversion starts and remains high until the conversion completes. 24 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7366-5/AD7367-5. The DGND pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Rev. A | Page 10 of 28 AD7366-5/AD7367-5 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 1.0 –76 0.8 0V TO +10V RANGE 0.6 –78 0.4 0.2 ±10V RANGE –80 ±5V RANGE 0 –0.2 –82 –0.4 AV = 5V, DV = 5V CC CC AV = 5V, DV = 5V V = 15V, V = –15V CC CC DD SS –0.6 –84 V = 15V, V = –15V V = 3V DD SS DRIVE V = 3V DRIVE f = 500kSPS S –0.8 f = 500kSPS T = 25°C S A INTERNAL REFERENCE INTERNAL REFERENCE –1.0 –86 0 2000 4000 6000 8000 10000 12000 14000 16000 10 100 1000 CODE ANALOG INPUT FREQUENCY (kHz) Figure 3. AD7367-5 Typical DNL Figure 6. THD vs. Analog Input Frequency 2.0 AV = 5V, DV = 5V –66 CC CC V = 15V, V = –15V DD SS V = 3V 1.5 DRIVE R = 2000Ω IN f = 500kSPS S INTERNAL REFERENCE 1.0 ±5V RANGE –71 0.5 R = 1300Ω IN R = 3000Ω IN 0 R = 470Ω –76 IN R = 5100Ω IN –0.5 AV = 5V, DV = 5V –1.0 CC CC –81 V = 15V, V = –15V DD SS V = 3V R = 240Ω DRIVE IN –1.5 R = 56Ω f = 500kSPS IN S T = 25°C A R = 3900Ω INTERNAL REFERENCE IN –2.0 –86 0 2000 4000 6000 8000 10000 12000 14000 16000 10 100 1000 CODE ANALOG INPUT FREQUENCY (kHz) Figure 4. AD7367-5 Typical INL Figure 7. THD vs. Analog Input Frequency for Various Source Impedances 0 AV = 5V, DV = 5V CC CC 77 V = 15V, V = –15V DD SS –20 V = 3V DRIVE f = 500kSPS, f = 50kHz S IN ±10V RANGE –40 INTERNAL REFERENCE 75 SNR = 76dB, SINAD = 75dB –60 0V TO +10V RANGE 73 –80 –100 71 –120 AV = 5V, DV = 5V CC CC 69 V = 15V, V = –15V DD SS V = 3V –140 DRIVE f = 500kSPS S ±5V RANGE INTERNAL REFERENCE –160 67 0 50 100 150 200 250 10 100 1000 ANALOG INPUT FREQUENCY (kHz) FREQUENCY (kHz) Figure 5. AD7367-5 FFT Figure 8. SINAD vs. Analog Input Frequency Rev. A | Page 11 of 28 (dB) INL ERROR (LSB) DNL ERROR (LSB) 06842-004 06842-003 06842-005 SINAD (dB) THD (dB) THD (dB) 06842-008 06842-006 06842-007 AD7366-5/AD7367-5 –70 –70 V , ADC A CC –75 100mV p-p SINE WAVE ON AV CC –80 NO DECOUPLING CAPACITOR –80 V = 15V, V = –15V DD SS V , ADC B CC V = 3V DRIVE ±5V RANGE f = 500kSPS S –85 –90 V ADC B DD, 0V TO +10V RANGE –90 –100 –95 ±10V RANGE V , ADC B V , ADC A SS DD –100 AV = 5V, DV = 5V CC CC –110 V = 15V, V = –15V DD SS V = 3V DRIVE –105 V , ADC A SS f = 500kSPS S INTERNAL REFERENCE –110 –120 0 100 200 300 400 500 600 0 200 400 600 800 1000 1200 FREQUENCY OF INPUT NOISE (kHz) SUPPLY RIPPLE FREQUENCY (kHz) Figure 9. Channel-to-Channel Isolation Figure 11. PSRR vs. Supply Ripple Frequency Without Supply Decoupling 110000 106091 CODES AV = 5V, DV = 5V 31 CODES 344 CODES CC CC 40 V = 15V, V = –15V 100000 DD SS V = 3V V = 0V TO +10V IN DRIVE f = 500kSPS 90000 S 30 INTERNAL REFERENCE 80000 V = +5V 70000 IN 20 60000 V = +10V IN 10 50000 40000 0 30000 20000 –10 V = –10V IN V = –5V IN 10000 0 –20 8191 8192 8193 8194 8195 8196 100 150 200 250 300 350 400 450 500 CODE THROUGHPUT RATE (kSPS) Figure 10. Histogram of Codes for 200k Samples Figure 12. Analog Input Current vs. Throughput Rate Rev. A | Page 12 of 28 CHANNEL-TO-CHANNEL ISOLATION (dB) 06842-010 06842-009 PSRR (dB) ANALOG INPUT CURRENT (µA) 06842-012 06842-011 AD7366-5/AD7367-5 2.5050 45 AV = 5V, DV = 5V CC CC V = 15V, V = –15V 2.5045 DD SS V = 3V DRIVE 40 f = 500kSPS 2.5040 S INTERNAL REFERENCE 2.5035 35 2.5030 0V TO +10V RANGE ±5V RANGE 2.5025 30 2.5020 25 2.5015 2.5010 ±10V RANGE 20 AV = 5V, DV = 5V CC CC V = 15V, V = –15V 2.5005 DD SS V = 3V, DRIVE 2.5000 15 0 102030405060708090 100 150 200 250 300 350 400 450 500 CURRENT (µA) SAMPLING FREQUENCY (kSPS) Figure 13. V vs. Reference Output Current Drive Figure 15. Power vs. Sampling Frequency in Normal Mode REF 0.300 0.250 D SOURCE CURRENT OUT 0.200 D OUT 0.150 SINK CURRENT 0.100 AV = 5V, DV = 5V CC CC 0.50 V = 15V, V = 15V DD SS V = 3V, f = 500kSPS DRIVE S INTERNAL REFERENCE 0 0 500 1000 1500 2000 2500 CURRENT (µA) Figure 14. DOUT Source Current vs. (VCC − VOUT ) and DOUT Sink Current vs. VOUT Rev. A | Page 13 of 28 V OR V – V (V) OUT CC OUT V (V) REF 06842-013 06842-014 POWER (mW) 06842-015 AD7366-5/AD7367-5 TERMINOLOGY Differential Nonlinearity (DNL) Total Harmonic Distortion (THD) DNL is the difference between the measured and the ideal THD is the ratio of the rms sum of harmonics to the 1 LSB change between any two adjacent codes in the ADC. fundamental. For the AD7366-5/AD7367-5, it is defined as: 2 2 2 2 2 Integral Nonlinearity (INL) V + V + V + V + V 2 3 4 5 6 THD(dB)= 20 log INL is the maximum deviation from a straight line passing V 1 through the endpoints of the ADC transfer function. The where: endpoints of the transfer function are zero scale, a single (1) V1 is the rms amplitude of the fundamental. LSB point below the first code transition and full scale, a point V2, V3, V4, V5, and V6 are the rms amplitudes of the second 1 LSB above the last code transition. through the sixth harmonics. Zero Code Error Peak Harmonic or Spurious Noise This is the deviation of the midscale transition (all 1s to all 0s) Peak harmonic, or spurious noise, is defined as the ratio of the from the ideal VIN voltage, that is, AGND – ½ LSB for bipolar rms value of the next largest component in the ADC output ranges and 2 × V − 1 LSB for the unipolar range. REF spectrum (up to f /2, excluding dc) to the rms value of the S Positive Full-Scale Error fundamental. Normally, the value of this specification is deter- This is the deviation of the last code transition (011…110) to mined by the largest harmonic in the spectrum. However, for − 1 LSB or 2 × V ADCs where the harmonics are buried in the noise floor, it is (011…111) from the ideal (that is, 4 × VREF REF a noise peak. – 1 LSB) after the zero code error has been adjusted out. Channel-to-Channel Isolation Negative Full-Scale Error Channel-to-channel isolation is a measure of the level of cross- This is the deviation of the first code transition (10…000) to talk between any two channels when operating in any of the (10…001) from the ideal (that is, −4 × VREF + 1 LSB, −2 × VREF + 1 LSB, or AGND + 1 LSB) after the zero code error has been input ranges. It is measured by applying a full-scale, 150 kHz adjusted out. sine wave signal to all unselected input channels and determin- ing how much that signal is attenuated in the selected channel Zero Code Error Match with a 50 kHz signal. The figure given is the typical across all This is the difference in zero code error across all 12 channels. four channels for the AD7366-5/AD7367-5 (see the Figure 9 for more information). Positive Full-Scale Error Match This is the difference in positive full-scale error across all channels. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa Negative Full-Scale Error Match and fb, any active device with nonlinearities creates distortion This is the difference in negative full-scale error across all channels. products at the sum, and different frequencies of mfa ± nfb Track-and-Hold Acquisition Time where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion The track-and-hold amplifier returns to track mode at the end terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and of a conversion. Track-and-hold acquisition time is the time (fa − fb), while the third-order terms include (2fa + fb), required for the output of the track-and-hold amplifier to reach (2fa − fb), (fa + 2fb), and (fa − 2fb). its final value, within ±½ LSB, after the end of conversion. The AD7366-5/AD7367-5 is tested using the CCIF standard Signal-to-Noise (+ Distortion) Ratio (SINAD) where two input frequencies near the top end of the input This ratio is the measured ratio of signal-to-noise (+ distortion) bandwidth are used. In this case, the second-order terms are at the output of the ADC. The signal is the rms amplitude of the usually distanced in frequency from the original sine waves, fundamental. Noise is the sum of all nonfundamental signals up while the third-order terms are usually at a frequency close to to half the sampling frequency (f /2), excluding dc. The ratio is S the input frequencies. As a result, the second- and third-order dependent on the number of quantization levels in the digitiza- terms are specified separately. The calculation of the intermodula- tion process: the more levels, the smaller the quantization noise. tion distortion is as per the THD specification, where it is the ratio The theoretical signal-to-noise (+ distortion) ratio for an ideal of the rms sum of the individual distortion products to the rms N-bit converter with a sine wave input is given by: amplitude of the sum of the fundamentals expressed in decibels. Signal-to-Noise (+ Distortion) = (6.02N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Rev. A | Page 14 of 28 AD7366-5/AD7367-5 Power Supply Rejection Ration (PSRR) It is expressed in ppm using the following equation: Variations in power supply affect the full-scale transition but V (25°C)−V (T _ HYS) REF REF 6 not the converter’s linearity. PSRR is the maximum change in V (ppm)= × 10 HYS V (25°C) REF the full-scale transition point due to a change in power supply voltage from the nominal value (see Figure 11). where: V (25°C) is V at 25°C. REF REF Thermal Hysteresis (T_HYS) is the maximum change of V at T_HYS+ VREF REF Thermal hysteresis is defined as the absolute maximum change or T_HYS−. of reference output voltage after the device is cycled through temperature from either T_HYS+ = +25°C to T to +25°C MAX or T_HYS− = +25°C to TMIN to +25°C Rev. A | Page 15 of 28 AD7366-5/AD7367-5 THEORY OF OPERATION CIRCUIT INFORMATION If the internal reference is the preferred option, the user must tie the REFSEL pin logic high. Alternatively, if REFSEL is tied to The AD7366-5/AD7367-5 are fast, dual, 2-channel, 12-/14-bit, GND, an external reference can be supplied to both ADCs bipolar input, simultaneous sampling, serial ADCs. The through the DCAPA and DCAPB pins. AD7366-5/AD7367-5 can accept bipolar input ranges of ±10 V and ±5 V. They can also accept a 0 V to 10 V unipolar input The analog inputs are configured as two single-ended inputs for range. The AD7366-5/AD7367-5 require VDD and VSS dual each ADC. The various different input voltage ranges can be supplies for the high voltage analog input structure. These selected by programming the RANGE bits as shown in Table 8. supplies must be greater than or equal to the analog input range (see Table 7 for the minimum requirements on these supplies CONVERTER OPERATION for each analog input range). The AD7366-5/AD7367-5 require The AD7366-5/AD7367-5 have two successive approximation a low voltage 4.75 V to 5.25 V V supply to power the ADC core. CC ADCs, each based around two capacitive DACs. Figure 16 and Figure 17 show simplified schematics of an ADC in acquisition Table 7. Reference and Supply Requirements for Each and conversion phases, respectively. The ADC is comprised of Analog Input Range control logic, a SAR, and a capacitive DAC. In Figure 16 (the Selected Full-Scale acquisition phase), SW2 is closed, SW1 is in Position A, the Analog Input Reference Input Minimum comparator is held in a balanced condition, and the sampling Range (V) Voltage (V) Range (V) AV (V) V /V (V) CC DD SS capacitor arrays acquire the signal on the input. ±10 +2.5 ±10 +5 ±10 +3.0 ±12 +5 ±12 ±5 +2.5 ±5 +5 ±5 CAPACITIVE DAC +3.0 ±6 +5 ±6 0 to +10 +2.5 0 to +10 +5 +10/AGND A V IN CONTROL +3.0 0 to +12 +5 +12/AGND SW1 LOGIC B SW2 Each AD7366-5/AD7367-5 contains two on-chip, track-and-hold COMPARATOR amplifiers, two successive approximation ADCs, and a serial AGND interface with two separate data output pins. The device is housed Figure 16. ADC Acquisition Phase in a 24-lead TSSOP, offering the user considerable space-saving advantages over alternative solutions. When the ADC starts a conversion (see Figure 17), SW2 opens, and SW1 moves to Position B, causing the comparator to The AD7366-5/AD7367-5 require a CNVST signal to start a become unbalanced. The control logic and the charge redis- conversion. On the falling edge of CNVST, both track-and- tribution DAC is used to add and subtract fixed amounts of holds are placed into hold mode, and the conversions are charge from the sampling capacitor to bring the comparator initiated. The BUSY signal goes high to indicate that the back into a balanced condition. When the comparator is conversions are taking place. The clock source for each balanced again, the conversion is complete. The control logic successive approximation ADC is provided by an internal generates the ADC output code. oscillator. The BUSY signal goes low to indicate the end of conversion. On the falling edge of BUSY, the track-and-hold CAPACITIVE returns to track mode. Once the conversion is finished, the DAC serial clock input accesses data from the part. A V IN CONTROL SW1 The AD7366-5/AD7367-5 have an on-chip 2.5 V reference that LOGIC B SW2 can be disabled when an external reference is preferred. If the COMPARATOR internal reference is to be used elsewhere in a system, the output AGND from D A and D B must first be buffered. On power-up, the CAP CAP Figure 17. ADC Conversion Phase REFSEL pin must be tied to a high or low logic state to select either the internal or external reference option. Rev. A | Page 16 of 28 06842-019 06842-018 AD7366-5/AD7367-5 TRANSFER FUNCTION ANALOG INPUTS The output coding of the AD7366-5/AD7367-5 is twos comple- Each ADC in the AD7366-5/AD7367-5 has two single-ended ment. The designed code transitions occur at successive integer analog inputs. Figure 18 shows the equivalent circuit of the LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is analog input structure of the AD7366-5/AD7367-5. The two dependent on the analog input range selected (see Table 10). diodes provide ESD protection. Care must be taken to ensure The ideal transfer characteristic is shown in Figure 19. that the analog input signals never exceed the supply rails by more than 300 mV. Otherwise, these diodes become forward- Table 10. LSB Sizes for Each Analog Input Range biased and start conducting current into the substrate. The AD7366-5 AD7367-5 diodes can conduct up to 10 mA without causing irreversible Input Full-Scale LSB Size Full-Scale LSB Size damage to the part. The resistors are lumped components made Range Range (mV) Range (mV) up of the on resistance of the switches. The value of these resistors ±10 V 20 V/4096 4.88 20 V/16384 1.22 is typically 170 Ω. Capacitor C1 can primarily be attributed to ±5 V 10 V/4096 2.44 10 V/16384 0.61 pin capacitance while Capacitor C2 is the sampling capacitor of 0 V to +10 V 10 V/4096 2.44 10 V/16384 0.61 the ADC. The total lumped capacitance of C1 and C2 is approxi- mately 9 pF for the ±10 V input range and approximately 13 pF for all other input ranges. 011...111 011...110 V DD 000...001 D C2 R1 000...000 V 0 IN 111...111 C1 D 100...010 V SS 100...001 100...000 Figure 18. Equivalent Analog Input Structure –FSR/2 + 1LSB +FSR/2 – 1LSB The AD7366-5/AD7367-5 can handle true bipolar input voltages. 0V ANALOG INPUT The analog input can be set to one of three ranges: ±10 V, ±5 V, or Figure 19. Transfer Characteristic 0 V to +10 V. The logic levels on Pin RANGE0 and Pin RANGE1 determine which input range is selected as outlined in Table 8. Track-and-Hold These range bits should not be changed during the acquisition The track-and-hold on the analog input of the AD7366-5/ time prior to a conversion, but can change at any other time. AD7367-5 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 12-/14-bit accuracy. The input Table 8. Analog Input Range Selection bandwidth of the track-and-hold is greater than the Nyquist RANGE0 RANGE1 Range Selected rate of the ADC. The AD7366-5/AD7367-5 can handle 0 0 ±10 V frequencies up to 35 MHz. 1 0 ±5 V 0 1 0 V to +10 V The track-and-hold enters its tracking mode once the BUSY 1 1 Do not program CS signal goes low after the falling edge. The time required to The parts require VDD and VSS dual supplies for the high voltage acquire an input signal depends on how quickly the sampling analog input structures. These supplies must be greater than or capacitor is charged. With zero source impedance, 140 ns is equal to ±5 V (see Table 7 for the requirements on these supplies). sufficient to acquire the signal to the 12-bit level for the AD7366-5 The AD7366-5/AD7367-5 require a low voltage 4.75 V to 5.25 V and the 14-bit level for the AD7367-5. The acquisition time for AV supply to power the ADC core, a 4.75 V to 5.25 V DV CC CC the ±10 V, ±5 V, and 0 V to +10 V ranges to settle to within ±½ LSB supply for digital power, and a 2.7 V to 5.25 V VDRIVE supply for is typically 140 ns. The ADC goes back into hold mode on the interface power. CNVST falling edge of . Channel selection is made via the ADDR pin as shown in Table 9. The acquisition time required is calculated using the following The logic level on the ADDR pin is latched on the rising edge of formula: the BUSY signal for the next conversion, not the one in progress. t = 10 × ((R + R) × C) ACQ SOURCE When power is first supplied to the AD7366-5/AD7367-5, the default channel selection is V and V . A1 B1 where: C is the sampling capacitance. Table 9. Channel Selection R is the resistance seen by the track-and-hold amplifier looking ADDR Channels Selected at the input. 0 V , V A1 B1 R should include any extra source impedance on the SOURCE 1 V , V A2 B2 analog input. Rev. A | Page 17 of 28 06842-020 ADC CODE 06842-021 AD7366-5/AD7367-5 TYPICAL CONNECTION DIAGRAM Unlike other bipolar ADCs, the AD7366-5/AD7367-5 do not have a resistive analog input structure. On the AD7366-5/ Figure 20 shows a typical connection diagram for the AD7366-5/ AD7366-5, the bipolar analog signal is sampled directly onto AD7367-5. In this configuration, the AGND pin is connected the sampling capacitor. This gives the devices high analog input to the analog ground plane of the system, and the DGND pin impedance. The analog input impedance can be calculated from is connected to the digital ground plane of the system. The the following formula: analog inputs on the AD7366-5/AD7367-5 accept bipolar single-ended signals. The AD7366-5/AD7367-5 can operate Z = 1/(fS × CS) with either an internal or an external reference. In Figure 20, the where: AD7366-5/AD7367-5 is configured to operate with the internal f is the sampling frequency. S 2.5 V reference. A 680 nF decoupling capacitor is required when C is the sampling capacitor value. S operating with the internal reference. C depends on the analog input range chosen (see the Analog S The AVCC and DVCC pins are connected to a 5 V supply voltage. Inputs section). When operating at 500 kSPS, the analog input The V and V are the dual supplies for the high voltage analog DD SS impedance is typically 260 kΩ for the ±10 V range. As the input structures. The voltage on these pins must be greater than sampling frequency is reduced, the analog input impedance pin or equal to ±5 V (see Table 7 for more information). The VDRIVE further increases. As the analog input impedance increases, the is connected to the supply voltage of the microprocessor. The current required to drive the analog input therefore, decreases voltage applied to the VDRIVE input controls the voltage of the (see Figure 7 for more information). serial interface. VDRIVE can be set to 3 V or 5 V. + 0.1µF +5V SUPPLY +5V TO +16.5V SUPPLY + + + + 10µF 0.1µF 0.1µF 10µF V DV AV DD CC CC +3V OR +5V SUPPLY V DRIVE ++ V A1 AD7366-5/ 0.1µF 10µF AD7367-5 V A2 CS ANALOG INPUTS ±10V, SCLK ±5V, AND 0V TO +10V CNVST D A OUT V B1 D B OUT BUSY V B2 ADDR V REFSEL D A DRIVE CAP SERIAL + INTERFACE RANGE0 680nF D B CAP RANGE1 + 680nF V SS AGND DGND –16.5V TO –5V SUPPLY 10µF 0.1µF + + Figure 20. Typical Connection Diagram for ±10 V Range Using Internal Reference Rev. A | Page 18 of 28 MICROCONTROLLER/ MICROPROCESSOR 06842-022 AD7366-5/AD7367-5 V DRIVE DRIVER AMPLIFIER CHOICE The AD7366-5/AD7367-5 also have a VDRIVE feature to control Each AD7366-5/AD7367-5 has a total of four analog inputs, the voltage at which the serial interface operates. VDRIVE allows which operate in single-ended mode. Both ADC analog inputs the ADC to easily interface to both 3 V and 5 V processors. For can be programmed to one of the three analog input ranges. In example, if the AD7366-5/AD7367-5 is operated with a VCC of applications where the signal source is high impedance, it is 5 V, the V pin could be powered from a 3 V supply, allowing DRIVE recommended to buffer the signal before applying it to the a large dynamic range with low voltage digital processors. Thus, ADC analog inputs. Figure 21 shows the configuration of the the AD7366-5/AD7367-5 could be used with the ±10 V input AD7366-5/AD7367-5 in single-ended mode. range while still being able to interface to 3 V digital parts. In applications where the THD and SNR are critical specifi- REFERENCE cations, the analog input of the AD7366-5/AD7367-5 should be The AD7366-5/AD7367-5 can operate with either the internal driven from a low impedance source. Large source impedances 2.5 V on-chip reference or an externally applied reference. The significantly affect the ac performance of the ADC and can logic state of the REFSEL pin determines whether the internal necessitate the use of an input buffer amplifier. reference is used. The internal reference is selected for both ADCs When no amplifier is used to drive the analog input, the source when the REFSEL pin is tied to logic high. If the REFSEL pin is impedance should be limited to low values. The maximum source tied to GND, an external reference can be supplied through the impedance depends on the amount of THD that can be tolerated DCAPA and DCAPB pins. On power-up, the REFSEL pin must be in the application. The THD increases as the source impedance tied to either a low logic or high logic state for the part to operate. increases and performance degrades. Figure 7 shows THD vs. Suitable reference sources for the AD7366-5/AD7367-5 include the analog input frequency for various source impedances. the AD780, AD1582, ADR431, REF193, and ADR391. Depending on the input range and analog input configuration The internal reference circuitry consists of a 2.5 V band gap selected, the AD7366-5/AD7367-5 can handle source reference and a reference buffer. When operating the AD7366-5/ impedances as illustrated in Figure 7. AD7367-5 in internal reference mode, the 2.5 V internal reference Due to the programmable nature of the analog inputs on the is available at the DCAPA and DCAPB pins, which should be AD7366-5/AD7367-5, the choice of op amp used to drive the decoupled to AGND using a 680 nF capacitor. It is recommended inputs is a function of the particular application and depends that the internal reference be buffered before applying it elsewhere on the selected analog input voltage ranges. in the system. The internal reference is capable of sourcing up to 150 μA with an analog input range of ±10 V and 70 μA for The driver amplifier must be able to settle for a full-scale step to both the ±5 V range and 0 V to +10 V range a 14-bit level, 0.0061%, in less than the specified acquisition time of the AD7366-5/AD7367-5. An op amp such as the AD8021 If the internal reference operation is required for the ADC meets this requirement when operating in single-ended mode. conversion, the REFSEL pin must be tied to logic high on power- The AD8021 needs an external compensating NPO type of up. The reference buffer requires 70 μs to power up and charge capacitor. The AD8022 can also be used in high frequency the 680 nF decoupling capacitor during the power-up time. applications where a dual version is required. For lower frequency The AD7366-5/AD7367-5 is specified for a 2.5 V to 3 V reference applications, recommended op amps are the AD797, AD845, range. When a 3 V reference is selected, the ranges are ±12 V, and AD8610. ±6 V, and 0 V to +12 V. For these ranges, the V and V supply DD SS V+ must be greater than or equal to the +12 V and −12 V, respectively. 10µF +5V +10V/+5V 0.1µF + AGND AD8021 V A1 V DV /AV DD CC CC –10V/–5V 1kΩ AD7366-5/ AD7367-5* 15pF V 1kΩ SS 0.1µF C = 10pF COMP 10µF V– *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 21. Typical Connection Diagram with the AD8021 Driving the Analog Input in Single-Ended Mode Rev. A | Page 19 of 28 + + + + 06842-023 AD7366-5/AD7367-5 MODES OF OPERATION The mode of operation for the AD7366-5/AD7367-5 is selected The BUSY signal remains high for the duration of the conversion. by the (logic) state of the CNVST signal at the end of a conver- The CS pin must be brought low to bring the data bus out of sion. There are two possible modes of operation: normal mode three-state; subsequently 12 SCLK cycles are required to read and shutdown mode. These modes of operation are designed to the conversion result from the AD7366-5, while 14 SCLK cycles provide flexible power management options, which can be are required to read from the AD7367-5. The D lines return OUT chosen to optimize the power dissipation/throughput rate CS CS to three-state only when is brought high. If is left low for ratio for differing application requirements. a further 12 SCLK cycles for the AD7366-5 or 14 SCLK cycles for the AD7367-5, the result from the other on-chip ADC is NORMAL MODE also accessed on the same DOUT line, as shown in Figure 27 and Normal mode is intended for applications needing fast Figure 28 (see the Serial Interface section). throughput rates because the user does not have to worry After 24 SCLK cycles have elapsed for the AD7366-5 and 28 SCLK about any power-up times (with the AD7366-5/AD7367-5 cycles have elapsed for the AD7367-5, the DOUT line returns to remaining fully powered at all times). Figure 22 shows the th th CS three-state when is brought high (not on the 24 or 28 SCLK normal mode of operation for the AD7366-5, while Figure 23 CS falling edge). If is brought high prior to this, the DOUT line illustrates normal mode for the AD7367-5. CS returns to three-state at that point. Thus, must be brought The conversion is initiated on the falling edge of CNVST as high once the read is completed because the bus does not described in the Circuit Information section. To ensure that automatically return to three-state upon completion of the CNVST the part remains fully powered up at all times, must be dual result read. at a logic high state prior to the BUSY signal going low. If Once a data transfer is complete and DOUTA and DOUTB have CNVST is at a logic low state when the BUSY signal goes low, returned to three-state, another conversion can be initiated after the analog circuitry powers down and the part ceases converting. CNVST the quiet time, tQUIET, has elapsed by bringing low again. t 1 CNVST t QUIET t 2 BUSY t CONVERT t 3 CS SCLK SERIAL READ OPERATION 1 12 Figure 22. Normal Mode Operation for the AD7366-5 t 1 CNVST t QUIET t 2 BUSY t CONVERT t 3 CS SCLK SERIAL READ OPERATION 1 14 Figure 23. Normal Mode Operation for the AD7367-5 Rev. A | Page 20 of 28 06842-025 06842-024 AD7366-5/AD7367-5 POWER-UP TIMES SHUTDOWN MODE As described in the Shutdown Mode section, the AD7366-5/ Shutdown mode is intended for use in applications where slow AD7367-5 have one power-down mode. This section deals with throughput rates are required. Shutdown mode is suited to the power-up time required when coming out of this mode. It applications where a series of conversions performed at a should be noted that these power-up times apply with the relatively high throughput rate are followed by a long period of recommended capacitors in place on the D A and D B pins. CAP CAP inactivity and, thus, shutdown. When the AD7366-5/AD7367-5 CNVST To power up from shutdown, must be brought high and are in full power-down, all analog circuitry is powered down. remain high for a minimum of 70 μs, as shown in Figure 24. The falling edge of CNVST initiates the conversion. The BUSY When power supplies are first applied to the AD7366-5/AD7367-5, output subsequently goes high to indicate that the conversion is the ADC can power up with CNVST in either the low or high in progress. Once the conversion is completed, the BUSY output logic state. Before attempting a valid conversion, CNVST must returns low. If the CNVST signal is at logic low when BUSY be brought high and remain high for the recommended power- goes low, the part enters shutdown at the end of the conversion CNVST up time of 70 μs. can then be brought low to initiate a phase. While the part is in shutdown mode, the digital output conversion. With the AD7366-5/AD7367-5, no dummy conversion code from the last conversion on each ADC can still be read is required before valid data can be read from the D pins. from the D pins. To read the D data, CS must be brought OUT OUT OUT low as described in the Serial Interface section. The D pins OUT If it is intended to place the part in shutdown mode when the return to three-state once CS is brought back to logic high. supplies are first applied, the AD7366-5/AD7367-5 must be powered up, and a conversion initiated. However, CNVST To exit full power-down and to power up the AD7366-5/ should remain in the logic low state, and when the BUSY signal CNVST AD7367-5, a rising edge of is required. After the goes low, the part enters shutdown. CNVST required power-up time has elapsed, may be brought low again to initiate another conversion, as shown in Figure 24 Once supplies are applied to the AD7366-5/AD7367-5, sufficient time must be allowed for any external reference to power up and to charge the various reference buffer decoupling capacitors to their final values. t POWER-UP ENTERS SHUTDOWN CNVST t 2 BUSY t CONVERT t 3 CS SCLK SERIAL READ OPERATION 1 12 Figure 24. Autoshutdown Mode for AD7366-5 Rev. A | Page 21 of 28 06842-026 AD7366-5/AD7367-5 SERIAL INTERFACE Figure 25 and Figure 26 show the detailed timing diagrams for On the rising edge of CS, the conversion is terminated, and D A OUT serial interfacing to the AD7366-5 and the AD7367-5, respectively. and D B go back into three-state. If CS is not brought high, OUT On the falling edge of CNVST, the AD7366-5/AD7367-5 simulta- but is instead held low for a further 12 SCLK cycles for the neously converts the selected channels. These conversions are AD7366-5 or 14 SCLK cycles for the AD7367-5 on either DOUTA performed using the on-chip oscillator. After the falling edge of or D B, the data from the other ADC follows on that D pin. OUT OUT CNVST , the BUSY signal goes high, indicating the conversion has This is illustrated in Figure 27 and Figure 28 where the case for started. It returns low once the conversion has been completed. D A is shown. In this case, the D line in use goes back into OUT OUT CS The data can now be read from the D pins. three-state on the rising edge of . OUT CS and SCLK signals are required to transfer data from the If the falling edge of SCLK coincides with the falling edge of CS, AD7366-5/AD7367-5. The parts have two output pins corre- the falling edge of SCLK is not acknowledged by the AD7366-5/ sponding to each ADC. Data can be read from the AD7366-5/ AD7367-5, and the next falling edge of the SCLK is the first AD7367-5 using both DOUTA and DOUTB. Alternatively, a single CS registered after the falling edges of the . output pin of the user’s choice can be used. The SCLK input signal CS The pin can be brought low before the BUSY signal goes low, provides the clock source for the serial interface. The CS goes CS indicating the end of a conversion. Once is at a logic low state, low to access data from the AD7366-5/AD7367-5. The falling edge the data bus is brought out of three-state. This feature can be CS of takes the bus out of three-state and clocks out the MSB of utilized to ensure that the MSB is valid on the falling edge of the conversion result. The data stream consists of 12 bits of data BUSY by bringing CS low a minimum of t ns before the BUSY 4 for the AD7366-5 and 14 bits of data for the AD7367-5, MSB first. CS signal goes low. The dotted line in Figure 22 and Figure 23 The first bit of the conversion result is valid on the first SCLK illustrates this. falling edge after the CS falling edge. The subsequent 11-bits/ 13-bits of data for the AD7366-5/AD7367-5, respectively, are Alternatively, the CS pin can be tied to a low logic state continu- clocked out on the falling edge of the SCLK signal. A minimum ously. In this case, the DOUT pins never enter three-state, and the of 12 clock pulses must be provided to the AD7366-5 to access data bus is continuously active. Under these conditions, the MSB each conversion result, while a minimum of 14 clock pulses must of the conversion result for the AD7366-5/AD7367-5 is available be provided to the AD7367-5 to access the conversion result. on the falling edge of the BUSY signal. The next most significant Figure 25 shows how a 12 SCLK read is used to access the bit is available on the first SCLK falling edge after the BUSY conversion results, while Figure 26 illustrates the case for the signal has gone low. This mode of operation enables the user to AD7367-5 with a 14 SCLK read. read the MSB as soon as it is made available by the converter. CS t 8 SCLK 1 2 34512 t t 9 7 t t t 5 6 4 D A OUT DB10 DB9 DB8 DB2 DB1 DB0 D B THREE-STATE OUT THREE- DB11 STATE Figure 25. Serial Interface Timing Diagram for the AD7366-5 CS t 8 34514 SCLK 1 2 t t 9 7 t t t 5 6 4 D A OUT DB12 DB11 DB10 DB2 DB1 DB0 D B THREE-STATE OUT THREE- DB13 STATE Figure 26. Serial Interface Timing Diagram for the AD7367-5 Rev. A | Page 22 of 28 06842-028 06842-027 AD7366-5/AD7367-5 CS t 8 SCLK 34 5 1 2 10 11 12 13 24 t 7 t t t 4 5 6 DB10 DB9 DB1 DB0 DB11 DB10 DB1 DB0 D A A A A A B B B B OUT THREE- THREE- DB11 A STATE STATE Figure 27. Reading Data from Both ADCs on One D Line with 24 SCLKs for the AD7366-5 OUT CS t 8 SCLK 1 2 34 5 12 13 14 15 28 t 7 t t t 3 5 6 DB12 DB11 DB1 DB0 DB13 DB12 DB1 DB0 D A A A A A B B B B OUT THREE- THREE- DB13 A STATE STATE Figure 28. Reading Data from Both ADCs on One DOUT Line with 28 SCLKs for the AD7367-5 Rev. A | Page 23 of 28 06842-029 06842-030 AD7366-5/AD7367-5 MICROPROCESSOR INTERFACING The serial interface on the AD7366-5/AD7367-5 allows the Table 11. SPORT0 Control Register Setup parts to be directly connected to a range of different micro- Setting Description processors. This section explains how to interface the AD7366-5/ TFSW = RFSW = 1 Alternate framing. AD7367-5 with some more common microcontrollers and DSP INVRFS = INVTFS = 1 Active low frame signal. serial interface protocols. DTYPE = 00 Right justify data. SLEN = 1111 16-bit data-word (or can be set to 1101 AD7366-5/AD7367-5 TO ADSP-218x for 14-bit data-word). The ADSP-218x family of DSPs interfaces directly to the ISCLK = 1 Internal serial clock. AD7366-5/AD7367-5 with no glue logic required. The VDRIVE TFSR = RFSR = 1 Frame every word. pin of the AD7366-5/AD7367-5 takes the same supply voltage IRFS = 0 as that of the ADSP-218x. This allows the ADC to operate at a ITFS = 1 higher supply voltage than its serial interface and therefore, the ADSP-218x, if necessary. The connection diagram in Figure 29 Table 12. SPORT1 Control Register Setup shows both DOUTA and DOUTB of the AD7366-5/AD7367-5 Setting Description connected to both serial ports of the ADSP-218x. The SPORT0 TFSW = RFSW = 1 Alternate framing. and SPORT1 control registers should be set up as shown in INVRFS = INVTFS = 1 Active low frame signal. Table 11 and Table 12. DTYPE = 00 Right justify data. SLEN = 1111 16-bit data-word (or can be set to 1101 ADSP-218x* AD7366-5/ for 14-bit data-word). AD7367-5* SCLK SCLK0 ISCLK = 0 External serial clock. SCLK1 TFSR = RFSR = 1 Frame every word. CS TFS0 IRFS = 0 RFS0 ITFS = 1 RFS1 The ADSP-218x has the TFS0 and RFS0 of the SPORT0 and the D A DR0 OUT RFS1 of SPORT1 tied together. TFS0 is set as an output, and both DBDR1 OUT RFS0 and RFS1 are set as inputs. The DSP operates in alternate BUSY IRQn framing mode, and the SPORT control registers are set up as CNVST FLn described in Table 11 and Table 12. The frame synchronization V DRIVE CS signal generated on the TFS0 is tied to . V The AD7366-5/AD7367-5 BUSY line provides an interrupt to DD *ADDITIONAL PINS OMITTED FOR CLARITY. the ADSP-218x when the conversion is complete. The conversion Figure 29. Interfacing the AD7366-5/AD7367-5 to the ADSP-218x results can then be read from the AD7366-5/AD7367-5 using a read operation. When an interrupt is received on IRQn from the BUSY signal, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and, therefore, the reading of data. Rev. A | Page 24 of 28 06842-031 AD7366-5/AD7367-5 AD7366-5/AD7367-5 TO TMS320VC5506 AD7366-5/AD7367-5 TO ADSP-BF53x The serial interface on the TMS320VC5506 uses a continuous The ADSP-BF53x family of DSPs interfaces directly to the serial clock and frame synchronization signals to synchronize AD7366-5/AD7367-5 with no glue logic required. The availability the data transfer operations with peripheral devices like the of secondary receive registers on the serial ports of the Blackfin® CS AD7366-5/AD7367-5. The input allows easy interfacing DSPs means that only one serial port is necessary to read from between the TMS320VC5506 and the AD7366-5/AD7367-5 both D A and D B pins simultaneously. Figure 30 shows OUT OUT with no glue logic required. The serial ports of the TMS320VC5506 D A and D B of the AD7366-5/AD7367-5 connected to OUT OUT are set up to operate in burst mode with internal CLKX0 (Tx Serial Port 0 of the ADSP-BF53x. The SPORT0 Receive serial clock on Serial Port 0) and FSX0 (Tx frame sync from Configuration 1 register and SPORT0 Receive Configuration 2 Serial Port 0). The connection diagram is shown in Figure 31. register should be set up as outlined in Table 13 and Table 14. The serial port control registers (SPC) must be setup as shown ADSP-BF53x* AD7366-5/ in Table 15. SERIAL AD7367-5* DEVICE A SPORT0 (PRIMARY) TMS320VC5506* D A DR0PRI AD7366-5/ OUT AD7367-5* SCLK RCLKO SCLK CLKX0 CS RFS0 CLKR0 CLKX1 BUSY RXINPUTS CLKR1 CNVST PFn D A DR0 OUT D B DR0SEC OUT D B DR1 OUT SERIAL V DRIVE DEVICE B CS FSX0 (SECONDARY) FSR0 FSR1 V DD *ADDITIONAL PINS OMITTED FOR CLARITY. BUSY INTn Figure 30. Interfacing the AD7366-5/AD7367-5 to the ADSP-BF53x CNVST XF V DRIVE Table 13. SPORT0 Receive Configuration 1 Register (SPORT0_RCR1) Setup V *ADDITIONAL PINS OMITTED FOR CLARITY. DD Setting Description Figure 31. Interfacing the AD7366-5/AD7367-5 to the TMS320VC5506 RCKFE = 1 Sample data with falling edge of RSCLK. LRFS = 1 Active low frame signal. Table 15. Serial Port Control Register Setup RFSR = 1 Frame every word. SPC FO FSM MCM TXM IRFS = 1 Internal RFS used. SPC0 0 1 1 1 RLSBIT = 0 Receive MSB first. SPC1 0 1 0 0 RDTYPE = 00 Zero fill. IRCLK = 1 Internal receive clock. The V pin of the AD7366-5/AD7367-5 takes the same DRIVE RSPEN = 1 Receive enabled. supply voltage as that of the TMS320VC5506. This allows the SLEN = 1111 16-bit data-word (or can be set to 1101 for ADC to operate at a higher voltage than its serial interface and, 14-bit data-word). therefore, the TMS320VC5506, if necessary. TFSR = RFSR = 1 As with the previous interfaces, conversion can be initiated Table 14. SPORT0 Receive Configuration 2 Register from the TMS320VC5506 or from an external source, and the (SPORT0_RCR2) Setup processor is interrupted when the conversion sequence is Setting Description complete. RXSE = 1 Secondary side enabled. SLEN = 1111 16-bit data-word (or can be set to 1101 for 14-bit data-word). Rev. A | Page 25 of 28 06842-032 06842-033 AD7366-5/AD7367-5 Normal operation of the ESSI is selected by making MOD = 0 in AD7366-5/AD7367-5 TO DSP563xx the CRB register. Set the word length to 16 by setting Bit WL1 = 1 The connection diagram in Figure 32 shows how the AD7366-5/ and Bit WL0 = 0 in the CRA register. The FSP bit in the CRB AD7367-5 can be connected to the enhanced synchronous register should be set to 1 so that the frame sync is negative. serial interface (ESSI) of the DSP563xx family of DSPs from Motorola. There are two on-board ESSIs, and each is operated in In Figure 32, the serial clock is taken from the ESSI0 so the SCK0 synchronous mode (Bit SYN = 1 in the CRB register) with pin must be set as an output (SCKD = 1) while the SCK1 pin is set internally generated word length frame sync for both Tx and Rx as an input (SCKD = 0). The frame sync signal is taken from SC02 (Bit FSL1 = 0 and Bit FSL0 = 0 in the CRB register). on ESSI0, so SCD2 = 1, while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an input. The V pin of the AD7366-5/ DRIVE DSP563xx* AD7366-5/ AD7367-5 takes the same supply voltage as that of the DSP563xx. AD7367-5* SCLK SCK0 This allows the ADC to operate at a higher voltage than its SCK1 serial interface and, therefore, the DSP563xx, if necessary. D A SRD0 OUT D B SRD1 OUT CS SC02 SC12 BUSY IRQn CNVST PBn V DRIVE V *ADDITIONAL PINS OMITTED FOR CLARITY. DD Figure 32. Interfacing the AD7366-5/AD7367-5 to the DSP563xx Rev. A | Page 26 of 28 06842-034 AD7366-5/AD7367-5 APPLICATION HINTS LAYOUT AND GROUNDING To avoid radiating noise to other sections of the board, com- ponents such as clocks with fast switching signals, should be The printed circuit board that houses the AD7366-5/AD7367-5 shielded with digital ground and should never be run near the should be designed so that the analog and digital sections are analog inputs. Avoid crossover of digital and analog signals. To confined to their own separate areas of the board. This design reduce the effects of feedthrough within the board, traces should facilitates the use of ground planes that can be easily separated. be run at right angles to each other. A microstrip technique is To provide optimum shielding for ground planes, a minimum the best method, but its use may not be possible with a double- etch technique is generally the best option. All AGND pins on sided board. In this technique, the component side of the board the AD7366-5/AD7367-5 should be connected to the AGND is dedicated to ground planes, and signals are placed on the plane. Digital and analog ground pins should be joined in only other side. one place. If the AD7366-5/AD7367-5 are in a system where Good decoupling is also important. All analog supplies should multiple devices require an AGND and DGND connection, the be decoupled with 10 μF tantalum capacitors in parallel with connection should still be made at only one point. A star point 0.1 μF capacitors to AGND. To achieve the best results from should be established as close as possible to the ground pins on these decoupling components, they must be placed as close as the AD7366-5/AD7367-5. possible to the device, ideally right up against the device. The Good connections should be made to the power and ground 0.1 μF capacitors should have a low effective series resistance planes. This can be done with a single via or multiple vias for (ESR) and low effective series inductance (ESI), such as is typical each supply and ground pin. of common ceramic and surface mount types of capacitors. These low ESR, low ESI capacitors provide a low impedance path to Avoid running digital lines under the AD7366-5/AD7367-5 ground at high frequencies to handle transient currents due to devices because this couples noise onto the die. However, the internal logic switching. analog ground plane should be allowed to run under the AD7366-5/AD7367-5 to avoid noise coupling. The power EVALUATING THE AD7366-5/AD7367-5 supply lines to the AD7366-5/AD7367-5 should use as large Evaluation boards for the AD7366 and AD7367, the a trace as possible to provide low impedance paths and reduce EVAL-AD7366CBZ and EVAL-AD7367CBZ, can also be the effects of glitches on the power supply line. used to evaluate the performance of the AD7366-5 and AD7367-5, respectively. These evaluation boards can be used in conjunction with EVAL-CONTROL BRD2 to provide a full-featured evaluation platform. Rev. A | Page 27 of 28 AD7366-5/AD7367-5 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0.30 0° 0.60 0.20 SEATING 0.19 0.45 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7366BRUZ-5 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD7366BRUZ-5-RL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD7366BRUZ-5500RL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD7367BRUZ-5 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD7367BRUZ-5-RL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 AD7367BRUZ-5500RL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 1 Z = RoHS Compliant Part. ©2007-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06842-0-8/09(A) Rev. A | Page 28 of 28