ANALOG DEVICES AD7366

True Bipolar Input, Dual 12-Bit/14-Bit, 2-Channel, Simultaneous Sampling SAR ADC AD7366/AD7367 FEATURES FUNCTIONAL BLOCK DIAGRAM V D A AV DV DD CAP CC CC Dual 12-bit/14-bit, 2-channel ADC True bipolar analog inputs REF BUF Programmable input ranges: AD7366/AD7367 ±10 V, ±5 V, 0 V to 10 V ±12 V with 3 V external reference V A1 Throughput rate: 1 MSPS 12-/14-BIT SUCCESSIVE OUTPUT MUX T/H D A OUT Simultaneous conversion with read in less than 1 μs APPROXIMATION DRIVERS ADC High analog input impedance V A2 SCLK Low current consumption: CNVST 8.3 mA typical in normal mode CS BUSY CONTROL 320 nA typical in shutdown mode LOGIC ADDR AD7366 RANGE0 RANGE1 72 dB SNR at 50 kHz input frequency REFSEL 12-bit no missing codes V B1 V DRIVE AD7367 76 dB SNR at 50 kHz input frequency MUX T/H 12-/14-BIT SUCCESSIVE OUTPUT D B 14-bit no missing codes OUT APPROXIMATION DRIVERS ADC Accurate on-chip reference: 2.5 V ± 0.2% V B2 BUF −40°C to +85°C operation High speed serial interface Compatible with SPI®, QSPI™, MICROWIRE™, and DSP AGND AGND V D B DGND SS CAP iCMOS® process technology Figure 1. Available in a 24-lead TSSOP GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1 The AD7366/AD7367 are dual 12-bit/14-bit, high speed, low 1. The AD7366/AD7367 can accept true bipolar analog input power, successive approximation analog-to-digital converters signals, as well as ±10 V, ±5 V, ±12 V (with external refer- (ADCs) that feature throughput rates up to 1 MSPS. The device ence), and 0 V to 10 V unipolar signals. contains two ADCs, each preceded by a 2-channel multiplexer, 2. Two complete ADC functions allow simultaneous sampling and a low noise, wide bandwidth track-and-hold amplifier. and conversion of two channels. 3. 1 MSPS serial interface: SPI-/QSPI-/DSP-/MICROWIRE- The AD7366/AD7367 are fabricated on the Analog Devices, Inc., 2 compatible interface. industrial CMOS process (iCMOS ), which is a technology platform combining the advantages of low and high voltage Table 1. Related Products CMOS. The iCMOS process allows the AD7366/AD7367 to Throughput Number of accept high voltage bipolar signals in addition to reducing Device Resolution Rate Channels power consumption and package size. The AD7366/AD7367 AD7366 12-Bit 1 MSPS Dual, 2-channel can accept true bipolar analog input signals in the ±10 V range, AD7366-5 12-Bit 500 kSPS Dual, 2-channel ±5 V range, and 0 V to 10 V range. AD7367 14-Bit 1 MSPS Dual, 2-channel AD7367-5 14-Bit 500 kSPS Dual, 2-channel The AD7366/AD7367 have an on-chip 2.5 V reference that can be disabled to allow the use of an external reference. 1 Protected by U.S. Patent No. 6,731,232. If a 3 V reference is applied to the D A and D B pins, the 2 CAP CAP iCMOS Process Technology. For analog systems designers within industrial/instrumentation equipment OEMs who need high performance AD7366/AD7367 can accept a true bipolar ±12 V analog input. ICs at higher voltage levels, iCMOS is a technology platform that enables the Minimum ±12 V V and V supplies are required for the DD SS development of analog ICs capable of 30 V and operating at ±15 V supplies ±12 V input range. while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007-2010 Analog Devices, Inc. All rights reserved. 06703-001 AD7366/AD7367 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Connection Diagram ................................................... 18 Functional Block Diagram .............................................................. 1 Driver Amplifier Choice ........................................................... 19 General Description ......................................................................... 1 Reference ..................................................................................... 19 Product Highlights ........................................................................... 1 Modes of Operation ....................................................................... 20 Revision History ............................................................................... 2 Normal Mode .............................................................................. 20 Specifications ..................................................................................... 3 Shutdown Mode ......................................................................... 21 Timing Specifications .................................................................. 7 Power-Up Times ......................................................................... 21 Absolute Maximum Ratings ............................................................ 8 Serial Interface ................................................................................ 22 ESD Caution .................................................................................. 8 Microprocessor Interfacing ........................................................... 24 Pin Configuration and Function Descriptions ............................. 9 AD7366/AD7367 to ADSP-218x .............................................. 24 Typical Performance Characteristics ........................................... 11 AD7366/AD7367 to ADSP-BF53x ........................................... 24 Terminology .................................................................................... 14 AD7366/AD7367 to TMS320VC5506 ..................................... 25 Theory of Operation ...................................................................... 16 AD7366/AD7367 to DSP563xx ................................................ 25 Circuit Information .................................................................... 16 Application Hints ........................................................................... 27 Converter Operation .................................................................. 16 Layout and Grounding .............................................................. 27 Analog Inputs .............................................................................. 16 Outline Dimensions ....................................................................... 28 Transfer Function ....................................................................... 17 Ordering Guide .......................................................................... 28 REVISION HISTORY 11/10—Rev. C to Rev. D Changes to D A and D B Description in Table 6 ................. 9 OUT OUT Changes to Serial Interface Section .............................................. 22 Changes to Figure 27 ...................................................................... 23 10/10—Rev. B to Rev. C Changes to D A and D B Description in Table 6 ................. 9 OUT OUT Changes to Serial Interface Section .............................................. 22 Changes to Figure 27 ...................................................................... 23 8/09—Rev. A to Rev. B Changes to Table 2 ............................................................................ 4 Changes to Table 3 ............................................................................ 6 9/07—Rev. 0 to Rev. A Changes to Title ............................................................................... 1 Changes to Specifications ................................................................ 3 Changes to Figure 5 ........................................................................ 11 Changes to Terminology Section.................................................. 14 Changes to Figure 20 ...................................................................... 18 Changes to Figure 28 ...................................................................... 23 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 5/07—Revision 0: Initial Version Rev. D | Page 2 of 28 AD7366/AD7367 SPECIFICATIONS AV = DV = 4.75 V to 5.25 V, V = 11.5 V to 16.5 V, V = −16.5 V to −11.5 V, V = 2.7 V to 5.25 V, f = 1.12 MSPS, f = 48 MHz, CC CC DD SS DRIVE S SCLK V = 2.5 V internal/external, T = −40°C to +85°C, unless otherwise noted. REF A Table 2. AD7366 Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave IN 1 Signal-to-Noise Ratio (SNR) 70 72 dB 1 Signal-to-Noise + Distortion Ratio (SINAD) 70 71 dB 1 Total Harmonic Distortion (THD) −85 −78 dB Spurious-Free Dynamic Range (SFDR) −87 −78 dB 1 Intermodulation Distortion (IMD) fa = 49 kHz, fb = 51 kHz Second-Order Terms −88 dB Third-Order Terms −88 dB 1 Channel-to-Channel Isolation −90 dB SAMPLE AND HOLD 2 Aperture Delay 10 ns 2 Aperture Jitter 40 ps 2 Aperture Delay Matching ±100 ps Full Power Bandwidth 35 MHz @ 3 dB, ±10 V range 8 MHz @ 0.1 dB, ±10 V range DC ACCURACY Resolution 12 Bits 1 Integral Nonlinearity (INL) ±0.5 ±1 LSB 1 Differential Nonlinearity (DNL) ±0.25 ±0.5 LSB Guaranteed no missed codes to 12 bits 1 Positive Full-Scale Error ±1 ±7 LSB ±5 V and ±10 V analog input range ±1 ±6 LSB 0 V to 10 V analog input range 1 Positive Full-Scale Error Match ±1.5 LSB Matching from ADC A to ADC B ±0.1 LSB Channel-to-channel matching for ADC A and ADC B 1 Zero Code Error ±0.5 ±3 LSB ±5 V and ±10 V analog input range ±1 ±6 LSB 0 V to 10 V analog input range 1 Zero Code Error Match ±1.5 LSB Matching from ADC A to ADC B ±0.1 LSB Channel-to-channel matching for ADC A and ADC B 1 Negative Full-Scale Error ±1 ±7 LSB ±5 V and ±10 V analog input range ±1 ±6 LSB 0 V to 10 V analog input range 1 Negative Full-Scale Error Match ±1.5 LSB Matching from ADC A to ADC B ±0.1 LSB Channel-to-channel matching for ADC A and ADC B ANALOG INPUT Input Voltage Ranges Programmed via RANGE pins; see Table 8 ±10 V ±5 V 0 to 10 V DC Leakage Current ±0.01 ±1 µA Input Capacitance 9 pF When in track, ±10 V range 13 pF When in track, ±5 V and 0 V to 10 V range Input Impedance 260 kΩ ±10 V @ 1 MSPS 2.5 MΩ ±10 V @ 100 kSPS 125 kΩ ±5 V and 0 V to 10 V range @ 1 MSPS 1.2 MΩ ±5 V and 0 V to 10 V range @ 100 kSPS Rev. D | Page 3 of 28 AD7366/AD7367 Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT 3 Reference Output Voltage 2.495 2.5 2.505 V ±0.2% max @ 25°C Long-Term Stability 150 ppm 1000 hours 1 Output Voltage Hysteresis 50 ppm Reference Input Voltage Range 2.5 3.0 V DC Leakage Current ±0.01 ±1 µA External reference applied to Pin D A/Pin D B CAP CAP Input Capacitance 25 pF ±5 V and ±10 V analog input range 17 pF 0 V to 10 V analog input range D A, D B Output Impedance 7 Ω CAP CAP Reference Temperature Coefficient 6 25 ppm/°C V Noise 20 µV rms Bandwidth = 3 kHz REF LOGIC INPUTS Input High Voltage, V 0.7 × V V INH DRIVE Input Low Voltage, V 0.8 V INL Input Current, I ±0.01 ±1 µA V = 0 V or V IN IN DRIVE 2 Input Capacitance, C 6 pF IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V OH DRIVE Output Low Voltage, V 0.4 V OL Floating State Leakage Current ±0.01 ±1 µA 2 Floating State Output Capacitance 8 pF CONVERSION RATE Conversion Time 610 ns 2 Track/Hold Acquisition Time 140 ns Full-scale step input Throughput Rate 1.12 MSPS 4.75 V ≤ V ≤ 5.25 V, f = 48 MHz DRIVE SCLK 1 MSPS 2.7 V ≤ V < 4.75 V, f = 35 MHz DRIVE SCLK POWER REQUIREMENTS Digital inputs = 0 V or V DRIVE V 4.75 5.25 V See Table 7 CC V +11.5 +16.5 V See Table 7 DD V −16.5 −11.5 V See Table 7 SS V 2.7 5.25 V DRIVE Normal Mode (Static) I 370 550 µA V = +16.5 V DD DD I 40 60 µA V = −16.5 V SS SS I 1.5 2.25 mA V = 5.5 V CC CC Normal Mode (Operational) f = 1.12 MSPS S I 1.8 2.0 mA V = +16.5 V DD DD I 1.5 1.6 mA V = −16.5 V SS SS I 5 5.65 mA V = 5.25 V, internal reference enabled CC CC Shutdown Mode I 0.01 1 µA V = +16.5 V DD DD I 0.01 1 µA V = −16.5 V SS SS I 0.3 3 µA V = 5.25 V CC CC Power Dissipation Normal Mode (Operational) 89.1 mW V = +16.5 V, V = −16.5 V, V = 5.25 V, DD SS CC f = 1.12 MSPS S 50 mW ±10 V input range, f = 1.12 MSPS S 70 mW ±5 V and 0 V to 10 V input range, f = 1.12 MSPS S Shutdown Mode 1.9 48.75 µW V = +16.5 V, V = −16.5 V, V = 5.25 V DD SS CC 1 See the Terminology section. 2 Sample tested during initial release to ensure compliance. 3 o Refers to Pin D A or Pin D B specified for 25 C. CAP CAP Rev. D | Page 4 of 28 AD7366/AD7367 AV = DV = 4.75 V to 5.25 V, V = 11.5 V to 16.5 V, V = −16.5 V to −11.5 V, V = 2.7 V to 5.25 V, f = 1 MSPS, f = 48 MHz, CC CC DD SS DRIVE S SCLK V = 2.5 V internal/external, T = −40°C to +85°C, unless otherwise noted. REF A Table 3. AD7367 Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave IN 1 Signal-to-Noise Ratio (SNR) 74 76 dB 1 Signal-to-Noise + Distortion Ratio (SINAD) 73 75 dB 1 Total Harmonic Distortion (THD) −84 −78 dB Spurious-Free Dynamic Range (SFDR) −87 −79 dB 1 Intermodulation Distortion (IMD) fa = 49 kHz, fb = 51 kHz Second-Order Terms −91 dB Third-Order Terms −89 dB 1 Channel-to-Channel Isolation −90 dB SAMPLE AND HOLD 2 Aperture Delay 10 ns 2 Aperture Jitter 40 ps 2 Aperture Delay Matching ±100 ps Full Power Bandwidth 35 MHz @ 3 dB, ±10 V range 8 MHz @ 0.1 dB, ±10 V range DC ACCURACY Resolution 14 Bits 1 Integral Nonlinearity (INL) ±2 ±3.5 LSB 1 Differential Nonlinearity (DNL) ±0.5 ±0.90 LSB Guaranteed no missed codes to 14 bits 1 Positive Full-Scale Error ±4 ±20 LSB ±5 V and ±10 V analog input range ±5 ±20 LSB 0 V to 10 V analog input range 1 Positive Full-Scale Error Match ±3 LSB Matching from ADC A to ADC B ±0.2 LSB Channel-to-channel matching for ADC A and ADC B 1 Zero Code Error ±1 ±10 LSB ±5 V and ±10 V analog input range ±5 ±20 LSB 0 V to 10 V analog input range 1 Zero Code Error Match ±3 LSB Matching from ADC A to ADC B ±0.2 LSB Channel-to-channel matching for ADC A and ADC B 1 Negative Full-Scale Error ±4 ±20 LSB ±5 V and ±10 V analog input range ±5 ±20 LSB 0 V to 10 V analog input range 1 Negative Full-Scale Error Match ±3 LSB Matching from ADC A to ADC B ±0.2 LSB Channel-to-channel matching for ADC A and ADC B ANALOG INPUT Input Voltage Ranges Programmed via RANGE pins; see Table 8 ±10 V ±5 V 0 to 10 V DC Leakage Current ±0.01 ±1 µA Input Capacitance 9 pF When in track, ±10 V range 13 pF When in track, ±5 V and 0 V to 10 V range Input Impedance 260 kΩ ±10 V @ 1 MSPS 2.5 MΩ ±10 V @ 100 kSPS 125 kΩ ±5 V and 0 V to 10 V range @ 1 MSPS 1.2 MΩ ±5 V and 0 V to 10 V range @ 100 kSPS Rev. D | Page 5 of 28 AD7366/AD7367 Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT 3 Reference Output Voltage 2.495 2.5 2.505 V ±0.2% max @ 25°C Long-Term Stability 150 ppm 1000 hours 1 Output Voltage Hysteresis 50 ppm Reference Input Voltage Range 2.5 3.0 V DC Leakage Current ±0.01 ±1 µA External reference applied to Pin D A/Pin D B CAP CAP Input Capacitance 25 pF ±5 V and ±10 V analog input range 17 pF 0 V to 10 V analog input range D A, D B Output Impedance 7 Ω CAP CAP Reference Temperature Coefficient 6 25 ppm/°C V Noise 20 µV rms Bandwidth = 3 kHz REF LOGIC INPUTS Input High Voltage, V 0.7 × V V INH DRIVE Input Low Voltage, V 0.8 V INL Input Current, I ±0.01 ±1 µA V = 0 V or V IN IN DRIVE 2 Input Capacitance, C 6 pF IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V OH DRIVE Output Low Voltage, V 0.4 V OL Floating State Leakage Current ±0.01 ±1 µA 2 Floating State Output Capacitance 8 pF CONVERSION RATE Conversion Time 680 ns 2 Track/Hold Acquisition Time 140 ns Full-scale step input Throughput Rate 1 MSPS 4.75 V ≤ V ≤ 5.25 V, f = 48 MHz DRIVE SCLK 900 kSPS 2.7 V ≤ V < 4.75 V, f = 35 MHz DRIVE SCLK POWER REQUIREMENTS Digital inputs = 0 V or V DRIVE V 4.75 5.25 V See Table 7 CC V +11.5 +16.5 V See Table 7 DD V −16.5 −11.5 V See Table 7 SS V 2.7 5.25 V DRIVE Normal Mode (Static) I 370 550 µA V = +16.5 V DD DD I 40 60 µA V = −16.5 V SS SS I 1.5 2.25 mA V = 5.5 V CC CC Normal Mode (Operational) f = 1 MSPS S I 1.8 2.0 mA V = +16.5 V DD DD I 1.5 1.6 mA V = −16.5 V SS SS I 5 5.65 mA V = 5.25 V, internal reference enabled CC CC Shutdown Mode I 0.01 1 µA V = +16.5 V DD DD I 0.01 1 µA V = −16.5 V SS SS I 0.3 3 µA V = 5.25 V CC CC Power Dissipation Normal Mode (Operational) 80.7 89.1 mW V = +16.5 V, V = −16.5 V, V = 5.25 V DD SS CC 50 mW ±10 V input range, f = 1 MSPS S 70 mW ±5 V and 0 V to 10 V input range, f = 1 MSPS S Shutdown Mode 1.9 48.75 µW V = +16.5 V, V = −16.5 V, V = 5.25 V DD SS CC 1 See the Terminology section. 2 Sample tested during initial release to ensure compliance. 3 o Refers to Pin D A or Pin D B specified for 25 C. CAP CAP Rev. D | Page 6 of 28 AD7366/AD7367 TIMING SPECIFICATIONS AV = DV = 4.75 V to 5.25 V, V = 11.5 V to 16.5 V, V = −16.5 V to −11.5 V, V = 2.7 V to 5.25 V, T = −40°C to +85°C, CC CC DD SS DRIVE A 1 unless otherwise noted. Table 4. Limit at T , T MIN MAX Parameter 2.7 V ≤ V < 4.75 V 4.75 V ≤ V ≤ 5.25 V Unit Test Conditions/Comments DRIVE DRIVE t Conversion time, internal clock; falling edge to CNVST CONVERT BUSY falling edge 680 680 ns max AD7367 610 610 ns max AD7366 f 10 10 kHz min Frequency of serial read clock SCLK 35 48 MHz max t 30 30 ns min Minimum quiet time required between the end of serial QUIET read and the start of the next conversion t 10 10 ns min Minimum CNVST low pulse 1 t 40 40 ns min CNVST falling edge to BUSY rising edge 2 t 0 0 ns min BUSY falling edge to MSB, valid when CS is low for t prior 3 4 to BUSY going low t 10 10 ns max Delay from CS falling edge until Pin 1 (D A) and Pin 23 4 OUT (D B) are three-state disabled OUT 2 t 20 14 ns max Data access time after SCLK falling edge 5 t 7 7 ns min SCLK to data valid hold time 6 t 0.3 × t 0.3 × t ns min SCLK low pulse width 7 SCLK SCLK t 0.3 × t 0.3 × t ns min SCLK high pulse width 8 SCLK SCLK t 10 10 ns max CS rising edge to D A, D B, high impedance 9 OUT OUT t 70 70 µs max Power-up time from shutdown mode; time required POWER-UP between CNVST rising edge and CNVST falling edge 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. R F DRIVE All timing specifications are with a 25 pF load capacitance. With a load capacitance greater than 25 pF, a digital buffer or latch must be used. See the Terminology section, Figure 25, and Figure 26. 2 The time required for the output to cross is 0.4 V or 2.4 V. Rev. D | Page 7 of 28 AD7366/AD7367 ABSOLUTE MAXIMUM RATINGS Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to AGND, DGND −0.3 V to +16.5 V DD rating only; functional operation of the device at these or any V to AGND, DGND −16.5 V to +0.3 V SS other conditions above those indicated in the operational V to DGND −0.3 V to DV DRIVE CC section of this specification is not implied. Exposure to absolute V to AV (V − 0.3 V) to +16.5 V DD CC CC maximum rating conditions for extended periods may affect AV to AGND, DGND −0.3 V to +7 V CC device reliability. DV to AV −0.3 V to +0.3 V CC CC DV to DGND −0.3 V to +7 V ESD CAUTION CC V to AGND −0.3 V to DV DRIVE CC AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND V − 0.3 V to V + 0.3 V SS DD Digital Input Voltage to DGND −0.3 V to V + 0.3 V DRIVE Digital Output Voltage to GND −0.3 V to V + 0.3 V DRIVE D A, D B Input to AGND −0.3 V to AV + 0.3 V CAP CAP CC Input Current to Any Pin Except ±10 mA 1 Supplies Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package θ Thermal Impedance 128°C/W JA θ Thermal Impedance 42°C/W JC Pb-Free Temperature, Soldering Reflow 260°C ESD 1.5 kV 1 Transient currents of up to 100 mA will not cause latch-up. Rev. D | Page 8 of 28 AD7366/AD7367 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D A 1 24 DGND OUT V 2 23 D B DRIVE OUT DV 3 22 BUSY CC 4 AD7366/ 21 RANGE1 CNVST AD7367 RANGE0 5 20 SCLK TOP VIEW ADDR 6 19 CS (Not to Scale) 18 REFSEL AGND 7 AV 8 17 AGND CC D A 9 16 D B CAP CAP V 15 10 V SS DD V 11 14 V A1 B1 V 12 13 V A2 B2 Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1, 23 D A, D B Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on OUT OUT the falling edge of the SCLK input; 12 SCLK cycles are required to access a result from the AD7366, and 14 SCLK cycles are required for the AD7367. The data simultaneously appears on both pins from the simultaneous con- versions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366 and 14 bits for the AD7367 and is provided MSB first. If CS is held low for a further 14 SCLK cycles, on either D A or D B, the OUT OUT data from the other ADC follows on that D pin. Note, the second serial result from the AD7366 is preceeded OUT by two zeros. Therfore data from a simultaneous conversion on both ADCs can be gathered in serial format on either D A or D B using only one serial port. See the Serial Interface section for more information. OUT OUT 2 V Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. DRIVE This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different from the voltage at AV and DV , but should never exceed either by more than 0.3 V. To achieve a throughput CC CC rate of 1.12 MSPS for the AD7366 or 1 MSPS for the AD7367, V must be ≥ 4.75 V. DRIVE 3 DV Digital Supply Voltage, 4.75 V to 5.25 V. The DV and AV voltages should ideally be at the same potential. CC CC CC For best performance, it is recommended that the DV and AV pins be shorted together, to ensure that the CC CC voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled to DGND. Place 10 µF and 100 nF decoupling capacitors on the DV pin. CC 4, 5 RANGE1, Analog Input Range Selection, Logic Inputs. The polarity on these pins determines the input range of the analog RANGE0 input channels. See the Analog Inputs section and Table 8 for details. 6 ADDR Multiplexer Select, Logic Input. This input is used to select the pair of channels to be simultaneously converted, either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B. The logic state on this pin is latched on the rising edge of BUSY to set up the multiplexer for the next conversion. 7, 17 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7366/AD7367. All analog input signals and any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 8 AV Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AV and DV voltages CC CC CC should ideally be at the same potential. For best performance, it is recommended that the DV and AV pins be CC CC shorted together, to ensure that the voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled to AGND. Place 10 µF and 100 nF decoupling capacitors on the AV pin. CC 9, 16 D A, D B Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer CAP CAP for each respective ADC. For best performance, it is recommended that a 680 nF decoupling capacitor be used on these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. 10 V Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure SS of the AD7366/AD7367. The supply must be less than a maximum voltage of −11.5 V for all analog input ranges. See Table 7 for more details. Place 10 µF and 100 nF decoupling capacitors on the V pin. SS 11, 12 V , V Analog Inputs of ADC A. Both analog inputs are single-ended. The analog input range on these channels is A1 A2 determined by the RANGE0 and RANGE1 pins. 13, 14 V , V Analog Inputs of ADC B. Both analog inputs are single-ended. The analog input range on these channels is B2 B1 determined by the RANGE0 and RANGE1 pins. 15 V Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure of DD the AD7366/AD7367. The supply must be greater than a minimum voltage of 11.5 V for all analog input ranges. See Table 7 for more details. Place 10 µF and 100 nF decoupling capacitors on the V pin. DD Rev. D | Page 9 of 28 06703-002 AD7366/AD7367 Pin No. Mnemonic Description 18 REFSEL Internal/External Reference Selection, Logic Input. If this pin is tied to logic high, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, Pin D A and Pin D B must be tied to CAP CAP decoupling capacitors. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7366/ AD7367 through the D A pin, the D B pin, or both pins. CAP CAP 19 CS Chip Select, Active Low Logic Input. This input frames the serial data transfer. When CS is logic low, the output bus is enabled and the conversion result is output on D A and D B. OUT OUT 20 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7366/AD7367. 21 CNVST Conversion Start, Logic Input. This pin is edge triggered. On the falling edge of this input, the track/hold goes into hold mode and the conversion is initiated. If CNVST is low at the end of a conversion, the part goes into power-down mode. In this case, the rising edge of CNVST instructs the part to power up again. 22 BUSY Busy Output. BUSY transitions high when a conversion is started and remains high until the conversion is complete. 24 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7366/AD7367. The DGND pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Rev. D | Page 10 of 28 AD7366/AD7367 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A 1.0 –76 0V TO 10V RANGE 0.8 0.6 –78 0.4 0.2 ±10V RANGE –80 ±5V RANGE 0 –0.2 –82 –0.4 AV = 5V, DV = 5V CC CC AV = 5V, DV = 5V CC CC V = 15V, V = –15V DD SS –0.6 –84 V = 15V, V = –15V DD SS V = 3V DRIVE V = 3V DRIVE f = 1MSPS S –0.8 f = 1MSPS S T = 25°C A INTERNAL REFERENCE INTERNAL REFERENCE –86 –1.0 10 100 1000 0 2000 4000 6000 8000 10000 12000 14000 16000 ANALOG INPUT FREQUENCY (kHz) CODE Figure 3. AD7367 Typical DNL Figure 6. THD vs. Analog Input Frequency 2.0 AV = 5V, DV = 5V –66 CC CC V = 15V, V = –15V DD SS V = 3V DRIVE R = 2000Ω 1.5 IN f = 1MSPS S INTERNAL REFERENCE 1.0 ±5V RANGE –71 0.5 R = 1300Ω IN R = 3000Ω IN 0 –76 R = 470Ω IN R = 5100Ω IN –0.5 AV = 5V, DV = 5V –81 –1.0 CC CC V = 15V, V = –15V DD SS R = 240Ω IN V = 3V DRIVE R = 56Ω IN –1.5 f = 1MSPS S T = 25°C A R = 3900Ω IN INTERNAL REFERENCE –86 –2.0 10 100 1000 0 2000 4000 6000 8000 10000 12000 14000 16000 ANALOG INPUT FREQUENCY (kHz) CODE Figure 4. AD7367 Typical INL Figure 7. THD vs. Analog Input Frequency for Various Source Impedances 0 AV = 5V, DV = 5V 77 CC CC V = 15V, V = –15V DD SS –20 V = 3V DRIVE f = 1MSPS, f = 50kHz S IN ±10V RANGE –40 INTERNAL REFERENCE 75 SNR = 76dB, SINAD = 75dB –60 0V TO 10V RANGE 73 –80 71 –100 –120 AV = 5V, DV = 5V CC CC 69 V = 15V, V = –15V DD SS V = 3V DRIVE –140 f = 1MSPS S ±5V RANGE INTERNAL REFERENCE 67 –160 10 100 1000 0 50 100 150 200 250 300 350 400 450 500 ANALOG INPUT FREQUENCY (kHz) FREQUENCY (kHz) Figure 5. AD7367 FFT Figure 8. SINAD vs. Analog Input Frequency Rev. D | Page 11 of 28 (dB) INL ERROR (LSB) DNL ERROR (LSB) 06703-004 06703-003 06703-005 THD (dB) SINAD (dB) THD (dB) 06703-006 06703-008 06703-007 AD7366/AD7367 –70 80 AV = 5V, DV = 5V CC CC V = 15V, V = –15V DD SS V = 0V TO 10V IN –75 V = 3V DRIVE 60 f = 1MSPS S INTERNAL REFERENCE –80 ±5V RANGE 40 V = +5V IN –85 0V TO 10V RANGE V = +10V IN –90 20 –95 ±10V RANGE 0 –100 AV = 5V, DV = 5V CC CC V = 15V, V = –15V DD SS –20 V = –10V IN V = 3V DRIVE –105 f = 1MSPS S INTERNAL REFERENCE V = –5V IN –110 –40 0 100 200 300 400 500 600 100 200 300 400 500 600 700 800 900 1000 FREQUENCY OF INPUT NOISE (kHz) THROUGHPUT RATE (kSPS) Figure 9. Channel-to-Channel Isolation Figure 12. Analog Input Current vs. Throughput Rate 110000 2.5050 106091 CODES 31 CODES 344 CODES 100000 2.5045 90000 2.5040 80000 2.5035 70000 2.5030 60000 2.5025 50000 2.5020 40000 2.5015 30000 2.5010 20000 AV = 5V, DV = 5V CC CC 2.5005 V = 15V, V = –15V 10000 DD SS V = 3V DRIVE 0 2.5000 8191 8192 8193 8194 8195 8196 0 10 20 30 40 50 60 70 80 CODE CURRENT LOAD (µA) Figure 10. Histogram of Codes for 200k Samples Figure 13. V vs. Reference Output Current Drive REF –70 0.300 V , ADC A CC 100mV p-p SINE WAVE ON AV 0.250 CC –80 SOURCE CURRENT NO DECOUPLING CAPACITOR V = 15V, V = –15V DD SS V , ADC B CC V = 3V DRIVE 0.200 f = 1MSPS S –90 V ADC B DD, SINK CURRENT 0.150 –100 0.100 V , ADC B V , ADC A SS DD –110 AV = 5V, DV = 5V CC CC 0.50 V = 15V, V = –15V DD SS V , ADC A SS V = 3V, f = 1MSPS DRIVE S INTERNAL REFERENCE –120 0 0 200 400 600 800 1000 1200 0 500 1000 1500 2000 2500 SUPPLY RIPPLE FREQUENCY (kHz) CURRENT (µA) Figure 11. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 14. D Source Current vs. (V − V ) and D Sink Current vs. V OUT CC OUT OUT OUT Rev. D | Page 12 of 28 PSRR (dB) CHANNEL-TO-CHANNEL ISOLATION (dB) 06703-010 06703-009 06703-011 ANALOG INPUT CURRENT (µA) V OR V – V (V) V (V) OUT CC OUT REF 06703-014 06703-013 06703-012 AD7366/AD7367 AV = 5V, DV = 5V CC CC 0V TO 10V RANGE V = 15V, V = –15V 65 DD SS V = 3V DRIVE f = 1MSPS S INTERNAL REFERENCE 55 ±5V RANGE 45 35 ±10V RANGE 25 15 100 200 300 400 500 600 700 800 900 1000 SAMPLING FREQUENCY (kSPS) Figure 15. Power vs. Sampling Frequency in Normal Mode Rev. D | Page 13 of 28 POWER (mV) 06703-017 AD7366/AD7367 TERMINOLOGY Total Harmonic Distortion (THD) Differential Nonlinearity (DNL) THD is the ratio of the rms sum of harmonics to the fundamental. DNL is the difference between the measured and the ideal For the AD7366/AD7367, THD is defined as follows: 1 LSB change between any two adjacent codes in the ADC. 2 2 2 2 2 Integral Nonlinearity (INL) V +V +V +V +V 2 3 4 5 6 THD(dB)= 20 log INL is the maximum deviation from a straight line passing V 1 through the endpoints of the ADC transfer function. The where: endpoints of the transfer function are zero scale, a point 1 LSB V is the rms amplitude of the fundamental. 1 below the first code transition, and full scale, a point 1 LSB above V , V , V , V , and V are the rms amplitudes of the second 2 3 4 5 6 the last code transition. through the sixth harmonics. Zero Code Error Peak Harmonic or Spurious Noise The deviation of the midscale transition (all 1s to all 0s) from Peak harmonic, or spurious noise, is the ratio of the rms value the ideal V voltage, that is, AGND − ½ LSB for bipolar ranges IN of the next largest component in the ADC output spectrum and 2 × V − 1 LSB for the unipolar range. REF (up to f /2, excluding dc) to the rms value of the fundamental. S Positive Full-Scale Error Normally, the value of this specification is determined by the The deviation of the last code transition (011…110) to (011…111) largest harmonic in the spectrum. However, for ADCs where from the ideal (that is, +4 × V − 1 LSB or +2 × V – 1 LSB) REF REF the harmonics are buried in the noise floor, it is a noise peak. after the zero code error has been factored out. Channel-to-Channel Isolation Negative Full-Scale Error Channel-to-channel isolation is a measure of the level of cross- The deviation of the first code transition (10…000) to (10…001) talk between any two channels when operating in any of the from the ideal (that is, −4 × V + 1 LSB, −2 × V + 1 LSB, or REF REF input ranges. It is measured by applying a full-scale, 150 kHz AGND + 1 LSB) after the zero code error has been factored out. sine wave signal to all unselected input channels and determining Zero Code Error Match how much that signal is attenuated in the selected channel with The difference in zero code error across all channels. a 50 kHz signal. The figure given is the typical value across all four channels for the AD7366/AD7367 (see Figure 9 for more Positive Full-Scale Error Match information). The difference in positive full-scale error across all channels. Intermodulation Distortion (IMD) Negative Full-Scale Error Match With inputs consisting of sine waves at two frequencies, fa and The difference in negative full-scale error across all channels. fb, any active device with nonlinearities creates distortion prod- Track-and-Hold Acquisition Time ucts at the sum, and different frequencies of mfa ± nfb, where The track-and-hold amplifier returns to track mode at the end m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms of a conversion. Track-and-hold acquisition time is the time are those for which neither m nor n is equal to zero. For example, required for the output of the track-and-hold amplifier to reach the second-order terms include (fa + fb) and (fa − fb), and the its final value, within ±½ LSB, after the end of a conversion. third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and Signal-to-Noise (+ Distortion) Ratio (SINAD) (fa − 2fb). This ratio is the measured ratio of signal-to-noise (+ distortion) The AD7366/AD7367 are tested using the CCIF standard where at the output of the ADC. The signal is the rms amplitude of the two input frequencies near the top end of the input bandwidth fundamental. Noise is the sum of all nonfundamental signals up are used. In this case, the second-order terms are usually distanced to half the sampling frequency (f /2), excluding dc. The ratio is S in frequency from the original sine waves, and the third-order dependent on the number of quantization levels in the digitiza- terms are usually at a frequency close to the input frequencies. tion process: the more levels, the smaller the quantization noise. As a result, the second- and third-order terms are specified The theoretical signal-to-noise (+ distortion) ratio for an ideal separately. The calculation of the intermodulation distortion is N-bit converter with a sine wave input is as follows: as per the THD specification, where it is the ratio of the rms Signal-to-Noise (+ Distortion) = (6.02N + 1.76) dB sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Thus, for a 12-bit converter, the SINAD is 74 dB. Rev. D | Page 14 of 28 AD7366/AD7367 Power Supply Rejection Ratio (PSRR) It is expressed in ppm using the following equation: Variations in power supply affect the full-scale transition but V (25°C)− V (T_ HYS) REF REF 6 not the converter’s linearity. PSRR is the maximum change in V (ppm)= × 10 HYS V (25°C) REF the full-scale transition point due to a change in power supply voltage from the nominal value (see Figure 11). where: V (25°C) is V at 25°C. Thermal (or Output Voltage) Hysteresis REF REF Thermal (or output voltage) hysteresis is defined as the absolute V (T_HYS) is the maximum change of V at T_HYS+ REF REF maximum change of reference output voltage after the device is or T_HYS−. cycled through temperature from either T_HYS+ = +25°C to T to +25°C MAX or T_HYS− = +25°C to T to +25°C MIN Rev. D | Page 15 of 28 AD7366/AD7367 THEORY OF OPERATION CONVERTER OPERATION CIRCUIT INFORMATION The AD7366/AD7367 have two successive approximation The AD7366/AD7367 are fast, dual, 2-channel, 12-/14-bit, ADCs, each based around two capacitive DACs. Figure 16 and bipolar input, simultaneous sampling, serial ADCs. The Figure 17 show simplified schematics of an ADC in acquisition AD7366/AD7367 can accept bipolar input ranges of ±10 V and conversion phases. The ADC comprises control logic, a and ±5 V. They can also accept a unipolar input range of 0 V to SAR, and a capacitive DAC. In Figure 16 (the acquisition phase), 10 V. The AD7366/AD7367 require V and V dual supplies DD SS SW2 is closed and SW1 is in Position A, the comparator is held for the high voltage analog input structures. These supplies must in a balanced condition, and the sampling capacitor arrays be equal to or greater than ±11.5 V. See Table 7 for the minimum acquire the signal on the input. requirements on these supplies for each analog input range. The AD7366/AD7367 require a low voltage 4.75 V to 5.25 V AV CC CAPACITIVE supply to power the ADC core. DAC A Table 7. Reference and Supply Requirements for Each V IN CONTROL SW1 Analog Input Range LOGIC B SW2 Selected Full-Scale COMPARATOR Analog Input Reference Input Minimum AGND Range (V) Voltage (V) Range (V) AV (V) V /V (V) CC DD SS Figure 16. ADC Acquisition Phase ±10 2.5 ±10 5 ±11.5 3.0 ±12 5 ±12 When the ADC starts a conversion (see Figure 17), SW2 opens ±5 2.5 ±5 5 ±11.5 and SW1 moves to Position B, causing the comparator to 3.0 ±6 5 ±11.5 become unbalanced. The control logic and the charge redis- 0 to 10 2.5 0 to 10 5 ±11.5 tribution DAC are used to add and subtract fixed amounts of 3.0 0 to 12 5 ±12 charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is The AD7366/AD7367 contain two on-chip, track-and-hold balanced again, the conversion is complete. The control logic amplifiers, two successive approximation ADCs, and a serial generates the ADC output code. interface with two separate data output pins. The AD7366/AD7367 are available in a 24-lead TSSOP, offering the user considerable CAPACITIVE space-saving advantages over alternative solutions. The AD7366/ DAC CNVST AD7367 require a signal to start conversion. On the A V IN falling edge of CNVST, both track-and-holds are placed into CONTROL SW1 LOGIC B hold mode and the conversions are initiated. The BUSY signal SW2 COMPARATOR goes high to indicate that the conversions are taking place. The clock source for each successive approximation ADC is provided AGND by an internal oscillator. The BUSY signal goes low to indicate Figure 17. ADC Conversion Phase the end of conversion. On the falling edge of BUSY, the track- ANALOG INPUTS and-hold returns to track mode. When the conversion is Each ADC in the AD7366/AD7367 has two single-ended finished, the serial clock input accesses data from the part. analog inputs. Figure 18 shows the equivalent circuit of the The AD7366/AD7367 have an on-chip 2.5 V reference that can analog input structure of the AD7366/AD7367. The two diodes be disabled if an external reference is preferred. If the internal provide ESD protection. Care must be taken to ensure that the reference is to be used elsewhere in a system, the output from analog input signals never exceed the supply rails by more than D A and D B must first be buffered. On power-up, the CAP CAP 300 mV. This causes these diodes to become forward-biased REFSEL pin must be tied to either a high or low logic state to and to start conducting current into the substrate. These diodes select either the internal or external reference option. If the can conduct up to 10 mA without causing irreversible damage internal reference is the preferred option, the user must tie the to the part. The resistors are lumped components made up of REFSEL pin logic high. Alternatively, if REFSEL is tied to GND the on resistance of the switches. The value of these resistors is then an external reference can be supplied to both ADCs typically about 170 Ω. Capacitor C1 can primarily be attributed through the D A and D B pins. CAP CAP to pin capacitance, while Capacitor C2 is the sampling capacitor The analog inputs are configured as two single-ended inputs of the ADC. The total lumped capacitance of C1 and C2 is for each ADC. The input voltage range can be selected by approximately 9 pF for the ±10 V input range and approxi- programming the RANGE bits as shown in Table 8. mately 13 pF for all other input ranges. Rev. D | Page 16 of 28 06703-019 06703-018 AD7366/AD7367 V Table 10. LSB Sizes for Each Analog Input Range DD AD7366 AD7367 D C2 R1 V Input Full-Scale LSB Size Full-Scale LSB Size IN C1 Range Range (mV) Range (mV) D ±10 V 20 V/4096 4.88 20 V/16,384 1.22 V SS ±5 V 10 V/4096 2.44 10 V/16,384 0.61 Figure 18. Equivalent Analog Input Structure 0 V to 10 V 10 V/4096 2.44 10 V/16,384 0.61 The AD7366/AD7367 can handle true bipolar input voltages. The analog input can be set to one of three ranges: ±10 V, ±5 V, or 0 V to 10 V. The logic levels on Pin RANGE0 and Pin RANGE1 011...111 determine which input range is selected as outlined in Table 8. 011...110 These range bits should not be changed during the acquisition 000...001 time prior to a conversion, but can be changed at any other time. 000...000 111...111 Table 8. Analog Input Range Selection RANGE1 RANGE0 Range Selected 100...010 100...001 0 0 ±10 V 100...000 0 1 ±5 V –FSR/2 + 1LSB +FSR/2 – 1LSB 0V 1 0 0 V to 10 V ANALOG INPUT 1 1 Do not program Figure 19. Transfer Characteristic The AD7366/AD7367 require V and V dual supplies for the DD SS Track-and-Hold high voltage analog input structures. These supplies must be The track-and-hold on the analog input of the AD7366/AD7367 equal to or greater than ±11.5 V. See Table 7 for the require- allows the ADC to accurately convert an input sine wave of full- ments on these supplies. The AD7366/AD7367 require a low scale amplitude to 12-/14-bit accuracy. The input bandwidth of voltage 4.75 V to 5.25 V AV supply to power the ADC core, CC the track-and-hold is greater than the Nyquist rate of the ADC. a 4.75 V to 5.25 V DV supply for digital power, and a 2.7 V CC The AD7366/AD7367 can handle frequencies up to 35 MHz. to 5.25 V V supply for interface power. DRIVE The track-and-hold enters its tracking mode when the BUSY Channel selection is made via the ADDR pin, as shown in signal goes low after the CS falling edge. The time required to Table 9. The logic level on the ADDR pin is latched on the acquire an input signal depends on how quickly the sampling rising edge of the BUSY signal for the next conversion, not capacitor is charged. With zero source impedance, 140 ns is suffi- the one in progress. When power is first supplied to the cient to acquire the signal to the 12-bit level for the AD7366 and AD7366/AD7367, the default channel selection is V and V . A1 B1 the 14-bit level for the AD7367. The acquisition time for the ±10 V, ±5 V, and 0 V to 10 V ranges to settle to within ±½ LSB Table 9. Channel Selection is typically 140 ns. The ADC returns to hold mode on the ADDR Channels Selected falling edge of CNVST. 0 V , V A1 B1 1 V , V A2 B2 The acquisition time required is calculated using the following formula: TRANSFER FUNCTION t = 10 × ((R + R) C) ACQ SOURCE The output coding of the AD7366/AD7367 is twos complement. The designed code transitions occur at successive integer LSB where: values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent C is the sampling capacitance. on the analog input range selected (see Table 10). The ideal R is the resistance seen by the track-and-hold amplifier looking transfer characteristic is shown in Figure 19. at the input. R should include any extra source impedance on the SOURCE analog input. Rev. D | Page 17 of 28 06703-020 ADC CODE 06703-021 AD7366/AD7367 Unlike other bipolar ADCs, the AD7366/AD7367 do not have a TYPICAL CONNECTION DIAGRAM resistive analog input structure. On the AD7366/AD7367, the Figure 20 shows a typical connection diagram for the AD7366/ bipolar analog signal is sampled directly onto the sampling AD7367. In this configuration, the AGND pin is connected capacitor. This gives the AD7366/AD7367 high analog input to the analog ground plane of the system, and the DGND pin impedance. The analog input impedance can be calculated from is connected to the digital ground plane of the system. The the following formula: analog inputs on the AD7366/AD7367 accept bipolar single- Z = 1/(f × C ) ended signals. The AD7366/AD7367 can operate with either S S an internal or an external reference. In Figure 20, the AD7366/ where: AD7367 are configured to operate with the internal 2.5 V reference. f is the sampling frequency. S A 680 nF decoupling capacitor is required when operating with C is the sampling capacitor value. S the internal reference. C depends on the analog input range chosen (see the Analog S The AV and DV pins are connected to a 5 V supply voltage. CC CC Inputs section). When operating at 1 MSPS, the analog input The V and V are the dual supplies for the high voltage analog DD SS impedance is typically 260 kΩ for the ±10 V range. As the input structures. The voltage on these pins must be equal to or sampling frequency is reduced, the analog input impedance greater than ±11.5 V (see Table 7 for more information). The further increases. As the analog input impedance increases, the V pin is connected to the supply voltage of the microprocessor. DRIVE current required to drive the analog input therefore decreases The voltage applied to the V input controls the voltage of DRIVE (see Figure 7 for more information). the serial interface. V can be set to 3 V or 5 V. DRIVE + 0.1µF +5V SUPPLY +11.5V TO +16.5V SUPPLY + + + + 10µF 0.1µF 0.1µF 10µF V DV AV DD CC CC +3V OR +5V SUPPLY V DRIVE + + V A1 0.1µF 10µF AD7366/ AD7367 V A2 CS ANALOG INPUTS ±10V, SCLK ±5V, AND 0V TO +10V CNVST D A OUT V B1 D B OUT BUSY V B2 ADDR V REFSEL DRIVE D A CAP SERIAL RANGE0 INTERFACE + D B RANGE1 680nF CAP + DGND 680nF V AGND SS –16.5V TO –11.5V SUPPLY 0.1µF 10µF + + Figure 20. Typical Connection Diagram Using Internal Reference Rev. D | Page 18 of 28 MICROCONTROLLER/ MICROPROCESSOR 06703-022 AD7366/AD7367 V DRIVER AMPLIFIER CHOICE DRIVE The AD7366/AD7367 also have a V feature to control the The AD7366/AD7367 have a total of four analog inputs, which DRIVE voltage at which the serial interface operates. V allows the operate in single-ended mode. The analog inputs for both ADCs DRIVE ADC to easily interface to both 3 V and 5 V processors. For can be programmed to one of the three analog input ranges. In example, if the AD7366/AD7367 were operated with a V of applications where the signal source is high impedance, it is CC 5 V, the V pin could be powered from a 3 V supply, allowing recommended that the signal be buffered before applying it to DRIVE a large dynamic range with low voltage digital processors. Thus, the ADC analog inputs. Figure 21 shows the configuration of the AD7366/AD7367 can be used with the ±10 V input range the AD7366/AD7367 in single-ended mode. while still being able to interface to 3 V digital parts. In applications where the THD and SNR are critical specifi- To achieve the maximum throughput rate of 1.12 MSPS for the cations, the analog input of the AD7366/AD7367 should be AD7366 or 1 MSPS for the AD7367, V must be greater than driven from a low impedance source. Large source impedances DRIVE or equal to 4.75 V (see Table 2 and Table 3). The maximum significantly affect the ac performance of the ADC and can throughput rate with the V voltage set to less than 4.75 V necessitate the use of an input buffer amplifier. DRIVE and greater than 2.7 V is 1 MSPS for the AD7366 and 900 kSPS When no amplifier is used to drive the analog input, the source for the AD7367. impedance should be limited to low values. The maximum source REFERENCE impedance depends on the amount of THD that can be tolerated in the application. The THD increases as the source impedance The AD7366/AD7367 can operate with either the internal 2.5 V increases and performance degrades. Figure 7 shows THD vs. on-chip reference or an externally applied reference. The logic the analog input frequency for various source impedances. state of the REFSEL pin determines whether the internal refer- Depending on the input range and analog input configuration ence is used. The internal reference is selected for both ADCs selected, the AD7366/AD7367 can handle source impedances as when the REFSEL pin is tied to logic high. If the REFSEL pin is illustrated in Figure 7. tied to GND, an external reference can be supplied through the Due to the programmable nature of the analog inputs on the D A and D B pins. On power-up, the REFSEL pin must be CAP CAP tied to either a low or high logic state for the part to operate. AD7366/AD7367, the choice of op amp used to drive the Suitable reference sources for the AD7366/AD7367 include the inputs is a function of the particular application and depends AD780, AD1582, ADR431, REF193, and ADR391. on the analog input voltage range selected. The internal reference circuitry consists of a 2.5 V band gap The driver amplifier must be able to settle for a full-scale step reference and a reference buffer. When operating the AD7366/ to a 14-bit level, 0.0061%, in less than the specified acquisition time of the AD7366/AD7367. An op amp such as the AD8021 AD7367 in internal reference mode, the 2.5 V internal reference meets this requirement when operating in single-ended mode. is available at the D A and D B pins, which should be CAP CAP The AD8021 needs an external compensating NPO type of decoupled to AGND using a 680 nF capacitor. It is recom- mended that the internal reference be buffered before applying capacitor. The AD8022 can also be used in high frequency it elsewhere in the system. The internal reference is capable of applications where a dual version is required. For lower fre- sourcing up to 150 μA with an analog input range of ±10 V quency applications, recommended op amps are the AD797, and 70 μA for both the ±5 V and 0 V to 10 V ranges. AD845, and AD8610. V+ If the internal reference operation is required for the ADC con- version, the REFSEL pin must be tied to logic high on power-up. 10µF +5V The reference buffer requires 70 µs to power up and charge the +10V/+5V 680 nF decoupling capacitor during the power-up time. 0.1µF + AGND AD8021 V A1 The AD7366/AD7367 are specified for a 2.5 V to 3 V reference. V V DD CC –10V/–5V When a 3 V reference is selected, the analog input ranges are 1kΩ AD7366/ AD7367* ±12 V, ±6 V, and 0 V to 12 V. For these ranges, the V supply DD 15pF V 1kΩ SS must be greater than or equal to +12 V and the V supply must SS 0.1µF C = 10pF COMP be less than or equal to −12 V. 10µF V– *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 21. Typical Connection Diagram with the AD8021 for Driving the Analog Input Rev. D | Page 19 of 28 + + + + 06703-023 AD7366/AD7367 MODES OF OPERATION The mode of operation of the AD7366/AD7367 is selected by The CS pin must be brought low to bring the data bus out of the logic state of the CNVST signal at the end of a conversion. three-state. Therefore, 12 SCLK cycles are required to read the There are two possible modes of operation: normal mode and conversion result from the AD7366 and 14 SCLK cycles are shutdown mode. These modes of operation are designed to required to read the conversion result from the AD7367. The provide flexible power management options, which can be CS D lines return to three-state only when is brought high. If OUT chosen to optimize the power dissipation/throughput rate CS is left low for an additional 12 SCLK cycles for the AD7366 or ratio for differing application requirements. 14 SCLK cycles for the AD7367, the result from the other on-chip ADC is also accessed on the same D line, as shown in Figure 27 OUT NORMAL MODE and Figure 28 (see the Serial Interface section). Normal mode is intended for applications that require fast When 24 SCLK cycles have elapsed for the AD7366 or 28 SCLK throughput rates. In normal mode, the AD7366/AD7367 cycles for the AD7367, the D line returns to three-state only remain fully powered at all times, so the user does not need to OUT th th CS when is brought high, not on the 24 or 28 SCLK falling worry about power-up times. Figure 22 shows the general mode CS edge. If is brought high prior to this, the D line returns to of operation of the AD7366 in normal mode; Figure 23 shows OUT CS normal mode for the AD7367. three-state at that point. Thus, must be brought high when the read is completed, because the bus does not automatically CNVST The conversion is initiated on the falling edge of as return to three-state upon completion of the dual result read. described in the Circuit Information section. To ensure that CNVST When a data transfer is complete and D A and D B have the part remains fully powered up at all times, must be OUT OUT returned to three-state, another conversion can be initiated after CNVST at logic state high before the BUSY signal goes low. If is CNVST the quiet time, t , has elapsed by bringing low again. at logic state low when the BUSY signal goes low, the analog QUIET circuitry powers down and the part ceases converting. The BUSY signal remains high for the duration of the conversion. t 1 CNVST t QUIET t 2 BUSY t CONVERT t 3 CS SCLK SERIAL READ OPERATION 1 12 Figure 22. Normal Mode Operation for the AD7366 t 1 CNVST t QUIET t 2 BUSY t CONVERT t 3 CS SCLK SERIAL READ OPERATION 1 14 Figure 23. Normal Mode Operation for the AD7367 Rev. D | Page 20 of 28 06703-025 06703-024 AD7366/AD7367 SHUTDOWN MODE POWER-UP TIMES Shutdown mode is intended for use in applications where slow The AD7366/AD7367 have one power-down mode, which is throughput rates are required. Shutdown mode is suited to described in detail in the Shutdown Mode section. This section applications where a series of conversions performed at a deals with the power-up time required when coming out of relatively high throughput rate are followed by a long period shutdown mode. It should be noted that the power-up times (as of inactivity and thus, shutdown. When the AD7366/AD7367 explained in this section) apply with the recommended capaci- are in full power-down, all analog circuitry is powered down. tors in place on the D A and D B pins. To power up from CAP CAP The falling edge of CNVST initiates the conversion. The BUSY shutdown, CNVST must be brought high and remain high for a output subsequently goes high to indicate that the conversion is minimum of 70 μs, as shown in Figure 24. in progress. After the conversion is completed, the BUSY output When power supplies are first applied to the AD7366/AD7367, CNVST returns low. If the signal is at logic low when BUSY CNVST the ADC can power up with in either the low or high goes low, the part enters shutdown at the end of the conversion CNVST logic state. Before attempting a valid conversion, must phase. While the part is in shutdown mode, the digital output be brought high and remain high for the recommended power- code from the last conversion on each ADC can still be read up time of 70 μs. Then CNVST can be brought low to initiate a from the D pins. To read the D data, CS must be brought OUT OUT conversion. With the AD7366/AD7367, no dummy conversion low as described in the Serial Interface section. The D pins OUT is required before valid data can be read from the D pins. OUT return to three-state when CS is brought back to logic high. To place the part in shutdown mode when the supplies are first To exit full power-down and to power up the AD7366/AD7367, applied, the AD7366/AD7367 must be powered up and a CNVST a rising edge of is required. After the required power-up conversion initiated. However, CNVST should remain in the CNVST time has elapsed, can be brought low again to initiate logic low state so that when the BUSY signal goes low, the part another conversion, as shown in Figure 24 (see the Power-Up enters shutdown. Times section for power-up times associated with the AD7366/ When supplies are applied to the AD7366/AD7367, sufficient AD7367). time must be allowed for any external reference to power up and to charge the various reference buffer decoupling capacitors to their final values. t POWER-UP ENTERS SHUTDOWN CNVST t 2 BUSY t CONVERT t 3 CS SCLK SERIAL READ OPERATION 1 12 Figure 24. Autoshutdown Mode for the AD7366 Rev. D | Page 21 of 28 06703-026 AD7366/AD7367 SERIAL INTERFACE On the rising edge of CS the conversion is terminated and Figure 25 and Figure 26 show the detailed timing diagram for D A and D B return to three-state. If CS is not brought OUT OUT serial interfacing to the AD7366 and the AD7367. On the high, but is instead held low for an additional 14 SCLK cycles falling edge of CNVST, the AD7366/AD7367 simultaneously the data from the other DOUT pin follows on the selected convert the selected channels. These conversions are performed DOUT pin. Note, the second serial result from the AD7366 is CNVST using the on-chip oscillator. After the falling edge of , preceeded by two zeros. See Figure 27 and Figure 28, where the BUSY signal goes high, indicating that the conversion has D A is shown. In this case, the D line in use returns to OUT OUT started. The BUSY signal returns low when the conversion has three-state on the rising edge of CS. been completed. The data can now be read from the D pins. OUT If the falling edge of SCLK coincides with the falling edge of CS, CS The and SCLK signals are required to transfer data from the the falling edge of SCLK is not acknowledged by the AD7366/ AD7366/AD7367. The AD7366/AD7367 have two output pins AD7367, and the next falling edge of SCLK is the first one corresponding to each ADC. Data can be read from the AD7366/ CS registered after the falling edge of . AD7367 using both D A and D B. Alternatively, a single OUT OUT output pin of the user’s choice can be used. The SCLK input CS The pin can be brought low before the BUSY signal goes CS signal provides the clock source for the serial interface. The CS low, indicating the end of a conversion. When is at a logic goes low to access data from the AD7366/AD7367. The falling low state, the data bus is brought out of three-state. This feature CS edge of takes the bus out of three-state and clocks out the can be used to ensure that the MSB is valid on the falling edge MSB of the conversion result. The data stream consists of of BUSY by bringing CS low a minimum of t before the BUSY 4 12 bits of data for the AD7366 and 14 bits of data for the signal goes low. The dotted CS line in Figure 22 and Figure 23 AD7367, MSB first. The first bit of the conversion result is illustrates this feature. valid on the first SCLK falling edge after the CS falling edge. CS Alternatively, the pin can be tied to a low logic state continu- The subsequent 11/13 bits of data for the AD7366/AD7367, ously. In this case, the D pins never enter three-state and the OUT respectively, are clocked out on the falling edge of the SCLK data bus is continuously active. Under these conditions, the MSB signal. A minimum of 12 clock pulses must be provided to the of the conversion result for the AD7366/AD7367 is available on AD7366 to access each conversion result, and a minimum of the falling edge of the BUSY signal. The next most significant 14 clock pulses must be provided to the AD7367 to access the bit is available on the first SCLK falling edge after the BUSY conversion result. Figure 25 shows how a 12 SCLK read is used signal has gone low. This mode of operation enables the user to to access the conversion results for the AD7366, and Figure 26 read the MSB as soon as it is made available by the converter. illustrates the case for the AD7367 with a 14 SCLK read. CS t 8 3 4 5 12 SCLK 1 2 t t 7 9 t t t 5 6 4 D A OUT DB10 DB9 DB8 DB2 DB1 DB0 D B THREE-STATE OUT THREE- DB11 STATE Figure 25. Serial Interface Timing Diagram for the AD7366 CS t 8 SCLK 1 2 3 4 5 14 t t 9 7 t t t 5 6 4 D A OUT DB12 DB11 DB10 DB2 DB1 DB0 D B OUT THREE-STATE THREE- DB13 STATE Figure 26. Serial Interface Timing Diagram for the AD7367 Rev. D | Page 22 of 28 06703-028 06703-027 AD7366/AD7367 CS t 8 SCLK 3 4 5 1 2 10 11 12 13 14 26 t 7 t t t 4 5 6 DB10 DB9 DB1 DB0 0 0 DB11 DB1 DB0 D A A A A A B B B OUT THREE- THREE- DB11 STATE A STATE Figure 27. Reading Data from Both ADCs on One D Line with 26 SCLKs for the AD7366 OUT CS t 8 SCLK 3 4 5 1 2 12 13 14 15 28 t 7 t t t 4 5 6 DB12 DB11 DB1 DB0 DB13 DB12 DB1 DB0 D A B B A A A A B B OUT THREE- THREE- DB13 A STATE STATE Figure 28. Reading Data from Both ADCs on One D Line with 28 SCLKs for the AD7367 OUT Rev. D | Page 23 of 28 06703-029 06703-030 AD7366/AD7367 MICROPROCESSOR INTERFACING The serial interface on the AD7366/AD7367 allows the parts to ADSP-218x* AD7366/ AD7367* be directly connected to a range of different microprocessors. SCLK SCLK0 This section explains how to interface the AD7366/AD7367 SCLK1 with some common microcontrollers and DSP serial interface CS TFS0 protocols. RFS0 AD7366/AD7367 TO ADSP-218x RFS1 D A DR0 The ADSP-218x family of DSPs interfaces directly to the OUT D B DR1 AD7366/AD7367 without any glue logic required. The V OUT DRIVE BUSY IRQ pin of the AD7366/AD7367 takes the same supply voltage as the CNVST FLO power supply pin of the ADSP-218x. This allows the ADC to V operate at a higher supply voltage than its serial interface and DRIVE therefore, the ADSP-218x, if necessary. This example shows both D A and D B of the AD7366/AD7367 connected to V OUT OUT DD both serial ports of the ADSP-218x. The SPORT0 and SPORT1 *ADDITIONAL PINS OMITTED FOR CLARITY. control registers should be set up as shown in Table 11 and Figure 29. Interfacing the AD7366/AD7367 to the ADSP-218x Table 12. The AD7366/AD7367 BUSY line provides an interrupt to the ADSP-218x when the conversion is complete. The conver- Table 11. SPORT0 Control Register Setup sion results can then be read from the AD7366/AD7367 using Setting Description a read operation. When an interrupt is received on IRQ from TFSW = RFSW = 1 Alternate framing the BUSY signal, a value is transmitted with TFS/DT (ADC INVRFS = INVTFS = 1 Active low frame signal control word). The TFS is used to control the RFS and, therefore, DTYPE = 00 Right-justify data the reading of data. SLEN = 1111 16-bit data-word (or can be set to 1101 for 14-bit data-word) AD7366/AD7367 TO ADSP-BF53x ISCLK = 1 Internal serial clock The ADSP-BF53x family of DSPs interfaces directly to the TFSR = RFSR = 1 Frame every word AD7366/AD7367 without any glue logic required. The avail- IRFS = 0 ability of secondary receive registers on the serial ports of the ITFS = 1 Blackfin® DSPs means that only one serial port is necessary to read from both the D A and D B pins simultaneously. Table 12. SPORT1 Control Register Setup OUT OUT Figure 30 shows both D A and D B of the AD7366/AD7367 OUT OUT Setting Description connected to Serial Port 0 of the ADSP-BF53x. The SPORT0 TFSW = RFSW = 1 Alternate framing Receive Configuration 1 register and the SPORT0 Receive INVRFS = INVTFS = 1 Active low frame signal Configuration 2 register should be set up as outlined in Table 13 DTYPE = 00 Right-justify data and Table 14. SLEN = 1111 16-bit data-word (or can be set to 1101 for 14-bit data-word) ADSP-BF53x* AD7366/ SERIAL ISCLK = 0 External serial clock AD7367* DEVICE A SPORT0 (PRIMARY) TFSR = RFSR = 1 Frame every word D A DR0PRI OUT IRFS = 0 SCLK RCLK0 ITFS = 1 CS RFS0 BUSY RXINTS The connection diagram is shown in Figure 29. The ADSP-218x CNVST PF N has the TFS0 and RFS0 of the SPORT0 and the RFS1 of SPORT1 D B DR0SEC OUT tied together. TFS0 is set as an output, and both RFS0 and RFS1 SERIAL V DRIVE DEVICE B are set as inputs. The DSP operates in alternate framing mode, (SECONDARY) and the SPORT control register is set up as described in Table 11 and Table 12. The frame synchronization signal generated on V *ADDITIONAL PINS OMITTED FOR CLARITY. DD CS the TFS is tied to . Figure 30. Interfacing the AD7366/AD7367 to the ADSP-BF53x Rev. D | Page 24 of 28 06703-032 06703-031 AD7366/AD7367 TMS320VC5506* Table 13. SPORT0 Receive Configuration 1 Register AD7366/ AD7367* (SPORT0_RCR1) SCLK CLKX0 Setting Description CLKR0 CLKX1 RCKFE = 1 Sample data with falling edge of RSCLK CLKR1 LRFS = 1 Active low frame signal D A DR0 OUT RFSR = 1 Frame every word D B DR1 OUT IRFS = 1 Internal RFS used CS FSX0 RLSBIT = 0 Receive MSB first FSR0 RDTYPE = 00 Zero fill FSR1 IRCLK = 1 Internal receive clock BUSY INTn RSPEN = 1 Receive enabled CNVST XF SLEN = 1111 16-bit data-word (or can be set to 1101 for V DRIVE 14-bit data-word) TFSR = RFSR = 1 V *ADDITIONAL PINS OMITTED FOR CLARITY. DD Figure 31. Interfacing the AD7366/AD7367 to the TMS320VC5506 Table 14. SPORT0 Receive Configuration 2 Register (SPORT0_RCR2) As with the previous interfaces, conversion can be initiated Setting Description from the TMS320VC5506 or from an external source, and the RXSE = 1 Secondary side enabled processor is interrupted when the conversion sequence is SLEN = 1111 16-bit data-word (or can be set to 1101 for completed. 14-bit data-word) AD7366/AD7367 TO DSP563xx AD7366/AD7367 TO TMS320VC5506 The connection diagram in Figure 32 shows how the AD7366/ AD7367 can be connected to the enhanced synchronous serial The serial interface on the TMS320VC5506 uses a continuous interface (ESSI) of the DSP563xx family of DSPs from Motorola. serial clock and frame synchronization signals to synchronize There are two on-board ESSIs, and each is operated in synchro- the data transfer operations with peripheral devices such as the nous mode (Bit SYN = 1 in the CRB register) with internally CS AD7366/AD7367. The input allows easy interfacing between generated word length frame sync for both Tx and Rx (Bit the TMS320VC5506 and the AD7366/AD7367 without any glue FSL1 = 0 and Bit FSL0 = 0 in the CRB register). logic required. The serial ports of the TMS320VC5506 are set up to operate in burst mode with internal CLKX0 (Tx serial Normal operation of the ESSI is selected by setting MOD = 0 in clock on Serial Port 0) and FSX0 (Tx frame sync from Serial the CRB register. Set the word length to 16 by setting Bit WL1 = 1 Port 0). The serial port control (SPC) registers must be set up as and Bit WL0 = 0 in the CRA register. The FSP bit in the CRB register should be set to 1 so that the frame sync is negative. shown in Table 15. Table 15. Serial Port Control Register Setup SPC FO FSM MCM TXM SPC0 0 1 1 1 SPC1 0 1 0 0 The connection diagram is shown in Figure 31. The V pin DRIVE of the AD7366/AD7367 takes the same supply voltage as the power supply pin of the TMS320VC5506. This allows the ADC to operate at a higher voltage than its serial interface and, therefore, the TMS320VC5506, if necessary. Rev. D | Page 25 of 28 06703-033 AD7366/AD7367 In the example shown in Figure 32, the serial clock is taken DSP563xx* AD7366/ AD7367* from the ESSI0, so the SCK0 pin must be set as an output SCLK SCK0 (SCKD = 1) while the SCK1 pin is set as an input (SCKD = 0). SCK1 The frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1, D A SRD0 OUT while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an D B SRD1 OUT input. The V pin of the AD7366/AD7367 takes the same DRIVE CS SC02 supply voltage as the power supply pin of the DSP563xx. This SC12 allows the ADC to operate at a higher voltage than its serial BUSY IRQ N interface and, therefore, the DSP563xx, if necessary. CNVST PB N V DRIVE V *ADDITIONAL PINS OMITTED FOR CLARITY. DD Figure 32. Interfacing the AD7366/AD7367 to the DSP563xx Rev. D | Page 26 of 28 06703-034 AD7366/AD7367 APPLICATION HINTS To avoid radiating noise to other sections of the board, com- LAYOUT AND GROUNDING ponents with fast switching signals, such as clocks, should be The printed circuit board that houses the AD7366/AD7367 shielded with digital ground and should never be run near the should be designed so that the analog and digital sections are analog inputs. Avoid crossover of digital and analog signals. To confined to separate areas of the board. This design facilitates the reduce the effects of feedthrough within the board, traces should use of ground planes that can be easily separated. be run at right angles to each other. A microstrip technique is To provide optimum shielding for ground planes, a minimum the best method, but its use may not be possible with a double- etch technique is generally the best option. All AGND pins on sided board. In the microstrip technique, the component side of the AD7366/AD7367 should be connected to the AGND plane. the board is dedicated to ground planes, and signals are placed Digital and analog ground pins should be joined in only one on the other side. place. If the AD7366/AD7367 are in a system where multiple Good decoupling is also important. All analog supplies should devices require an AGND and DGND connection, the connec- be decoupled with 10 µF tantalum capacitors in parallel with tion should still be made at only one point. A star point should 0.1 µF capacitors to AGND. To achieve the best results from be established as close as possible to the ground pins on the these decoupling components, they must be placed as close as AD7366/AD7367. possible to the device, ideally right up against the device. The Good connections should be made to the power and ground 0.1 µF capacitors should have a low effective series resistance planes. This can be done with a single via or multiple vias for (ESR) and low effective series inductance (ESI), such as is typical each supply and ground pin. of common ceramic and surface mount types of capacitors. These Avoid running digital lines under the AD7366/AD7367 devices low ESR, low ESI capacitors provide a low impedance path to because this couples noise onto the die. However, the analog ground at high frequencies to handle transient currents due to internal logic switching. ground plane should be allowed to run under the AD7366/ AD7367 to avoid noise coupling. The power supply lines to the AD7366/AD7367 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Rev. D | Page 27 of 28 AD7366/AD7367 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 0.75 8° 0.30 0° 0.60 0.20 SEATING 0.19 0.45 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD7366BRUZ −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7366BRUZ-RL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7366BRUZ-500RL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7367BRUZ −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7367BRUZ-500RL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7367BRUZ-RL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 EVAL-AD7366CBZ Evaluation Board EVAL-AD7367CBZ Evaluation Board EVAL-CONTROL BRD2 Control Board 1 Z = RoHS Compliant Part. ©2007-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06703-0-11/10(D) Rev. D | Page 28 of 28