ANALOG DEVICES AD7357

Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC AD7357 FEATURES FUNCTIONAL BLOCK DIAGRAM V V DD DRIVE Dual 14-bit SAR ADC Simultaneous sampling AD7357 Throughput rate: 4.2 MSPS per channel V INA+ 14-BIT T/H Specified for a V of 2.5 V DD SUCCESSIVE V SDATA INA– APPROXIMATION A Power dissipation: 36 mW at 4.2 MSPS ADC REF A On-chip reference: 2.048 V ± 0.25%, 6 ppm/°C Dual conversion with read BUF High speed serial interface SCLK CONTROL SPI-/QSPI-/MICROWIRE-/DSP-compatible REF LOGIC CS −40°C to +125°C operation BUF 16-lead TSSOP package Qualified for automotive applications REF B 14-BIT SUCCESSIVE APPLICATIONS SDATA V INB+ B APPROXIMATION T/H ADC Automotive radar V INB– Data acquisition systems Motion control AGND AGND REFGND DGND I and Q demodulation Figure 1. RFID readers GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1 The AD7357 is a dual, 14-bit, high speed, low power, successive 1. Two Complete ADC Functions. approximation analog-to-digital converter (ADC) that operates These functions allow simultaneous sampling and conversion from a single 2.5 V power supply and features throughput rates of two channels. The conversion result of both channels is up to 4.2 MSPS. The part contains two ADCs, each preceded by simultaneously available on separate data lines or in suc- a low noise, wide bandwidth track-and-hold circuit that can cession on one data line if only one serial port is available. handle input frequencies in excess of 110 MHz. 2. High Throughput with Low Power Consumption. The AD7357 offers a 4.2 MSPS throughput rate with The conversion process and data acquisition use standard 36 mW power consumption. control inputs allowing for easy interfacing to microprocessors 3. Simultaneous Sampling. or DSPs. The input signal is sampled on the falling edge of CS; a The part features two standard successive approximation conversion is also initiated at this point. The conversion time is ADCs with accurate control of the sampling instant via a determined by the SCLK frequency. CS input and once off conversion control. The AD7357 uses advanced design techniques to achieve very low power dissipation at high throughput rates. With a 2.5 V Table 1. Related Devices supply and a 4.2 MSPS throughput rate, the part consumes 14 mA Generic Resolution Throughput Analog Input typically. The part also offers flexible power/throughput rate AD7356 12-bit 5 MSPS Differential management options. AD7352 12-bit 3 MSPS Differential AD7266 12-bit 2 MSPS Differential/single-ended The analog input range for the part is the differential common AD7866 12-bit 1 MSPS Single-ended mode ±VREF/2. The AD7357 has an on-chip 2.048 V reference AD7366 12-bit 1 MSPS Single-ended bipolar that can be overdriven when an external reference is preferred. AD7367 14-bit 1 MSPS Single-ended bipolar The AD7357 is available in a 16-lead thin shrink small outline package (TSSOP). 1 Protected by U.S. Patent No. 6,681,332. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07757-001 AD7357 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs ............................................................................. 13 Applications....................................................................................... 1 Driving Differential Inputs ....................................................... 13 Functional Block Diagram .............................................................. 1 Voltage Reference ....................................................................... 14 General Description ......................................................................... 1 ADC Transfer Function............................................................. 14 Product Highlights ........................................................................... 1 Modes of Operation ....................................................................... 15 Revision History ............................................................................... 2 Normal Mode.............................................................................. 15 Specifications..................................................................................... 3 Partial Power-Down Mode ....................................................... 15 Timing Specifications .................................................................. 5 Full Power-Down Mode ............................................................ 16 Absolute Maximum Ratings............................................................ 6 Power-Up Times......................................................................... 17 ESD Caution.................................................................................. 6 Power vs. Throughput Rate....................................................... 17 Pin Configuration and Function Descriptions............................. 7 Serial Interface ................................................................................ 18 Typical Performance Characteristics ............................................. 8 Application Hints ........................................................................... 19 Terminology .................................................................................... 10 Grounding and Layout .............................................................. 19 Theory of Operation ...................................................................... 12 Evaluating the AD7357 Performance ...................................... 19 Circuit Information.................................................................... 12 Outline Dimensions....................................................................... 20 Converter Operation.................................................................. 12 Ordering Guide .......................................................................... 20 Analog Input Structure.............................................................. 12 Automotive Products................................................................. 20 REVISION HISTORY 8/11—Rev. A to Rev. B Changes to Midscale Error Match Parameter, Table 2 ................ 3 Changes to Figure 21 and Figure 22............................................. 14 Added Voltage Reference Section ........................................................14 2/11—Rev. 0 to Rev. A Changes to Features and Applications Sections ........................... 1 Changes to Table 2............................................................................ 3 Added AD7357WY Temperature Range to Endnote 1 in Table 3 ...5 Changes to SDATAB, SDATAA Pin Description............................ 7 Changes to Figure 20 and Figure 22............................................. 14 Changes to Figure 31...................................................................... 18 Changes to Ordering Guide .......................................................... 20 Added Automotive Products Section .......................................... 20 4/09—Revision 0: Initial Version Rev. B | Page 2 of 20 AD7357 SPECIFICATIONS 1 VDD = 2.5 ± 10% V, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, fSCLK = 80 MHz, fSAMPLE = 4.2 MSPS; TA = TMIN to TMAX , unless otherwise noted. Table 2. AD7357B/AD7357Y AD7357WY Test Conditions/ Parameter Unit Comments Min Typ Max Min Typ Max DYNAMIC PERFORMANCE f = 500 kHz sine wave IN Signal-to-Noise Ratio (SNR) 74.5 76.5 74.5 76.5 dB 74 −40°C to +25°C only 2 Signal-to-Noise and Distortion (SINAD) 74 76 74 76 dB 73.5 −40°C to +25°C only 2 −83 −80 −83 −80 dB Total Harmonic Distortion (THD) −79 −40°C to +25°C only Spurious Free Dynamic Range (SFDR) −85 −82 −85 −82 dB −81 −40°C to +25°C only 2 Intermodulation Distortion (IMD) fa = 1 MHz + 50 kHz, fb = 1 MHz – 50 kHz Second-Order Terms −86 −86 dB Third-Order Terms −79 −79 dB 2 −100 −100 dB fIN = 1 MHz, fNOISE = 100 kHz ADC-to-ADC Isolation to 2.5 MHz 2 −100 −100 dB fNOISE = 100 kHz to 2.5 MHz CMRR SAMPLE-AND-HOLD Aperture Delay 3.5 3.5 ns Aperture Delay Match 40 40 ps Aperture Jitter 16 16 ps Full Power Bandwidth @ 3 dB 110 110 MHz @ 0.1 dB 77 77 MHz @ 0.1 dB DC ACCURACY Resolution 14 14 Bits 2 Integral Nonlinearity (INL) ±2 ±3 ±2 ±3 LSB 2 ±0.5 ±0.99 ±0.5 ±0.99 LSB Guaranteed no missed Differential Nonlinearity (DNL) codes to 14 bits 2 ±20 ±20 LSB Positive Full-Scale Error 2 ±20 ±20 LSB Positive Full-Scale Error Match 2 0/35 0/38 LSB Midscale Error 2 ±12 ±15 LSB Midscale Error Match 2 Negative Full-Scale Error ±20 ±20 LSB 2 ±20 ±20 LSB Negative Full-Scale Error Match ANALOG INPUT Fully Differential Input Range V ± V /2 V ± V V = common-mode CM REF CM CM (VIN+ and VIN−) VREF/2 voltage; VIN+ and VIN− must remain within GND and VDD Common-Mode Voltage Range 0.5 1.6 0.5 1.6 V The voltage around which VIN+ and VIN− are centered DC Leakage Current ±0.5 ±5 ±0.5 ±5 μA Input Capacitance 32 32 pF When in track mode 8 8 pF When in hold mode Rev. B | Page 3 of 20 AD7357 AD7357B/AD7357Y AD7357WY Test Conditions/ Parameter Unit Comments Min Typ Max Min Typ Max REFERENCE INPUT/OUTPUT V Input Voltage Range 2.048 + 0.1 V 2.048 + 0.1 V V REF DD DD V Input Current 0.3 0.45 0.3 0.45 mA When in reference REF overdrive mode VREF Output Voltage 2.038 2.058 2.038 2.058 V ±2.048 V ± 0.5% max @ VDD = 2.5 V ± 5% 2.043 2.053 2.043 2.053 V 2.048 V ± 0.25% max @ VDD = 2.5 V ± 5% and 25°C VREF Temperature Coefficient 6 20 6 20 ppm/°C VREF Long Term Stability 100 100 ppm For 1000 hours VREF Thermal Hysteresis 50 50 ppm VREF Noise 60 60 μV rms VREF Output Impedance 1 1 Ω LOGIC INPUTS Input High Voltage, VINH 0.6 × VDRIVE 0.6 × VDRIVE V Input Low Voltage, VINL 0.3 × VDRIVE 0.3 × VDRIVE V Input Current, IIN ±1 ±1 μA VIN = 0 V or VDRIVE Input Capacitance, CIN 3 3 pF LOGIC OUTPUTS Output High Voltage, V V − 0.2 V − 0.2 V OH DRIVE DRIVE Output Low Voltage, V 0.2 0.2 V OL Floating-State Leakage Current ±1 ±1 μA Floating-State Output Capacitance 5.5 5.5 pF Output Coding Straight binary Straight binary CONVERSION RATE Conversion Time t + 15.5 t + 15.5 ns 2 2 × t × t SCLK SCLK 2 33 33 ns Full-scale step input Track-and-Hold Acquisition Time Throughput Rate 4.2 4.2 MSPS POWER REQUIREMENTS VDD 2.25 2.75 2.25 2.75 V Nominal VDD = 2.5 V 3 VDRIVE 2.25 3.6 2.25 3.6 V 4 ITOTAL Digital inputs = 0 V or VDRIVE Normal Mode (Operational) 14 20 14 20 mA Normal Mode (Static) 6 7.6 6 7.6 mA SCLK on or off Partial Power-Down Mode 3.5 4.5 3.5 4.5 mA SCLK on or off Full Power-Down Mode 5 40 5 40 μA SCLK on or off Power Dissipation Normal Mode (Operational) 36 59 36 59 mW Normal Mode (Static) 16 21 16 21 mW SCLK on or off Partial Power-Down Mode 9.5 11.5 9.5 11.5 mW SCLK on or off Full Power-Down Mode 16 110 16 110 μW SCLK on or off 1 Temperature ranges are as follows: AD7357Y: −40°C to +125°C, AD7357B: −40°C to +85°C, AD7357WY: −40°C to +125°C. 2 See the Terminology section. 3 The interface is functional with VDRIVE voltages down to 1.8 V. In this condition, the SCLK speed may need to be slowed down. See the access and hold times in the Timing Specifications section. 4 ITOTAL is the total current flowing in VDD and VDRIVE. Rev. B | Page 4 of 20 AD7357 TIMING SPECIFICATIONS 1 VDD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN , unless otherwise noted. Table 3. Parameter Limit at TMIN, TMAX Unit Description f 500 kHz min SCLK 80 MHz max tCONVERT t2 + 15.5 × tSCLK ns min tSCLK = 1/fSCLK tQUIET 5 ns min Minimum time between end of serial read and next falling edge of CS t 5 ns min CS to SCLK setup time 2 2 t 6 ns max Delay from CS until SDATA and SDATA are three-state disabled 3 A B 2, 3 t4 Data access time after SCLK falling edge 12.5 ns max 1.8 V ≤ VDRIVE < 2.25 V 11 ns max 2.25 V ≤ VDRIVE < 2.75 V 9.5 ns max 2.75 V ≤ V < 3.3 V DRIVE 9 ns max 3.3 V ≤ V ≤ 3.6 V DRIVE t 5 ns min SCLK low pulse width 5 t6 5 ns min SCLK high pulse width 2 t7 SCLK to data valid hold time 3.5 ns min 1.8 V ≤ VDRIVE < 2.75 V 3 ns min 2.75 V ≤ V ≤ 3.6 V DRIVE t 9.5 ns max CS rising edge to SDATA , SDATA , high impedance 8 A B t9 5 ns min CS rising edge to falling edge pulse width 2 t10 4.5 ns min SCLK falling edge to SDATAA, SDATAB, high impedance 9.5 ns max SCLK falling edge to SDATAA, SDATAB, high impedance Latency 1 conversion latency 1 Temperature ranges are as follows: AD7357Y: −40°C to +125°C, AD7357B: −40°C to +85°C, AD7357WY: −40°C to +125°C. 2 Specified with a load capacitance of 10 pF on SDATAA and SDATAB. 3 The time required for the output to cross 0.4 V or 2.4 V. Rev. B | Page 5 of 20 AD7357 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 4. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to AGND, DGND, REFGND −0.3 V to +3 V DD other conditions above those indicated in the operational VDRIVE to AGND, DGND, REFGND −0.3 V to +5 V section of this specification is not implied. Exposure to absolute VDD to VDRIVE −5 V to +3 V maximum rating conditions for extended periods may affect AGND to DGND to REFGND −0.3 V to +0.3 V device reliability. 1 Analog Input Voltages to AGND −0.3 V to VDD + 0.3 V 2 Digital Input Voltages to DGND −0.3 V to VDRIVE + 0.3V 3 Digital Output Voltages to DGND −0.3 V to V + 0.3 V ESD CAUTION DRIVE 4 Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range AD7357Y −40°C to +125°C AD7357B −40°C to +85°C AD7357WY −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package θ Thermal Impedance 143°C/W JA θ Thermal Impedance 45°C/W JC Lead Temperature, Soldering Reflow Temperature (10 sec to 30 sec) 255°C ESD 2 kV 1 Analog input voltages are VINA+, VINA−, VINB+, VINB−, REFA, and REFB. 2 CS Digital input voltages are and SCLK. 3 Digital output voltages are SDATAA and SDATAB. 4 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. B | Page 6 of 20 AD7357 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 16 V V INA+ DRIVE 2 15 V SCLK INA– 3 14 REF SDATA A A AD7357 4 TOP VIEW 13 REFGND SDATA B (Not to Scale) 5 12 AGND DGND 6 11 REF AGND B 7 10 V CS INB– 8 9 V V INB+ DD Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1, 2 V , V Analog Inputs of ADC A. These analog inputs form a fully differential pair. INA+ INA− 3, 6 REF , REF Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the A B REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each reference pin with a 10 μF capacitor. Provided that the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048 V and appears at these pins. These pins can also be overdriven by an external reference. The input voltage range for the external reference is 2.048 V + 100 mV to V . DD 4 REFGND Reference Ground. This is the ground reference point for the reference circuitry on the AD7357. Any external reference signal should be referred to this REFGND voltage. Decoupling capacitors must be placed between this pin and the REFA and REFB pins. 5, 11 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7357. All analog input signals should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 7, 8 V , V Analog Inputs of ADC B. These analog inputs form a fully differential pair. INB− INB+ 9 VDD Power Supply Input. The VDD range for the AD7357 is 2.5 V ± 10%. The supply should be decoupled to AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor. 10 CS Chip Select. Active low, logic input. This input provides the dual function of initiating conversions on the AD7357 and framing the serial data transfer. 12 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7357. This pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 13, 14 SDATAB, SDATAA Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. 16 SCLK falling edges are required to access the 14 bits of data from the AD7357. The data simultaneously appears on both data output pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros, followed by the 14 bits of conversion data. The data is provided MSB first. If CS is held low for 18 SCLK cycles rather than 16, then two trailing zeros appear after the 14 bits of data. If CS is held low for an additional 18 SCLK cycles on either SDATAA or SDATAB , the data from the other ADC follows on the SDATA pins. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either SDATA or SDATA . A B 15 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7357. This clock is also used as the clock source for the conversion process. 16 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VDD. Rev. B | Page 7 of 20 07757-002 AD7357 TYPICAL PERFORMANCE CHARACTERISTICS 0 20,000 16,384 POINT FFT f = 4.2MSPS SAMPLE –20 f = 1MHz IN SINAD = 76.8dB THD = –84.5dB –40 15,000 –60 10,000 –80 –100 5000 –120 32 HITS –140 0 250 500 750 1000 1250 1500 1750 2000 0 8188 8189 8190 8191 8192 8193 8194 8195 FREQUENCY (kHz) CODE Figure 3. Typical FFT Figure 6. Histogram of Codes 1.0 79 0.8 77 0.6 0.4 75 0.2 73 0 71 –0.2 –0.4 69 –0.6 67 –0.8 –1.0 65 0 4000 8000 12,000 16,000 0 1 2 345 CODE ANALOG INPUT FREQUENCY (MHz) Figure 4. Typical DNL Figure 7. SNR vs. Analog Input Frequency 1.5 –60 1.0 –65 0.5 –70 0 –75 –0.5 –80 –1.0 –1.5 –85 0 4000 8000 12,000 16,000 0 5 10 15 20 25 CODE SUPPLY RIPPLE FREQUENCY (MHz) Figure 5. Typical INL Figure 8. PSRR vs. Supply Ripple with No Supply Decoupling Rev. B | Page 8 of 20 dB INL ERROR (LSB) DNL ERROR (LSB) 07757-003 07757-005 07757-004 NUMBER OF OCCURRENCES PSSR (dB) SNR (dB) 07757-007 07757-008 07757-006 AD7357 2.0482 10 2.0480 +125°C 2.0478 9 +85°C 2.0476 +25°C –40°C 2.0474 8 2.0472 2.0470 7 2.0468 2.0466 6 2.0464 2.0462 5 2.0460 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0 500 1000 1500 2000 2500 3000 V (V) CURRENT LOAD (µA) DRIVE Figure 9. VREF vs. Reference Output Current Drive Figure 12. Access Time vs. VDRIVE 2.0 8 1.5 INL MAX +125°C +85°C 7 +25°C 1.0 –40°C 0.5 DNL MAX 6 0 DNL MIN –0.5 5 –1.0 INL MIN 4 –1.5 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0 1020304050607080 V (V) DRIVE SCLK FREQUENCY (MHz) Figure 10. Linearity Error vs. SCLK Frequency Figure 13. Hold Time vs. VDRIVE 1.5 INL MAX 1.0 0.5 DNL MAX 0 DNL MIN –0.5 INL MIN –1.0 –1.5 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 EXTERNAL V (V) REF Figure 11. Linearity Error vs. External VREF Rev. B | Page 9 of 20 V (V) REF ERROR (LSB) ERROR (LSB) 07757-011 07757-010 07757-009 HOLD TIME (ns) ACCESS TIME (ns) 07757-113 07757-012 AD7357 TERMINOLOGY Common-Mode Rejection Ratio (CMRR) Integral Nonlinearity (INL) CMRR is defined as the ratio of the power in the ADC output INL is the maximum deviation from a straight line passing at full-scale frequency, f, to the power of a 100 mV p-p sine through the endpoints of the ADC transfer function. The wave applied to the common-mode voltage of VIN+ and VIN− endpoints of the transfer function are zero scale (1 LSB below of frequency, f , as follows: S the first code transition) and full scale (1 LSB above the last code transition). CMRR (dB) = 10log (Pf/Pf ) S Differential Nonlinearity (DNL) where: DNL is the difference between the measured and the ideal Pf is the power at frequency, f, in the ADC output. 1 LSB change between any two adjacent codes in the ADC. PfS is the power at frequency, fS, in the ADC output. Negative Full-Scale Error Track-and-Hold Acquisition Time Negative full-scale error is the deviation of the first code transi- The track-and-hold amplifier returns to track mode at the end tion (00 … 000) to (00 … 001) from the ideal (that is, −VREF + of a conversion. The track-and-hold acquisition time is the time 0.5 LSB) after the midscale error has been adjusted out. required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of conversion. Negative Full-Scale Error Match Negative full-scale error match is the difference in negative full- Signal-to-(Noise + Distortion) Ratio (SINAD) scale error between the two ADCs. SINAD is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the Midscale Error fundamental. Noise is the sum of all nonfundamental signals up Midscale error is the deviation of the midscale code transition to half the sampling frequency (fS/2), excluding dc. The ratio is (011 … 111) to (100 … 000) from the ideal (that is, 0 V). dependent on the number of quantization levels in the digitiza- Midscale Error Match tion process; the more levels, the smaller the quantization noise. Midscale error match is the difference in midscale error The theoretical SINAD for an ideal N-bit converter with a sine between the two ADCs. wave input is given by Positive Full-Scale Error SINAD = (6.02 N + 1.76) dB Positive full-scale error is the deviation of the last code transi- tion (111 … 110) to (111 … 111) from the ideal (that is, VREF − Thus, for a 12-bit converter, SINAD is 74 dB and for a 14-bit 1.5 LSB) after the midscale error has been adjusted out. converter, SINAD is 86 dB. Positive Full-Scale Error Match Total Harmonic Distortion (THD) Positive full-scale error match is the difference in positive full- THD is the ratio of the rms sum of harmonics to the funda- scale error between the two ADCs. mental. For the AD7357, it is defined as ADC-to-ADC Isolation 2 2 2 2 2 V + V + V + V + V 2 3 4 5 6 ADC-to-ADC isolation is a measure of the level of crosstalk THD() dB=−20 log V 1 between ADC A and ADC B. It is measured by applying a full- scale 1 MHz sine wave signal to one of the two ADCs and where: applying a full-scale signal of variable frequency to the other V1 is the rms amplitude of the fundamental. ADC. The ADC-to-ADC isolation is defined as the ratio of the V2, V3, V4, V5, and V6 are the rms amplitudes of the second power of the 1 MHz signal on the converted ADC to the power through the sixth harmonics. of the noise signal on the other ADC that appears in the FFT. Peak Harmonic or Spurious Noise The noise frequency on the unselected channel varies from Peak harmonic or spurious noise is defined as the ratio of the 100 kHz to 2.5 MHz. rms value of the next largest component in the ADC output Power Supply Rejection Ratio (PSRR) spectrum (up to fS/2 and excluding dc) to the rms value of PSRR is defined as the ratio of the power in the ADC output at the fundamental. Normally, the value of this specification is full-scale frequency, f, to the power of a 100 mV p-p sine wave determined by the largest harmonic in the spectrum, but for applied to the ADC V supply of the frequency, f . The frequency ADCs where the harmonics are buried in the noise floor, it DD S of the input varies from 5 kHz to 25 MHz. is a noise peak. PSRR (dB) = 10 log(Pf/Pf ) S where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Rev. B | Page 10 of 20 AD7357 Intermodulation Distortion (IMD) Thermal Hysteresis With inputs consisting of sine waves at two frequencies, fa Thermal hysteresis is defined as the absolute maximum change and fb, any active device with nonlinearities creates distortion of the reference output voltage after the device is cycled through temperature from either products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms T_HYS+ = 25°C to TMAX to 25°C are those for which neither m nor n are equal to zero. For T_HYS– = 25°C to TMIN to 25°C example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + It is expressed in ppm using the following equation: 2fb), and (fa − 2fb). V (25°C)−V (T _ HYS) REF REF 6 V (ppm)= × 10 The AD7357 is tested using the CCIF standard where two input HYS V (25°C) REF frequencies near the top end of the input bandwidth are used. where: In this case, the second-order terms are usually distanced in V (25°C) is V at 25°C. frequency from the original sine waves, while the third-order REF REF V (T_HYS) is the maximum change of V at T_HYS+ or terms are usually at a frequency close to the input frequencies. REF REF As a result, the second- and third-order terms are specified T_HYS–. separately. The calculation of the intermodulation distortion is as per the THD specification (see Table 2), where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (dB). Rev. B | Page 11 of 20 AD7357 THEORY OF OPERATION back into a balanced condition. When the comparator is CIRCUIT INFORMATION rebalanced, the conversion is complete. The control logic The AD7357 is a high speed, dual, 14-bit, single-supply, successive generates the ADC output code. The output impedances of approximation analog-to-digital converter. The part operates the sources driving the VIN+ and VIN− pins must be matched; from a 2.5 V power supply and features throughput rates up to otherwise, the two inputs have different settling times, resulting 4.2 MSPS. in errors. The AD7357 contains two on-chip differential track-and-hold amplifiers, two successive approximation analog-to-digital CAPACITIVE DAC converters, and a serial interface with two separate data output COMPARATOR C B S pins. The part is housed in a 16-lead TSSOP package, offering V IN+ A the user considerable space-saving advantages over alternative SW1 CONTROL SW3 C LOGIC solutions. S SW2 A V IN– The serial clock input accesses data from the part, but also B provides the clock source for each successive approximation V REF CAPACITIVE ADC. The AD7357 has an on-chip 2.048 V reference. If an DAC external reference is desired the internal reference can be Figure 15. ADC Conversion Phase overdriven with a reference value ranging from (2.048 V + ANALOG INPUT STRUCTURE 100 mV) to V . If the internal reference is to be used else- DD where in the system, the reference output needs to be buffered Figure 16 shows the equivalent circuit of the analog input struc- first. The differential analog input range for the AD7357 is V CM ture of the AD7357. The four diodes provide ESD protection for ± V /2. REF the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. The AD7357 features power-down options to allow power Exceeding the limit causes these diodes to become forward- saving between conversions. The power-down feature is biased and start conducting into the substrate. These diodes implemented via the standard serial interface, as described can conduct up to 10 mA without causing irreversible damage in the Modes of Operation section. to the part. CONVERTER OPERATION The C1 capacitors in Figure 16 are typically 8 pF and can The AD7357 has two successive approximation ADCs, each primarily be attributed to pin capacitance. The R1 resistors based around two capacitive DACs. Figure 14 and Figure 15 are lumped components made up of the on resistance of the show simplified schematics of one of these ADCs in acquisition switches. The value of these resistors is typically about 30 Ω. and conversion phases, respectively. The ADC comprises The C2 capacitors are the ADC’s sampling capacitors with a control logic, a SAR, and two capacitive DACs. In Figure 14 capacitance of 32 pF typically. (the acquisition phase), SW3 is closed, SW1 and SW2 are in V DD Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays may acquire the differential D C2 R1 signal on the input. V IN+ C1 D CAPACITIVE DAC COMPARATOR C V B S DD V IN+ A SW1 CONTROL D SW3 C2 C LOGIC R1 S SW2 A V IN– V IN– C1 D B V REF CAPACITIVE DAC Figure 16. Equivalent Analog Input Circuit, Figure 14. ADC Acquisition Phase Conversion Phase—Switches Open, Track Phase—Switches Closed When the ADC starts a conversion (see Figure 15), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected when the conversion begins. The control logic and charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator Rev. B | Page 12 of 20 07757-013 07757-015 07757-014 AD7357 ANALOG INPUTS For ac applications, it is recommended to remove high frequency components from the analog input signal by the use of an RC Differential signals have some benefits over single-ended low-pass filter on the analog input pins. In applications where signals, including noise immunity based on the device’s harmonic distortion and signal-to-noise ratio are critical, the common-mode rejection and improvements in distortion analog input should be driven from a low impedance source. Large performance. Figure 19 defines the fully differential input source impedances significantly affect the ac performance of the of the AD7357. ADC and may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular V p-p V REF IN+ application. AD7357* COMMON MODE When no amplifier is used to drive the analog input, the source VOLTAGE V p-p V REF IN– impedance should be limited to low values. The maximum source impedance depends on the amount of THD that can be tole- * ADDITIONAL PINS OMITTED FOR CLARITY. rated. The THD increases as the source impedance increases Figure 19. Differential Input Definition and performance degrades. Figure 17 shows a graph of the The amplitude of the differential signal is the difference THD vs. the analog input signal frequency for various source between the signals applied to the VIN+ and VIN− pins in impedances. each differential pair (VIN+ − VIN−). VIN+ and VIN− should be –65 simultaneously driven by two signals each of amplitude VREF –67 that are 180° out of phase. This amplitude of the differential –69 10Ω 33Ω signal is, therefore, –V to +V peak-to-peak regardless of REF REF –71 50Ω the common mode (CM). 100Ω –73 CM is the average of the two signals and is, therefore, the –75 voltage on which the two inputs are centered. –77 –79 CM = (VIN+ + VIN−)/2 –81 This results in the span of each input being CM ± VREF/2. This –83 voltage has to be set up externally. When setting up the CM, –85 ensure that that V and V remain within GND/V . When IN+ IN− DD –87 a conversion takes place, CM is rejected, resulting in a virtually –89 100 200 1000 1500 2000 2500 noise free signal of amplitude –V to +V corresponding to REF REF FREQUENCY (kHz) the digital codes of 0 to 16,383. Figure 17. THD vs. Analog Input Frequency for Various Source Impedances DRIVING DIFFERENTIAL INPUTS Figure 18 shows a graph of the THD vs. the analog input Differential operation requires V and V to be driven simulta- IN+ IN− frequency while sampling at 4.2 MSPS. In this case, the neously with two equal signals that are 180° out of phase. Because source impedance is 33 Ω. not all applications have a signal preconditioned for differential –66.0 operation, there is often a need to perform a single-ended-to- differential conversion. –70.0 Differential Amplifier –74.0 An ideal method of applying differential drive to the AD7357 is to use a differential amplifier such as the AD8138. This part –78.0 can be used as a single-ended-to-differential amplifier or as a differential-to-differential amplifier. The AD8138 also provides –82.0 common-mode level shifting. Figure 20 shows how the AD8138 can be used as a single-ended-to-differential amplifier. The –86.0 positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC via a pair of series resistors –90.0 0 1000 2000 3000 4000 5000 to minimize the effects of switched capacitance on the front ANALOG INPUT FREQUENCY (kHz) end of the ADC. The architecture of the AD8138 results in Figure 18. THD vs. Analog Input Frequency outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. Rev. B | Page 13 of 20 THD (dB) THD (dB) 07757–118 07757-017 07757-034 AD7357 2.048V If the analog inputs source being used has zero impedance, all 2 × V p-p 220Ω REF 1.024V four resistors (R 1, R 2, R 1, and R 2) should be the same. If G G F F 440Ω V+ 0V GND 27Ω the source has a 50 Ω impedance and a 50 Ω termination, for V IN+ V– example, the value of RG2 should be increased by 25 Ω to 220Ω 2.048V balance this parallel impedance on the input and thus ensure AD7357* 220Ω 1.024V 220Ω that both the positive and negative analog inputs have the 0V V+ 27Ω same gain. The outputs of the amplifier are perfectly matched REF /REF V A B IN– balanced differential outputs of identical amplitude and are A V– 20kΩ exactly 180° out of phase. 10µF 10kΩ C 1 F 2.048V 1.024V R 1 F 0V *ADDITIONAL PINS OMITTED FOR CLARITY. R * S Figure 22. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal into R 1 G V IN+ a Differential Unipolar Signal V OCM +2.048V AD8138 AD7357 51Ω R 2 GND G R * S VOLTAGE REFERENCE V REF /REF –2.048V IN– A B 2.048V R 2 F The AD7357 allows the choice of a very low temperature drift 1.024V C 2 internal voltage reference or an external reference. The internal 0V F 2.048 V reference of the AD7357 provides excellent perfor- 10kΩ 10µF mance and can be used in almost all applications. When the 10kΩ internal reference is used, the reference voltage is present on the REFA and REFB pins. These pins should be decoupled to *MOUNT AS CLOSE TO THE AD7357 AS POSSIBLE REFGND with 10 μF capacitors. The internal reference voltage AND ENSURE THAT HIGH PRECISION R RESISTORS ARE USED. S R – 33Ω; R 1 = R 1 = R 2 = 499Ω; C 1 = C 2 = 39pF; S G F F F F can be used elsewhere in the system, provided it is buffered R 2 = 523Ω G externally. Figure 20. Using the AD8138 as a Single-Ended-to-Differential Amplifier The REFA and REFB pins can also be overdriven with an Op Amp Pair external voltage reference if desired. The applied reference An op amp pair can be used to directly couple a differential signal voltage can range from 2.048 V + 100 mV to VDD. A common to one of the analog input pairs of the AD7357. The circuit choice would be to use an external 2.5 V reference such as the configurations shown in Figure 21 and Figure 22 show how ADR441 or ADR431. an op amp pair can be used to convert a single-ended signal ADC TRANSFER FUNCTION into a differential signal for a bipolar and unipolar input The output coding for the AD7357 is straight binary. The signal, respectively. The voltage applied to Point A sets up designed code transitions occur at successive LSB values (such the common-mode voltage. In both diagrams, Point A is as, 1 LSB, 2 LSBs). The LSB size is (2 × V )/16,384. The ideal connected in some way to the reference. The AD8022 is a REF transfer characteristic of the AD7357 is shown in Figure 23. suitable dual op amp that can be used in this configuration to provide differential drive to the AD7357. 2.048V V p-p 220Ω REF 1.024V 111 ... 111 V 220Ω V+ REF 0V 111 ... 110 2 27Ω V 111 ... 101 IN+ GND V– 220Ω 2.048V AD7357* 220Ω 1.024V 0V V+ 27Ω REF /REF V A B IN– A V– 10kΩ 000 ... 010 10µF 000 ... 001 10kΩ 000 ... 000 –V + 1 LSB +V – 1 LSB REF REF –V + 0.5 LSB +V – 1.5 LSB REF REF *ADDITIONAL PINS OMITTED FOR CLARITY. ANALOG INPUT Figure 21. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal Figure 23. Deal Transfer Characteristic into a Differential Signal Rev. B | Page 14 of 20 07757-131 07757-132 ADC CODE 07757-023 07757-133 AD7357 MODES OF OPERATION The AD7357 mode of operation is selected by controlling the When a data transfer is complete and SDATAA and SDATAB logic state of the CS signal during a conversion. There are three have returned to three-state, another conversion can be initiated after the quiet time, t , has elapsed by bringing CS low again possible modes of operation: normal mode, partial power-down QUIET mode, and full power-down mode. After a conversion has been (assuming the required acquisition time has been allowed). CS initiated, the point at which is pulled high determines which PARTIAL POWER-DOWN MODE power-down mode, if any, the device enters. Similarly, if already This mode is intended for use in applications where slower CS in a power-down mode, can control whether the device throughput rates are required. Either the ADC is powered returns to normal operation or remains in a power-down mode. down between each conversion, or a series of conversions These modes of operation are designed to provide flexible power can be performed at a high throughput rate and the ADC is management options. These options can be chosen to optimize then powered down for a relatively long duration between the power dissipation/throughput rate ratio for the differing these bursts of several conversions. When the AD7357 is in application requirements. partial power-down, all analog circuitry is powered down NORMAL MODE except for the on-chip reference and reference buffers. Normal mode is intended for applications needing the fastest To enter partial power-down mode, the conversion process throughput rates. The user does not have to worry about any must be interrupted by bringing CS high anywhere after the power-up times because the AD7357 remains fully powered at th second falling edge of SCLK and before the 10 falling edge of all times. Figure 24 shows the general diagram of the operation CS SCLK, as shown in Figure 25. When is brought high in this of the AD7357 in this mode. window of SCLKs, the part enters partial power-down mode, CS the conversion that was initiated by the falling edge of is CS terminated, and SDATAA and SDATAB go back into three-state. If 1 1014 CS is brought high before the second SCLK falling edge, the SCLK part remains in normal mode and does not power down. This SDATA avoids accidental power-down due to glitches on the CS line. A LEADING ZEROS + CONVERSION RESULT SDATA B Figure 24. Normal Mode Operation CS The conversion is initiated on the falling edge of CS, as described 11 2 104 SCLK in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least SDATA THREE-STATE A CS 10 SCLK falling edges have elapsed after the falling edge of . SDATA B th CS If is brought high any time after the 10 SCLK falling edge Figure 25. Entering Partial Power-Down Mode th but before the 16 SCLK falling edge, the part remains powered To exit this mode of operation and to power up the AD7357 up, but the conversion is terminated and SDATA and SDATA A B again, perform a dummy conversion. On the falling of CS, the go back into three-state. 16 serial clock cycles are required to device begins to power up and continues to power up as long complete the conversion and access the conversion result for th CS as is held low until after the falling edge of the 10 SCLK. the AD7357. The SDATA lines do not return to three-state The device is fully powered up after approximately 200 ns after 16 SCLK cycles have elapsed, but instead do so when CS elapses (or one full conversion), and valid data results from the CS is brought high again. If is left low for another 2 SCLK next conversion, as shown in Figure 26. If CS is brought high CS cycles, two trailing zeros are clocked out after the data. If before the second falling edge of SCLK, the AD7357 again goes is left low for a further 16 SCLK cycles, the result for the other into partial power-down mode. This avoids accidental power- ADC on board is also accessed on the same SDATA line as up due to glitches on the CS line. Although the device may shown in Figure 31 (see the Serial Interface section). CS begin to power up on the falling edge of , it powers down When 32 SCLK cycles have elapsed, the SDATA line returns to CS again on the rising edge of . If the AD7357 is already in nd three-state on the 32 SCLK falling edge. If CS is brought high CS partial power-down mode and is brought high between prior to this, the SDATA line returns to three-state at that point. th the second and 10 falling edges of SCLK, the device enters CS Thus, may idle low after 32 SCLK cycles until it is brought full power-down mode. high again sometime prior to the next conversion, if so desired, because the bus still returns to three-state upon completion of the dual result read. Rev. B | Page 15 of 20 07757-018 07757-019 AD7357 To reach full power-down, the next conversion cycle must be FULL POWER-DOWN MODE CS interrupted in the same way, as shown in Figure 27. When This mode is intended for use in applications where throughput has been brought high in this window of SCLKs, the part rates slower than those in the partial power-down mode are completely powers down. required, as power-up from a full power-down takes substantially longer than that from a partial power-down. This mode is more Note that it is not necessary to complete the 16 SCLKs once CS suited to applications where a series of conversions performed has been brought high to enter a power-down mode. at a relatively high throughput rate are followed by a long period To exit full power-down mode and power up the AD7357, perform of inactivity and, thus, power-down. When the AD7357 is in a dummy conversion, such as powering up from partial power- full power-down, all analog circuitry is powered down. Full CS down. On the falling edge of , the device begins to power up, power-down is entered in a way that is similar to partial power- th CS as long as is held low until after the falling edge of the 10 down, except that the timing sequence shown in Figure 25 must SCLK. The required power-up time must elapse before a con- be executed twice. The conversion process must be interrupted version can be initiated, as shown in Figure 28. CS in a similar fashion by bringing high anywhere after the th second falling edge of SCLK and before the 10 falling edge of SCLK. The device enters partial power-down mode at this point. THE PART IS FULLY THE PART BEGINS POWERED UP; SEE THE TO POWER UP. POWER-UP TIMES t POWER-UP1 SECTION. CS 11014 1 14 SCLK SDATA A INVALID DATA VALID DATA SDATA B Figure 26. Exiting Partial Power-Down Mode THE PART ENTERS THE PART BEGINS THE PART ENTERS PARTIAL POWER DOWN. TO POWER UP. FULL POWER DOWN. CS 11 2 014 11 2 014 SCLK SDATA THREE-STATE THREE-STATE A INVALID DATA INVALID DATA SDATA B Figure 27. Entering Full Power-Down Mode THE PART IS FULLY POWERED UP, SEE POWER-UP TIMES SECTION. THE PART BEGINS TO POWER UP. t POWER-UP2 CS 14 14 10 1 1 SCLK SDATA A INVALID DATA VALID DATA SDATA B Figure 28. Exiting Full Power-Down Mode Rev. B | Page 16 of 20 07757-022 07757-021 07757-020 AD7357 Alternatively, if the part is to be placed into full power-down POWER-UP TIMES mode when the supplies are applied, three dummy cycles must The AD7357 has two power-down modes: partial power- be initiated. The first dummy cycle must hold low until after CS down and full power-down. There are described in detail in th the 10 SCLK falling edge; the second and third dummy cycles the Partial Power-Down Mode and Full Power-Down Mode place the part into full power-down mode (see Figure 27 and sections. This section deals with the power-up time required the Modes of Operation section). when coming out of either of these modes. It should be noted that the power-up times apply with the recommended decoupling POWER vs. THROUGHPUT RATE capacitors in place on the REF and REF pins. A B The power consumption of the AD7357 varies with the To power up from partial power-down mode, one dummy cycle throughput rate. When using very slow throughput rates is required. The device is fully powered up after approximately and as fast an SCLK frequency as possible, the various power- 200 ns from the falling edge of CS has elapsed. Once the partial down options can be used to make significant power savings. power-up time has elapsed, the ADC is fully powered up and However, the AD7357 quiescent current is low enough that the input signal is acquired properly. The quiet time, t , must QUIET even without using the power-down options, there is a noticeable still be allowed from the point where the bus goes back into three- variation in power consumption with sampling rate. This is true state after the dummy conversion to the next falling edge of . CS whether a fixed SCLK value is used or if it is scaled with the sam- pling rate. Figure 29 shows a plot of power vs. throughput rate To power up from full power-down, approximately 6 ms should when operating in normal mode for a fixed maximum SCLK be allowed from the falling edge of CS, shown in Figure 28 as frequency and an SCLK frequency that scales with the sampling tPOWER-UP2. rate. The internal reference was used for Figure 29. Note that during power-up from partial power-down mode, the 38 track-and-hold, which is in hold mode while the part is powered down, returns to track mode after the first SCLK edge that the 34 part receives after the falling edge of CS. 30 When power supplies are first applied to the AD7357, the ADC can power up in either of the power-down modes or in normal 26 80MHz SCLK mode. Because of this, it is best to allow a dummy cycle to elapse VARIABLE SCLK 22 to ensure that the part is fully powered up before attempting a valid conversion. Likewise, if the part is to be kept in partial 18 power-down mode immediately after the supplies are applied, then two dummy cycles must be initiated. The first dummy 14 th cycle must hold CS low until after the 10 SCLK falling edge; 10 in the second cycle, CS must be brought high between the 0 1000 2000 3000 4000 th second and 10 SCLK falling edges (see Figure 25). THROUGHPUT (kSPS) Figure 29. Power vs. Throughput Rate Rev. B | Page 17 of 20 TOTAL POWER (mW) 07757-129 AD7357 SERIAL INTERFACE Likewise, if CS is held low for an additional 16 SCLK cycles on Figure 30 shows the detailed timing diagram for serial inter- SDATAA, the data from the conversion on ADC A is output facing to the AD7357. The serial clock provides the conversion on SDATAB (see Figure 31). In this case, the SDATA line in use clock and controls the transfer of information from the AD7357 nd goes back into three-state on the 32 SCLK falling edge or the during conversion. There is a single sample delay in the result CS rising edge of , whichever occurs first. that is clocked out from the AD7357. A minimum of 16 serial clock cycles are required to perform CS The signal initiates the data transfer and conversion process. the conversion process and to access data from one conversion CS The falling edge of puts the track-and-hold into hold mode on either data line of the AD7357. Note that the data that is at which point the analog input is sampled and the bus is taken accessed on SDATAA and SDATAB is the result of the previous out of three-state. The conversion is also initiated at this point conversion. CS going low provides the leading zero to be read and requires a minimum of 16 SCLKs to complete. When 16 in by the microcontroller or DSP. The remaining data is then SCLK falling edges have elapsed, the track-and-hold goes back clocked out by subsequent SCLK falling edges, beginning with into track on the next SCLK rising edge, as shown in Figure 30 a second leading zero. Thus, the first falling clock edge on the CS at Point B. On the rising edge of , the conversion is terminated serial clock has the leading zero provided and also clocks out CS and SDATAA and SDATAB go back into three-state. If is not the second leading zero. The 14-bit result then follows with the brought high but is, instead, held low for an additional 16 SCLK th final bit in the data transfer valid on the 16 falling edge, having cycles on SDATAA, the data from the conversion on ADC B th been clocked out on the previous (15 ) falling edge. In applica- is output on SDATAA. tions with a slower SCLK, it may be possible to read in data on each SCLK rising edge depending on the SCLK frequency. The CS first rising edge of SCLK after the falling edge has the second th leading zero provided, and the 15 rising SCLK edge has DB0 provided. t ACQUISITION CS t t 9 CONVERT t t 2 6 B SCLK 34 5 1 2 15 16 t 5 t t 8 7 t t 3 4 t QUIET SDATA A 0 0 DB13 DB12 DB11 DB10 DB2 DB1 DB0 0 SDATA B THREE- THREE-STATE STATE 2 LEADING ZEROS Figure 30. Serial Interface Timing Diagram CS t t 6 2 SCLK 34 5 1 2 15 16 17 18 31 32 t 5 t t t 3 4 7 0 0 DB13 DB12 DB11 DB0 0 0 DB13 DB12 DB1 DB0 SDATA A A A A B B B B A THREE- THREE- STATE STATE 2 LEADING 2 ZEROS ZEROS Figure 31. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs Rev. B | Page 18 of 20 07757-024 07757-025 AD7357 APPLICATION HINTS Good decoupling is important; all supplies should be decoupled GROUNDING AND LAYOUT with 10 μF tantalum capacitors in parallel with 0.1 μF capacitors The analog and digital supplies to the AD7357 are independent to GND. To achieve the best results from these decoupling compo- and separately pinned out to minimize coupling between the nents, they must be placed as close as possible to the device, analog and digital sections of the device. The printed circuit ideally right up against the device. The 0.1 μF capacitor should board (PCB) that houses the AD7357 should be designed so have low effective series resistance (ESR) and effective series that the analog and digital sections are separated and confined inductance (ESI), such as the common ceramic types or surface- to certain areas of the board. This design facilitates the use of mount types. These low ESR and ESI capacitors provide a ground planes that can be easily separated. low impedance path to ground at high frequencies to handle To provide optimum shielding for ground planes, a minimum transient currents due to logic switching. etch technique is generally best. The two AGND pins of the EVALUATING THE AD7357 PERFORMANCE AD7357 should be sunk in the AGND plane. Digital and analog The recommended layout for the AD7357 is outlined in eval- ground plans should be joined in only one place. If the AD7357 uation board documentation. The evaluation board package is in a system where multiple devices require an AGND and includes a fully assembled and tested evaluation board, docu- DGND connection, the connection should still be made at one mentation, and software for controlling the board from the PC point only. A star ground point should be established as close as via the converter evaluation and development board (CED). possible to the ground pins on the AD7357. The CED can be used in conjunction with the AD7357 evalua- Avoid running digital lines under the device because this couples tion board (as well as many other evaluation boards ending in noise onto the die. The analog ground planes should be allowed the ED designator from Analog Devices, Inc.) to demonstrate/ to run under the AD7357 to avoid noise coupling. The power evaluate the ac and dc performance of the AD7357. supply lines to the AD7357 should use as large a trace as poss- The software allows the user to perform ac (fast Fourier transform) ible to provide low impedance paths and reduce the effects of and dc (linearity) tests on the AD7357. The software and docu- glitches on the power supply line. mentation are on a CD that is shipped with the evaluation board. To avoid radiating noise to other sections of the board, fast switching signals such as clocks should be shielded with digital ground, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces on opposite sides of the board should run at right angles to each other. A microstrip technique is the best method, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Rev. B | Page 19 of 20 AD7357 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 32. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE 1, 2, 3, 4 Model Temperature Range Package Description Package Option AD7357BRUZ −40°C to +85°C 16-Lead TSSOP RU-16 AD7357BRUZ-500RL7 −40°C to +85°C 16-Lead TSSOP RU-16 AD7357BRUZ-RL −40°C to +85°C 16-Lead TSSOP RU-16 AD7357YRUZ −40°C to +125°C 16-Lead TSSOP RU-16 AD7357YRUZ-500RL7 −40°C to +125°C 16-Lead TSSOP RU-16 AD7357YRUZ-RL −40°C to +125°C 16-Lead TSSOP RU-16 AD7357WYRUZ −40°C to +125°C 16-Lead TSSOP RU-16 AD7357WYRUZ-RL −40°C to +125°C 16-Lead TSSOP RU-16 EVAL-AD7357EDZ Evaluation Board EVAL-CED1Z Converter Evaluation and Development Board 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications 3 The EVAL-AD7357EDZ can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z board for evaluation/demonstration purposes. 4 The EVAL-CED1Z is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the ED designator. AUTOMOTIVE PRODUCTS The AD7357W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07757-0-8/11(B) Rev. B | Page 20 of 20