ANALOG DEVICES AD7298

8-Channel, 1 MSPS, 12-Bit SAR ADC with Temperature Sensor AD7298 FEATURES FUNCTIONAL BLOCK DIAGRAM V DD GND 12-bit SAR ADC 8 single-ended inputs V Channel sequencer functionality REF Fast throughput of 1 MSPS REF BUF Analog input range: 0 V to 2.5 V 12-bit temperature-to-digital converter 12-BIT V IN0 SUCCESSIVE T/H Temperature sensor accuracy of ±1°C APPROXIMATION ADC Temperature range: −40°C to +125°C INPUT Specified for V : 2.8 V to 3.6 V DD AD7298 V MUX IN7 Logic voltage VDRIVE : 1.65 V to 3.6 V Power-down current: <10 μA SEQUENCER SCLK Internal 2.5 V reference DOUT CONTROL DIN Internal power-on reset LOGIC TEMP CS SENSOR High speed serial interface SPI V DRIVE 20-lead LFCSP T _BUSY PD/RST SENSE Figure 1. PRODUCT HIGHLIGHTS GENERAL DESCRIPTION 1. Ideally Suited to Monitoring System Variables in a Variety The AD7298 is a 12-bit, high speed, low power, 8-channel, of Systems. This includes telecommunications, and process successive approximation ADC with an internal temperature and industrial control. sensor. The part operates from a single 3.3 V power supply and features throughput rates up to 1 MSPS. The device contains a 2. High Throughput Rate of 1 MSPS with Low Power low noise, wide bandwidth track-and-hold amplifier that can Consumption. handle input frequencies in excess of 30 MHz. 3. Eight Single-Ended Inputs with a Channel Sequencer. The AD7298 offers a programmable sequencer, which enables A consecutive sequence of channels can be selected on the selection of a preprogrammable sequence of channels for which the ADC cycles and converts. conversion. The device has an on-chip, 2.5 V reference that can 4. Integrated Temperature Sensor with 0.25°C Resolution. be disabled to allow the use of an external reference. The AD7298 includes a high accuracy band gap temperature sensor, which is monitored and digitized by the 12-bit ADC to give a resolution of 0.25°C. The device offers a 4-wire serial interface compatible with SPI and DSP interface standards. The AD7298 uses advanced design techniques to achieve very low power dissipation at high throughput rates. The part also offers flexible power/throughput rate management options. The part is offered in a 20-lead LFCSP package. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Trademarks and registered trademarks are the property of their respective owners. 08754-001 AD7298 TABLE OF CONTENTS Features .............................................................................................. 1 Temperature Sensor Averaging ................................................ 14 General Description ......................................................................... 1 VDRIVE............................................................................................ 15 Functional Block Diagram .............................................................. 1 The Internal or External Reference.......................................... 15 Product Highlights ........................................................................... 1 Control Register.............................................................................. 16 Revision History ............................................................................... 2 Modes of Operation ....................................................................... 17 Specifications..................................................................................... 3 Traditional Multichannel Mode of Operation........................ 17 Timing Specifications .................................................................. 5 Repeat Operation ....................................................................... 18 Absolute Maximum Ratings............................................................ 6 Power-Down Modes .................................................................. 19 ESD Caution.................................................................................. 6 Powering Up the AD7298 ......................................................... 20 Thermal Resistance ...................................................................... 6 Reset ............................................................................................. 20 Pin Configuration and Function Description .............................. 7 Serial Interface ................................................................................ 21 Typical Performance Characteristics ............................................. 9 Temperature Sensor Read ......................................................... 22 Terminology .................................................................................... 12 Layout and Configuration............................................................. 23 Circuit Information........................................................................ 13 Power Supply Bypassing and Grounding................................ 23 Converter Operation.................................................................. 13 Temperature Monitoring........................................................... 23 Analog Input ............................................................................... 13 Outline Dimensions....................................................................... 24 Temperature Sensor Operation ................................................ 14 Ordering Guide .......................................................................... 24 REVISION HISTORY 6/11—Rev. A to Rev. B Changes to Internal Temperature Sensor, Accuracy Parameter in Table 1............................................................................................ 3 1/11—Rev. 0 to Rev. A Removed Input Impedance Parameter .......................................... 3 Added Input Capacitance Parameter of 8 pF................................ 3 Changes to Figure 11...................................................................... 10 Changed C1 Value to 8 pF in Analog Input Section.................. 13 Changes to Figure 23...................................................................... 14 Changes to Ordering Guide .......................................................... 24 9/10—Revision 0: Initial Version Rev. B | Page 2 of 24 AD7298 SPECIFICATIONS VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; fSAMPLE = 1 MSPS, fSCLK = 20 MHz, VREF = 2.5 V internal; TA = −40°C to +125°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave IN 1, 2 Signal-to-Noise Ratio (SNR) 70 72 dB 1 Signal-to-Noise (and Distortion) Ratio (SINAD)70 71 dB 1 Total Harmonic Distortion (THD) −82 −77 dB Spurious-Free Dynamic Range (SFDR) −84 −77.5 dB Intermodulation Distortion (IMD) f = 40.1 kHz, f = 41.5 kHz A B Second-Order Terms −84 dB Third-Order Terms −93 dB Channel-to-Channel Isolation −100 dB fIN = 50 kHz, fNOISE = 60 kHz SAMPLE AND HOLD 3 Aperture Delay 12 ns 3 Aperture Jitter 40 ps Full Power Bandwidth 30 MHz @ 3 dB 10 MHz @ 0.1 dB DC ACCURACY Resolution 12 Bits 1 Integral Nonlinearity (INL) ±0.5 ±1 LSB 1 Differential Nonlinearity (DNL) ±0.5 ±0.99 LSB Guaranteed no missed codes to 12 bits 1 Offset Error ±2 ±4.5 LSB 1 Offset Error Matching ±2.5 ±4.5 LSB Offset Temperature Drift 4 ppm/°C 1 Gain Error ±1 ±4 LSB 1 Gain Error Matching ±1 ±2.5 LSB Gain Temperature Drift 0.5 ppm/°C ANALOG INPUT Input Voltage Ranges 0 V V REF DC Leakage Current ±0.01 ±1 μA Input Capacitance 32 pF When in track 8 pF When in hold mode REFERENCE INPUT/OUTPUT 4 Reference Output Voltage 2.4925 2.5 2.5075 V ±0.3% maximum @ 25°C Long-Term Stability 150 ppm For 1000 hours Output Voltage Hysteresis 50 ppm 5 Reference Input Voltage Range 1 2.5 V DC Leakage Current ±0.01 ±1 μA External reference applied to Pin V REF VREF Output Impedance 1 Ω VREF Temperature Coefficient 12 35 ppm/°C VREF Noise 60 μV rms Bandwidth = 10 MHz Rev. B | Page 3 of 24 AD7298 Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V Input Low Voltage, VINL +0.3 × VDRIVE V Input Current, I ±0.01 ±1 μA V = 0 V or V IN IN DRIVE 3 Input Capacitance, C 3 pF IN LOGIC OUTPUTS Output High Voltage, V V − 0.3 V V < 1.8 OH DRIVE DRIVE V − 0.2 V V ≥ 1.8 DRIVE DRIVE Output Low Voltage, VOL 0.4 V Floating State Leakage Current ±0.01 ±1 μA 3 Floating State Output Capacitance 8 pF INTERNAL TEMPERATURE SENSOR Operating Range −40 +125 Accuracy ±1 ±2 °C TA = −40°C to +85°C ±1 ±3 °C T = +85°C to +125°C A Resolution 0.25 °C LSB size CONVERSION RATE Conversion Time 1 t + 16 × t μs For V to V , with one cycle latency 2 SCLK IN0 IN7 100 μs T temperature sensor channel SENSE 3 Track-and-Hold Acquisition Time 100 ns Full-scale step input Throughput Rate 1 MSPS fSCLK = 20 MHz, for analog voltage conversions, one cycle latency 10 KSPS For the TSENSE channel, one cycle latency POWER REQUIREMENTS Digital inputs = 0 V or VDRIVE VDD 2.8 3 3.6 V V 1.65 3 3.6 V DRIVE 6 I V = 3.6 V, V = 3.6 V TOTAL DD DRIVE Normal Mode (Operational) 5.8 6.3 mA Normal Mode (Static) 4.1 4.6 mA Partial Power-Down Mode 2.7 3.3 mA Full Power-Down Mode 1 1.6 μA TA = −40°C to +25°C 10 μA T = −40°C to +125°C A 7 Power Dissipation Normal Mode (Operational) 17.4 18.9 mW V = 3 V, V = 3 V DD DRIVE 22.7 mW Normal Mode (Static) 14.8 16.6 mW Partial Power-Down Mode 9.8 11.9 mW Full Power-Down Mode 3.6 5.8 μW T = −40°C to +25°C A 36 μW T = −40°C to +125°C A 1 See the Terminology section. 2 All specifications expressed in decibels are referred to full-scale input, FSR, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 3 Sample tested during initial release to ensure compliance. 4 o Refers to Pin V specified for 25 C. REF 5 A correction factor may be required on the temperature sensor results when using an external VREF (see the Temperature Sensor Averaging section). 6 I is the total current flowing in V and V . TOTAL DD DRIVE 7 Power dissipation is specified with VDD = VDRIVE = 3.6 V, unless otherwise noted. Rev. B | Page 4 of 24 AD7298 TIMING SPECIFICATIONS VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; VREF = 2.5 V internal; TA = −40°C to + 125°C, unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. Table 2. Parameter Limit at T , T Unit Test Conditions/Comments MIN MAX tCONVERT t2 + (16 × tSCLK) μs max Conversion time 820 ns typ Each ADC channel VIN0 to VIN7, fSCLK = 20 MHz 100 μs max Temperature sensor channel 1 f 50 kHz min Frequency of external serial clock SCLK 20 MHz max Frequency of external serial clock tQUIET 6 ns min Minimum quiet time required between the end of serial read and the start of the next voltage conversion in repeat and nonrepeat mode. t2 10 ns min CS to SCLK setup time 1 t 15 ns max Delay from CS (falling edge) until DOUT three-state disabled 3 1 t Data access time after SCLK falling edge 4 35 ns max VDRIVE = 1.65 V to 3 V 28 ns max VDRIVE = 3 V to 3.6 V t5 0.4 × tSCLK ns min SCLK low pulse width t 0.4 × t ns min SCLK high pulse width 6 SCLK 1 t 14 ns min SCLK to DOUT valid hold time 7 1 t 16/34 ns min/max SCLK falling edge to DOUT high impedance 8 t9 5 ns min DIN setup time prior to SCLK falling edge t10 4 ns min DIN hold time after SCLK falling edge t11 100 ns min TSENSE_BUSY falling edge to CS falling edge 1 t 30 ns max Delay from CS rising edge to DOUT high impedance 12 t 1 μs max Power-up time from partial power-down POWER-UP_PARTIAL t 6 ms max Internal reference power-up time from full power-down POWER-UP 1 Measured with a load capacitance on DOUT of 15 pF. Rev. B | Page 5 of 24 AD7298 ABSOLUTE MAXIMUM RATINGS ESD CAUTION Table 3. Parameter Rating V to GND, GND1 −0.3 V to +5 V DD VDRIVE to GND, GND1 −0.3 V to + 5 V Analog Input Voltage to GND1 −0.3 V to 3 V −0.3 V to V + 0.3 V Digital Input Voltage to GND DRIVE Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V VREF to GND1 −0.3 V to +3 V THERMAL RESISTANCE GND1 to GND −0.3 V to +0.3 V Table 4. Thermal Resistance Input Current to Any Pin Except Supplies ±10 mA Package Type θ θ Unit JA JC Operating Temperature Range −40°C to +125°C 20-Lead LFCSP 52 6.5 °C/W Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Pb-Free Temperature, Soldering Reflow 260(+0)°C ESD 3.5 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 6 of 24 AD7298 PIN CONFIGURATION AND FUNCTION DESCRIPTION 15 SCLK V 1 IN3 14 DOUT V 2 IN4 AD7298 V 3 13 DIN IN5 TOP VIEW (Not to Scale) T _BUSY V 4 12 SENSE IN6 11 CS V 5 IN7 NOTES 1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE SHOULD BE SOLDERED TO PCB GROUND FOR PROPER FUNCTIONALITY AND HEAT DISSIPATION. Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 to 5, V , V , Analog Inputs. The AD7298 has eight single-ended analog inputs that are multiplexed into the on-chip track- IN3 IN4 18 to 20 VIN5, VIN6, and-hold. Each input channel can accept analog inputs from 0 V to 2.5 V. Any unused input channels should be VIN7, VIN0, connected to GND1 to avoid noise pickup. VIN1, VIN2 6 GND1 Ground. Ground reference point for the internal reference circuitry on the AD7298. The external reference signals and all analog input signals should be referred to this GND1 voltage. The GND1 pin should be connected to the GND plane of a system. All ground pins should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. The VREF pin should be decoupled to this ground pin via a 10 μF decoupling capacitor. 7 VREF Internal Reference/External Reference Supply. The nominal internal reference voltage of 2.5 V appears at this pin. Provided the output is buffered, the on-chip reference can be taken from this pin and applied externally to the rest of a system. Decoupling capacitors should be connected to this pin to decouple the reference buffer. For best performance, it is recommended to use a 10 μF decoupling capacitor on this pin to GND1. The internal reference can be disabled and an external reference supplied to this pin, if required. The input voltage range for the external reference is 2.0 V to 2.5 V. 8 DCAP Decoupling Capacitor Pin. Decoupling capacitors (1 μF recommended) are connected to this pin to decouple the internal LDO. 9 GND Ground. Ground reference point for all analog and digital circuitry on the AD7298. The GND pin should be connected to the ground plane of the system. All ground pins should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Both DCAP and VDD pins should be decoupled to this GND pin. 10 V Supply Voltage, 2.8 V to 3.6 V. This supply should be decoupled to GND with 10 μF and 100 nF decoupling DD capacitors. 11 CS Chip Select, Active Low Logic Input. This pin is edge triggered on the falling edge of this input, the track-and- hold goes into hold mode, and a conversion is initiated. This input also frames the serial data transfer. When CS is low, the output bus is enabled, and the conversion result becomes available on the DOUT output. 12 TSENSE_BUSY Busy Output. This pin transitions high when a temperature sensor conversion starts and remains high until the conversion completes. 13 DIN Data In, Logic input. Data to be written to the AD7298 control register is provided on this input and is clocked into the register on the falling edge of SCLK. 14 DOUT Serial Data Output. The conversion result from the AD7298 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7298 consists of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data (MSB first). The output coding is straight binary for the voltage channels and twos complement for the temperature sensor result. 15 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7298. Rev. B | Page 7 of 24 08754-003 GND1 6 20 V IN2 V 19 V REF 7 IN1 D 8 18 V CAP IN0 GND 9 17 PD/RST V 10 16 V DD DRIVE AD7298 Pin No. Mnemonic Description 16 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at the voltage at which the interface operates. This pin should be decoupled to GND. The voltage range on this pin is 1.65 V to 3.6 V and may be less than the voltage at VDD, but should never exceed it by more than 0.3 V. 17 PD/RST Power-Down Pin. This pin places the part into full power-down mode and enables power conservation when operation is not required. This pin can be used to reset the device by toggling the pin low for a minimum of 1 ns and a maximum of 100 ns. If the maximum time is exceeded, the part enters power-down mode. When placing the AD7298 in full power-down mode, the analog inputs must return to 0 V. EPAD EPAD The exposed metal paddle on the bottom of the LFCSP package should be soldered to PCB ground for proper functionality and heat dissipation. Rev. B | Page 8 of 24 AD7298 TYPICAL PERFORMANCE CHARACTERISTICS 0 0.6 V = V = 3V DD DRIVE f = 1.17647MHz SAMPLE INL MAX f = 50kHz IN –20 0.4 f = 20MHz SCLK SNR = 72.621 THD = –82.562 –40 0.2 T = 25°C A V = 3V DRIVE V = 3V –60 0 DD –80 0.2 INL MIN –100 0.4 –120 0.6 0 50 100 150 200 250 300 350 400 450 500 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 FREQUENCY (kHz) REFERENCE VOLTAGE (V) Figure 3.Typical FFT Figure 6. INL vs. VREF 1.0 0.6 T = 25°C A V = 3V DRIVE 0.8 V = 2.5V DNL MAX REF V = 3 V 0.4 DD 0.6 0.4 0.2 0.2 T = 25°C A V = 3V DRIVE 0 0 V = 3V DD –0.2 –0.2 –0.4 DNL MIN –0.6 –0.4 –0.8 –1.0 –0.6 0 512 1024 1536 2048 2560 3072 3584 4096 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 256 768 1280 1792 2304 2816 3328 3840 CODE REFERENCE VOLTAGE (V) Figure 4.Typical ADC INL Figure 7. DNL vs. V REF 1.0 12 T = 25°C A V = 3V DRIVE 0.8 11 V = 2.5V REF V = 3 V DD 10 0.6 0.4 9 8 0.2 7 0 –0.2 6 5 –0.4 –0.6 4 3 –0.8 V = 3V DD V = 3V DRIVE 2 –1.0 00.5 1.0 1.5 2.0 2.5 0 512 1024 1536 2048 2560 3072 3584 4096 256 768 1280 1792 2304 2816 3328 3840 CODE V (V) REF Figure 8. Effective Number of Bits vs. V Figure 5. Typical ADC DNL REF Rev. B | Page 9 of 24 DNL (LSB) AMPLITUDE (dB) INL (LSB) 08754-017 08754-035 08754-016 EFFECTIVE NUMBER OF BITS INL (LSB) INL (LSB) 08754-020 08754-018 AD7298 3.0 110 V = V = 3V DD DRIVE 105 2.5 100 2.0 95 1.5 90 85 1.0 80 0.5 75 0 70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 50 100 150 200 250 300 350 400 450 500 550 CURRENT LOAD (mA) f (kHz) NOISE Figure 12. Channel-to-Channel Isolation, f = 50 kHz Figure 9. V vs. Reference Output Current Drive IN REF 76 55 74 R =47Ω IN 50 72 45 R =33Ω IN 70 R =0Ω IN 40 68 35 66 R =47Ω IN 30 64 R = 100Ω IN 25 62 R = 200Ω IN 60 20 10 100 500 0 20 406080 100 TIME (Seconds) INPUT FREQUENCY (kHz) Figure 10. Response to Thermal Shock from Room Temperature Figure 13. SINAD vs. Analog Input Frequency for Various Source Impedances into 50°C Stirred Oil 75 –90 V =3V DD 70 V =3V DRIVE –92 65 –94 60 –96 55 –98 50 45 –100 40 –102 35 –104 30 –106 25 V = 3V –108 DD 20 V = 3V DRIVE 15 –110 0 0.5 1.0 1.5 2.0 2.5 1k 10k 100k 1M 10M 100M V (V) RIPPLE FREQUENCY (Hz) REF Figure 14. SINAD vs. Reference Voltage Figure 11. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Rev. B | Page 10 of 24 PSRR (dB) TEMPERATURE READING (°C) V (V) REF 08754-021 08754-028 08754-027 ISOLATION (dB) SINAD (dB) SINAD (dB) 08754-022 08754-024 08754-029 AD7298 2.0 19 V = V = 3V DD DRIVE 18 1.5 17 1.0 16 0.5 15 14 0 13 –0.5 12 –1.0 11 –1.5 10 –40 –25 –10 0 10 20 25 30 35 45 60 85 105 125 0 100 200 300 400 500 600 700 800 900 1000 TEMPERATURE (°C) THROUGHPUT (kSPS) Figure 15. Temperature Accuracy at 3 V Figure 18. Power vs. Throughput in Normal Mode with V = 3 V DD –60 4.0 V = 3V –40°C +85°C DRIVE R = 47Ω SOURCE 0°C +105°C 3.5 +25°C +125°C –65 R = 200Ω SOURCE 3.0 –70 R = 100Ω 2.5 SOURCE –75 2.0 R = 43Ω SOURCE 1.5 –80 R = 33Ω SOURCE 1.0 –85 R = 0Ω SOURCE 0.5 –90 0 10 100 500 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SIGNAL FREQUENCY (kHz) V (V) DD Figure 16. THD vs. Analog Input Frequency for Various Source Impedances  Figure 19. Full Shutdown Current vs. Supply Voltage for Various Temperatures 6 V = V = 3V DD DRIVE 5 V CURRENT DD 4 3 2 1 V CURRENT DRIVE 0 0 200 400 600 800 1000 1200 THROUGHPUT (kSPS) Figure 17. Average Supply Current vs. Throughput Rate  Rev. B | Page 11 of 24 CURRENT (mA) TEMPERATURE ERROR (°C) THD (dB) 08754-036 08754-034 08754-026 POWER (mW) TOTAL CURRENT (µA) 08754-031 08754-025 AD7298 TERMINOLOGY Differential Nonlinearity Signal-to-Noise and Distortion Ratio (SINAD) The difference between the measured and the ideal 1 LSB The measured ratio of signal-to-noise and distortion at the change between any two adjacent codes in the ADC. output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals Offset Error up to half the sampling frequency (f /2), excluding dc. The The deviation of the first code transition (00…000) to S ratio is dependent on the number of quantization levels in the (00…001) from the ideal—that is, GND1 + 1 LSB. digitization process; the more levels, the smaller the quantization Offset Error Match noise. The theoretical signal-to-noise and distortion ratio for The difference in offset error between any two channels. an ideal N-bit converter with a sine wave input is given by Gain Error Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB The deviation of the last code transition (111…110) to Thus, the SINAD is 74 dB for an ideal 12-bit converter. (111…111) from the ideal (that is, REFIN − 1 LSB) after the offset error has been adjusted out. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For Gain Error Matching the AD7298, it is defined as The difference in gain error between any two channels. Track-and-Hold Acquisition Time 2 2 2 2 2 V +V +V +V +V 2 3 4 5 6 THD(dB)= 20log The track-and-hold amplifier returns to track mode at the end V 1 of conversion. Track-and-hold acquisition time is the time where V1 is the rms amplitude of the fundamental, and V2, V3, required for the output of the track-and-hold amplifier to reach V4, V5, and V6 are the rms amplitudes of the second through its final value, within ±1 LSB, after the end of conversion. sixth harmonics. Power Supply Rejection Ratio (PSRR) Peak Harmonic or Spurious Noise PSRR is defined as the ratio of the power in the ADC output at The ratio of the rms value of the next largest component in the full-scale frequency, f, to the power of a 100 mV p-p sine wave ADC output spectrum (up to f /2 and excluding dc) to the rms S applied to the ADC V supply of frequency, f . The frequency DD S value of the fundamental. Typically, the value of this specification of the input varies from 5 kHz to 25 MHz. is determined by the largest harmonic in the spectrum, but for PSRR (dB) = 10 log(Pf/PfS) ADCs where the harmonics are buried in the noise floor, it is a noise peak. where: Pf is the power at frequency, f, in the ADC output. Integral Nonlinearity Pf is the power at frequency, f , in the ADC output. S S The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Rev. B | Page 12 of 24 AD7298 CIRCUIT INFORMATION The AD7298 is a high speed, 8-channel, 12-bit ADC with an CAPACITIVE DAC internal temperature sensor. The part can be operated from a 2.8 V to 3.6 V supply and is capable of throughput rates of A V IN 1 MSPS per analog input channel. CONTROL SW1 B LOGIC SW2 The AD7298 provides the user with an on-chip, track-and-hold COMPARATOR GND1 ADC and a serial interface housed in a 20-lead LFCSP. The Figure 21. ADC Conversion Phase AD7298 has eight single-ended input channels with channel repeat functionality, which allows the user to select a channel ANALOG INPUT sequence through which the ADC can cycle with each conse- Figure 22 shows an equivalent circuit of the analog input struc- cutive CS falling edge. The serial clock input accesses data from ture of the AD7298. The two diodes, D1 and D2, provide ESD the part, controls the transfer of data written to the ADC, and protection for the analog inputs. Care must be taken to ensure provides the clock source for the successive approximation that the analog input signal never exceeds the internally ADC. The analog input range for the AD7928 is 0 V to V . REF generated LDO voltage of 2.5 V (DCAP) by more than 300 mV. The AD7298 operates with one cycle latency, which means that This causes the diodes to become forward-biased and start the conversion result is available in the serial transfer following conducting current into the substrate. The maximum current the cycle in which the conversion is performed. these diodes can conduct without causing irreversible damage to the part is 10 mA. Capacitor C1, in Figure 22, is typically The AD7298 includes a high accuracy band gap temperature about 8 pF and can primarily be attributed to pin capacitance. sensor, which is monitored and digitized by the 12-bit ADC The Resistor R1 is a lumped component made up of the on to give a resolution of 0.25°C. The AD7298 provides flexible resistance of a switch (track-and-hold switch) and also includes power management options to allow the user to achieve the best the on resistance of the input multiplexer. The total resistance is power performance for a given throughput rate. These options typically about 155 Ω. The capacitor, C2, is the ADC sampling are selected by programming the partial power-down bit, PPD, capacitor and has a capacitance of 34 pF typically. in the control register and using the PD/RST pin. D (2.5V) CAP CONVERTER OPERATION C2 The AD7298 is a 12-bit successive approximation ADC based D1 pF R1 around a capacitive DAC. Figure 20 and Figure 21 show simplified V IN schematics of the ADC. The ADC is comprised of control logic, D2 CONVERSION PHASE: SWITCH OPEN C1 TRACK PHASE: SWITCH CLOSED pF SAR, and a capacitive DAC that are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. Figure 20 shows Figure 22. Equivalent Analog Input Circuit the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition For ac applications, removing high frequency components from and the sampling capacitor acquires the signal on the selected the analog input signal is recommended by using an RC low- VIN channel. pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratios are CAPACITIVE DAC critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac A V IN performance of the ADC. This may necessitate the use of an SW1 CONTROL B LOGIC SW2 input buffer amplifier. The choice of the op amp is a function COMPARATOR GND1 of the particular application performance criteria. Figure 20. ADC Acquisition Phase ADC Transfer Function When the ADC starts a conversion (see Figure 21), SW2 The output coding of the AD7298 is straight binary for the opens and SW1 moves to Position B, causing the comparator analog input channel conversion results and twos complement, to become unbalanced. The control logic and the capacitive for the temperature conversion result. The designed code DAC are used to add and subtract fixed amounts of charge to transitions occur at successive LSB values (that is, 1 LSB, 2 LSBs, bring the comparator back into a balanced condition. When the and so forth). The LSB size is V /4096 for the AD7298. The REF comparator is rebalanced, the conversion is complete. The ideal transfer characteristic for the AD7298 for straight binary control logic generates the ADC output code. Figure 23 shows coding is shown in Figure 23. the ADC’s transfer functions. Rev. B | Page 13 of 24 08754-004 08754-006 08754-005 AD7298 The temperature conversion consists of two phases, the integra- tion followed by the conversion. The integration is initiated on 111...111 the falling edge. It takes a period of approximately 100 μs to CS 111...110 complete the integration and conversion of the temperature result. When the integration is completed, the conversion is 111...000 initiated automatically. Once the temperature integration is 011...111 1LSB = V /4096 initiated, the T BUSY signal goes high to indicate that a SENSE_ REF temperature conversion is in progress and remains high until the conversion is completed. 000...010 000...001 Theoretically, the temperature measuring circuit can measure 000...000 temperatures from –512°C to +511°C with a resolution of 0V 1LSB +V –1LSB REF 0.25°C. However, temperatures outside TA (the specified ANALOG INPUT NOTES temperature range for the AD7298) are outside the guaranteed 1. V IS 2.5V. REF operating temperature range of the device. The temperature Figure 23. Straight Binary Transfer Characteristic sensor is selected by setting the T bit in the control register. SENSE TEMPERATURE SENSOR OPERATION TEMPERATURE SENSOR AVERAGING The AD7298 contains one local temperature sensor. The The AD7298 incorporates a temperature sensor averaging on-chip, band gap temperature sensor measures the temp- feature to enhance the accuracy of the temperature measure- erature of the AD7298 die. ments. To enable the temperature sensor averaging feature, both the T AVG bit and the T bit must be enabled in the The temperature sensor module on the AD7298 is based on SENSE SENSE the three-current principle (see Figure 24), where three currents control register. In this mode the temperature is internally averaged to reduce the effect of noise on the temperature result. are passed through a diode and the forward voltage drop is The temperature is measured each time a TSENSE conversion is measured, allowing the temperature to be calculated free of performed and a moving average method is used to determine errors caused by series resistance. the result in the T Result Register. The average result is SENSE V DD given by the following equation: I4 × I 8 × I I BIAS 7 1 T AVG=() Previous_Average_Result +() Current_Result SENSE 8 8 The TSENSE result read when averaging is enabled is the V OUT+ TSENSEAVG result, a moving average temperature measurement. TO ADC The first T conversion result given by the AD7298 after the SENSE temperature sensor and averaging mode has been selected in V INTERNAL OUT– SENSE the control register (Bit D1 and Bit D5) is the actual first T SENSE TRANSISTOR conversion result. If the control register is written to and the BIAS DIODE content of the TSENSEAVG bit changed, the averaging function is reset and the next TSENSE average conversion result is the current temperature conversion result. If the status of the TSENSEAVG bit Figure 24. Top-Level Structure of Internal Temperature Sensor is not changed on successive writes to the control register, the averaging function is reinitialized and continues calculating the cumulative average. The user has the option of disabling the averaging by setting Bit TSENSEAVG to 0 in the control register. The AD7298 defaults on power-up with the averaging function disabled. The total time to measure a temperature channel is typically 100 μs. Rev. B | Page 14 of 24 ADC CODE 08754-007 08754-008 AD7298 Temperature Value Format V DRIVE One LSB of the ADC corresponds to 0.25°C. The temperature The AD7298 also provides the VDRIVE feature. VDRIVE controls the reading from the ADC is stored in a 12-bit twos complement voltage at which the serial interface operates. VDRIVE allows the format to accommodate both positive and negative temperature ADC to easily interface to both 1.8 V and 3 V processors. For measurements. The temperature data format is provided in example, if the AD7298 is operated with a V of 3.3 V, the DD Table 6. V pin can be powered from a 1.8 V supply. DRIVE This enables the AD7298 to operate with a larger dynamic Table 6. Temperature Data Format range with a VDD of 3.3 V while still being able to interface to Temperature (°C) Digital Output 1.8 V processors. Take care to ensure VDRIVE does not exceed −40 1111 0110 0000 VDD by more than 0.3 V (see the Absolute Maximum Ratings −25 1111 1001 1100 section). −10 1111 1101 1000 −0.25 1111 1111 1111 THE INTERNAL OR EXTERNAL REFERENCE 0 0000 0000 0000 The AD7298 can operate with either the internal 2.5 V on-chip +0.25 0000 0000 0001 reference or an externally applied reference. The EXT_REF bit +10 0000 0010 1000 in the control register is used to determine whether the internal +25 0000 0110 0100 reference is used. If the EXT_REF bit is selected in the control +50 0000 1100 1000 register, an external reference can be supplied through the +75 0001 0010 1100 V pin. On power-up, the internal reference is enabled. REF +100 0001 1001 0000 Suitable external reference sources for the AD7298 include +105 0001 1010 0100 AD780, AD1582, ADR431, REF193, and ADR391. +125 0001 1111 0100 The internal reference circuitry consists of a 2.5 V band gap The temperature conversion formulas are as follows: reference and a reference buffer. When the AD7298 operates in internal reference mode, the 2.5 V internal reference is available Positive Temperature = ADC Code/4 at the V pin, which should be decoupled to GND1 using a 10 μF REF Negative Temperature = (4096 − ADC Code)/4 capacitor. It is recommended that the internal reference be buffered The previous formulas are for a VREF of 2.5 V only. before applying it elsewhere in the system. If an external reference is used, the temperature sensor requires The internal reference is capable of sourcing up to 2 mA of an external reference of between 2 V and 2.5 V for correct current when the converter is static. The reference buffer operation. When an external reference of less than 2.5 V is requires 5.5 ms to power up and charge the 10 μF decoupling applied, the temperature results are calculated using the capacitor during the power-up time. following formula, where VEXT_REF is the value of the external reference voltage. ADCCode ⎛ ⎞ Temperature=V +109.3 −273.15 ⎜ ⎟ EXT _ REF 10 ⎝ ⎠ Rev. B | Page 15 of 24 AD7298 CONTROL REGISTER The control register of the AD7298 is a 16-bit, write-only register. Data is loaded from the DIN pin of the AD7298 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on the DIN line corresponds to the AD7298 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 16 falling clock edges (after the falling edge of CS) is loaded to the control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 7 and Table 8. On power-up, the default content of the control register is all zeros. Table 7. Control Register Bit Functions MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 WRITE REPEAT CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 TSENSE DONTC DONTC EXT_REF TSENSEAVG PPD Table 8. Control Register Bit Function Description Bit Mnemonic Description D15 WRITE The value written to this bit determines whether the subsequent 15 bits are loaded to the control register. If this bit is a 1, the following 15 bits are written to the control register; if it is a 0, then the remaining 15 bits are not loaded to the control register and it remains unchanged. D14 REPEAT This bit enables the repeated conversion of the selected sequence of channels. CH0 to CH7 D13 to These eight channel selection bits are loaded at the end of the current conversion and select which analog input D6 channel is to be converted in the next serial transfer, or they may select the sequence of channels for conversion in the subsequent serial transfers. Each CHX bit corresponds to an analog input channel. A channel or sequence of channels is selected for conversion by writing a 1 to the appropriate CHX bit/bits. Channel address bits corresponding to the conversion result are output on DOUT prior to the 12 bits of data. The next channel to be th converted is selected by the mux on the 14 SCLK falling edge. D4 TSENSE Writing a 1 to this bit enables the temperature conversion. When the temperature sensor is selected for conversion, the TSENSE_BUSY pin goes high after the next CS falling edge to indicate that the conversion is in progress; the previous conversion result can be read while the temperature conversion is in progress. Once T _BUSY goes low, CS can be brought low 100 ns later to read the T conversion result. SENSE SENSE 4 to 3 DONTC Don’t care. D2 EXT_REF Writing a Logic 1 to this bit, enables the use of an external reference. The input voltage range for the external reference is 1 V to 2.5 V. The external reference should not exceed 2.5 V or the device performance is affected. D1 TSENSEAVG Writing a 1 to this bit enables the temperature sensor averaging function. When averaging is enabled, the AD7298 internally computes a running average of the conversion results to determine the final TSENSE result (see the Temperature Sensor Averaging section for more details). This mode reduces the influence of noise on the final T result. Selecting this feature does not automatically select the T for conversion. The T bit must also be SENSE SENSE SENSE set to start a temperature sensor conversion. D0 PPD This partial power-down mode is selected by writing a 1 to this bit in the control register. In this mode, some of the internal analog circuitry is powered down. The AD7298 retains the information in the control register while in partial power-down mode. The part remains in this mode until a 0 is written to this bit. Table 9. Channel Address Bits ADD3 ADD2 ADD1 ADD0 Analog Input Channel 0 0 0 0 V IN0 0 0 0 1 V IN1 0 0 1 0 V IN2 0 0 1 1 VIN3 0 1 0 0 VIN4 0 1 0 1 V IN5 0 1 1 0 V IN6 0 1 1 1 V IN7 1 0 0 0 TSENSE 1 0 0 1 TSENSE with averaging enabled Rev. B | Page 16 of 24 AD7298 MODES OF OPERATION third falling edge will have the result (V ) available for The AD7298 offers different modes of operation that are CS IN2 designed to provide additional flexibility for the user. These reading. The AD7298 operates with one cycle latency, thus the options can be chosen by programming the content of the conversion result corresponding to each conversion is available control register to select the desired mode. one serial read cycle after the cycle in which the conversion was initiated. TRADITIONAL MULTICHANNEL MODE OF OPERATION As the device operates with one cycle latency, the control register configuration sets up the configuration for the next The AD7298 can operate as a traditional multichannel conversion, which is initiated on the next CS falling edge, but ADC, where each serial transfer selects the next channel for the first bit of the corresponding result is not clocked out until conversion. One must write to the control register to configure the subsequent falling edge, as shown in Figure 25. CS and select the desired input channel prior to initiating any conversions. In the traditional mode of operation, the CS signal If more than one channel is selected in the control register, the is used to frame the first write to the converter on the DIN pin. AD7298 converts all selected channels sequentially in ascending In this mode of operation, the REPEAT bit in the control order on successive falling edges. Once all the selected CS register is set to a low logic level, 0, thus the REPEAT function channels in the control register are converted, the AD7298 is not in use. The data, which appears on the DOUT pin during ceases converting until the user rewrites to the control register the initial write to the control register, is invalid. The first CS to select the next channel for conversion. This operation is falling edge initiates a write to the control register to configure shown in Figure 26. DOUT returns all 1s if the sequence of the device; a conversion is then initiated for the selected analog conversions is completed or if no channel is selected. nd input channel (VIN0) on the subsequent (2 ) CS falling edge; the CS 1 12 16 1 16 1 16 1 16 SCLK CONVERSION RESULT CONVERSION RESULT INVALID DATA INVALID DATA DOUT FOR CHANNEL 1 FOR CHANNEL 4 DATA WRITTEN TO CONTROL DATA WRITTEN TO CONTROL NO WRITE TO THE NO WRITE TO THE DIN REGISTER CHANNEL 1 SELECTED REGISTER CHANNEL 4 SELECTED CONTROL REGISTER CONTROL REGISTER Figure 25. Configuring a Conversion and Read with the AD7298. One channel selected for conversion. CS 11216 1 16 1 16 SCLK CONVERSION RESULT INVALID DATA INVALID DATA DOUT FOR CHANNEL 1 DATA WRITTEN TO CONTROL NO WRITE TO THE DATA WRITTEN TO CONTROL DIN REGISTER CH 1 AND 2 SELECTED CONTROL REGISTER REGISTER CHANNEL 5 SELECTED CS 1161 16 SCLK CONVERSION RESULT CONVERSION RESULT DOUT FOR CHANNEL 2 FOR CHANNEL 5 NO WRITE TO THE NO WRITE TO THE DIN CONTROL REGISTER CONTROL REGISTER Figure 26. Configuring a Conversion and Read with the AD7298. Numerous channels selected for conversion. Rev. B | Page 17 of 24 08754-010 08754-009 AD7298 CS 11216 1 16 1 16 SCLK CONVERSION RESULT INVALID DATA INVALID DATA DOUT FOR CHANNEL 0 NO WRITE TO THE NO WRITE TO THE DIN CONTROL REGISTER CONTROL REGISTER DATA WRITTEN TO CONTROL REGISTER CH 0, CH 1, AND CH 2 SELECTED: REPEAT = 1 CS 116116116 SCLK CONVERSION RESULT CONVERSION RESULT CONVERSION RESULT DOUT FOR CHANNEL 1 FOR CHANNEL 2 FOR CHANNEL 0 NO WRITE TO THE NO WRITE TO THE NO WRITE TO THE DIN CONTROL REGISTER CONTROL REGISTER CONTROL REGISTER Figure 27. Configuring a Conversion and Read in Repeat Mode REPEAT OPERATION The REPEAT bit in the control register allows the user to select To select a sequence of channels, the associated channel bit a sequence of channels on which the AD7298 continuously must be set to a logic high state (1) for each analog input whose converts. When the REPEAT bit is set in the control register, conversion is required. For example, if the REPEAT bit = 1, the AD7298 continuously cycles through the selected channels then CH0, CH1, and CH2 = 1. The VIN0 analog input is in ascending order, beginning with the lowest channel and converted on the first CS falling edge following the write to converting all channels selected in the control register. On the control register, the V channel is converted on the IN1 completion of the sequence, the AD7298 returns to the first subsequent CS falling edge, and the VIN0 conversion result is selected channel in the control register and recommences the available for reading. The third CS falling edge following the sequence. write operation initiates a conversion on VIN2 and has the VIN1 The conversion sequence of the selected channels in the repeat result available for reading. The AD7298 operates with one mode of operation continues until such time as the control cycle latency, thus the conversion result corresponding to each register of the AD7298 is reprogrammed. If the TSENSE bit is conversion is available one serial read cycle after the cycle in selected in the control register, then the temperature conversion which the conversion is initiated. will be available for conversion after the last analog input This mode of operation simplifies the operation of the device by channel in the sequence has been converted. It is not necessary allowing consecutive channels to be converted without having to write to the control register once a repeat operation is to reprogram the control register or write to the part on each initiated unless a change in the AD7298 configuration is serial transfer. Figure 27 illustrates how to set up the AD7298 required. The WRITE bit must be set to zero or the DIN line to continuously convert on a particular sequence of channels. tied low to ensure that the control register is not accidentally To exit the repeat mode of operation and revert back to the overwritten, or the automatic conversion sequence interrupted. traditional mode of operation of a multichannel ADC, ensure A write to the control register during the repeat mode of that the REPEAT bit = 0 on the next serial write. operation resets the cycle even if the selected channels are unchanged. Thus, the next conversion by the AD7298 after a write operation will be the first selected channel in the sequence. Rev. B | Page 18 of 24 08754-011 AD7298 CS POWER-DOWN MODES 116 The AD7298 has a number of power conservation modes SCLK of operation that are designed to provide flexible power 4 CHANNEL ADDRESS BITS DOUT + CONVERSION RESULT management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for different DATA WRITTEN TO CONTROL DIN REGISTER IF REQUIRED application requirements. The power-down modes of operation Figure 28. Normal Mode Operation of the AD7298 are controlled by the power-down (PPD) bit in the control register and the PD/RST pin on the device. Partial Power-Down Mode When power supplies are first applied to the AD7298, care In this mode, part of the internal circuitry on the AD7298 is should be taken to ensure that the part is placed in the required powered down. The AD7298 enters partial power-down on mode of operation the CS rising edge once the current serial write operation Normal Mode containing 16 SCLK clock cycles is completed. To enter partial power-down, the PPD bit in the control register should be set Normal mode is intended for the fastest throughput rate to 1 on the last required read transfer from the AD7298. performance because the user does not have to be concerned Once in partial power-down mode, the AD7298 transmits about any power-up times because the AD7298 remains fully all 1s on the DOUT pin if CS is toggled low. If the averaging powered on at all times. Figure 28 shows the general diagram feature for the temperature sensor is enabled in the control of operation of the AD7298 in this mode. The conversion is register, the averaging is reset once the device enters partial initiated on the falling edge of CS and the track-and-hold enters th power-down mode. hold mode. On the 14 SCLK falling edge, the track-and-hold returns to track mode and starts acquiring the analog input, as The AD7298 remains in partial power-down until the power- described in the Serial Interface section. The data presented to down bit, PPD, in the control register is changed to a logic level the AD7298 on the DIN line during the first 16 clock cycles of zero (0). The AD7298 begins powering up on the rising edge the data transfer are loaded into the control register (provided of CS following the write to the control register disabling the the WRITE bit is 1). The part remains fully powered up in power-down bit. Once t has elapsed, a full 16-SCLK write QUIET normal mode at the end of the conversion as long as the PPD to the control register must be completed to update its content bit is set to 0 in the write transfer during that conversion. with the desired channel configuration for the subsequent conversion. A valid conversion is then initiated on the next CS To ensure continued operation in normal mode, the PPD bit falling edge. should be loaded with 0 on every data write operation. Sixteen serial clock cycles are required to complete the conversion and Because the AD7298 has one cycle latency, the first conversion access the conversion result. For specified performance, the result after exiting partial power-down mode is available in the throughput rate should not exceed 1 MSPS. Once a conversion fourth serial transfer, as shown in Figure 29. The first cycle is complete and the has returned high, a minimum of the CS updates the PPD bit, the second cycle updates the configuration quiet time, tQUIET, must elapse before bringing CS low again and Channel ID bits, the third completes the conversion, and to initiate another conversion and access the previous conver- the fourth accesses the DOUT valid result. The use of this sion result. mode enables a reduction in the overall power consumption of the device. THE PART IS FULLY PART IS IN PART BEGINS TO POWERED UP ONCE THE PARTIAL POWER UP ON CS WRITE TO THE CONTROL POWER DOWN RISING EDGE. REGISTER IS COMPLETED. t t QUIET QUIET CS 11216 1 16 1 16 SCLK INVALID DATA INVALID DATA DOUT WRITE TO CONTROL WRITE TO THE CONTROL NO WRITE TO DIN REGISTER, PPD = 0. REGISTER, SELECT CH1, PPD = 0 CONTROL REGISTER CONTROL REGISTER CONFIGURED SELECT ANALOG INPUT CHANNELS AD7298 CONVERTING CHANNEL 1 TO POWER UP DEVICE. FOR CONVERSION. THE NEXT CYCLE NEXT CYCLE HAS CHANNEL 1 WILL CONVERT THE FIRST CHANNEL RESULT AVAILABLE FOR READING. PROGRAMMED IN THIS WRITE OPERATION. Figure 29. Partial Power-Down Mode of Operation Rev. B | Page 19 of 24 08754-013 08754-012 AD7298 Full Power-Down Mode If an external reference is being used, the user does not need to wait for the internal reference to power-up fully. The AD7298 In this mode, all internal circuitry on the AD7298 is powered digital interface is fully functional after 500 μs from initial down and no information is retained in the control register or any power-up. Therefore, the user can write to the control register other internal register. If the averaging feature for the tempera- after 500 μs to switch to external reference mode. The AD7298 ture sensor is enabled in the control register (TSENSEAVG), the is then immediately ready to convert once the external reference averaging is reset once the device enters power-down mode. is available on the VREF pin. The AD7298 is placed into full power-down mode by bringing When supplies are first applied to the AD7298, the user must PD RST the logic level on the / pin low for greater than 100 ns. wait the specified 500 μs before programming the control When placing the AD7298 in full power-down mode, the ADC register to select the desired channels for conversion. inputs must return to 0 V. The PD/RST pin is asynchronous to the clock, thus it can be triggered at any time. The part can be RESET powered up for normal operation by bringing the PD/RST pin The AD7298 includes a reset feature that can be used to reset the device and the contents of all internal registers, including logic level back to a high logic state. the control register, to their default state. The full power-down feature can be used to reduce the average PD RST To activate the reset operation, the / pin should be power consumed by the AD7298 when operating at lower brought low for no longer than 100 ns. It is asynchronous with throughput rates. The user should ensure that t has POWER_UP the clock, thus it can be triggered at any time. If the PD/RST pin elapsed prior to programming the control register and initiating is held low for greater than 100 ns, the part enters full power- a valid conversion. PD RST down mode. It is imperative that the / pin be held at a POWERING UP THE AD7298 stable logic level at all times to ensure normal operation. The AD7298 contains a power-on reset circuit, which sets the control register to its default setting of all zeros, thus the internal reference is enabled and the device is configured for the normal mode of operation. On power-up, the internal reference is by default enabled, which takes up 6 ms (maximum) to power-up. Rev. B | Page 20 of 24 AD7298 SERIAL INTERFACE The going low provides the first address bit to be read in by CS Figure 30 shows the detailed timing diagram for the serial the microcontroller or DSP. The remaining data is then clocked interface to the AD7298. The serial clock provides the conver- out by subsequent SCLK falling edges, beginning with a second sion clock and controls the transfer of information to and from address bit. Thus, the first falling clock edge on the serial clock the AD7298 during each conversion. has the first address bit provided for reading and also clocks out The CS signal initiates the data transfer and conversion process. the second address bit. The three remaining address bits and The falling edge of CS puts the track-and-hold into hold mode 12 data bits are clocked out by subsequent SCLK falling edges. at which point the analog input is sampled and the bus is taken The final bit in the data transfer is valid for reading on the th th out of three-state. The conversion is also initiated at this point 16 falling edge having been clocked out on the previous (15 ) and requires 16 SCLK cycles to complete. The track-and-hold falling edge. th goes back into track on the 14 SCLK falling edge as shown in In applications with a slower SCLK, it may be possible to read th Figure 30 at Point B. On the 16 SCLK falling edge or on the in data on each SCLK rising edge depending on the SCLK rising edge of CS , the DOUT line goes back into three-state. frequency. The first rising edge of SCLK after the falling CS If the rising edge of occurs before 16 SCLKs have elapsed, CS th edge would have the first address bit provided, and the 15 the conversion is terminated, the DOUT line goes back into tri- rising SCLK edge would have last data bit provided. state, and the control register is not updated; otherwise, DOUT th Writing information to the control register takes place on the returns to three-state on the 16 SCLK falling edge. Sixteen serial first 16 falling edges of SCLK in a data transfer, assuming the MSB clock cycles are required to perform the conversion process and (that is, the WRITE bit) has been set to 1. The 16-bit word read to access data from the AD7298. from the AD7298 always contains four channel address bits that For the AD7298, four-channel address bits (ADD3 to ADD0) the conversion result corresponds to, followed by the 12-bit that identify which channel the conversion result corresponds conversion result. to precede the 12 bits of data (see Table 9). t QUIET CS t ACQUISITION t 2 t 6 B 12345 13 14 15 16 SCLK t 5 t t t t 4 7 8 3 THREE- STATE DOUT ADD3 ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0 THREE- STATE t t 9 10 DIN WRITE REPEAT CH0 CH1 CH2 CH3 EXT_REF T AVG PPD SENSE Figure 30. Serial Interface Timing Diagram Rev. B | Page 21 of 24 08754-014 AD7298 TEMPERATURE SENSOR READ The temperature sensor conversion involves two phases, the Alternatively, if CS remains high while T _BUSY is high, SENSE integration phase and the conversion phase as detailed in the then the DOUT bus remains in three-state. Temperature Sensor Operation section. The integration phase If the user writes to the control register during the first 16 SCLK CS is initiated on the falling edge of and once completed the cycles following T _BUSY going high, the configuration of SENSE conversion is automatically initiated internally by the AD7298. the device for the next conversion, which is initiated on the When a temperature conversion integration is initiated, the CS subsequent falling edge after TSENSE_BUSY goes low, is TSENSE_BUSY signal goes high to indicate that a temperature altered. If the user configures the part for partial power-down in conversion is in progress and remains high until the conversion a write to the control register during the first 16 SCLK cycles is completed. following TSENSE_BUSY going high, the temperature sensor The total time to measure and convert a temperature channel conversion is aborted and the part enters partial power-down th with the AD7298 is 100 μs max. Once the T _BUSY signal SENSE on the 16 SCLK falling edge. goes low to indicate that the temperature conversion is Thus, it is recommended not to write to the control register if completed, 100 ns must elapse prior to the next falling edge CS the signal will be toggling while TSENSE_BUSY is high. Care CS of . If a minimum of 100 ns is not adhered to between the should be taken to ensure that the WRITE bit is set to zero falling edge of TSENSE_BUSY and the subsequent falling edge of during the temperature conversion phase when CS is toggling. CS, the next conversion will be corrupted but the temperature If an SCLK frequency of more than 10 kHz is used, the result that is framed by the CS will not be affected. This temperature conversion requires more than one standard restriction is in place to ensure that sufficient acquisition time read cycle to complete. In this case, the user can monitor the is allowed for the next conversion. T _BUSY signal to determine when the conversion is SENSE Once the T _BUSY signal goes high, the user may provide a SENSE completed and the result is available for reading. CS falling edge to frame the read of the previous conversion and program the control register if required (see Figure 31). Once the previous conversion result has been read, any subsequent CS falling edges which occur while the T _BUSY SENSE signal is high are internally ignored by the AD7298. If addi- CS tional falling edges are provided while TSENSE_BUSY is high, the AD7298 provides an invalid digital output of all 1s. ENSURES ADEQUATE ACQUISITION THE TEMPERATURE TIME FOR NEXT ADC CONVERSION INTEGRATION BEGINS t 11 CS 11216 1 16 1 16 SCLK PREVIOUS CONVERSION TEMPERATURE SENSOR RESULT DOUT RESULT DATA WRITTEN TO CONTROL CONFIGURE CONTROL REGISTER DIN REGISTER CH T SELECTED FOR NEXT CONVERSION SENSE T _BUSY SENSE THE TEMPERATURE CONVERSION IS COMPLETED Figure 31. Serial Interface Timing Diagram for the Temperature Sensor Conversion Rev. B | Page 22 of 24 08754-015 AD7298 LAYOUT AND CONFIGURATION The best board layout technique is the microstrip technique POWER SUPPLY BYPASSING AND GROUNDING where the component side of the board is dedicated to the For optimum performance, carefully consider the power supply ground plane only and the signal traces are placed on the solder and ground return layout on any PCB where the AD7298 is side; however, this is not always possible with a 2-layer board. used. The PCB containing the AD7298 should have separate analog and digital sections, each having its own area of the TEMPERATURE MONITORING board. The AD7298 should be located in the analog section The AD7298 is ideal for monitoring the thermal environment. on any PCB. The die accurately reflects the exact thermal conditions that Decouple the power supply to the AD7298 to ground with affect nearby integrated circuits. The AD7298 measures and 10 μF and 0.1 μF capacitors. Place the capacitors as physically converts the temperature at the surface of its own semicon- close as possible to the device, with the 0.1 μF capacitor ideally ductor chip. right up against the device. It is important that the 0.1 μF When it is used to measure the temperature of a nearby heat capacitor have low effective series resistance (ESR) and low source, the thermal impedance between the heat source and the effective series inductance (ESL); common ceramic types of AD7298 must be considered. When the thermal impedance is capacitors are suitable. The 0.1 μF capacitor provides a low determined, the temperature of the heat source can be inferred impedance path to ground for high frequencies caused by from the AD7298 output. transient currents due to internal logic switching. The 10 μF As much as 60% of the heat transferred from the heat source to capacitors are the tantalum bead type. the thermal sensor on the AD7298 die is discharged via the The power supply line should have as large a trace as possible copper tracks and the bond pads. Of the pads on the AD7298, to provide a low impedance path and reduce glitch effects on the GND pad transfers most of the heat. Therefore, to measure the supply line. Shield clocks and other components with fast the temperature of a heat source, it is recommended that the switching digital signals from other parts of the board by a thermal resistance between the AD7298 GND pad and the digital ground. Avoid crossover of digital and analog signals, GND of the heat source be reduced as much as possible. if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. Rev. B | Page 23 of 24 AD7298 OUTLINE DIMENSIONS 4.10 0.30 4.00 SQ 0.25 3.90 0.18 PIN 1 INDICATOR 16 20 0.50 15 1 BSC EXPOSED 2.75 PAD 2.60 SQ 2.35 11 5 10 6 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. Figure 32. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very, Very Thin Quad (CP-20-8) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD7298BCPZ −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-8 AD7298BCPZ-RL7 −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-8 EVAL-AD7298SDZ Evaluation Board 1 Z = RoHS Compliant Part. ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08754-0-6/11(B) Rev. B | Page 24 of 24 N PI 1 INDICATOR 020509-B