ANALOG DEVICES AD7264

1 MSPS, 14-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators AD7264 FEATURES FUNCTIONAL BLOCK DIAGRAM AV V A CC REF Dual, simultaneous sampling, 14-bit, 2-channel ADC True differential analog inputs REF BUF AD7264 Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, ×128 14-BIT V + A SUCCESSIVE OUTPUT D A PGA T/H OUT APPROXIMATION Throughput rate per ADC DRIVERS V – A ADC 1 MSPS for AD7264 SCLK 500 kSPS for AD7264-5 CAL CS Analog input impedance: >1 GΩ REFSEL CONTROL Wide input bandwidth G0 LOGIC G1 −3 dB bandwidth: 1.7 MHz at gain = 2 G2 G3 4 on-chip comparators V DRIVE SNR: 78 dB typical at gain = 2, 71 dB typical at gain = 32 14-BIT V + B SUCCESSIVE OUTPUT Device offset calibration PGA T/H D B OUT APPROXIMATION DRIVERS V – B ADC System gain calibration PD0/D IN PD1 On-chip reference: 2.5 V BUF PD2 −40°C to +105°C operation V B REF High speed serial interface C _C V A B CC Compatible with SPI, QSPI™, MICROWIRE™, and DSP C + A OUTPUT C A OUT DRIVERS C – A 48-lead LFCSP and LQFP packages COMP C + B OUTPUT C B OUT DRIVERS C – B GENERAL DESCRIPTION COMP C _C _GND A B The AD7264 is a dual, 14-bit, high speed, low power, successive C _C V C D CC C + C OUTPUT approximation ADC that operates from a single 5 V power supply C C OUT DRIVERS C – C COMP and features throughput rates of up to 1 MSPS per on-chip C + D OUTPUT C D OUT C – DRIVERS ADC (500 kSPS for the AD7264-5). Two complete ADC func- D COMP C _C _GND C D tions allow simultaneous sampling and conversion of two channels. Each ADC is preceded by a true differential analog AGND DGND input with a PGA. There are 14 gain settings available: ×1, ×2, Figure 1. ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128. The AD7264 contains four comparators. Comparator A and PRODUCT HIGHLIGHTS Comparator B are optimized for low power, whereas Comparator C and Comparator D have fast propagation delays. The AD7264 1. Integrated PGA with a variety of flexible gain settings to features a calibration function to remove any device offset error allow detection and conversion of low level analog signals. and programmable gain adjust registers to allow for input path 2. Each PGA is followed by a dual simultaneous sampling (for example, sensor) offset and gain compensation. The AD7264 ADC, featuring throughput rates of 1 MSPS per ADC has an on-chip 2.5 V reference that can be disabled if an external (500 kSPS for the AD7264-5). The conversion result of reference is preferred. The AD7264 is available in 48-lead LFCSP both ADCs is simultaneously available on separate data and LQFP packages. lines or in succession on one data line if only one serial port is available. The AD7264 is ideally suited for monitoring small amplitude 3. Four integrated comparators that can be used to count signals from a variety of sensors. The parts include all the signals from pole sensors in motor control applications. functionality needed for monitoring the position feedback signals 4. Internal 2.5 V reference. from a variety of analog encoders used in motor control systems. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06732-001 AD7264 TABLE OF CONTENTS Features .............................................................................................. 1  Typical Connection Diagrams .................................................. 17  General Description ......................................................................... 1  Application Details ..................................................................... 19  Functional Block Diagram .............................................................. 1  Modes of Operation ....................................................................... 20  Product Highlights ........................................................................... 1  Pin Driven Mode ........................................................................ 20  Revision History ............................................................................... 2  Gain Selection ............................................................................. 20  Specif ica t ions ..................................................................................... 3  Power-Down Modes .................................................................. 20  Timing Specifications .................................................................. 6  Control Register ......................................................................... 21  Absolute Maximum Ratings ............................................................ 7  On-Chip Registers ...................................................................... 22  ESD Caution .................................................................................. 7  Serial Interface ................................................................................ 23  Pin Configuration and Function Descriptions ............................. 8  Calibration ....................................................................................... 25  Typical Performance Characteristics ........................................... 10  Internal Offset Calibration ........................................................ 25  Terminology .................................................................................... 14  Adjusting the Offset Calibration Register ............................... 26  Theory of Operation ...................................................................... 15  System Gain Calibration............................................................ 26  Circuit Information .................................................................... 15  Application Hints ........................................................................... 27  C om p ara tors ................................................................................ 15  Grounding and Layout .............................................................. 27  Operation ..................................................................................... 15  PCB Design Guidelines for LFCSP .......................................... 27  Analog Inputs .............................................................................. 15  Outline Dimensions ....................................................................... 28  VDRIVE ............................................................................................ 16  Ordering Guide .......................................................................... 29  Reference ..................................................................................... 16  REVISION HISTORY 7/08—Rev. 0 to Rev. A Added AD7264-5 ................................................................ Universal Added LQFP Package ......................................................... Universal Changes to Figure 1 .......................................................................... 1 Changes to Common-Mode Voltage Range, V Parameter ..... 3 CM Changes to Table 3 ............................................................................ 7 Changes to Pin Configuration and Function Description Section .......................................................................... 8 Changes to Figure 29 ...................................................................... 19 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 29 5/08—Revision 0: Initial Version Rev. A | Page 2 of 32 AD7264 SPECIFICATIONS AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fS = 1 MSPS and fSCLK = 34 MHz for the AD7264, fS = 500 kSPS and fSCLK = 20 MHz for the AD7264-5, VREF = 2.5 V internal/external; TA = −40°C to +105°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments 1 DYNAMIC PERFORMANCE fIN = 100 kHz sine wave 2 Signal-to-Noise Ratio (SNR) 76 78 dB PGA gain setting = 2 Signal-to-(Noise + Distortion) Ratio 74 77 dB 2 (SINAD) 2 Total Harmonic Distortion (THD) −85 −77 dB Spurious-Free Dynamic Range (SFDR) −97 dB Common-Mode Rejection Ratio (CMRR) −76 dB For PGA gain setting = 2, ripple frequency of 50 Hz/60 Hz; see Figure 17 and Figure 18 2 ADC-to-ADC Isolation −90 dB 3 Bandwidth 1.2 MHz @ −3 dB; PGA gain setting = 128 1.7 MHz @ −3 dB; PGA gain setting = 2 DC ACCURACY Resolution 14 Bits 2 Integral Nonlinearity ±1.5 ±3 LSB 2 Differential Nonlinearity ±0.5 ±0.99 LSB Guaranteed no missed codes to 14 bits 2 Positive Full-Scale Error ±0.122 ±0.305 % FSR Precalibration ±0.018 % FSR Postcalibration 2 Positive Full-Scale Error Match ±0.061 % FSR 2 Zero Code Error ±0.092 ±0.244 % FSR Precalibration ±0.012 % FSR Postcalibration 2 Zero Code Error Match ±0.061 % FSR 2 Negative Full-Scale Error ±0.122 ±0.305 % FSR Precalibration ±0.018 % FSR Postcalibration 2 Negative Full-Scale Error Match ±0.061 % FSR Zero Code Error Drift 2.5 μV/°C ANALOG INPUT Input Voltage Range, V + and V − V V = AV /2; PGA gain setting ≥ 2 IN IN CM CC V REF V ± CM 2× Gain Common-Mode Voltage Range, V V − 100 mV V + 100 mV V V = 2 V; PGA gain setting = 1; CM CM CM CM 4 see Figure 19 (VCC/2) − 0.4 (VCC/2) + 0.2 V VCM = AVCC/2; PGA gain setting = 2 (VCC/2) − 0.4 (VCC/2) + 0.4 V VCM = AVCC/2; 3 ≤ PGA gain setting ≤ 32 (V /2) − 0.6 (V /2) + 0.8 V V = AV /2; PGA gain setting ≥ 48 CC CC CM CC DC Leakage Current ±0.001 ±1 μA 3 Input Capacitance 5 pF 3 Input Impedance 1 GΩ REFERENCE INPUT/OUTPUT 5 Reference Output Voltage 2.495 2.5 2.505 V 2.5 V ± 5 mV max @ 25°C Reference Input Voltage 2.5 V DC Leakage Current ±0.3 ±1 μA External reference applied to Pin VREFA/Pin VREFB 3 Input Capacitance 20 pF 3 V A, V B Output Impedance 4 Ω REF REF Reference Temperature Coefficient 20 ppm/°C 3 VREF Noise 20 μV rms Rev. A | Page 3 of 32 AD7264 Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V Input Low Voltage, VINL 0.8 V Input Current, I ±1 μA V = 0 V or V IN IN DRIVE 3 Input Capacitance, C 4 pF IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V OH DRIVE Output Low Voltage, V 0.4 V OL Floating State Leakage Current ±1 μA 3 Floating State Output Capacitance 5 pF Output Coding Twos complement CONVERSION RATE Conversion Time 19 × tSCLK ns 2 Track-and-Hold Acquisition Time 400 ns Throughput Rate 1 MSPS AD7264 500 kSPS AD7264-5 COMPARATORS Input Offset Comparator A and Comparator B ±2 ±4 mV T = 25°C to 105°C only A Comparator C and Comparator D ±2 ±4 mV Offset Voltage Drift 0.5 μV/°C All comparators 3 Input Common-Mode Range 0 to 4 V CA_CBVCC = 5 V 0 to 1.7 V CA_CBVCC = 2.7 V 3 Input Capacitance 4 pF 3 Input Impedance 1 GΩ 6 IDD Normal Mode (Static) 25 pF load, COUTx = 0 V, VCM = AVCC/2, VOVERDRIVE = 200 mV differential Comparator A and Comparator B 3 μA CA_CBVCC = 3.3 V 6 8.5 μA C _C V = 5.25 V A B CC Comparator C and Comparator D 60 μA C _C V = 3.3 V C D CC 120 170 μA C _C V = 5.25 V C D CC 2 Propagation Delay Time VCM = AVCC/2, VOVERDRIVE = 200 mV differential High to Low, tPHL Comparator A and Comparator B 1.4 3.5 μs C _C V = 2.7 V A B CC 0.95 μs C _C V = 5 V A B CC Comparator C and Comparator D 0.20 0.32 μs CC_CDVCC = 2.7 V 0.13 μs CC_CDVCC = 5 V Low to High, tPLH Comparator A and Comparator B 2 4 μs C _C V = 2.7 V A B CC 0.93 μs C _C V = 5 V A B CC Comparator C and Comparator D 0.18 0.28 μs C _C V = 2.7 V C D CC 0.12 μs CC_CDVCC = 5 V Delay Matching VCM = AVCC/2, VOVERDRIVE = 200 mV differential Comparator A and Comparator B ±250 ns Comparator C and Comparator D ±10 ns Rev. A | Page 4 of 32 AD7264 Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS Digital inputs = 0 V or VDRIVE AVCC 4.75 5.25 V CA_CBVCC, CC_CDVCC 2.7 5.25 V V 2.7 5.25 V DRIVE I DD ADC Normal Mode (Static) 20 31.5 mA AV = 5.25 V CC ADC Normal Mode (Dynamic) 23 33.3 mA fS = 1 MSPS, AVCC = 5.25 V Shutdown Mode 0.5 1 μA AVCC = 5.25 V, ADCs and comparators powered down Power Dissipation ADC Normal Mode (Static) 105 165 mW ADC Normal Mode (Dynamic) 120 175 mW Shutdown Mode 2.625 5.25 μW 1 These specifications were determined without the use of the gain calibration feature. 2 See the Terminology section. 3 Samples are tested during initial release to ensure compliance; they are not subject to production testing. 4 For PGA gain = 1, to utilize the full analog input range (V ± V /2) of the AD7264, the V voltage should be dropped to lie within a range from 1.95 V to 2.05 V. CM REF CM 5 Refers to Pin VREFA or Pin VREFB. 6 This specification includes the I for both comparators. The I per comparator is the specified value divided by 2. DD DD Rev. A | Page 5 of 32 AD7264 TIMING SPECIFICATIONS 1 AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VREF = 2.5 V internal/external; TA = TMIN to TMAX, unless otherwise noted. Table 2. Limit at TMIN, TMAX Parameter 2.7 V ≤ VDRIVE ≤ 3.6 V 4.75 V ≤ VDRIVE ≤ 5.25 V Unit Description f 200 200 kHz min SCLK 2 34 34 MHz max AD7264 20 20 MHz max AD7264-5 tCONVERT 19 × tSCLK 19 × tSCLK ns max tSCLK = 1/fSCLK 560 560 ns max AD7264 950 950 ns max AD7264-5 t 13 13 ns min Minimum time between end of serial read/bus relinquish QUIET and next falling edge of CS t2 10 10 ns min CS to SCLK setup time 3 th t3 15 15 ns max Delay from 19 SCLK falling edge until DOUTA and DOUTB are three-state disabled t 29 23 ns max Data access time after SCLK falling edge 4 t 15 13 ns min SCLK to data valid hold time 5 t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t8 13 13 ns min CS rising edge to falling edge pulse width t 13 13 ns max CS rising edge to D A, D B high impedance/bus 9 OUT OUT relinquish t10 5 5 ns min SCLK falling edge to DOUTA, DOUTB high impedance 35 35 ns max SCLK falling edge to DOUTA, DOUTB high impedance t 2 2 μs min Minimum CAL pin high time 11 t12 2 2 μs min Minimum time between the CAL pin high and the CS falling edge t 3 3 ns min D setup time prior to SCLK falling edge 13 IN t 3 3 ns min D hold time after SCLK falling edge 14 IN t 240 240 μs max Internal reference, with a 1 μF decoupling capacitor POWER-UP 15 15 μs max With an external reference, 10 μs typical 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Terminology section. 2 The AD7264 is functional with a 40 MHz SCLK at 25°C, but specified performance is not guaranteed with SCLK frequencies greater than 34 MHz. 3 The time required for the output to cross 0.4 V or 2.4 V. CS t 8 t 2 t 6 SCLK15 23 4 1819 20 21 31 32 33 t t 7 9 t t 5 3 t t 4 QUIET DB13 DB12 DB11 DB1 DB0 D A A A A A A OUT THREE-STATE THREE- STATE DB13 DB12 DB11 DB1 DB0 D B B B B B B OUT THREE-STATE THREE- STATE Figure 2. Serial Interface Timing Diagram Rev. A | Page 6 of 32 06732-002 AD7264 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 3. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to DGND −0.3 V to AV DRIVE CC other conditions above those indicated in the operational V to AGND −0.3 V to AV DRIVE CC section of this specification is not implied. Exposure to absolute AVCC to AGND, DGND −0.3 V to +7 V maximum rating conditions for extended periods may affect CA_CBVCC to CA_CB_GND −0.3 V to +7 V device reliability. C _C V to C _C _GND −0.3 V to +7 V C D CC C D AGND to DGND −0.3 V to +0.3 V CA_CB_GND, CC_CD_GND to DGND −0.3 V to +0.3 V ESD CAUTION Analog Input Voltage to AGND −0.3 V to AVCC + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V + 0.3 V DRIVE V A, V B Input to AGND −0.3 V to AV + 0.3 V REF REF CC C A, C B, C C, C D to GND −0.3 V to V + 0.3 V OUT OUT OUT OUT DRIVE CA±, CB±, CC±, CD± to −0.3 V to CA_CB_GND, CC_CD_GND CA_CBVCC/CC_CDVCC + 0.3 V Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C LQFP Package θJA Thermal Impedance 55°C/W θJC Thermal Impedance 16°C/W LFCSP Package θ Thermal Impedance 30°C/W JA θ Thermal Impedance 3°C/W JC Pb-Free Temperature, Soldering Reflow 255°C ESD 2 kV Rev. A | Page 7 of 32 V + B V + B AD7264 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 C _C V 1 36 CAL A B CC PIN 1 AV 2 CS 1 36 CAL INDICATOR 35 C _C V CC A B CC PIN 1 V – SCLK 3 34 2 35 CS A AV INDICATOR CC AV V + 4 33 CC A 34 SCLK V – 3 A D A AGND 5 32 OUT 33 AV V + 4 AD7264 A CC D B AGND 6 31 OUT TOP VIEW 32 D A AGND 5 OUT C A AV 7 30 CC (Not to Scale) OUT AD7264 6 31 D B AGND OUT AGND 8 29 C B OUT TOP VIEW AV 7 30 C A CC (Not to Scale) OUT 9 28 DGND 8 29 C B V – V AGND OUT B 10 27 DRIVE AV C C 9 28 DGND CC 11 26 OUT C _C V C D C D CC 12 25 10 27 V OUT DRIVE V – B AV 11 26 C C CC OUT C _C V C D CC 12 25 C D OUT 13 14 15 16 17 18 19 20 21 22 23 24 NOTES 1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR NOISE AND MECHANICAL STRENGTH BENEFITS. Figure 4. 48-Lead LFCSP Pin Configuration Figure 3. 48-Lead LQFP Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 2, 7, 11, 20, 33, 41 AV Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the CC AD7264. All AVCC pins can be tied together. This supply should be decoupled to AGND with a 100 nF ceramic capacitor per supply and a 10 μF tantalum capacitor. 1 CA_CBVCC Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and Comparator B. This supply should be decoupled to C _C _GND. AV , C _C V , and C _C V can be A B CC C D CC A B CC tied together. 12 C _C V Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and C D CC Comparator D. This supply should be decoupled to CC_CD_GND. AVCC, CC_CDVCC, and CA_CBVCC can be tied together. 4, 3 VA+, VA− Analog Inputs of ADC A. True differential input pair. 9, 10 V +, V − Analog Inputs of ADC B. True differential input pair. B B 43, 18 V A, V B Reference Input/Output. Decoupling capacitors are connected to these pins to decouple the REF REF internal reference buffer for each respective ADC. Typically, 1 μF capacitors are required to decouple the reference. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. 34 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7264. This clock is also used as the clock source for the conversion process. A minimum of 33 clocks are required to perform the conversion and access the 14-bit result. 35 CS Chip Select. Active low logic input. This input initiates conversions on the AD7264. 36 CAL Logic Input. Initiates an internal offset calibration. 21 PD2 Logic Input. Places the AD7264 in the selected shutdown mode in conjunction with the PD1 and PD0 pins. See Table 7. 22 PD1 Logic Input. Places the AD7264 in the selected shutdown mode in conjunction with the PD2 and PD0 pins. See Table 7. 23 PD0/DIN Logic Input/Data Input. Places the AD7264 in the selected shutdown mode in conjunction with the PD2 and PD1 pins. See Table 7. If all gain selection pins, G0 to G3, are tied low, this pin acts as the data input pin and all programming is via the control register (see Table 8). Data to be written to the AD7264 control register is provided on this input and is clocked into the register on the falling edge of SCLK. Rev. A | Page 8 of 32 C + C + C A C – C – C A C + C + D B C – D C – B C _C _GND C _C _GND C D A B V B V A REF REF AGND AGND AV AV CC CC G0 PD2 G1 PD1 PD0/D G2 IN REFSEL G3 06732-003 C + C + 48 C 13 A C – C – C 14 47 A C + C + D 15 46 B C – C – D 16 45 B C _C _GND C _C _GND C D 17 44 A B V B V A 18 43 REF REF AGND 19 42 AGND AV AV CC 20 41 CC PD2 G0 21 40 PD1 22 39 G1 PD0/D 23 38 G2 IN REFSEL 24 37 G3 06732-004 AD7264 Pin No. Mnemonic Description 48, 47, 46, 45 CA+, CA−, Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator A CB+, CB− and Comparator B. These two comparators have very low power consumption. 13, 14, 15, 16 CC+, CC−, Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator C C +, C − and Comparator D. These two comparators offer very fast propagation delays. D D 5, 6, 8, 19, 42 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7264. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected to the AGND plane of a system. The AGND, DGND, CA_CB_GND, and CC_CD_GND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. C _C _GND and C _C _GND can be tied to AGND. A B C D 28 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7264. The DGND pin should be connected to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 30, 29, 26, 25 COUTA, COUTB, Comparator Outputs. These pins provide a CMOS (push-pull) output from each respective COUTC, COUTD comparator. These are digital output pins with logic levels determined by the VDRIVE supply. 32, 31 D A, D B Serial Data Outputs. The data output from the AD7264 is supplied to each pin as a serial data stream OUT OUT in twos complement format. The bits are clocked out on the falling edge of the SCLK input. A total of 33 SCLK cycles are required to perform the conversion and access the 14-bit data. During the conversion process, the data output pins are in three-state and, when the conversion is completed, th the 19 SCLK edge clocks out the MSB. The data appears simultaneously on both pins from the simultaneous conversions of both ADCs. The data is provided MSB first. If CS is held low for a further 14 SCLK cycles on either D A or D B following the initial 33 SCLK cycles, the data from the other OUT OUT ADC follows on the D pin. This allows data from a simultaneous conversion on both ADCs to be OUT gathered in serial format on either DOUTA or DOUTB using only one serial port. 40, 39, 38, 37 G0, G1, G2, G3 Logic Inputs. These pins are used to program the gain setting of the front-end amplifiers. If all four pins are tied low, the PD0/DIN pin acts as a data input pin, DIN, and all programming is made via the control register. See Table 6. 27 V Logic Power Supply Input, 2.7 V to 5.25 V. The voltage supplied at this pin determines at what DRIVE voltage the interface operates, including the comparator outputs. This pin should be decoupled to DGND. 44, 17 CA_CB_GND, Comparator Ground. Ground reference point for all comparator circuitry on the AD7264. Both the CC_CD_GND CA_CB_GND and CC_CD_GND pins should connect to the GND plane of a system and can be tied to AGND. The DGND, AGND, C _C _GND, and C _C _GND voltages should ideally be at the same A B C D potential and must not be more than 0.3 V apart, even on a transient basis. 24 REFSEL Internal/External Reference Selection. Logic input. If this pin is tied to a logic high voltage, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7264 through the VREFA and/or V B pins. REF Rev. A | Page 9 of 32 AD7264 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 AV = 5V CC V = 5V DRIVE –0.6 –0.6 f = 1MSPS S AV = 5V T = 25°C CC A T = 25°C A –0.8 –0.8 V = 5V INTERNAL REFERENCE DRIVE INTERNAL REFERENCE f = 1MSPS GAIN = 32 S GAIN = 2 –1.0 –1.0 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 CODE CODE Figure 5. Typical DNL at Gain of 2 Figure 8. Typical DNL at Gain of 32 2.0 2.0 AV = 5V CC V = 5V DRIVE 1.5 –1.5 f = 1MSPS S T = 25°C A INTERNAL REFERENCE 1.0 –1.0 GAIN = 32 0.5 –0.5 0 0 –0.5 –0.5 AV = 5V CC –1.0 –1.0 V = 5V DRIVE f = 1MSPS S T = 25°C –1.5 A –1.5 INTERNAL REFERENCE GAIN = 2 –2.0 –2.0 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 CODE CODE Figure 6. Typical INL at Gain of 2 Figure 9. Typical INL at Gain of 32 0 0 AV = 5V AV = 5V CC CC V = 2.7V V = 2.7V DRIVE DRIVE –20 f = 1MSPS –20 f = 1MSPS S S T = 25°C T = 25°C A A f = 100kHz f = 100kHz IN IN –40 INTERNAL REFERENCE –40 INTERNAL REFERENCE SNR = 79dB SNR = 72dB THD = –96dB THD = –87dB –60 –60 GAIN = 2 GAIN = 32 –80 –80 –100 –100 –120 –120 –140 –140 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (kHz) FREQUENCY (kHz) Figure 7. Typical FFT at Gain of 2 Figure 10. Typical FFT at Gain of 32 Rev. A | Page 10 of 32 (dB) INL ERROR (LSB) DNL ERROR (LSB) 06732-009 06732-006 06732-005 DNL ERROR (LSB) (dB) INL ERROR (LSB) 06732-010 06732-008 06732-007 AD7264 8000 2.4968 7793 7000 2.4967 6000 2.4966 5000 2.4965 4000 2.4964 3000 2.4963 2000 AV = 5V CC 1117 1084 V = 3V 2.4962 DRIVE 1000 f = 1MSPS S 6 INTERNAL REFERENCE 0 0 0 2.4961 8189 8190 8191 8192 8193 8194 0 20 40 60 80 100 120 140 160 180 200 CODE CURRENT LOAD (µA) Figure 11. Histogram of Codes for 10k Samples at Gain of 2 Figure 14. VREF vs. Reference Output Current Drive 3000 1900 1800 2486 1700 2500 2180 1600 1500 2000 1861 1400 1300 1500 1200 1222 1081 1100 1000 1000 900 498 381 AV = 5V CC 500 800 V = 5V DRIVE f = 1MSPS 132 S 700 82 22 16 INTERNAL REFERENCE 2 0 600 8188 8190 8192 8194 8196 8186 1 2 3 4 6 8 12 162432 486496 128 8187 8189 8191 8193 8195 8197 GAIN CODE Figure 12. Histogram of Codes for 10k Samples at Gain of 32 Figure 15. 3 dB Bandwidth vs. Gain –65 80 AV = 5V CC V = 5V DRIVE 75 f = 1MSPS S INTERNAL REFERENCE –70 70 GAIN = 32 65 –75 60 55 GAIN = 2 –80 50 45 AV = 5V CC –85 40 V = 5V DRIVE f = 1MSPS S 35 INTERNAL REFERENCE f = 100kHz IN –90 30 10 110 210 310 410 510 610 710 810 910 1234 68 12 16 24 32 48 64 96128 ANALOG INPUT FREQUENCY (kHz) PGA GAIN Figure 13. THD vs. Analog Input Frequency up to 1 MHz at Gain of 2 and 32 Figure 16. SNR vs. PGA Gain for an Analog Input Tone of 100 kHz Rev. A | Page 11 of 32 THD (dB) NUMBER OF HITS NUMBER OF HITS 06732-012 06732-011 06732-014 V (V) REF SNR (dB) 3dB BANDWIDTH (kHz) 06732-017 06732-016 06732-015 AD7264 –90 10 AV = 5V CC V = 3.3V –88 9 DRIVE T = 25°C A –86 8 H TO L, C _C V = 3.6V A B CC –84 7 H TO L, C _C V = 4.5V A B CC H TO L, C _C V = 2.7V A B CC –82 6 H TO L, C _C V = 5V A B CC L TO H, C _C V = 2.7V –80 5 A B CC L TO H, C _C V = 3.6V A B CC –78 4 L TO H, C _C V = 4.5V A B CC _C V = 5V L TO H, C A B CC –76 3 AV = 5V CC –74 2 V = 5V DRIVE f = 1MSPS S –72 INTERNAL REFERENCE 1 f = 50kHz RIPPLE –70 0 1 2346 8 12 16 24 32 48 64 96128 0 1020 3040 5060 708090 100 GAIN OVERDRIVE VOLTAGE (mV) Figure 20. Propagation Delay for Comparator A and Comparator B Figure 17. Common-Mode Rejection vs. Gain vs. Overdrive Voltage for Various Supply Voltages 2.0 –80 AV = 5V CC V = 3.3V 1.8 DRIVE –79 T = 25°C A 1.6 –78 1.4 –77 L TO H, C _C V = 2.7V C D CC L TO H, C _C V = 3.6V C D CC 1.2 –76 L TO H, C _C V = 4.5V C D CC 1.0 L TO H, C _C V = 5V –75 C D CC H TO L, C _C V = 2.7V C D CC 0.8 –74 H TO L, C _C V = 3.6V C D CC H TO L, C _C V = 5V C D CC 0.6 –73 AV = 5V CC H TO L, C _C V = 4.5V C D CC V = 5V DRIVE 0.4 –72 f = 1MSPS S V = 700mV p-p RIPPLE 0.2 –71 GAIN = 2 INTERNAL REFERENCE 0 –70 0 102030405060 708090 100 0 20 40 60 80 100 120 140 160 180 200 OVERDRIVE VOLTAGE (mV) RIPPLE FREQUENCY (kHz) Figure 21. Propagation Delay for Comparator C and Comparator D Figure 18. Common-Mode Rejection vs. Common-Mode Ripple Frequency vs. Overdrive Voltage for Various Supply Voltages –70 –10 V = 5V AV = 5V DRIVE CC G = 1 GAIN = 2 V = 5V –75 DRIVE –20 T = 25°C f = 1MSPS A S G = 2 INTERNAL REFERENCE f = 100kHz –80 IN –30 100mV p-p SINE WAVE ON AV INTERNAL REFERENCE CC AV DECOUPLED WITH –85 CC G = 3 10µF AND 100nF CAPACITORS –40 –90 G = 4 –50 –95 –60 –100 G = 6 –70 –105 G = 16 –80 G ≥ 32 –110 G = 24 –90 –115 G = 12 G = 8 –120 –100 0 200 400 600 800 1000 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 SUPPLY RIPPLE FREQUENCY (kHz) V RANGE (V) CM Figure 22. Power Supply Rejection Ratio Figure 19. THD vs. Common-Mode Voltage Range for Various PGA Gain Settings Rev. A | Page 12 of 32 THD (dB) CMR (dB) CMR (dB) 06732-018 06732-020 06732-019 PROPAGATION DELAY (µs) PROPAGATION DELAY (µs) PSRR (dB) 06732-036 06732-022 06732-021 AD7264 300 C A/C B SINK CURRENT OUT OUT C C/C D SINK CURRENT OUT OUT 200 D SINK CURRENT OUT 100 0 –100 D SOURCE CURRENT OUT –200 C A/C B SOURCE CURRENT OUT OUT C C/C D SOURCE CURRENT OUT OUT –300 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 CURRENT (mA) Figure 23. D and C Source and Sink Current OUT OUT Rev. A | Page 13 of 32 V (V) OR V – V (mV) OUT DD OUT 06732-037 AD7264 TERMINOLOGY Differential Nonlinearity (DNL) The theoretical signal-to-(noise + distortion) ratio for an ideal Differential nonlinearity is the difference between the measured N-bit converter with a sine wave input is given by and the ideal 1 LSB change between any two adjacent codes in Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB the ADC. Thus, for a 14-bit converter, this is 86 dB. Integral Nonlinearity (INL) Total Harmonic Distortion (THD) Integral nonlinearity is the maximum deviation from a straight Total harmonic distortion is the ratio of the rms sum of line passing through the endpoints of the ADC transfer function. harmonics to the fundamental. For the AD7264, it is defined as The endpoints of the transfer function are zero scale, a single (1) LSB point below the first code transition, and full scale, a 2 2 2 2 2 V +V +V +V +V 2 3 4 5 6 THD(dB)= 20 log point 1 LSB above the last code transition. V 1 Zero Code Error where V is the rms amplitude of the fundamental and V , V , 1 2 3 This is the deviation of the midscale transition (all 1s to all 0s) V4, V5, and V6 are the rms amplitudes of the second through the from the ideal V voltage, that is, V − ½ LSB. IN CM sixth harmonics. Positive Full-Scale Error Peak Harmonic or Spurious Noise This is the deviation of the last code transition (011 … 110 to Peak harmonic, or spurious noise, is defined as the ratio of the 011 … 111) from the ideal, that is, rms value of the next largest component in the ADC output V ⎛ ⎞ REF spectrum (up to f /2, excluding dc) to the rms value of the fun- S V + − 1 LSB ⎜ ⎟ CM 2× Gain ⎝ ⎠ damental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where after the zero code error has been adjusted out. the harmonics are buried in the noise floor, it is a noise peak. Negative Full-Scale Error ADC-to-ADC Isolation This is the deviation of the first code transition (10 … 000 to ADC-to-ADC isolation is a measure of the level of crosstalk 10 … 001) from the ideal, that is, between ADC A and ADC B. It is measured by applying a full- V ⎛ ⎞ REF scale, 100 kHz sine wave signal to all unselected input channels and V − + 1 LSB ⎜ ⎟ CM 2× Gain ⎝ ⎠ determining how much that signal is attenuated in the selected channel with a 40 kHz signal. The figure given is the worst-case. after the zero code error has been adjusted out. Power Supply Rejection Ration (PSRR) Zero Code Error Match Variations in power supply affect the full-scale transition but This is the difference in zero code error across both ADCs. not the linearity of the converter. PSRR is the maximum change Positive Full-Scale Error Match in the full-scale transition point due to a change in power This is the difference in positive full-scale error across both ADCs. supply voltage from the nominal value (see Figure 22). Negative Full-Scale Error Match Propagation Delay Time, Low to High (t ) PLH This is the difference in negative full-scale error across both ADCs. Propagation delay time from low to high is defined as the time Track-and-Hold Acquisition Time taken from the 50% point on a low to high input signal until the The track-and-hold amplifier returns to track mode at the end digital output signal reaches 50% of its final low value. of conversion. Track-and-hold acquisition time is the time Propagation Delay Time, High to Low (tPHL) required for the output of the track-and-hold amplifier to reach Propagation delay time from high to low is defined as the time its final value, within ±1/2 LSB, after the end of conversion. taken from the 50% point on a high to low input signal until the Signal-to-(Noise + Distortion) Ratio digital output signal reaches 50% of its final high value. This ratio is the measured ratio of signal-to-(noise + distortion) Comparator Offset at the output of the analog-to-digital converter. The signal is the Comparator offset is the measure of the density of digital 1s rms amplitude of the fundamental. Noise is the sum of all non- and 0s in the comparator output when the negative analog fundamental signals up to half the sampling frequency (f /2), S terminal of the comparator input is held at a static potential, excluding dc. The ratio is dependent on the number of quan- and the analog input to the positive terminal of the comparators tization levels in the digitization process; the more levels, the is varied proportionally about the static negative terminal voltage. smaller the quantization noise. Rev. A | Page 14 of 32 AD7264 THEORY OF OPERATION and CC_CDVCC can be tied to the AVCC supply. The four compa- CIRCUIT INFORMATION rators on the AD7264 are functional with CA_CBVCC, CC_CDVCC The AD7264 is a fast, dual, simultaneous sampling, differential, greater than or equal to 1.8 V. However, no specifications are 14-bit, serial ADCs. The AD7264 contains two on-chip diffe- guaranteed for comparator supplies less than 2.7 V. The wide rential programmable gain amplifiers, two track-and-hold range of supply voltages ensures that the comparators can be amplifiers, and two successive approximation analog-to-digital used in a variety of battery backup modes. converters with a serial interface with two separate data output The four on-chip comparators on the AD7264 are ideally suited pins. The AD7264 also includes four on-chip comparators. The for monitoring signals from pole sensors in motor control part is housed in a 48-lead LFCSP or 48-lead LQFP package, offering the user considerable space-saving advantages over systems. The comparators can be used to monitor signals from alternative solutions. The AD7264 requires a low voltage 5 V ± Hall effect sensors or the inner tracks from an optical encoder. 5% AV to power the ADC core and supply the digital power, a One of the comparators can be used to count the index marker CC _C V , C _C V supply for the comparators, or z marker, which is used on startup to place the motor in a 2.7 V to 5.25 V CA B CC C D CC known position. and a 2.7 V to 5.25 V VDRIVE supply for interface power. The on-board PGA allows the user to select from 14 program- OPERATION mable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, The AD7264 has two successive approximation ADCs, each ×48, ×64, ×96, and ×128. The PGA accepts fully differential based around two capacitive DACs and two programmable gain analog signals. The gain can be selected either by setting the amplifiers. logic state of the G0 to G3 pins or by programming the control The ADC itself comprises control logic, a SAR, and two capacitive register. DACs. The control logic and the charge redistribution DACs are The serial clock input accesses data from the part while also used to add and subtract fixed amounts of charge from the sam- providing the clock source for each successive approximation pling capacitor amplifiers to bring the comparator back into a ADC. The AD7264 has an on-chip 2.5 V reference that can be balanced condition. When the comparator is rebalanced, the disabled when an external reference is preferred. If the internal conversion is complete. The control logic generates the ADC reference is used elsewhere in a system, the output from V A REF output code. and V B must first be buffered. If the internal reference is the REF Each ADC is preceded by its own programmable gain stage. preferred option, the user must tie the REFSEL pin to a logic The PGA features high analog input impedance, true differential high voltage. Alternatively, if REFSEL is tied to GND, an analog inputs that allow the output from any source or sensor to external reference can be supplied to both ADCs through the be connected directly to the PGA inputs without any requirement VREFA and VREFB pins (see the Reference section). for additional external buffering. The variable gain settings ensure The AD7264 also features a range of power-down options to that the device can be used for amplifying signals from a variety allow the user great flexibility with the independent circuit of sources. The AD7264 offers the flexibility to choose the most components while allowing for power savings between conver- appropriate gain setting to utilize the wide dynamic range of sions. The power-down feature is implemented via the control the device. register or the PD0 to PD2 pins, as described in the Control ANALOG INPUTS Register section. Each ADC in the AD7264 has two high impedance differential COMPARATORS analog inputs. Figure 24 shows the equivalent circuit of the The AD7264 has four on-chip comparators. Comparator A and analog input structure of the AD7264. It consists of a fully Comparator B have ultralow power consumption, with static differential input amplifier that buffers the analog input signal power consumption typically less than 10 μW with a 3.3 V and provides the gain selected by using the gain pins. supply. Comparator C and Comparator D feature very fast The two diodes provide ESD protection. Care must be taken propagation delays of 130 ns for a 200 mV differential overdrive. to ensure that the analog input signals never exceed the supply These comparators have push-pull output stages that operate rails by more than 300 mV. This causes these diodes to become from the V supply. This feature allows operation with a DRIVE forward-biased and to start conducting current into the sub- minimum amount of power consumption. strate. These diodes can conduct up to 10 mA without causing Each pair of comparators operates from its own independent irreversible damage to the part. The C1 capacitors in Figure 24 supply, C _C V or C _C V . The comparators are specified A B CC C D CC are typically 5 pF and can primarily be attributed to pin for supply voltages from 2.7 V to 5.25 V. If desired, CA_CBVCC capacitance. Rev. A | Page 15 of 32 AD7264 V DD ⎛ ⎞ ⎛ V ⎞ ⎛ V ⎞ ⎛ ⎞ ⎛ ⎞ REF REF ⎜ ⎟ ⎜V + ⎟−⎜V − ⎟ ⎜ ⎟ ⎜ ⎟ CM CM ⎜ ⎟ ⎜ ⎟ ⎜ 2×Gain 2×Gain ⎟ ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ ⎝ ⎠ 2× V + IN ⎜ ⎟ V + 16,384 AMP OUT C1 ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ 011...111 V DD 011...110 AMP V – OUT V – IN 000...001 C1 000...000 111...111 Figure 24. Analog Input Structure The AD7264 can accept differential analog inputs from 100...010 V V ⎛ ⎞ ⎛ ⎞ REF REF 100...001 V − to V + . ⎜ ⎟ ⎜ ⎟ CM CM 100...000 2× Gain 2× Gain ⎝ ⎠ ⎝ ⎠ 0V Table 5 details the analog input range for the AD7264 for the (V – (FSR/2)) + 1LSB (V + (FSR/2)) – 1LSB CM CM ANALOG INPUT various PGA gain settings. V = 2.5 V and V = 2.5 V REF CM NOTES (AV /2, with AV = 5 V). CC CC 1. FULL-SCALE RANGE (FSR) = V + – V –. IN IN Figure 25. Twos Complement Transfer Function Table 5. Analog Input Range for Various PGA Gain Settings PGA Gain Setting Analog Input Range for V + and V − IN IN V DRIVE 1 1 0.75 V to 3.25 V The AD7264 has a V feature to control the voltage at which DRIVE 2 1.875 V to 3.125 V the serial interface operates. VDRIVE allows the ADC and the 3 2.083 V to 2.916 V comparators to easily interface to both 3 V and 5 V processors. 4 2.187 V to 2.813 V For example, when the AD7264 is operated with AVCC = 5 V, the 6 2.292 V to 2.708 V VDRIVE pin can be powered from a 3 V supply, allowing a large 8 2.344 V to 2.656 V analog input range with low voltage digital processors. 12 2.396 V to 2.604 V REFERENCE 16 2.422 V to 2.578 V 24 2.448 V to 2.552 V The AD7264 can operate with either the internal 2.5 V on-chip 32 2.461 V to 2.539 V reference or an externally applied reference. The logic state of 48 2.474 V to 2.526 V the REFSEL pin determines whether the internal reference is 64 2.480 V to 2.520 V used. The internal reference is selected for both ADCs when the 96 2.487 V to 2.513 V REFSEL pin is tied to logic high. If the REFSEL pin is tied to 128 2.490 V to 2.510 V AGND, an external reference can be supplied through the VREFA and/or VREFB pins. On power-up, the REFSEL pin must be tied to 1 For V = 2 V. If V = AV /2, the analog input range for V + and V − is 1.6 V CM CM CC IN IN either a low or high logic state for the part to operate. Suitable to 3.4 V. reference sources for the AD7264 include the AD780, AD1582, When a full-scale step input is applied to either differential ADR431, REF193, and ADR391. input on the AD7264 while the other analog input is held at a constant voltage, 3 μs of settling time is typically required prior The internal reference circuitry consists of a 2.5 V band gap refer- to capturing a stable digital output code. ence and a reference buffer. When operating the AD7264 in internal reference mode, the 2.5 V internal reference is available at Transfer Function the VREFA and VREFB pins, which should be decoupled to AGND The AD7264 output is twos complement; the ideal transfer using a 1 μF capacitor. It is recommended that the internal refer- function is shown in Figure 25. The designed code transitions ence be buffered before applying it elsewhere in the system. The occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and internal reference is capable of sourcing up to 90 μA of current so on). The LSB size is dependent on the analog input range when the converter is static. If internal reference operation is selected. required for the ADC conversion, the REFSEL pin must be tied to logic high on power-up. The reference buffer requires 240 μs The LSB size for the AD7264 is to power up and charge the 1 μF decoupling capacitor during the power-up time. Rev. A | Page 16 of 32 06732-024 ADC CODE 06732-025 AD7264 pin driven mode. Both circuit configurations illustrate the use TYPICAL CONNECTION DIAGRAMS of the internal 2.5 V reference. Figure 26 and Figure 27 are typical connection diagrams for the The C _C V and C _C V pins can be connected to either a AD7264. In these configurations, the AGND pin is connected A B CC C D CC to the analog ground plane of the system, and the DGND pin is 3 V or 5 V supply voltage. The AVCC pin must be connected to connected to the digital ground plane of the system. The analog a 5 V supply. All supplies should be decoupled with a 100 nF inputs on the AD7264 are true differential and have an input capacitor at the device pin, and some supply sources may impedance in excess of 1 GΩ; thus, no driving op amps are require a 10 μF capacitor where the source is supplied to the circuit board. The V pin is connected to the supply voltage required. The AD7264 can operate with either an internal or an DRIVE of the microprocessor. The voltage applied to the V input external reference. In Figure 26, the AD7264 is configured to DRIVE controls the voltage of the serial interface. V can be set to operate in control register mode; thus, G0 to G3, PD1, and PD2 DRIVE 3 V or 5 V. can be connected to ground (low logic state). Figure 27 has the gain pins configured for a gain of 2 setup; thus, the device is in +5V ANALOG SUPPLY 1 100nF 10µF 100nF 100nF 1 100nF 10µF 100nF COMPARATOR 2 SUPPLY 3V TO 5V 100nF 100nF 100nF 17 44 5 6 8 19 42 28 2 7 11 20 41 12 1 33 3.125V 27 3 3V OR 5V V V DRIVE DRIVE V 2.500V A– SUPPLY V AND V 1 A– A+ 100nF 10µF 1.875V 40 CONNECT GAIN 2 G0 39 DIRECTLY G1 TO SENSOR 3.125V 38 G2 4 OUTPUTS V 37 2.500V A+ G3 1.875V GAIN 2 SERIAL INTERFACE 43 V A REF 34 SCLK THIS REFERENCE SIGNAL 1µF MUST BE BUFFERED 35 AD7264 BEFORE IT CAN BE CS MICROPROCESSOR/ USED ELSEWHERE IN MICROCONTROLLER 32 THE CIRCUIT D A OUT 18 V B REF 31 D B OUT 1µF 24 V REFSEL DRIVE 36 CAL 3.125V 9 2.500V V B+ V AND V B– B+ 23 CONNECT 1.875V PD0/D IN GAIN 2 DIRECTLY 22 PD1 TO SENSOR 3.125V OUTPUTS 10 21 V 2.500V B– PD2 1.875V GAIN 2 13 14 15 16 45 46 47 48 25 26 29 30 FAST PROPAGATION DELAY LOW POWER COMPARATOR INPUTS COMPARATOR INPUTS 1 THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE REQUIRED IN ALL SYSTEMS. 2 THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED. Figure 26. Typical Connection Diagram for the AD7264 in Control Register Mode (All Gain Pins Tied to Ground) Configured for a PGA Gain of 2 Rev. A | Page 17 of 32 C C+ C C C GND C– D– C– C C GND C A– B– D+ AGND C D– AGND AGND AGND AGND DGND C B– AV CC C B+ C AV CC A– C AV CC A+ AV CC AV C D CC OUT C C V C– D CC C C OUT C C V A– B CC C B OUT AV C A CC OUT 06732-026 AD7264 +5V ANALOG SUPPLY 1 100nF 10µF 100nF 100nF 1 100nF 10µF 100nF COMPARATOR 2 SUPPLY 3V TO 5V 100nF 100nF 100nF 17 44 5 6 8 19 42 28 2 7 11 20 41 12 1 33 3.125V 27 3 3V OR 5V V V V DRIVE DRIVE 2.500V A– SUPPLY V AND V 1 A– A+ 100nF 10µF 1.875V 40 CONNECT GAIN 2 G0 DIRECTLY 39 V G1 DRIVE TO SENSOR 3.125V 38 G2 4 OUTPUTS V 37 GAIN 2 2.500V A+ G3 SETUP 1.875V GAIN 2 SERIAL INTERFACE 43 V A 34 REF SCLK THIS REFERENCE SIGNAL 1µF MUST BE BUFFERED 35 AD7264 MICROPROCESSOR/ BEFORE IT CAN BE CS MICROCONTROLLER USED ELSEWHERE IN 32 THE CIRCUIT D A OUT 18 V B REF 31 D B OUT 1µF 24 V REFSEL DRIVE 36 CAL 3.125V 9 2.500V V B+ V AND V B– B+ 23 PD0/D V CONNECT 1.875V DRIVE IN GAIN 2 BOTH DIRECTLY 22 PD1 COMPARATORS TO SENSOR 3.125V AND ADCs OUTPUTS 10 21 POWERED ON V B– 2.500V PD2 V DRIVE 1.875V GAIN 2 13 14 15 16 45 46 47 48 25 26 29 30 FAST PROPAGATION DELAY LOW POWER COMPARATOR INPUTS COMPARATOR INPUTS 1 THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE REQUIRED IN ALL SYSTEMS. 2 THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED. Figure 27. Typical Connection Diagram for the AD7264 in Pin Driven Mode with Gain of 2 and Both ADCs and Comparators Fully Powered On Comparator Application Details The amount of hysteresis chosen must be sufficient to eliminate the effects of analog noise at the comparator inputs, which may The comparators on the AD7264 have been designed with no affect the stability of the comparator outputs. The level of internal hysteresis, allowing users the flexibility to add external hysteresis required in any system depends on the noise in the hysteretic if required for systems operating in noisy environments. system; thus, the value of RF and RS needs to be carefully selected If the comparators on the AD7264 are used with external hyste- to eliminate any noise effects. To increase the level of hysteresis in resis, some external resistors and capacitors are required, as the system, increase the value of R or R . For example, R = 10 MΩ, S F F shown in Figure 28. The value of R and R , the external resistors, F S R = 1 kΩ gives 330 μV of hysteresis with a C _C V of 3.3 V; if S x x CC can be determined using the following equation, depending on hysteresis is increased to 1 mV, R = 3.1 kΩ. In certain applications, S the amount of hysteresis required in the application: a load capacitor (100 pF) may be required on the comparator R S outputs to suppress high frequency transient glitches. V = × C _C V HYS X X CC R + R S F where CX_CXVCC = CA_CBVCC or CC_CDVCC. Rev. A | Page 18 of 32 C C+ C C C GND C– D– C– C C GND A– B– C D+ AGND C D– AGND AGND AGND AGND C DGND B– C AV B+ CC C AV A– CC AV C A+ CC AV CC AV C D CC OUT C C V C C C– D CC OUT C C V C B A– B CC OUT AV C A CC OUT 06732-027 AD7264 R F variety of sensors, which results in reduced design cycles and R costs. S C x– R C x SENSOR OUT S C x+ The two simultaneous sampling ADCs are used to sample the sine and cosine outputs from the sensor. No external buffering Figure 28. Recommended Comparator Connection Diagram is required between the sensor/transducer and the analog inputs APPLICATION DETAILS of the AD7264. The on-chip comparators can be used to monitor the pole sensors, which can be Hall effect sensors or The AD7264 has been specifically designed to meet the require- the inner tracks from an optical encoder. ments of any motor control shaft position feedback loop. The device can interface directly to multiple sensor types, including Figure 29 shows how the AD7264 can be used in a typical optical encoders, magnetoresistive sensors, and Hall effect sensors. application. An optical encoder is shown in Figure 29, but other Its flexible analog inputs, which incorporate programmable sensor types could as easily be used. Figure 29 indicates a gain, ensure that identical board design can be utilized for a typical application configuration only; there are several other configurations that render equally effective results. COMP COMP AV V A CC REF REF AD7264 BUF 14-BIT A V + A SUCCESSIVE OUTPUT D A V – PGA T/H OUT APPROXIMATION A DRIVERS ADC SCLK CAL CS CONTROL REFSEL LOGIC G0 G1 G2 G3 B V DRIVE V + B 14-BIT SUCCESSIVE OUTPUT V – T/H D B B PGA OUT APPROXIMATION DRIVERS ADC PD0/D IN PD1 BUF PD2 V B REF C _C V A B CC H.E. Z C + A OUTPUT C A OUT DRIVERS C – A COMP U C + B OUTPUT C B OUT DRIVERS C – B COMP C _C _GND A B C _C V C D CC V C + C OUTPUT C C OUT DRIVERS C – C COMP C + W D OUTPUT C D OUT DRIVERS C – D COMP C _C _GND C D AGND DGND Figure 29. Typical System Connection Diagram with Optical Encoder Rev. A | Page 19 of 32 06732-028 06732-029 AD7264 MODES OF OPERATION The AD7264 allows the user to choose between two modes of POWER-DOWN MODES operation: pin driven mode and control register mode. The AD7264 offers the user several of power-down options to PIN DRIVEN MODE enable individual device components to be powered down independently. These options can be chosen to optimize power Pin driven mode allows the user to select the gain of the PGA, dissipation for different application requirements. The power- the power-down mode, internal or external reference, and to down modes can be selected by either programming the device initiate a calibration of the offset for both ADC A and ADC B. via the control register or by driving the PD pins to the These functions are implemented by setting the logic levels on appropriate logic levels. By setting the PD pins to a logic low the gain pins (G3 to G0), the power-down pins (PD2 to PD0), level when in pin driven mode, all four comparators and both the REFSEL pin, and the CAL pin, respectively. ADCs can be powered down. The PD2 and PD0 pins must be The logic state of the G3 to G0 pins determines which mode of set to logic high and the PD1 pin set to logic low level to power operation is selected. Pin driven mode is selected if at least one up all circuitry on the AD7264. The PD pin configurations for of the gain pins is set to a logic high state. Alternatively, if all the various power-down options are outlined in Table 7. four gain pins are connected to a logic low, the control register mode of operation is selected. Table 7. Power-Down Modes Comparator A, Comparator C, ADC A, GAIN SELECTION PD2 PD1 PD0 Comparator B Comparator D ADC B The on-board PGA allows the user to select from 14 program- 0 0 0 Off Off Off mable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, 0 0 1 Off Off On ×48, ×64, ×96, and ×128. The PGA accepts fully differential 0 1 0 Off On Off analog signals and provides three key functions, which include 0 1 1 On Off Off selecting gains for small amplitude input signals, driving the 1 0 0 On On Off ADCs switched capacitive load, and buffering the source from 1 0 1 On On On the switching effects of the SAR ADCs. The AD7264 offers the 1 1 1 1 1 1 Off Off Off user great flexibility in user interface, offering gain selection via 1 PD2 = PD1 = PD0 = 1; resets the AD7264 when in pin driven mode only. the control register or by driving the gain pins to the desired logic state. The AD7264 has four gain pins, G3, G2, G1 and G0, The AV and V supplies must continue to be supplied to CC DRIVE as shown in Figure 3 and Figure 4. Each gain setting is selected the AD7264 when the comparators are powered up but the by setting up the appropriate logic state on each of the four gain ADCs are powered down. External diodes can be used from the pins, as outlined in Table 6. If all four gain pins are connected to C _C V and/or C _C V to both the AV and the V A B CC C D CC CC DRIVE a logic low level, the part is put in control register mode, and supplies to ensure that they retain a supply at all times. the gain settings are selected via the control register. The AD7264 can be reset in pin driven mode only by setting the Table 6. Gain Selection PD pins to a logic high state. When the device is reset, all the G3 G2 G1 G0 Gain registers are cleared and the four comparators and the two 0 0 0 0 Software control ADCs are left powered down. via control register In the normal mode of operation with the ADCs and compara- 0 0 0 1 1 tors powered on, the C _C V /C _C V supplies and the A B CC C D CC 0 0 1 0 2 AVCC supply can be at different voltage levels, as indicated in 0 0 1 1 3 Table 1. When the comparators on the AD7264 are in power- 0 1 0 0 4 down mode and the CA_CBVCC/CC_CDVCC supplies are at a 0 1 0 1 6 potential 0.3 V greater than or less than the AVCC supply, the 0 1 1 0 8 supplies consume more current than would be the case if both 0 1 1 1 12 sets of supplies were at the same potential. This configuration 1 0 0 0 16 does not damage the AD7264 but results in additional current 1 0 0 1 24 flowing in any or all of the AD7264 supply pins. This is due to 1 0 1 0 32 ESD protection diodes within the device. In applications where 1 0 1 1 48 power consumption in power-down mode is critical, it is 1 1 0 0 64 recommended that the CA_CBVCC/CC_CDVCC supply and the 1 1 0 1 96 AVCC supply be held at the same potential. 1 1 1 0 128 Rev. A | Page 20 of 32 AD7264 Power-Up Conditions to a low logic state. These functions can also be implemented by setting the logic levels on the gain pins, power-down pins, and On power-up, the status of the gain pins determines which CAL pin, respectively. The control register can also be used to mode of operation is selected, as outlined in the Gain Selection read the offset and gain registers. section. All registers are set to 0. Data is loaded from the PD0/DIN pin of the AD7264 on the If the AD7264 is powered up in pin driven mode, the gain pins falling edge of SCLK when CS is in a logic low state. The control and the PD pins should be configured to the appropriate logic register is selected by first writing the appropriate four WR bits, states and a calibration initiated if required. as outlined in Table 10. The 12 data bits must then be clocked Alternatively, if the AD7264 is powered up in control register th into the control register of the device. Thus, on the 16 falling mode, the comparators and ADCs are powered down and the SCLK edge, the LSB is clocked into the device. One more SCLK default gain is 1. Thus, powering up in control register mode cycle is then required to write to the internal device registers. In requires a write to the device to power up the comparators and total, 17 SCLK cycles are required to successfully write to the the ADCs. AD7264. The data is transferred on the PD0/DIN line while the It takes the AD7264 15 μs to power up when using an external conversion result is being processed. The data transferred on reference. When the internal reference is used, 240 μs are required the DIN line corresponds to the AD7264 configuration for the to power up the AD7264 with a 1 μF decoupling capacitor. next conversion. CONTROL REGISTER Only the information provided on the 12 falling clock edges after CS the falling edge and the initial four write address bits is loaded The control register on the AD7264 is a 12-bit read and write to the control register. The PD0/DIN pin should have a logic low register that is used to control the device when not in pin driven state for the four bits RD3 to RD0 when using the control register mode. The PD0/D pin serves as the serial D pin for the IN IN to select the power-down modes and gain setting, or when initia- AD7264 when the gain pins are set to 0 (that is, the part is not in lizing a calibration. The RD bits should also be set to a logic low pin driven mode). The control register can be used to select the level to access the ADC results from both DOUTA and DOUTB. gain of the PGAs, the power-down modes, and the calibration of the offset for both ADC A and ADC B. When in the control The power-up status of all bits is 0, and the MSB denotes the first register mode of operation, PD1 and PD2 should be connected bit in the data stream. The bit functions are outlined in Table 9. Table 8. Control Register Bits MSB LSB Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RD3 RD2 RD1 RD0 CAL PD2 PD1 PD0 G3 G2 G1 G0 Table 9. Control Register Bit Function Descriptions Bits Mnemonic Comment 11 to 8 RD3 to RD0 Register address bits. These bits select which register the subsequent read is from. See Table 11. 7 CAL Setting this bit high initiates an internal offset calibration. When the calibration is completed, this pin can be reset low, and the internal offset that is stored in the on-chip offset registers is automatically removed from the ADCs results. 6 to 4 PD2 to PD0 Power-down bits. These bits select which power-down mode is programmed. See Table 7. 3 to 0 G3 to G0 Gain selection bits. These bits select which gain setting is used on the front-end PGA. See Table 6. Table 10. Write Address Bits WR3 WR2 WR1 WR0 Read Register Addressed 0 0 0 1 Control register CS t 8 t 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 32 33 SCLK t QUIET THREE-STATE DB13 DB12 DB0 D A OUT THREE- t t 13 14 STATE THREE-STATE WR3 WR2 WR1 WR0 RD3 RD2 RD1 RD0 CAL PD2 PD1 PD0 G3 G2 G1 G0 PD0/D IN Figure 30. Timing Diagram for a Write Operation to the Control Register Rev. A | Page 21 of 32 06732-030 AD7264 ON-CHIP REGISTERS Table 11. Read and Write Register Addresses The AD7264 contains a control register, two offset registers for RD3 RD2 RD1 RD0 Comment storing the offsets for each ADC, and two external gain registers 0 0 0 0 ADC result (default) for storing the gain error. The control, offset, and gain registers 0 0 0 1 Control register are read and write registers. On power-up, all registers in the 0 0 1 0 Offset ADC A internal AD7264 are set to 0 by default. 0 0 1 1 Offset ADC B internal 0 1 0 0 Gain ADC A external Writing to a Register 0 1 0 1 Gain ADC B external Data is loaded from the PD0/DIN pin of the AD7264 on the falling edge of SCLK when CS is in a logic low state. Four Reading from a Register address bits and 12 data bits must be clocked into the device. The internal offset of the device, which has been measured by th Thus, on the 16 falling SCLK edge, the LSB is clocked into the the AD7264 and stored in the on-chip registers during the AD7264. One more SCLK cycle is then required to write to the calibration, can be read back by the user. The contents of the internal device registers. In total, 17 SCLK cycles are required to external gain registers can also be read. To read the contents of successfully write to the AD7264. The control and offset any register, the user must first write to the control register by registers are 12-bits registers, and the gain registers are 7-bit writing 0001 to the WR3 to WR0 bits via the PD0/D pin (see IN registers. Table 10). The next four bits in the control register are the RD When writing to a register, the user must first write the address bits, which are used to select the desired register from which to bits corresponding to the selected register. Table 11 shows the read. The appropriate 4-bit addresses for each of the offset and decoding of the address bits. The four RD bits are written MSB gain registers are listed in Table 11. The remaining eight SCLK first, that is, RD3 followed by RD2, RD1, and RD0. The AD7264 cycle bits are used to set the remaining bits in the control decodes these bits to determine which register is being addressed. register to the desired state for the next ADC conversion. The subsequent 12 bits of data are written to the addressed register. th The 19 SCLK falling edge clocks out the first data bit of the When writing to the external gain registers, the seven bits of digital code corresponding to the value stored in the selected data immediately after the four address bits are written to the internal device register on the D A pin. D B outputs the OUT OUT register. However, 17 SCLK cycles are still required, and the conversion result from ADC B. When the selected register has PD0/D pin of the AD7264 should be tied low for the five IN been read, the control register must be reset to output the ADC additional clock cycles. results for future conversions. This is achieved by writing 0001 to the WR3 to WR0 bits, followed by 0000 to the RD bits. The remaining eight bits in the control register should then be set to the required configuration for the next ADC conversion. CS t 8 t 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 32 33 SCLK t QUIET THREE-STATE DB13 DB12 DB0 D A A A A OUT THREE- t t 13 14 STATE THREE-STATE RD3 RD2 RD1 RD0 MSB DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PD0/D IN Figure 31. Timing Diagram for Writing to a Register CS t 8 t 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 32 33 SCLK t QUIET THREE-STATE DB13 DB12 DB0 A A A D A OUT THREE- t t 13 14 STATE THREE-STATE PD0/D 0 0 0 1 RD3 RD2 RD1 RD0 0 0 0 0 0 0 0 0 IN Figure 32. Timing Diagram for a Read Operation with PD0/DIN as an Input Rev. A | Page 22 of 32 06732-032 06732-031 AD7264 SERIAL INTERFACE Figure 33 and Figure 34 show the detailed timing diagrams for access time (t4) is 23 ns, which enables reading on the subse- the serial interface on the AD7264. The serial clock provides the quent falling SCLK edge after the data has been clocked out, as conversion clock and controls the transfer of information from described previously. However, if a VDRIVE voltage of 3 V is used the AD7264 after the conversion. The AD7264 has two output for the AD7264 and the setup time of the microcontroller or pins corresponding to each ADC. Data can be read from the DSP is too large to enable reading on the falling SCLK edge, it AD7264 using both D A and D B. Alternatively, a single may be necessary to read on the SCLK rising edge. In this case, OUT OUT th output pin of the user’s choice can be used. The SCLK input the MSB of the conversion result is clocked out on the 19 SCLK th signal provides the clock source for the serial interface. falling edge to be read on the 20 SCLK rising edge, as shown in Figure 35. This is possible because the hold time (t5) is longer for The falling edge of CS puts the track-and-hold into hold mode, lower VDRIVE voltages. If the data access time is too long to accom- at which point the analog input is sampled. The conversion is modate the setup time of the chosen processor, an alternative to also initiated at this point and requires a minimum of 19 SCLK reading on the rising SCLK edge is to use a slower SCLK frequency. cycles to complete. The DOUTx lines remain in three-state while th CS the conversion is taking place. On the 19 SCLK falling edge, the On the rising edge of , DOUTA and DOUTB go back into three- AD7264 returns to track mode and the D A and D B lines CS OUT OUT state. If is not brought high after 33 SCLK cycles but is instead are enabled. The data stream consists of 14 bits of data, MSB first. held low for an additional 14 SCLK cycles, the data from ADC B th is output on DOUTA after the ADC A result. Likewise, the data The MSB of the conversion result is clocked out on the 19 from ADC A is output on DOUTB after the ADC B result. This is SCLK falling edge to be read by the microcontroller or DSP on th illustrated in Figure 34, which shows the DOUTA example. In this the subsequent SCLK falling edge (the 20 falling edge). The th case, the DOUT line in use goes back into three-state on the 47 remaining data is then clocked out by subsequent SCLK falling th CS SCLK falling edge or the rising edge of , whichever occurs first. edges. Thus, the 20 falling clock edge on the serial clock has the MSB provided and also clocks out the second data bit. The CS If the falling edge of SCLK coincides with the falling edge of , remainder of the 14-bit result follows, with the final bit in the the falling edge of SCLK is not acknowledged by the AD7264, rd data transfer being valid for reading on the 33 falling edge. and the next falling edge of SCLK is the first one registered after nd falling clock edge. The LSB is provided on the 32 the falling edge of CS. The AD7264-5, with its 20 MHz SCLK frequency, easily facilitates reading on the SCLK falling edge. When using a VDRIVE voltage of 5 V with the AD7264, the maximum specified FIRST DATA BIT CLOCKED FIRST DATA BIT READ OUT ON THIS EDGE ON THIS EDGE CS t 8 t 2 t 6 1 2 34 5 SCLK 18 19 20 21 31 32 33 t t 7 9 t 5 t 3 t t 4 QUIET DB13 DB12 DB11 DB1 DB0 D A A A A A A OUT THREE-STATE THREE- STATE DB13 DB12 DB11 DB1 DB0 D B B B B B B OUT THREE-STATE THREE- STATE Figure 33. Normal Mode Operation CS SCLK 12 18 19 20 21 31 32 33 45 46 47 t 10 D A DB13 DB12 DB1 DB0 DB13 DB12 DB1 DB0 OUT A A A A B B B B THREE-STATE THREE- STATE Figure 34. Reading Data from Both ADCs on One D Line with 47 SCLK Cycles OUT Rev. A | Page 23 of 32 06732-033 06732-034 AD7264 FIRST DATA BIT CLOCKED FIRST DATA BIT READ OUT ON THIS EDGE ON THIS EDGE CS t 8 t 2 SCLK15 23 4 1819 20 21 22 31 32 33 t t 5 4 DB13 DB12 DB11 DB1 DB0 D A A A A A A OUT THREE-STATE THREE- STATE DB13 DB12 DB11 DB1 DB0 D B B B B B B OUT THREE-STATE THREE- STATE Figure 35. Serial Interface Timing Diagram When Reading Data on the Rising SCLK Edge with VDRIVE = 3 V Rev. A | Page 24 of 32 06732-039 AD7264 CALIBRATION The AD7264 registers store the offset value, which can easily be INTERNAL OFFSET CALIBRATION accessed by the user (see the Reading from a Register section). The AD7264 allows the user to calibrate the offset of the device When the device is calibrating, the differential analog inputs using the CAL pin. This is achieved by setting the CAL pin to a for each respective ADC are shorted together internally and a CS high logic level, which initiates a calibration on the next conversion is performed. A digital code representing the offset is falling edge. The calibration requires one full conversion cycle, stored internally in the offset registers, and subsequent conver- which contains a CS falling edge followed by 19 SCLK cycles. sion results have this measured offset removed. The CAL pin can remain high for more than one conversion, if When the AD7264 is calibrated, the calibration results stored in desired, and the AD7264 continues to calibrate. the internal device registers are relevant only for the particular CS The CAL pin should be driven high only when the pin is PGA gain selected at the time of calibration. If the PGA gain is CS high or after 19 SCLK cycles have elapsed when is low, that changed, the AD7264 must be recalibrated. If the device is not is, between conversions. The CAL pin must be driven high t 12 recalibrated when the PGA gain is changed, the offset for the CS CS before goes low. If the pin goes low before t12 elapses, the previous gain setting continues to be removed from the digital calibration result will be inaccurate for the current conversion; output code, which may lead to inaccuracies. if the CAL pin remains high, the subsequent calibration conver- The offset range that can be calibrated for is ±500 LSB at a gain sion is correct. If the CAL pin is set to a logic high state during a of 1. The maximum offset voltage that can be calibrated for is conversion, that conversion result is corrupted. reduced as the gain of the PGA is increased. If the CAL pin has been held high for a minimum of one Table 12 details the maximum offset voltage that can be conversion and when t and t have been adhered to, the 12 11 removed by the AD7264 without compromising the available th calibration is complete after the 19 SCLK cycle and the CAL digital output code range. The least significant bit size is pin can be driven to a logic low state. The next CS falling edge Bits AV /2 , which is 5/16,384 or 305 μV for the AD7264. The CC after the CAL pin has been driven to a low logic state initiates maximum removable offset voltage is given by a conversion of the differential analog input signal for both 305 μV ADC A and ADC B. ± 500 LSB× Gain Alternatively, the control register can be used to initiate an offset calibration. This is done by setting the CAL bit in the Table 12. Offset Voltage Range control register to 1. The calibration is then initiated on the next Gain Maximum Removable Offset Voltage CS falling edge, but the current conversion is corrupted. The 1 ±152.5 mV ADCs on the AD7264 must remain fully powered up to 2 ±76.25 mV complete the internal calibration. 3 ±50.83 mV 32 ±4.765 mV t 11 t 12 CAL t 8 CS t 6 t 2 1 2 3 19 20 21 32 33 12 3 19 20 21 SCLK t 7 Figure 36. Calibration Timing Diagram Rev. A | Page 25 of 32 06732-035 AD7264 ADJUSTING THE OFFSET CALIBRATION REGISTER SYSTEM GAIN CALIBRATION The internal offset calibration register can be adjusted manually The AD7264 also allows the user to write to an external gain to compensate for any signal path offset from the sensors to the register, thus enabling the removal of any overall system gain ADC. No internal calibration is required, and the CAL pin can error. Both ADC A and ADC B have independent external gain remain at a low logic state. By changing the contents of the registers, allowing the user to calibrate independently the gain offset register, different amounts of offset on the analog input on both ADC A and ADC B signal paths. The gain calibration signal can be compensated for. Use the following steps to feature can be used to implement accurate gain matching determine the digital code to be written to the offset register: between ADC A and ADC B. 1. Configure the sensor to its offset state. The system calibration function is used by setting the sensors to 2. Perform a number of conversions using the AD7264. which the AD7264 is connected to a 0 gain state. The AD7264 3. Take the mean digital output code from both DOUTA and converts this analog input to a digital output code, which D B. This is a 14-bit result but the offset register is only corresponds to the system gain and is available on the D pins, OUT OUT 12 bits; thus, the 14-bit result needs to be converted to a This digital output code can then be stored in the appropriate 12-bit result that can be stored in the offset register. This is external register. For details on how to write to a register, see the achieved by keeping the sign bit and removing the second Writing to a Register section and Table 11. and third MSBs. The gain calibration register contains seven bits of data. By 4. The resultant digital code can then be written to the offset changing the contents of the gain register, different amounts of registers to calibrate the AD7264. gain on the analog input signal can be compensated for. The MSB is a sign bit, while the remaining six bits store the multiplica- Example: tion factor, which is used to adjust the analog input range. The Mean digital code from D A = 8100 (01 1111 1010 0100) OUT gain register value is effectively multiplied by the analog input Code written to offset register = 0111 1010 0100 to scale the conversion result over the full range. Increasing the If a +10 mV offset is present in the analog input signal and the gain register multiplication factor compensates for a larger gain of the PGA is 2, the code that needs to be written to the analog input range, and decreasing the gain register multiplier offset register to compensate for the offset is compensates for a smaller analog input range. Each bit in the −4 gain calibration register has a resolution of 2.4 × 10 V (1/4096). +10 mV = 65.57 = 0000 0100 0001 A maximum of 1.538% of the analog range can be calibrated for. (305 μV/ 2) The multiplier factor stored in the gain register can be decoded If a −10 mV offset is present in the analog input signal and the as outlined in Table 13. gain of the PGA is 2, the code that needs to be written to the The gain registers can be cleared by writing all 0s to each register, offset register to compensate for the offset is as described in the Writing to a Register section. For accurate −10 mV gain calibration, both the positive and negative full-scale digital = −65.57 = 1000 0100 0001 (305 μV/ 2) output codes should be measured prior to determining the multiplication factor that is written to the gain register. Table 13. Decoding of Multiplication Factors for Gain Calibration Multiplier Gain Register Equation Digital Gain Code Multiplier Analog Input (V) Error (LSB) (Sign Bit + 6 Bits) (1 ± x/4096) Value Comments VIN max 0 LSB 0 000000 1 − 0/4096 1 Sign bit = 0; negative sign in multiplier equation V max − 244 μV −2 LSB 0 000001 1 − 1/4096 0.999755859 Sign bit = 0; negative sign in multiplier IN equation VIN max − (63 × 244 μV) −126 LSB 0 111111 1 − 63/4096 0.98461914 Sign bit = 0; negative sign in multiplier equation VIN max 0 LSB 1 000000 1 + 0/4096 1 Sign bit = 1; plus sign in multiplier equation V max + 244 μV +2 LSB 1 000001 1 + 1/4096 1.000244141 Sign bit = 1; plus sign in multiplier IN equation VIN max + (63 × 244 μV) +126 LSB 1 111111 1 + 63/4096 1.015380859 Sign bit = 1; plus sign in multiplier equation Rev. A | Page 26 of 32 AD7264 APPLICATION HINTS Good decoupling is also important. All analog supplies should GROUNDING AND LAYOUT be decoupled with 10 μF tantalum capacitors in parallel with The analog and digital supplies to the AD7264 are independent 100 nF capacitors to GND. To achieve the best results from and separately pinned out to minimize coupling between the these decoupling components, they must be placed as close as analog and digital sections of the device. The printed circuit possible to the device, ideally right up against the device. The board (PCB) that houses the AD7264 should be designed so 0.1 μF capacitors should have low effective series resistance that the analog and digital sections are separated and confined (ESR) and low effective series inductance (ESI), such as the to certain areas of the board. This design facilitates the use of common ceramic types or surface-mount types. These low ESR ground planes that can be easily separated. and low ESI capacitors provide a low impedance path to ground To provide optimum shielding for ground planes, a minimum at high frequencies to handle transient currents due to internal etch technique is generally best. All five AGND pins of the logic switching. AD7264 should be sunk in the AGND plane. Digital and analog PCB DESIGN GUIDELINES FOR LFCSP ground planes should be joined in only one place. If the AD7264 is in a system where multiple devices require an AGND to The lands on the chip scale package (CP-48-1) are rectangular. DGND connection, the connection should still be made at only The PCB pad for these should be 0.1 mm longer than the one point, a star ground point, that should be established as package land length, and 0.05 mm wider than the package land close as possible to the ground pins on the AD7264. width, leaving a portion of the pad exposed. To ensure that the solder joint size is maximized, the land should be centered on Avoid running digital lines under the device because this the pad. couples noise onto the die. However, the analog ground plane should be allowed to run under the AD7264 to avoid noise The bottom of the chip scale package has a thermal pad. The coupling. The power supply lines to the AD7264 should use as thermal pad on the PCB should be at least as large as the large a trace as possible to provide low impedance paths and exposed pad. On the PCB, there should be a clearance of at least reduce the effects of glitches on the power supply line. 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. To avoid radiating noise to other sections of the board, fast switching signals, such as clocks, should be shielded with digital To improve thermal performance of the package, use thermal ground, and clock signals should never run near the analog vias on the PCB, incorporating them in the thermal pad at 1.2 mm inputs. Avoid crossover of digital and analog signals. To reduce pitch grid. The via diameter should be between 0.3 mm and the effects of feedthrough within the board, traces on opposite 0.33 mm, and the via barrel should be plated with 1 oz copper sides of the board should run at right angles to each other. A to plug the via. The user should connect the PCB thermal pad microstrip technique is the best method but is not always possible to AGND. with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Rev. A | Page 27 of 32 AD7264 OUTLINE DIMENSIONS 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 PAD VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 25 12 0.40 13 24 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 THE EXPOSED METAL PADDLE ON THE 0.05 MAX 0.80 BOTTOM OF THE LFCSP PACKAGE 0.02 NOM MUST BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND COPLANARITY 0.50 BSC ALSO FOR NOISE AND MECHANICAL 0.08 0.20 REF SEATING STRENGTH BENEFITS. PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 37. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 37 48 1 36 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 0.20 (PINS DOWN) 6.80 1.40 0.09 1.35 7° 3.5° 25 12 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 38. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters Rev. A | Page 28 of 32 051706-A 061208-A AD7264 ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7264BCPZ −40°C to +105°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7264BCPZ-RL7 −40°C to +105°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7264BCPZ-5 −40°C to +105°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7264BCPZ-5-RL7 −40°C to +105°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7264BSTZ −40°C to +105°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 AD7264BSTZ-RL7 −40°C to +105°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 AD7264BSTZ-5 −40°C to +105°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 AD7264BSTZ-5-RL7 −40°C to +105°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 EVAL-AD7264EDZ Evaluation Board 1 EVAL-CED1Z Development Board 1 Z = RoHS Compliant Part. Rev. A | Page 29 of 32 AD7264 NOTES Rev. A | Page 30 of 32 AD7264 NOTES Rev. A | Page 31 of 32 AD7264 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06732-0-7/08(A) Rev. A | Page 32 of 32