ANALOG DEVICES AD7262

1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators AD7262 FEATURES FUNCTIONAL BLOCK DIAGRAM V A AV CC REF Dual simultaneous sampling 12-bit, 2-channel ADC True differential analog inputs REF AD7262 BUF Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, ×128 12-BIT V + SUCCESSIVE A OUTPUT D A PGA T/H OUT Throughput rate per ADC APPROXIMATION DRIVERS V – A ADC 1 MSPS for AD7262 500 kSPS for AD7262-5 SCLK CAL Analog input impedance: >1 GΩ CS CONTROL REFSEL Wide input bandwidth LOGIC G0 −3 dB bandwidth: 1.7 MHz at gain = 2 G1 G2 4 on-chip comparators G3 V DRIVE SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32 12-BIT V + Device offset calibration, system gain calibration B SUCCESSIVE OUTPUT T/H D B PGA OUT APPROXIMATION DRIVERS V – B On-chip reference: 2.5 V ADC PD0/D IN –40°C to +105°C operation PD1 BUF PD2 High speed serial interface V B REF SPI/QSPI™/MICROWIRE™/DSP compatible C _C V A B CC 48-lead LFCSP and LQFP packages C + A OUTPUT C A OUT DRIVERS C – A COMP GENERAL DESCRIPTION C + B OUTPUT C B OUT DRIVERS C – B COMP The AD7262/AD7262-5 are dual, 12-bit, high speed, low power, C _C _GND A B successive approximation ADCs that operate from a single 5 V C _C V C D CC C + power supply. The AD7262 features throughput rates of up to C OUTPUT C C OUT DRIVERS C – C COMP 1 MSPS per on-chip ADC. The AD7262-5 features throughput C + D OUTPUT C D OUT rates of up to 500 kSPS. Two complete ADC functions allow C – DRIVERS D COMP C _C _GND C D simultaneous sampling and conversion of two channels. Each ADC is preceded by a true differential analog input with a PGA. AGND DGND There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12, Figure 1. ×16, ×24, ×32, ×48, ×64, ×96, and ×128. The AD7262/AD7262-5 contain four comparators. Comparator A PRODUCT HIGHLIGHTS and Comparator B are optimized for low power, while Compara- 1. Integrated PGA with a variety of flexible gain settings to tor C and Comparator D have fast propagation delays. The allow detection and conversion of low level analog signals. AD7262/AD7262-5 feature a calibration function to remove any 2. Each PGA is followed by a dual simultaneous sampling device offset error and programmable gain adjust registers to ADC, featuring throughput rates of 1 MSPS per ADC for allow for input path (for example, sensor) offset and gain the AD7262. The conversion results of both ADCs are compensation. The AD7262/AD7262-5 have an on-chip 2.5 V simultaneously available on separate data lines or in succes- reference that can be disabled if an external reference is preferred. sion on one data line if only one serial port is available. The AD7262/AD7262-5 are ideally suited for monitoring small 3. Four integrated comparators that can be used to count amplitude signals from a variety of sensors. They include all the signals from pole sensors in motor control applications. functionality needed for monitoring the position feedback 4. Internal 2.5 V reference. signals from a variety of analog encoders used in motor control systems. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07606-001 AD7262 TABLE OF CONTENTS Features .............................................................................................. 1 Application Details ..................................................................... 20 General Description ......................................................................... 1 Modes of Operation ....................................................................... 22 Functional Block Diagram .............................................................. 1 Pin-Driven Mode ....................................................................... 22 Product Highlights ........................................................................... 1 Gain Selection ............................................................................. 22 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 22 Specif ica t ions ..................................................................................... 3 Control Register ......................................................................... 23 Timing Specifications .................................................................. 6 On-Chip Registers ...................................................................... 24 Timing Diagram ........................................................................... 6 Serial Interface ................................................................................ 25 Absolute Maximum Ratings ............................................................ 7 Calibration ....................................................................................... 27 ESD Caution .................................................................................. 7 Internal Offset Calibration ........................................................ 27 Pin Configurations and Function Descriptions ........................... 8 Adjusting the Offset Calibration Registers ................................. 28 Typical Performance Characteristics ........................................... 10 System Gain Calibration............................................................ 28 Terminology .................................................................................... 14 Microprocessor Interfacing ........................................................... 29 Theory of Operation ...................................................................... 15 AD7262/AD7262-5 to ADSP-BF53x ....................................... 29 Circuit Information .................................................................... 15 Application Hints ........................................................................... 30 C om p ara tors ................................................................................ 15 Grounding and Layout .............................................................. 30 Operation ..................................................................................... 15 PCB Design Guidelines for LFCSP .......................................... 30 Analog Inputs .............................................................................. 15 Outline Dimensions ....................................................................... 31 VDRIVE ............................................................................................ 16 Ordering Guide .......................................................................... 31 Reference ..................................................................................... 17 Typical Connection Diagrams .................................................. 17 REVISION HISTORY 7/08—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7262 SPECIFICATIONS AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSAMPLE = 1 MSPS and fSCLK = 40 MHz for AD7262, fSAMPLE = 500 kSPS and fSCLK = 20 MHz for AD7262-5, VREF = 2.5 V internal/external; TA = −40°C to +105°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments 1 DYNAMIC PERFORMANCE fIN = 100 kHz sine wave 2 Signal-to-Noise Ratio (SNR) 70 73 dB PGA gain setting = 2 Signal-to-(Noise + Distortion) Ratio 70 72 dB 2 (SINAD) 2 Total Harmonic Distortion (THD) −85 −77 dB 2 Spurious-Free Dynamic Range (SFDR) −97 dB 3 Common-Mode Rejection Ratio (CMRR) −76 dB For PGA gain setting = 2, ripple frequency of 50 Hz/60 Hz; see Figure 17 and Figure 18 3 ADC-to-ADC Isolation −90 dB 3 Bandwidth 1.2 MHz @ −3 dB; PGA gain setting = 128 1.7 MHz @ −3 dB; PGA gain setting = 2 DC ACCURACY Resolution 12 Bits 2 Integral Nonlinearity ±0.5 ±1 LSB 2 Differential Nonlinearity ±0.5 ±0.99 LSB Guaranteed no missed codes to 12 bits 2 Positive Full-Scale Error ±0.122 ±0.305 % FSR Pregain calibration ±0.018 % FSR Postgain calibration Positive Full-Scale Error Match ±0.061 % FSR 2 Zero Code Error ±0.092 ±0.244 % FSR Preoffset and pregain calibration ±0.012 % FSR Postoffset and postgain calibration Zero Code Error Match ±0.061 % FSR 2 Negative Full-Scale Error ±0.122 ±0.305 % FSR Pregain calibration ±0.018 % FSR Postgain calibration Negative Full-Scale Error Match ±0.061 % FSR Zero Code Error Drift 2.5 μV/°C ANALOG INPUT Input Voltage Range, V + and V − V V = AV /2; PGA gain setting ≥ 2 IN IN CM CC V REF V ± CM 2× Gain Common-Mode Voltage Range, V V − 100 mV V + 100 mV V V = 2; PGA gain setting = 1; CM CM CM CM 4 see Figure 19 (VCC/2) − 0.4 (VCC/2) + 0.2 V VCM = AVCC/2; PGA gain setting = 2 (VCC/2) − 0.4 (VCC/2) + 0.4 V VCM = AVCC/2; 3 ≤ PGA gain setting ≤ 32 (V /2) − 0.6 (V /2) + 0.8 V V = AV /2; PGA gain setting ≥ 48 CC CC CM CC DC Leakage Current ±0.001 ±1 μA 3 Input Capacitance 5 pF 3 Input Impedance 1 GΩ REFERENCE INPUT/OUTPUT 5 Reference Output Voltage 2.495 2.5 2.505 V 2.5 V ± 5 mV max @ 25°C Reference Input Voltage Range 2.5 V DC Leakage Current ±0.3 ±1 μA External reference applied to Pin VREFA/Pin VREFB 3 Input Capacitance 20 pF 3 V A, V B Output Impedance 4 Ω REF REF Reference Temperature Coefficient 20 ppm/°C 3 VREF Noise 20 μV rms Rev. 0 | Page 3 of 32 AD7262 Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V Input Low Voltage, VINL 0.8 V Input Current, I ±1 μA V = 0 V or V IN IN DRIVE 3 Input Capacitance, C 4 pF IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V OH DRIVE Output Low Voltage, V 0.4 V OL Floating State Leakage Current ±1 μA 3 Floating State Output Capacitance 5 pF Output Coding Twos complement CONVERSION RATE Conversion Time 19 × tSCLK ns Track-and-Hold Acquisition Time 400 ns Throughput Rate 1 MSPS AD7262 500 kSPS AD7262-5 COMPARATORS Input Offset Comparator A and Comparator B ±2 ±4 mV T = 25°C to 105°C only A Comparator C and Comparator D ±2 ±4 mV Offset Voltage Drift 0.5 μV/°C All comparators 3 Input Common-Mode Range 0 to 4 V CA_CBVCC = 5 V 0 to 1.7 V CA_CBVCC = 2.7 V 3 Input Capacitance 4 pF 3 Input Impedance 1 GΩ 6 IDD Normal Mode (Static) 25 pF load, COUTx = 0 V, VCM = AVCC/2, VOVERDRIVE = 200 mV differential Comparator A and Comparator B 3 μA CA_CBVCC = 3.3 V 6 8.5 μA C _C V = 5.25 V A B CC Comparator C and Comparator D 60 μA C _C V = 3.3 V C D CC 120 170 μA C _C V = 5.25 V C D CC Propagation Delay Time VCM = AVCC/2, VOVERDRIVE = 200 mV differential High to Low, tPHL Comparator A and Comparator B 1.4 3.5 μs C _C V = 2.7 V A B CC 0.95 μs C _C V = 5 V A B CC Comparator C and Comparator D 0.20 0.32 μs CC_CDVCC = 2.7 V 0.13 μs CC_CDVCC = 5 V Low to High, tPLH Comparator A and Comparator B 2 4 μs C _C V = 2.7 V A B CC 0.93 μs C _C V = 5 V A B CC Comparator C and Comparator D 0.18 0.28 μs C _C V = 2.7 V C D CC 0.12 μs CC_CDVCC = 5 V Delay Matching VCM = AVCC 2, VOVERDRIVE = 200 mV differential Comparator A and Comparator B ±250 ns Comparator C and Comparator D ±10 ns Rev. 0 | Page 4 of 32 AD7262 Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS Digital inputs = 0 V or VDRIVE AVCC 4.75 5.25 V CA_CBVCC, CC_CDVCC 2.7 5.25 V V 2.7 5.25 V DRIVE I DD ADC Normal Mode (Static) 20 31.5 mA AV = 5.25 V CC ADC Normal Mode (Dynamic) 23 33.3 mA AVCC = 5.25 V Shutdown Mode 0.5 1 μA AVCC = 5.25 V, ADCs and comparators powered down Power Dissipation ADC Normal Mode (Static) 105 165 mW ADC Normal Mode (Dynamic) 120 175 mW Shutdown Mode 2.625 5.25 μW 1 These specifications were determined without the use of the gain calibration feature. 2 See the Terminology section. 3 Samples tested during initial release to ensure compliance; they are not subject to production testing. 4 For PGA gain = 1; to use the full analog input range (V ± V /2) of the AD7262, the V voltage should be dropped to lie within a range from 1.95 V to 2.05 V. CM REF CM 5 Refers to Pin VREFA or Pin VREFB. 6 This specification includes the I for both comparators. The I per comparator is the specified value divided by two. DD DD Rev. 0 | Page 5 of 32 AD7262 TIMING SPECIFICATIONS 1 AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VREF = 2.5 V internal/external; TA = TMIN to TMAX, unless otherwise noted. Table 2. Limit at TMIN, TMAX Parameter 2.7 V ≤ VDRIVE ≤ 3.6 V 4.75 V ≤ VDRIVE ≤ 5.25 V Unit Description f 200 200 kHz min SCLK 2 40 40 MHz max AD7262 2 32 32 MHz typ AD7262 20 20 MHz max AD7262-5 tCONVERT 19 × tSCLK 19 × tSCLK ns max tSCLK = 1/fSCLK 475 475 ns max AD7262 950 950 ns max AD7262-5 tQUIET 13 13 ns min Minimum time between end of serial read/bus relinquish and next falling edge of CS t2 10 10 ns min CS to SCLK setup time 3 th t 15 15 ns max Delay from 19 SCLK falling edge until D A and D B are 3 OUT OUT three-state disabled t 29 23 ns max Data access time after SCLK falling edge 4 t5 15 13 ns min SCLK to data valid hold time t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t 13 13 ns min CS rising edge to falling edge pulse width 8 t 13 13 ns max CS rising edge to D A, D B, high impedance/bus 9 OUT OUT relinquish t10 5 5 ns min SCLK falling edge to DOUTA, DOUTB, high impedance 35 35 ns max SCLK falling edge to DOUTA, DOUTB, high impedance t 2 2 μs min Minimum CAL pin high time 11 t12 2 2 μs min Minimum time between the CAL pin high and the CS falling edge t 3 3 ns min D setup time prior to SCLK falling edge 13 IN t 3 3 ns min D hold time after SCLK falling edge 14 IN tPOWER-UP 240 240 μs max Internal reference, with a 1 μF decoupling capacitor 15 15 μs max With an external reference, 10 μs typical 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVCC) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Terminology section. 2 See the Serial Interface section. 3 The time required for the output to cross 0.4 V or 2.4 V. TIMING DIAGRAM CS t 8 t 2 t 6 SCLK15 23 4 1819 20 21 29 30 31 t t 7 9 t 5 t 3 t t 4 QUIET DB11 DB10 DB9 DB1 DB0 D A A A A A A OUT THREE-STATE THREE- STATE DB11 DB10 DB9 DB1 DB0 D B B B B B B OUT THREE-STATE THREE- STATE Figure 2. Serial Interface Timing Diagram Rev. 0 | Page 6 of 32 07606-002 AD7262 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 3. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to DGND −0.3 V to AV DRIVE CC other conditions above those indicated in the operational V to AGND −0.3 V to AV DRIVE CC section of this specification is not implied. Exposure to absolute AVCC to AGND/DGND −0.3 V to +7 V maximum rating conditions for extended periods may affect CA_CBVCC to CA_CB_GND −0.3 V to +7 V device reliability. C _C V to C _C _GND −0.3 V to +7 V C D CC C D AGND to DGND −0.3 V to +0.3 V CA_CB_GND/CC_CD_GND to DGND −0.3 V to +0.3 V ESD CAUTION Analog Input Voltage to AGND −0.3 V to AVCC + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V + 0.3 V DRIVE V A/V B Input to AGND −0.3 V to AV + 0.3 V REF REF CC C A/C B/C C/C D to GND −0.3 V to V + 0.3 V OUT OUT OUT OUT DRIVE CA±/CB±/CC±/CD± to −0.3 V to CA_CB_GND/CC_CD_GND CA_CBVCC/CC_CDVCC + 0.3 V Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C LFCSP Package θJA Thermal Impedance 30°C/W θJC Thermal Impedance 3°C/W LQFP Package θ Thermal Impedance 55°C/W JA θ Thermal Impedance 16°C/W JC Pb-Free Temperature, Soldering Reflow 255°C ESD 2 kV Rev. 0 | Page 7 of 32 V + B V + B AD7262 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 1 36 CAL C _C V A B CC PIN 1 2 35 CS AV INDICATOR CC C _C V 1 36 CAL 3 34 SCLK A B CC V – A PIN 1 AV 2 INDICATOR 35 CS CC V + 4 33 AV A CC SCLK V – 3 34 A 5 32 D A AGND OUT AV V + 33 AD7262 4 CC A 31 D B AGND 6 OUT D A TOP VIEW 5 32 AGND OUT AV 7 30 C A AD7262 CC OUT (Not to Scale) D B AGND 6 31 OUT C B TOP VIEW 8 29 AGND OUT AV C A 7 (Not to Scale) 30 OUT CC 9 28 DGND AGND 8 29 C B OUT 10 27 V V – DRIVE B 9 28 DGND AV 11 26 C C CC OUT V – V B 10 27 DRIVE C _C V C D CC 12 25 C D OUT AV C C CC 11 26 OUT C _C V 13 14 15 16 17 18 19 20 21 22 23 24 12 25 C D C D CC OUT NOTES 1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR NOISE AND MECHANICAL STRENGTH BENEFITS. Figure 3. 48-Lead LQFP Pin Configuration Figure 4. 48-Lead LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 2, 7, 11, 20, 33, 41 AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the AD7262/AD7262-5. All AV pins can be tied together. This supply should be decoupled to AGND CC with a 100 nF ceramic capacitor per supply and a 10 μF tantalum capacitor. 1 C _C V Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and A B CC Comparator B. This supply should be decoupled to CA_CB_GND. AVCC, CC_CDVCC, and CA_CBVCC can be tied together. 12 CC_CDVCC Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and Comparator D. This supply should be decoupled to C _C _GND. AV , C _C V , and C _C V can be C D CC C D CC A B CC tied together. 4, 3 V +, V − Analog Inputs of ADC A. True differential input pair. A A 9, 10 VB+, VB− Analog Inputs of ADC B. True differential input pair. 43, 18 VREFA, VREFB Reference Input/Output. Decoupling capacitors are connected to these pins to decouple the internal reference buffer for each respective ADC. Typically, 1 μF capacitors are required to decouple the reference. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. 34 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7262/AD7262-5. This clock is also used as the clock source for the conversion process. A minimum of 31 clocks is required to perform the conversion and access the 12-bit result. 36 CAL Logic Input. Initiates an internal offset calibration. 21 PD2 Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD1 and PD0 pins (see Table 7). 22 PD1 Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2 and PD0 pins (see Table 7). Rev. 0 | Page 8 of 32 C + C C + A C – C – C A C + C + D B C – C – D B C _C _GND C _C _GND C D A B V B V A REF REF AGND AGND AV AV CC CC PD2 G0 G1 PD1 G2 PD0/D IN G3 REFSEL 07606-003 C + C + C 13 48 A C – C – C 14 47 A C + C + 46 D 15 B C – C – 16 45 D B C _C _GND C _C _GND C D 17 44 A B V B V A REF 18 43 REF AGND 42 AGND 19 AV AV 20 41 CC CC PD2 21 40 G0 G1 PD1 22 39 PD0/D 38 G2 IN 23 REFSEL 24 37 G3 07606-004 AD7262 Pin No. Mnemonic Description 23 PD0/DIN Logic Input/Data Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2 and PD1 pins (see Table 7). If all gain selection pins, G0 to G3, are tied low, this pin acts as the data input pin, and all programming is via the control register (see Table 8). Data to be written to the AD7262/AD7262-5 control register is provided on this input and is clocked into the register on the falling edge of SCLK. 35 Chip Select. Active low logic input. This input initiates conversions on the AD7262/AD7262-5. CS 48, 47, 46, 45 CA+, CA−, Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator A CB+, CB− and Comparator B. These two comparators have very low power consumption. 13, 14, 15, 16 C +, C −, Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator C C C C +, C − and Comparator D. This pair of comparators offers very fast propagation delays. D D 5, 6, 8, 19, 42 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7262/AD7262-5. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should connect to the AGND plane of a system. The AGND, DGND, CA_CB_GND, and CC_CD_GND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. C _C _GND and C _C _GND can be tied to AGND. A B C D 28 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7262/AD7262-5. The DGND pin should be connected to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 30, 29, 26, 25 C A, C B, Comparator Outputs. These pins provide a CMOS (push-pull) output from each respective OUT OUT C C, C D comparator. These are digital output pins with logic levels determined by the V supply. OUT OUT DRIVE 32, 31 D A, D B Serial Data Outputs. The data output from the AD7262/AD7262-5 is supplied to each pin as a serial OUT OUT data stream in twos complement format. The bits are clocked out on the falling edge of the SCLK input. A total of 31 SCLKs is required to perform the conversion and access the 12-bit data. During the conversion process, the data output pins are in three-state and, when the conversion is th completed, the 19 SCLK edge clocks out the MSB. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data is provided MSB first. If CS is held low for an additional 12 SCLK cycles on either D A or D B following the initial 31 SCLKs, the data from OUT OUT the other ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB using only one serial port. 40, 39, 38, 37 G0, G1, G2, G3 Logic Inputs. These pins are used to program the gain setting of the front-end amplifiers. If all four pins are tied low, the PD0 pin acts as a data input pin, D , and all programming is made via the IN control register (see Table 6). 27 VDRIVE Logic Power Supply Input, 2.7 V to 5.25 V. The voltage supplied at this pin determines at what voltage the interface operates, including the comparator outputs. This pin should be decoupled to DGND. 44, 17 C _C _GND, Comparator Ground. This is the ground reference point for all comparator circuitry on the AD7262/ A B C _C _GND AD7262-5. Both the C _C _GND pin and the C _C _GND pin should connect to the GND plane of a C D A B C D system and can be tied to AGND. The DGND, AGND, C _C _GND, and C _C _GND voltages should A B C D ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 24 REFSEL Internal/External Reference Selection. Logic input. If this pin is tied to a logic high voltage, the on- chip 2.5 V reference is used as the reference source for both ADC A and ADC B. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7262/AD7262-5 through the V A REF and/or V B pin. REF Rev. 0 | Page 9 of 32 AD7262 TYPICAL PERFORMANCE CHARACTERISTICS 0.6 0.6 AV = 5V AV = 5V CC CC V = 5V V = 5V DRIVE DRIVE f = 1MSPS f = 1MSPS S S 0.4 0.4 T = 25°C T = 25°C A A INTERNAL REFERENCE INTERNAL REFERENCE PGA GAIN = 2 PGA GAIN = 32 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 04 500 1000 1500 2000 2500 3000 3500000 04 500 1000 1500 2000 2500 3000 3500000 CODE CODE Figure 5. Typical DNL at Gain of 2 Figure 8. Typical DNL at Gain of 32 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 AV = 5V AV = 5V CC CC V = 5V V = 5V DRIVE DRIVE –0.6 –0.6 f = 1MSPS f = 1MSPS S S T = 25°C T = 25°C A A –0.8 –0.8 INTERNAL REFERENCE INTERNAL REFERENCE PGA GAIN = 2 PGA GAIN = 32 –1.0 –1.0 04 500 1000 1500 2000 2500 3000 3500000 04 500 1000 1500 2000 2500 3000 3500000 CODE CODE Figure 6. Typical INL at Gain of 2 Figure 9. Typical INL at Gain of 32 0 0 AV = 5V AV = 5V CC CC V = 2.7V V = 5V DRIVE DRIVE –20 f = 1MSPS –20 f = 1MSPS S S T = 25°C T = 25°C A A f = 100kHz f = 100kHz IN IN –40 –40 INTERNAL REFERENCE INTERNAL REFERENCE SNR = 73dB, THD = –82.5dB SNR = 68.38dB, THD = –82dB PGA GAIN = 2 PGA GAIN = 32 –60 –60 –80 –80 –100 –100 –120 –120 –140 –140 0 50k 100k 150k 200k 250k 300k 350k 400k 450k 0 50k 100k 150k 200k 250k 300k 350k 400k 450k 500k FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. 3 dB Typical FFT at Gain of 2 Figure 10. Typical FFT at Gain of 32 Rev. 0 | Page 10 of 32 INL ERROR (LSB) DNL ERROR (LSB) (dB) 07606-007 07606-006 07606-005 (dB) INL ERROR (LSB) DNL ERROR (LSB) 07606-009 07606-008 07606-010 AD7262 9000 2.4968 8839 8000 2.4967 7000 2.4966 6000 2.4965 5000 4000 2.4964 3000 2.4963 2000 AV = 5V CC 828 2.4962 V = 3V DRIVE 1000 f = 1MSPS S 333 INTERNAL REFERENCE 0 0 0 2.4961 0 20 40 60 80 100 120 140 160 180 200 2043 2044 2045 CODE CURRENT LOAD (µA) Figure 11. Histogram of Codes for 10k Samples at Gain of 2 Figure 14. VREF vs. Reference Output Current Load 8000 1900 1800 6967 7000 1700 1600 6000 1500 5000 1400 1300 4000 1200 1100 3000 1000 2000 1732 900 1297 AV = 5V CC 800 V = 5V DRIVE 1000 f = 1MSPS S 700 INTERNAL REFERENCE 0 40 0 600 1 2 3 4 6 8 12 16 24 32 48 64 96 128 2044 2045 2046 2047 2048 2049 CODE GAIN Figure 12. Histogram of Codes for 10k Samples at Gain of 32 Figure 15. 3 dB Bandwidth vs. Gain 80 –50 AV = 5V CC V = 5V 75 DRIVE –55 f = 1MSPS S INTERNAL REFERENCE 70 –60 65 –65 60 GAIN = 32 –70 55 50 –75 GAIN = 2 45 –70 AV = 5V CC 40 V = 5V DRIVE f = 1MSPS S –85 35 INTERNAL REFERENCE F = 100kHz IN –90 30 1 2 3 4 6 8 12 16 24 32 48 64 96 128 10 110 210 310 410 510 610 710 810 910 PGA GAIN ANALOG INPUT FREQUENCY (kHz) Figure 16. SNR vs. PGA Gain for an Analog Input Tone of 100 kHz Figure 13. THD vs. Analog Input Frequency up to 1 MHz at Gain of 2 and 32 Rev. 0 | Page 11 of 32 THD (dB) NUMBER OF HITS NUMBER OF HITS 07606-013 07606-012 07606-011 V (V) REF SNR (dB) 3dB BANDWIDTH (kHz) 07606-016 07606-015 07606-014 AD7262 –90 10 AV = 5V CC V = 3.3V –88 9 DRIVE T = 25°C A –86 8 H TO L, C _C V = 3.6V A B CC –84 7 H TO L, C _C V = 4.5V A B CC H TO L, C _C V = 2.7V A B CC –82 6 H TO L, C _C V = 5V A B CC L TO H, C _C V = 2.7V –80 5 A B CC L TO H, C _C V = 3.6V A B CC –78 4 L TO H, C _C V = 4.5V A B CC L TO H, C _C V = 5V A B CC –76 3 AV = 5V CC –74 V = 5V 2 DRIVE f = 1MSPS S –72 INTERNAL REFERENCE 1 f = 50kHz RIPPLE –70 0 1 2 3 4 6 8 12 16 24 32 48 64 96 128 0 10 203040 5060 7080 90 100 GAIN OVERDRIVE VOLTAGE (mV) Figure 17. Common-Mode Rejection vs. Gain Figure 20. Propagation Delay for Comparator A and Comparator B vs. Overdrive Voltage for Various Supply Voltages –80 2.0 AV = 5V CC V = 3.3V –79 1.8 DRIVE T = 25°C A –78 1.6 –77 1.4 L TO H, C _C V = 2.7V C D CC L TO H, C _C V = 3.6V C D CC –76 1.2 L TO H, C _C V = 4.5V C D CC –75 1.0 L TO H, C _C V = 5V C D CC H TO L, C _C V = 2.7V C D CC –74 0.8 H TO L, C _C V = 3.6V C D CC H TO L, C _C V = 5V C D CC –73 0.6 AV = 5V CC H TO L, C _C V = 4.5V C D CC V = 5V DRIVE –72 0.4 f = 1MSPS S V = 700mV p-p RIPPLE –71 0.2 GAIN = 2 INTERNAL REFERENCE –70 0 0 20 40 60 80 100 120 140 160 180 200 0 10203040506070 8090 100 RIPPLE FREQUENCY (kHz) OVERDRIVE VOLTAGE (mV) Figure 18. Common-Mode Rejection vs. Common-Mode Ripple Frequency Figure 21. Propagation Delay for Comparator C and Comparator D vs. Overdrive Voltage for Various Supply Voltages –10 –70 GAIN 1 AV = 5V V = 5V CC DRIVE V = 5V GAIN = 2 DRIVE –75 –20 f = 1MSPS T = 25°C S A INTERNAL REFERENCE GAIN 2 INTERNAL REFERENCE –80 –30 f = 100kHz 100mV p-p SINE WAVE ON AV IN CC AV DECOUPLED WITH CC –85 –40 10µF AND 100nF CAPACITORS –90 –50 –95 –60 –100 GAIN 3 –70 –105 GAIN 8 GAIN 16 GAIN 4 –80 –110 –90 –115 GAIN 12 GAIN 6 GAIN 24 GAIN ≥ 32 –100 –120 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 0 200 400 600 800 1000 V RANGE (V) SUPPLY RIPPLE FREQUENCY (kHz) CM Figure 19. THD vs. Common-Mode Range for Various PGA Gain Settings Figure 22. Power Supply Rejection Ratio vs. Supply Ripple Frequency? Rev. 0 | Page 12 of 32 THD (dB) CMR (dB) CMR (dB) 07606-017 07606-019 07606-018 PROPAGATION DELAY (µs) PROPAGATION DELAY (µs) PSRR (dB) 07606-022 07606-021 07606-020 AD7262 300 C A/C B SINK CURRENT OUT OUT C C/C D SINK CURRENT OUT OUT 200 D SINK CURRENT OUT 100 0 –100 D SOURCE CURRENT OUT –200 C A/C B SOURCE CURRENT OUT OUT C C/C D SOURCE CURRENT OUT OUT –300 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 CURRENT (mA) Figure 23. D and C Source and Sink Current OUT OUT Rev. 0 | Page 13 of 32 V (V) OR V – V (mV) OUT DD OUT 07606-023 AD7262 TERMINOLOGY Differential Nonlinearity (DNL) Total Harmonic Distortion (THD) Differential nonlinearity is the difference between the measured Total harmonic distortion is the ratio of the rms sum of harmonics and the ideal 1 LSB change between any two adjacent codes in to the fundamental. For the AD7262/AD7262-5, it is defined as the ADC. 2 2 2 2 2 V + V + V + V + V 2 3 4 5 6 Integral Nonlinearity (INL) THD(dB)= 20 log V 1 Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. where V1 is the rms amplitude of the fundamental, and V2, V3, The endpoints of the transfer function are zero scale, a single V , V , and V are the rms amplitudes of the second through the 4 5 6 (1) LSB point below the first code transition and full scale, a single sixth harmonics. (1) LSB point above the last code transition. Peak Harmonic or Spurious Noise Zero Code Error Peak harmonic, or spurious noise, is defined as the ratio of the This is the deviation of the midscale transition (all 1s to all 0s) rms value of the next largest component in the ADC output from the ideal V voltage, that is, V – ½ LSB. IN CM spectrum (up to fS/2, excluding dc) to the rms value of the fun- damental. Normally, the value of this specification is determined Positive Full-Scale Error by the largest harmonic in the spectrum, but for ADCs where This is the deviation of the last code transition (011 … 110) to the harmonics are buried in the noise floor, it is a noise peak. (011 … 111) from the ideal, that is, ADC-to-ADC Isolation V ⎛ ⎞ REF V + −1 LSB ⎜ ⎟ ADC-to-ADC isolation is a measure of the level of crosstalk CM 2× Gain ⎝ ⎠ between the ADC A and ADC B. It is measured by applying a after the zero code error has been adjusted out. full-scale, 100 kHz sine wave signal to all unselected input channels and determining how much that signal is attenuated in the Negative Full-Scale Error selected channel with a 40 kHz signal. The figure given is the This is the deviation of the first code transition (10 … 000) to worst case. (10 … 001) from the ideal, that is, PSRR (Power Supply Rejection) V ⎛ ⎞ REF V − + 1 LSB ⎜ ⎟ CM Variations in power supply affect the full-scale transition but 2× Gain ⎝ ⎠ not the linearity of the converter. Power supply rejection is the after the zero code error has been adjusted out. maximum change in the full-scale transition point due to a Zero Code Error Match change in power supply voltage from the nominal value (see This is the difference in zero code error across both ADCs. Figure 22). Propagation Delay Time, Low to High (tPLH) Positive Full-Scale Error Match Propagation delay time from low to high is defined as the time This is the difference in positive full-scale error across both ADCs. taken from the 50% point on a low to high input signal until the Negative Full-Scale Error Match digital output signal reaches 50% of its final low value. This is the difference in negative full-scale error across both ADCs. Propagation Delay Time, High to Low (tPHL) Track-and-Hold Acquisition Time Propagation delay time from high to low is defined as the time The track-and-hold amplifier returns to track mode at the end taken from the 50% point on a high to low input signal until the of a conversion. Track-and-hold acquisition time is the time digital output signal reaches 50% of its final high value. required for the output of the track-and-hold amplifier to reach Comparator Offset its final value, within ±1/2 LSB, after the end of a conversion. Comparator offset is the measure of the density of digital 1s Signal-to-(Noise + Distortion) Ratio and 0s in the comparator output when the negative analog This ratio is the measured ratio of signal-to-(noise + distortion) terminal of the comparator input is held at a static potential at the output of the analog-to-digital converter. The signal is the and the analog input to the positive terminal of the comparators rms amplitude of the fundamental. Noise is the sum of all non- is varied proportionally about the static negative terminal voltage. fundamental signals up to half the sampling frequency (f /2), S excluding dc. The ratio is dependent on the number of quan- tization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Thus for a 12-bit converter, this is 86 dB. Rev. 0 | Page 14 of 32 AD7262 THEORY OF OPERATION Each pair of comparators operates from its own independent CIRCUIT INFORMATION supply, CA_CBVCC and CC_CDVCC. The comparators are specified The AD7262/AD7262-5 are fast, dual, simultaneous sampling, for supply voltages from 2.7 V to 5.25 V. If desired, CA_CBVCC differential, 12-bit, serial ADCs. The AD7262/ AD7262-5 and CC_CDVCC can be tied to the AVCC supply. The four compa- contain two on-chip differential programmable gain amplifiers, rators on the AD7262/AD7262-5 are functional with C _C V / A B CC two track-and-hold amplifiers, and two successive approxima- C _C V greater than or equal to 1.8 V. However, no specifica- C D CC tion analog-to-digital converters with a serial interface with two tions are guaranteed for comparator supplies less than 2.7 V. separate data output pins. The AD7262/ AD7262-5 also include The wide range of supply voltages ensures that the comparators four on-chip comparators. They are housed in 48-lead LFCSP can be used in a variety of battery backup modes. and LQFP packages, offering the user considerable space-saving advantages over alternative solutions. The AD7262/AD7262-5 The four on-chip comparators on the AD7262/AD7262-5 are require a low voltage 5 V ± 5% AV to power the ADC core and ideally suited for monitoring signals from pole sensors in motor CC supply the digital power, a 5.25 V to 2.7 V C _C V , C _C V control systems. The comparators can be used to monitor A B CC C D CC signals from Hall effect sensors or the inner tracks from an supply for the comparators, and a 2.7 V to 5.25 V VDRIVE supply optical encoder. One of the comparators can be used to count for interface power. the index marker or z marker, which is used on startup to place The on-board PGA allows the user to select from 14 program- the motor in a known position. mable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128. The PGA accepts fully differential OPERATION analog signals. The gain can be selected either by setting the The AD7262/AD7262-5 have two successive approximation logic state of the G0 to G3 pins or by programming the control ADCs, each based around two capacitive DACs and two register. programmable gate amplifiers. The serial clock input accesses data from the part while also The ADC itself comprises control logic, a SAR, and two capacitive providing the clock source for each successive approximation DACs. The control logic and the charge redistribution DACs are ADC. The AD7262/AD7262-5 have an on-chip 2.5 V reference used to add and subtract fixed amounts of charge from the sam- that can be disabled when an external reference is preferred. If pling capacitor amplifiers to bring the comparator back into a the internal reference is used elsewhere in a system, the output balanced condition. When the comparator is rebalanced, the from V A and V B must first be buffered. If the internal REF REF conversion is complete. The control logic generates the ADC reference is the preferred option, the user must tie the output code. REFSEL pin to a logic high voltage. Alternatively, if REFSEL Each ADC is preceded by its own programmable gain stage. The is tied to GND, an external reference can be supplied to both PGA features high analog input impedance, true differential analog ADCs through the VREFA and VREFB pins (see the Reference inputs that allow the output from any source or sensor to be section). connected directly to the PGA inputs without any requirement for The AD7262/AD7262-5 also feature a range of power-down additional external buffering. The variable gain settings ensure options to allow the user great flexibility with the independent that the device can be used for amplifying signals from a variety circuit components while allowing for power savings between of sources. The AD7262/AD7262-5 offer the flexibility to choose conversions. The power-down feature is implemented via the the most appropriate gain setting to use the wide dynamic range control register or the PD0 to PD2 pins, as described in the of the device. Control Register section. ANALOG INPUTS COMPARATORS Each ADC in the AD7262/AD7262-5 has two high impedance The AD7262/AD7262-5 have four on-chip comparators. Com- differential analog inputs. Figure 24 shows the equivalent circuit parator A and Comparator B have ultralow power consumption, of the analog input structure of the AD7262/AD7262-5. It consists with static power consumption typically less than 10 μW with a of a fully differential input amplifier that buffers the analog input 3.3 V supply. Comparator C and Comparator D feature very fast signal and provides the gain selected by using the gain pins or propagation delays of 130 ns for a 200 mV differential overdrive. the control register. These comparators have push-pull output stages that operate from the V supply. This feature allows operation with a DRIVE minimum amount of power consumption. Rev. 0 | Page 15 of 32 AD7262 The two diodes provide ESD protection. Care must be taken to When a full-scale step input is applied to either differential input ensure that the analog input signals never exceed the supply rails on the AD7262/AD7262-5 while the other analog input is held by more than 300 mV. Exceeding 300 mV causes these diodes to at a constant voltage, 3 μs of settling time is typically required prior to capturing a stable digital output code. become forward-biased and to start conducting current into the substrate. These diodes can conduct up to 10 mA without Transfer Function causing irreversible damage to the part. The C1 capacitors in Figure 24 are typically 5 pF and can primarily be attributed to The AD7262/AD7262-5 output is twos complement, and the pin capacitance. ideal transfer characteristic is shown in Figure 25. The designed code transitions occur at successive integer LSB values (that is, V DD 1 LSB, 2 LSB, and so on). The LSB size is dependent on the analog input range selected. The LSB size for the AD7262/AD7262-5 is V + IN V + AMP OUT shown in the following equation: C1 ⎛ ⎞ ⎛ V ⎞ ⎛ V ⎞ ⎛ ⎞ ⎛ ⎞ REF REF ⎜ ⎟ ⎜V + ⎟−⎜V − ⎟ ⎜ ⎟ ⎜ ⎟ CM CM 2×Gain 2× Gain ⎜ ⎝ ⎠ ⎝ ⎠ ⎟ ⎝ ⎠ ⎝ ⎠ 2× ⎜ ⎟ 4096 ⎜ ⎟ V ⎜ ⎟ DD ⎝ ⎠ AMP V – OUT V – IN C1 011...111 Figure 24. Analog Input Structure 011...110 The AD7262/AD7262-5 can accept differential analog inputs from V V 000...001 ⎛ ⎞ ⎛ ⎞ REF REF V − to V + ⎜ ⎟ ⎜ ⎟ CM CM 000...000 2×Gain 2×Gain ⎝ ⎠ ⎝ ⎠ 111...111 Table 5 details the analog input range for the AD7262/AD7262-5 for the various PGA gain settings. Here, VREF = 2.5 V and VCM = 100...010 2.5 V (AVCC/2, with AVCC = 5 V). 100...001 100...000 Table 5. Analog Input Range for Various PGA Gain Settings 0V (V – (FSR/2)) + 1LSB (V + (FSR/2)) – 1LSB CM CM PGA Gain Setting Analog Input Range for VIN+ and VIN− ANALOG INPUT 1 1 0.75 V to 3.25 V NOTES 2 1.875 V to 3.125 V 1. FULL-SCALE RANGE (FSR) = V + – V –. IN IN 3 2.083 V to 2.916 V Figure 25. Twos Complement Transfer Function 4 2.187 V to 2.813 V V DRIVE 6 2.292 V to 2.708 V The AD7262/AD7262-5 have a V feature to control the DRIVE 8 2.344 V to 2.656 V voltage at which the serial interface operates. V allows the DRIVE 12 2.396 V to 2.604 V ADC and the comparators to easily interface to both 3 V and 16 2.422 V to 2.578 V 5 V processors. For example, when the AD7262/AD7262-5 are 24 2.448 V to 2.552 V operated with AVCC = 5 V, the VDRIVE pin can be powered from 32 2.461 V to 2.539 V a 3 V supply, allowing a large analog input range with low voltage 48 2.474 V to 2.526 V digital processors. 64 2.480 V to 2.520 V 96 2.487 V to 2.513 V 128 2.490 V to 2.510 V 1 For VCM = 2 V. If VCM = AVCC /2, the analog input range for VIN+ and VIN− is 1.6 V to 3.4 V. Rev. 0 | Page 16 of 32 07606-024 ADC CODE 07606-025 AD7262 REFERENCE TYPICAL CONNECTION DIAGRAMS The AD7262/AD7262-5 can operate with either the internal Figure 26 and Figure 27 are typical connection diagrams for the 2.5 V on-chip reference or an externally applied reference. The AD7262/AD7262-5. In these configurations, the AGND pin is logic state of the REFSEL pin determines whether the internal connected to the analog ground plane of the system, and the reference is used. The internal reference is selected for both ADCs DGND pin is connected to the digital ground plane of the system. when the REFSEL pin is tied to logic high. If the REFSEL pin is The analog inputs on the AD7262/AD7262-5 are true differen- tied to AGND, an external reference can be supplied through tial and have an input impedance in excess of 1 GΩ; thus, no the VREFA and/or VREFB pins. On power-up, the REFSEL pin driving op amps are required. The AD7262/AD7262-5 can operate must be tied to either a low or high logic state for the part to with either an internal or an external reference. In Figure 26, the operate. Suitable reference sources for the AD7262/AD7262-5 AD7262/AD7262-5 are configured to operate in control register include AD780, AD1582, ADR431, REF193, and ADR391. mode; thus, G0 to G3, PD1, and PD2 can be connected to ground (low logic state). Figure 27 has the gain pins configured for a gain The internal reference circuitry consists of a 2.5 V band gap of 2 setup; thus, the device is in pin-driven mode. Both circuit reference and a reference buffer. When the AD7262/AD7262-5 configurations illustrate the use of the internal 2.5 V reference are operated in internal reference mode, the 2.5 V internal reference is available at the V A and V B pins, which should The C _C V and the C _C V pins can be connected to either REF REF A B CC C D CC be decoupled to AGND using a 1 μF capacitor. It is recommended a 3 V or a 5 V supply voltage. The AVCC pin must be connected that the internal reference be buffered before applying it elsewhere to a 5 V supply. All supplies should be decoupled with a 100 nF in the system. The internal reference is capable of sourcing up capacitor at the device pin, and some supply sources may require a to 90 μA of current when the converter is static. If the internal 10 μF capacitor where the source is supplied to the circuit board. reference operation is required for the ADC conversion, the The V pin is connected to the supply voltage of the micro- DRIVE REFSEL pin must be tied to logic high on power-up. The refer- processor. The voltage applied to the V input controls the DRIVE ence buffer requires 240 μs to power up and charge the 1 μF voltage of the serial interface. V can be set to 3 V or 5 V. DRIVE decoupling capacitor during the power-up time. Rev. 0 | Page 17 of 32 AD7262 +5V ANALOG SUPPLY 1 100nF 10µF 100nF 100nF 1 100nF 10µF 100nF COMPARATOR 2 SUPPLY 3V TO 5V 100nF 100nF 100nF 17 44 5 6 8 19 42 28 2 7 11 20 41 12 1 33 3.125V 27 3 3V OR 5V V V V – DRIVE DRIVE 2.500V A SUPPLY V – AND V + 1 A A 100nF 10µF 1.875V 40 CONNECT GAIN 2 G0 DIRECTLY 39 G1 TO SENSOR 3.125V 38 G2 4 OUTPUTS V + 37 2.500V A G3 1.875V GAIN 2 SERIAL INTERFACE 43 V A 34 REF SCLK THIS REFERENCE SIGNAL 1µF MUST BE BUFFERED 35 AD7262 MICROPROCESSOR/ BEFORE IT CAN BE CS MICROCONTROLLER USED ELSEWHERE IN 32 THE CIRCUIT D A OUT 18 V B REF 31 D B OUT 1µF 24 V REFSEL DRIVE 36 CAL 3.125V 9 2.500V V + B V – AND V + B B 23 PD0/D CONNECT 1.875V IN GAIN 2 DIRECTLY 22 PD1 TO SENSOR 3.125V OUTPUTS 10 21 V – B 2.500V PD2 1.875V GAIN 2 13 14 15 16 45 46 47 48 25 26 29 30 FAST PROPAGATION DELAY LOW POWER COMPARATOR INPUTS COMPARATOR INPUTS 1 THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE REQUIRED IN ALL SYSTEMS. 2 THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED. Figure 26. Typical Connection Diagram for the AD7262/AD7262-5 in Control Register Mode (All Gain Pins Tied to Ground) Configured for a PGA Gain of 2 Rev. 0 | Page 18 of 32 C + C C C GND C – C C– D– C C GND C + A– B– D AGND C – D AGND AGND AGND AGND DGND C – B AV CC C + B AV C – A CC AV C + A CC AV CC AV C D CC OUT C C V C C C– D CC OUT C C V C B A– B CC OUT AV C A CC OUT 07606-026 AD7262 +5V ANALOG SUPPLY 1 100nF 10µF 100nF 100nF 1 100nF 10µF 100nF COMPARATOR 2 SUPPLY 3V TO 5V 100nF 100nF 100nF 17 44 5 6 8 19 42 28 2 7 11 20 41 12 1 33 3.125V 27 3 3V OR 5V V V V – DRIVE DRIVE 2.500V A SUPPLY V – AND V + 1 A A 100nF 10µF 1.875V 40 CONNECT GAIN 2 G0 DIRECTLY 39 V G1 DRIVE TO SENSOR 3.125V 38 G2 4 OUTPUTS V + 37 GAIN 2 2.500V A G3 SETUP 1.875V GAIN 2 SERIAL INTERFACE 43 V A 34 REF SCLK THIS REFERENCE SIGNAL 1µF MUST BE BUFFERED 35 AD7262 MICROPROCESSOR/ BEFORE IT CAN BE CS MICROCONTROLLER USED ELSEWHERE IN 32 THE CIRCUIT D A OUT 18 V B REF 31 D B OUT 1µF 24 V REFSEL DRIVE 36 CAL 3.125V 9 2.500V V + B V – AND V + B B 23 PD0/D V CONNECT 1.875V DRIVE IN GAIN 2 BOTH DIRECTLY 22 PD1 COMPARATORS TO SENSOR 3.125V AND ADCs OUTPUTS 10 21 POWERED ON V – B 2.500V PD2 V DRIVE 1.875V GAIN 2 13 14 15 16 45 46 47 48 25 26 29 30 FAST PROPAGATION DELAY LOW POWER COMPARATOR INPUTS COMPARATOR INPUTS 1 THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE REQUIRED IN ALL SYSTEMS. 2 THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED. Figure 27. Typical Connection Diagram for the AD7262/AD7262-5 in Pin-Driven Mode with Gain of 2 and Both ADCs and Comparators Fully Powered On Rev. 0 | Page 19 of 32 C + C C C GND C – C C– D– C C GND C + A– B– D AGND C – D AGND AGND AGND AGND C – B DGND C + AV B CC AV C – A CC AV C + A CC AV CC AV C D CC OUT C C V C C C– D CC OUT C C V C B A– B CC OUT AV C A CC OUT 07606-027 AD7262 Comparator Application Details APPLICATION DETAILS The comparators on the AD7262/AD7262-5 have been The AD7262/AD7262-5 have been specifically designed to meet designed with no internal hysteresis, allowing users the the requirements of any motor control shaft position feedback flexibility to add external hysteretic if required for systems loop. The devices can interface directly to multiple sensor types, operating in noisy environments. If the comparators on the including optical encoders, magneto resistive sensors, and Hall AD7262/AD7262-5 are used with external hysteresis, some effect sensors. Flexible analog inputs that incorporate program- external resistors and capacitors are required, as shown in mable gain ensure that identical board design can be used for a Figure 28. The value of R and R , the external resistors, can be F S variety of sensors, which results in reduced design cycles and costs. determined using the following equation, depending on the The two simultaneous sampling ADCs are used to sample the amount of hysteresis required in the application: sine and cosine outputs from the sensor. No external buffering R is required between the sensor/transducer and the analog inputs S V = ×C _ C V x x HYS CC R + R of the AD7262/AD7262-5. The on-chip comparators can be S F used to monitor the pole sensors, which can be Hall effect sensors where Cx_CxVCC = CA_CBVCC or CC_CDVCC. or the inner tracks from an optical encoder. The amount of hysteresis chosen must be sufficient to eliminate Figure 29 shows how the AD7262/AD7262-5 can be used in a the effects of analog noise at the comparator inputs, which may typical application. An optical encoder is shown in Figure 29, affect the stability of the comparator outputs. The level of but other sensor types could as easily be used. Figure 29 indicates hysteresis required in any system depends on the noise in the a typical application configuration only, and there are several system; thus, the values of R and R need to be carefully selected F S other configurations that render equally effective results. to eliminate any noise effects. To increase the level of hysteresis in the system, increase the value of RS or RF. For example, RF = 10 MΩ, RS = 1 kΩ give 330 μV of hysteresis with a Cx_CxVCC of 3.3 V; if hysteresis is increased to 1 mV, RS = 3.1 kΩ. In certain applications, a load capacitor (100 pF) may be required on the comparator outputs to suppress high frequency transient glitches. R F R S C – x R C x SENSOR S C + OUT x Figure 28. Recommended Comparator Connection Diagram Rev. 0 | Page 20 of 32 07606-028 AD7262 COMP COMP AV V A CC REF REF BUF AD7262 12-BIT A V + A SUCCESSIVE OUTPUT D A V – PGA T/H OUT APPROXIMATION A DRIVERS ADC SCLK CAL CS CONTROL REFSEL LOGIC G0 G1 G2 G3 B V DRIVE V + B 12-BIT SUCCESSIVE OUTPUT V – T/H D B B PGA OUT APPROXIMATION DRIVERS ADC PD0/D IN PD1 BUF PD2 V B REF C _C V A B CC H.E. Z C + A OUTPUT C A OUT DRIVERS C – A COMP U C + B OUTPUT C B OUT DRIVERS C – B COMP C _C _GND A B C _C V C D CC C + V C OUTPUT C C OUT DRIVERS C – C COMP W C + D OUTPUT C D OUT DRIVERS C – D COMP C _C _GND C D AGND DGND Figure 29. Typical System Connection Diagram with Optical Encoder Rev. 0 | Page 21 of 32 07606-029 AD7262 MODES OF OPERATION The AD7262/AD7262-5 allow the user to choose between two POWER-DOWN MODES modes of operation, pin-driven mode and control register mode. The AD7262/AD7262-5 offer the user a number of power-down PIN-DRIVEN MODE options to enable individual device components to be powered down independently. These options can be chosen to optimize In pin-driven mode, the user can select the gain of the PGA, the the power dissipation for different application requirements. power-down mode, internal or external reference, and initiate The power-down modes can be selected by either programming a calibration of the offset for both ADC A and ADC B. These the device via the control register or by driving the PD pins to functions are implemented by setting the logic levels on the gain the appropriate logic levels. By setting the PD pins to a logic low pins (G3 to G0), the power-down pins (PD2 to PD0), the REFSEL level when in pin-driven mode, all four comparators and both pin, and the CAL pin, respectively. ADCs can be powered down. The PD2 and PD0 pins must be The logic state of Pin G3 to Pin G0 determines which mode of set to logic high and the PD1 pin set to logic low to power up all operation is selected. Pin-driven mode is selected if at least one circuitry on the AD7262/AD7262-5. The PD pin configurations of the gain pins is set to a logic high state. Alternatively, if all for the various power-down options are outlined in Table 7. four gain pins are connected to a logic low, the control register mode of operation is selected. Table 7. Power-Down Modes Comparator A, Comparator C, ADC A, GAIN SELECTION PD2 PD1 PD0 Comparator B Comparator D ADC B The on-board PGA allows the user to select from 14 program- 0 0 0 Off Off Off mable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, 0 0 1 Off Off On ×48, ×64, ×96, and ×128. The PGA accepts fully differential 0 1 0 Off On Off analog signals and provides three key functions, which include 0 1 1 On Off Off selecting gains for small amplitude input signals, driving the 1 0 0 On On Off ADCs switched capacitive load, and buffering the source from 1 0 1 On On On the switching effects of the SAR ADCs. The AD7262/AD7262-5 1 1 1 1 1 1 Off Off Off offer the user great flexibility in user interface, providing gain 1 PD2 = PD1 = PD0 = 1 resets the AD7262/AD7262-5 when in pin-driven mode selection via the control register or by driving the gain pins to only. the desired logic state. The AD7262/AD7262-5 have four gain The AVCC and VDRIVE supplies must continue to be supplied to pins, G3, G2, G1 and G0, as shown in Figure 3. Each gain setting the AD7262/AD7262-5 when the comparators are powered up is selected by setting up the appropriate logic state on each of but the ADCs are powered-down. External diodes can be used the four gain pins, as outlined in Table 6. If all four gain pins are from the CA_CBVCC and/or CC_CDVCC to both the AVCC and the connected to a logic low level, the part is put in control register V supplies to ensure they retain a supply at all instances. DRIVE mode and the gain settings are selected via the control register. The AD7262/AD7262-5 can be reset in pin-driven mode only Table 6. Gain Selection by setting the PDx pins to a logic high state. When the device is G3 G2 G1 G0 Gain reset, all the registers are cleared and the four comparators and 0 0 0 0 Software control the two ADCs are left powered down. via control register In normal mode of operation with the ADCs and comparators 0 0 0 1 1 powered on, the CA_CBVCC/CC_CDVCC supply and the AVCC 0 0 1 0 2 supply can be at different voltage levels, as indicated in Table 1. 0 0 1 1 3 When the comparators on the AD7262/AD7262-5 are in power- 0 1 0 0 4 down mode, and the C _C V /C _C V supplies are at a A B CC C D CC 0 1 0 1 6 potential 0.3 V greater than or less than the AV supply, the CC 0 1 1 0 8 supplies consume more current than would be the case if both 0 1 1 1 12 sets of supplies were at the same potential. This configuration 1 0 0 0 16 does not damage the AD7262/AD7262-5 but results in additional 1 0 0 1 24 current flowing in any or all of the AD7262/AD7262-5 supply 1 0 1 0 32 pins. This is due to ESD protection diodes within the device. In 1 0 1 1 48 applications where power consumption in power-down mode is 1 1 0 0 64 critical, it is recommended that the C _C V /C _C V supply A B CC C D CC 1 1 0 1 96 and the AV supply be held at the same potential. CC 1 1 1 0 128 Rev. 0 | Page 22 of 32 AD7262 Power-Up Conditions These functions can also be implemented by setting the logic levels on the gain pins, the power-down pins, and the CAL pin, On power-up, the status of the gain pins determine which mode respectively. The control register can also be used to read the of operation is selected, as outlined in the Gain Selection section. offset and gain registers. All registers are set to 0 by default. Data is loaded from the PD0/DIN pin of the AD7262/AD7262-5 If the AD7262/AD7262-5 are powered up in pin-driven mode, on the falling edge of SCLK when CS is in a logic low state. The the gain pins and the PDx pins should be configured to the control register is selected by first writing the appropriate four appropriate logic states and a calibration initiated if required. WR bits, as outlined in Table 10. The 12 data bits must then be Alternatively, if the AD7262/AD7262-5 are powered up in th clocked into the control register of the device. Thus, on the 16 control register mode, the comparators and ADCs are powered falling SCLK edge, the LSB is clocked into the device. One more down and the default gain is 1. Thus, powering up in control SCLK cycle is then required to write to the internal device register mode requires a write to the device to power up the registers. In total, 17 SCLK cycles are required to successfully comparators and the ADCs. write to the AD7262/AD7262-5. The data is transferred on the It takes 15 μs to power up the AD7262/AD7262-5 when using PD0/DIN line while the conversion result is being processed. an external reference. When the internal reference is used, 240 μs The data transferred on the DIN line corresponds to the AD7262/ are required to power up the AD7262/AD7262-5 with a 1 μF AD7262-5 configuration for the next conversion. decoupling capacitor. Only the information provided on the 12 falling clock edges CONTROL REGISTER CS after the falling edge and the initial four write address bits is loaded to the control register. The PD0/DIN pin should have a The control register on the AD7262/AD7262-5 is a 12-bit read logic low state for the four bits RD3 to RD0 when using the and write register, which is used to control the device when not control register to select the power-down modes or gain setting in pin-driven mode. The PD0/D pin serves as the serial IN or when initializing a calibration. The RD bits should also be set pin for the AD7262/AD7262-5 when the gain pins are set to DIN to a logic low level to access the ADC results from both D A OUT 0 (that is, the part is not in pin-driven mode). The control and D B. OUT register can be used to select the gain of the PGAs, the power- down modes, and the calibration of the offset for both ADC A The power-up status of all bits is 0 and the MSB denotes the first and ADC B. When operating in the control register mode, PD1 bit in the data stream. The bit functions are outlined in Table 8 and PD2 should be connected to a low logic state. and Table 9. Table 8. Control Register Bits MSB LSB Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RD3 RD2 RD1 RD0 CAL PD2 PD1 PD0 G3 G2 G1 G0 Table 9. Control Register Bit Function Description Bits Mnemonic Description 11 to 8 RD3 to RD0 Register address bits. These bits select which register the subsequent read is from. See Table 11. 7 CAL Setting this bit high initiates an internal offset calibration. Once the calibration is completed, this pin can be reset low, and the internal offset, which is stored in the on-chip offset registers, is automatically removed from the ADC results. 6 to 4 PD2 toPD0 Power-down bits. These bits select which power-down mode is programmed. See Table 7. 3 to 0 G3 to G0 Gain selection bits. These bits select which gain setting is used on the front-end PGA. See Table 6. Table 10. Write Address Bits WR3 WR2 WR1 WR0 Read Register Addressed 0 0 0 1 Control register CS t 8 t 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 31 SCLK t QUIET THREE-STATE DB11 DB10 DB0 D A OUT THREE- t t 13 14 STATE THREE-STATE PD0/D IN WR3 WR2 WR1 WR0 RD3 RD2 RD1 RD0 CAL PD2 PD1 PD0 G3 G2 G1 G0 Figure 30. Timing Diagram for a Write Operation to the Control Register Rev. 0 | Page 23 of 32 07606-030 AD7262 Table 11. Read and Write Register Addresses ON-CHIP REGISTERS RD3 RD2 RD1 RD0 Comment The AD7262/AD7262-5 contain a control register, two offset 0 0 0 0 ADC result (default) registers for storing the offsets for each ADC, and two external 0 0 0 1 Control register gain registers for storing the gain error. The control register and 0 0 1 0 Offset ADC A internal the offset and gain registers are read and write registers. On 0 0 1 1 Offset ADC B internal power-up, all registers in the AD7262/AD7262-5 are set to 0. 0 1 0 0 Gain ADC A external 0 1 0 1 Gain ADC B external Addressing the On-Chip Registers Writing to a Register Reading from a Register Data is loaded from the PD0/DIN pin of the AD7262/AD7262-5 The internal offset of the device, which has been measured by on the falling edge of SCLK when CS is in a logic low state. Four the AD7262/AD7262-5 and stored in the on-chip registers address bits and 12 data bits must be clocked into the device. during the calibration, can be read back by the user. The th Thus, on the 16 falling SCLK edge, the LSB is clocked into the content of the external gain registers can also be read. To read AD7262/AD7262-5. One more SCLK cycle is then required to the content of any register, the user must first write to the write to the internal device registers. In total, 17 SCLK cycles control register by writing 0001 to the WR3 to WR0 bits via the are required to successfully write to the AD7262/AD7262-5. PD0/DIN pin, as outlined in Table 10. The next four bits in the The control and offset registers are 12-bits registers; the gain control register are the RD bits, which are used to select the registers are 7-bit registers. desired register from which to read. The appropriate 4-bit address for each of the offset and gain registers is outlined in Table 11. When writing to a register, the user must first write the address The remaining eight SCLK cycles bits are used to set the bits corresponding to the selected register. Table 11 shows the remaining bits in the control register to the desired state for the decoding of the address bits. The four RD bits are written MSB next ADC conversion. first, that is, RD3 followed by RD2, RD1, and RD0. The th AD7262/AD7262-5 decodes these bits to determine which The 19 SCLK falling edge clocks out the first data bit of the register is being addressed. The subsequent 12 bits of data are digital code corresponding to the value stored in the selected written to the addressed register. internal device register on the DOUTA pin. DOUTB outputs the conversion result from ADC B. Once the selected register has When writing to the external gain registers, the seven bits of been read, the control register must be reset to output the ADC data immediately after the four address bits are written to the results for future conversions. This is achieved by writing 0001 register. However, 17 SCLK cycles are still required, and the to the WR3 to WR0 bits, followed by 0000 to the RD bits. The PD0/D pin of the AD7262/AD7262-5 should be tied low for IN remaining eight bits in the control register should then be set to the five additional clock cycles. the required configuration for the next ADC conversion. CS t 8 t 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 31 SCLK t QUIET THREE-STATE DB11 DB10 DB0 A A A A D OUT t t THREE- 13 14 STATE THREE-STATE RD3 RD2 RD1 RD0 MSB DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PD0/D IN Figure 31. Timing Diagram for Writing to a Register CS t 8 t 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 31 SCLK t QUIET THREE-STATE DB11A DB10A DB0A D A OUT t t 13 14 THREE- STATE THREE-STATE 0 0 0 1 RD3 RD2 RD1 RD0 0 0 0 0 0 0 0 0 PD0/D IN Figure 32. Timing Diagram for a Read Operation with PD0/DIN as an Input Rev. 0 | Page 24 of 32 07606-032 07606-031 AD7262 SERIAL INTERFACE st Figure 33 and Figure 34 show the detailed timing diagrams for reading on the 21 SCLK rising edge. The remainder of the 12-bit the serial interfacing of the AD7262/AD7262-5. The serial clock result follows, with the final bit in the data transfer being valid st th provides the conversion clock and controls the transfer of on the 31 rising edge. The LSB is provided on the 30 falling information from the AD7262/AD7262-5 after the conversion. clock edge. The AD7262/AD7262-5 has two output pins corresponding to An alternative to reading on the rising SCLK edge is to use a each ADC. Data can be read from the AD7262/AD7262-5 using slower SCLK frequency. If a slower SCLK frequency is used, for both D A and D B. Alternatively, a single output pin of the OUT OUT example 32 MHz with the AD7262, this will enable reading on user’s choice can be used. The SCLK input signal provides the the subsequent falling SCLK edge after the data has been clock source for the serial interface. clocked out, as illustrated in Figure 35. A throughput rate of The falling edge of CS puts the track-and-hold into hold mode, 1 MSPS can still be achieved for the AD7262 when a 32 MHz SCLK frequency is used. The remaining data is then clocked out at which point the analog input is sampled. The conversion is by subsequent SCLK falling edges. When using a 32 MHz or also initiated at this point and requires a minimum of 19 SCLKs less SCLK frequency with the AD7262 or when using the to complete. The D x lines remain in three-state while the OUT th th AD7262-5, the 20 falling clock edge on the serial clock has the conversion is taking place. On the 19 SCLK falling edge, the MSB provided for reading and also clocks out the second data bit. AD7262/AD7262-5 return to track mode and the D A and OUT The remainder of the 12-bit result follows, with the final bit in DOUTB lines are enabled. The data stream consists of 12 bits of st the data transfer being valid on the 31 falling edge. The LSB is data, MSB first. th provided on the 30 falling clock edge. th The MSB of the conversion result is clocked out on the 19 On the rising edge of CS, D A and D B go back into three- SCLK falling edge to be read by the microcontroller or DSP on OUT OUT th either the subsequent SCLK falling edge (20 falling edge) or CS state. If is not brought high after 31 SCLKs but is instead th the 20 SCLK rising edge. The choice of whether to read on the held low for an additional 12 SCLK cycles, the data from rising or falling SCLK edge depends on the SCLK frequency ADC B is output on D A after the ADC A result. Likewise, OUT being used. When the maximum SCLK frequency of 40 MHz is the data from ADC A is output on D B after the ADC B OUT used with a VDRIVE voltage of 5 V, the maximum specified access result. This is illustrated in Figure 34, which shows the DOUTA time (t4) is 23 ns, resulting in 2 ns of setup time, which may not example. In this case, the DOUT line in use goes back into three- th be sufficient for most DSPs or microcontrollers. Under these state on the 45 SCLK falling edge or the rising edge of CS, conditions, it is recommended to use the rising SCLK edge to whichever occurs first. read the data. In this case, the MSB of the conversion result is CS If the falling edge of SCLK coincides with the falling edge of , th th clocked out on the 19 SCLK falling edge to be read on the 20 the falling edge of SCLK is not acknowledged by the AD7262 SCLK rising edge, as shown in Figure 33. The remaining data is and the next falling edge of SCLK is the first one registered after then clocked out by subsequent SCLK falling edges. When using CS the falling edge of . th a 40 MHz SCLK frequency, the 20 falling clock edge on the serial clock clocks out the second data bit, which is provided for Rev. 0 | Page 25 of 32 AD7262 FIRST DATA BIT CLOCKED OUT FIRST DATA BIT READ TH TH ON THE 19 FALLING EDGE ON 20 RISING EDGE CS t 8 t 2 15 23 4 1819 20 21 22 29 30 31 SCLK t t 5 4 DB11 DB10 DB9 DB1 DB0 D A A A A A A OUT THREE-STATE THREE- STATE DB11 DB10 DB9 DB1 DB0 D B B B B B B OUT THREE-STATE THREE- STATE th Figure 33. Serial Interface Timing Diagram When Reading Data on the 20 Rising SCLK Edge with a 40 MHz SCLK CS 12 18 19 20 21 29 30 31 SCLK 43 44 45 t 10 D A DB13 DB12 DB1 DB0 DB13 DB12 DB1 DB0 OUT A A A A B B B B THREE- THREE-STATE STATE Figure 34. Reading Data from Both ADCs on One DOUT Line with 45 SCLKs FIRST DATA BIT CLOCKED FIRST DATA BIT READ OUT ON THIS EDGE ON THIS EDGE CS t 8 t 2 t 6 34 5 SCLK 1 2 18 19 20 21 29 30 31 t t 7 9 t 5 t 3 t t 4 QUIET DB11 DB10 DB9 DB1 DB0 D A A A A A A OUT THREE-STATE THREE- STATE DB11 DB10 DB9 DB1 DB0 D B B B B B B OUT THREE-STATE THREE- STATE Figure 35. Serial Interface Timing Diagram When Reading Data on the Falling SCLK Edge with a Slow SCLK Frequency Rev. 0 | Page 26 of 32 07606-035 07606-033 07606-034 AD7262 CALIBRATION The AD7262/AD7262-5 registers store the offset value that can INTERNAL OFFSET CALIBRATION be accessed easily by the user (see the Reading from a Register The AD7262/AD7262-5 allow the user to calibrate the device section). When the device is calibrating, the differential analog offset using the CAL pin. This is achieved by setting the CAL inputs for each respective ADC are shorted together internally pin to a high logic level, which initiates a calibration on the next and a conversion is performed. A digital code representing the CS falling edge. The calibration requires one full conversion offset is stored internally in the offset registers, and subsequent cycle, which contains a CS falling edge followed by 19 SCLKs to conversion results have this measured offset removed. complete. The CAL pin can remain high for more than one When the AD7262/AD7262-5 are calibrated, the calibration conversion if desired, and the AD7262/AD7262-5 continue to results stored in the internal device registers are only relevant calibrate. for the particular PGA gain selected at the time of calibration. If CS The CAL pin should only be driven high when the pin is high the PGA gain is changed, the AD7262/AD7262-5 must be CS or after 19 SCLK cycles have elapsed when is low (that is, recalibrated. If the device is not recalibrated when the PGA gain between conversions). The CAL pin must be driven high t ns 12 is changed, the offset for the previous gain setting continues to before CS goes low. If the CS pin goes low before the t has 12 be removed from the digital output code, which may lead to elapsed, the calibration result is inaccurate for the current inaccuracies. conversion, but, provided that the CAL pin remains high, the The offset range, which can be calibrated for, is ±128 least subsequent calibration conversion is correct. If the CAL pin is significant bits at a gain of 1. The maximum offset voltage, set to a logic high state during a conversion, that conversion result which can be calibrated for, is reduced as the gain of the PGA is corrupted. is increased. Provided that the CAL pin has been held high for a minimum Table 12 details the maximum offset voltage, which can be of one conversion, and once t12 and t11 have been adhered to, the removed by the AD7262/AD7262-5 without compromising the th calibration is complete after the 19 SCLK cycle, and the CAL available digital output code range. The least significant bit size is pin can be driven to a logic low state. The next CS falling edge BITs AV /2 , which is 5/4096 or 1.22 mV for the AD7262/ CC after the CAL pin has been driven to a low logic state initiates AD7262-5. The maximum removable offset voltage is given by a conversion of the differential analog input signal for both ADC A and ADC B. 1.22 mV Alternatively, one can use the control register to initiate an ±128 LSB× Gain offset calibration. This is done by setting the CAL bit in the control register to 1. The calibration is then initiated on the next Table 12. Offset Range CS falling edge, but the current conversion is corrupted. The Gain Maximum Removable Offset Voltage ADCs on the AD7262/AD7262-5 must remain fully powered 1 ±156.16 mV up to complete the internal calibration. 2 ±78.08 mV 3 ±52.053 mV 1 32 ±4.88 mV 1 This is the maximum removable offset for PGA gain ≥ 32. t 11 t 12 CAL t 8 CS t 6 t 2 1 2 3 19 20 21 30 31 12 3 19 20 21 SCLK t 7 Figure 36. Calibration Timing Diagram Rev. 0 | Page 27 of 32 07606-036 AD7262 ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION The internal offset calibration register can be adjusted manually The AD7262/AD7262-5 also allow the user to write to an to compensate for any signal path offset from the sensors to the external gain register, thus enabling the removal of any overall ADC. Here, no internal calibration is required, and the CAL pin system gain error. Both ADC A and ADC B have independent can remain at a low logic state. By changing the contents of the external gain registers, allowing the user to calibrate offset register, different amounts of offset on the analog input independently the gain on both ADC A and ADC B signal signal can be compensated for. To determine the digital code to paths. The gain calibration feature can be used to implement be written to the offset register accurate gain matching between ADC A and ADC B. 1. Configure the sensor to its offset state. The system calibration function is used by setting the sensors to 2. Perform a number of conversions using the AD7262/ which the AD7262/AD7262-5 are connected to a 0 gain state. AD7262-5. The AD7262/AD7262-5 convert this analog input to a digital 3. Take the mean digital output code from both D A output code, which corresponds to the system gain and is avail- OUT and D B. This is a 12-bit result and the offset register able on the D x pins. This digital output code can then be stored OUT OUT is 12 bits; thus, the result can be stored directly in the in the appropriate external register. For details on how to write to offset register. a register, see the Writing to a Register section and Table 11. 4. Write the digital code to the offset registers to calibrate the The gain calibration register contains seven bits of data. By AD7262/AD7262-5. changing the contents of the gain register, different amounts of gain on the analog input signal can be compensated for. The If a +10 mV offset is present in the analog input signal and the MSB is a sign bit, while the remaining six bits store the multiplica- gain of the PGA is 2, the code that needs to be written to the tion factor, which is used to adjust the analog input range. The offset register to compensate for the offset is gain register value is effectively multiplied by the analog input +10 mV to scale the conversion result over the full range. Increasing the = 16.39= 0000 0001 0000 (1.22 mV / 2 gain register multiplication factor compensates for a larger analog input range, and decreasing the gain register multiplier If a − 10 mV offset is present in the analog input signal and the compensates for a smaller analog input range. Each bit in the gain of the PGA is 2, the code that needs to be written to the −4 gain calibration register has a resolution of 2.4 × 10 V (1/4096). offset register to compensate for the offset is A maximum of 1.538% of the analog range can be calibrated for. −10 mV The multiplier factor stored in the gain register can be decoded = −16.39 = 1000 0001 0000 (305 μV/ 2) as outlined in Table 13. The gain registers can be cleared by writing all 0s to each register, as described in the Writing to a Register section. For accurate gain calibration, both the positive and negative full-scale digital output codes should be measured prior to determining the multiplication factor that is written to the gain register. Table 13. Decoding of Multiplication Factors for Gain Calibration Digital Gain Gain Register Multiplier Multiplier Analog Input Error Code Equation Value Comments V LSB (Sign bit + 6 bits) (1 ± x/4096) V max 0 LSB 0 000000 1 − 0/4096 1 Sign bit = 0, which implies negative sign IN in multiplier equation VIN max – 244 μV −2 LSB 0 000001 1 − 1/4096 0.999755859 Sign bit = 0, which implies negative sign in multiplier equation VIN max − (63 × 244 μV) −126 LSB 0 111111 1 − 63/4096 0.98461914 Sign bit = 0, which implies negative sign in multiplier equation V max 0 LSB 1 000000 1 + 0/4096 1 Sign bit = 1, which implies plus sign in IN multiplier equation VIN max + 244 μV +2 LSB 1 000001 1 + 1/4096 1.000244141 Sign bit = 1, which implies plus sign in multiplier equation VIN max + (63 × 244 μV) +126 LSB 1 111111 1 + 63/4096 1.015380859 Sign bit = 1, which implies plus sign in multiplier equation Rev. 0 | Page 28 of 32 AD7262 MICROPROCESSOR INTERFACING The serial interface on the AD7262/AD7262-5 allows the parts Table 14. The SPORT0 Receive Configuration 1 Register to be directly connected to a range of different microprocessors. (SPORT0_RCR1) This section explains how to interface the AD7262/AD7262-5 Setting Description with the Analog Devices, Inc., Blackfin® DSP, the ADSP-BF537. RCKFE = 1 Sample data with falling edge of RSCLK LRFS = 1 Active low frame signal AD7262/AD7262-5 TO ADSP-BF53x RFSR = 1 Frame every word The ADSP-BF53x family of DSPs interface directly to the IRFS = 1 Internal receive frame sync (RFS) used AD7262/AD7262-5 without any glue logic required. The RLSBIT = 0 Receive MSB first VDRIVE pin of the AD7262/AD7262-5 takes the same supply RDTYPE = 00 Zero fill voltage as that of the ADSP-BF53x. This allows the ADC to IRCLK = 1 Internal receive clock operate at a higher supply voltage than its serial interface and, RSPEN = 1 Receive enabled therefore, the ADSP-BF53x, if necessary. The availability of SLEN = 11110 31-bit data-word secondary receive registers on the serial ports of the Blackfin TFSR = RFSR = 1 DSPs means only one serial port is necessary to read from both DOUT pins simultaneously. Figure 37 shows both DOUTA and Table 15. The SPORT0 Receive Configuration 2 Register DOUTB of the AD7262/AD7262-5 connected to Serial Port 0 of (SPORT0_RCR2) the ADSP-BF53x. The SPORT0 Receive Configuration 1 Setting Description register and SPORT0 Receive Configuration 2 register should RXSE = 1 Secondary side enabled be set up as outlined in Table 14 and Table 15. A Blackfin driver for the AD7262/AD7262-5 is available to 1 1 ADSP-BF53x AD7262 download at www.analog.com. SERIAL SPORT0 DEVICE A (PRIMARY) D A DR0PRI OUT SCLK RCLK0 CS RFS0 D B DR0SEC OUT SERIAL DEVICE B V DRIVE (SECONDARY) V DD 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 37. Interfacing the AD7262 to the ADSP-BF53x Rev. 0 | Page 29 of 32 07606-037 AD7262 APPLICATION HINTS with a double-sided board. In this technique, the component GROUNDING AND LAYOUT side of the board is dedicated to ground planes, while signals are The analog and digital supplies to the AD7262/AD7262-5 are placed on the solder side. independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The Good decoupling is also important. All analog supplies should be decoupled with 10 μF tantalum capacitors in parallel with printed circuit board (PCB) that houses the AD7262/AD7262-5 100 nF capacitors to GND. To achieve the best results from these should be designed so that the analog and digital sections are decoupling components, they must be placed as close as possible separated and confined to certain areas of the board. This design facilitates the use of ground planes that can be easily to the device, ideally right up against the device. The 0.1 μF separated. capacitors should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic To provide optimum shielding for ground planes, a minimum types or surface-mount types. These low ESR and ESI capacitors etch technique is generally best. All five AGND pins of the provide a low impedance path to ground at high frequencies to AD7262/AD7262-5 should be sunk in the AGND plane. Digital handle transient currents due to internal logic switching. and analog ground planes should be joined in only one place. If the AD7262/AD7262-5 are in a system where multiple devices PCB DESIGN GUIDELINES FOR LFCSP require an AGND to DGND connection, the connection should The land on the chip scale packages (CP-48-1) are rectangular. still be made at one point only, a star ground point, that should The PCB pad for these should be 0.1 mm longer than the be established as close as possible to the ground pins on the package land length and 0.05 mm wider than the package land AD7262/AD7262-5. width, thereby having a portion of the pad exposed. To ensure Avoid running digital lines under the device because this that the solder joint size is maximized, the land should be centered on the pad. couples noise onto the die. However, the analog ground plane should be allowed to run under the AD7262/AD7262-5 to The bottom of the chip scale package has a thermal pad. The avoid noise coupling. The power supply lines to the AD7262/ thermal pad on the PCB should be at least as large as the AD7262-5 should use as large a trace as possible to provide low exposed pad. On the PCB, there should be a clearance of at least impedance paths and reduce the effects of glitches on the power 0.25 mm between the thermal pad and the inner edges of the supply line. pad pattern to ensure that shorting is avoided. To avoid radiating noise to other sections of the board, fast To improve thermal performance of the package, use thermal switching signals, such as clocks, should be shielded with digital vias on the PCB, incorporating them into the thermal pad at ground, and clock signals should never run near the analog 1.2 mm pitch grid. The via diameter should be between 0.3 mm inputs. Avoid crossover of digital and analog signals. To reduce and 0.33 mm, and the via barrel should be plated with 1 oz. the effects of feedthrough within the board, traces on opposite copper to plug the via. The user should connect the PCB thermal sides of the board should run at right angles to each other. A pad to AGND. microstrip technique is the best method but is not always possible Rev. 0 | Page 30 of 32 AD7262 OUTLINE DIMENSIONS 0.30 7.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 37 48 36 1 PIN 1 INDICATOR EXPOSED TOP 5.25 6.75 PAD VIEW BSC SQ 5.10 SQ (BOTTOM VIEW) 4.95 0.50 0.40 25 12 13 24 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 THE EXPOSED METAL PADDLE ON THE 0.05 MAX 0.80 BOTTOM OF THE LFCSP PACKAGE 0.02 NOM MUST BE SOLDERED TO PCB GROUND COPLANARITY FOR PROPER HEAT DISSIPATION AND 0.50 BSC 0.08 ALSO FOR NOISE AND MECHANICAL 0.20 REF SEATING STRENGTH BENEFITS. PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 38. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters 9.20 0.75 9.00 SQ 1.60 8.80 0.60 MAX 0.45 48 37 36 1 PIN 1 7.20 TOP VIEW 7.00 SQ 1.45 (PINS DOWN) 0.20 6.80 1.40 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 SEATING 0.05 0.08 0.27 PLANE VIEW A 0.50 COPLANARITY 0.22 BSC LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 39. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7262BCPZ −40°C to +105°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7262BCPZ-RL7 −40°C to +105°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7262BCPZ-5 −40°C to +105°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7262BCPZ-5-RL7 −40°C to +105°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 1 AD7262BSTZ −40°C to +105°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 AD7262BSTZ-RL7 −40°C to +105°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 AD7262BSTZ-5 −40°C to +105°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 AD7262BSTZ-5-RL7 −40°C to +105°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 EVAL-AD7262EDZ Evaluation Board 1 EVAL-CED1Z Development Board 1 Z = RoHS Compliant Part. Rev. 0 | Page 31 of 32 051706-A 061208-A AD7262 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07606-0-7/08(0) Rev. 0 | Page 32 of 32