ANALOG DEVICES AD7194

8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7194 FEATURES Pressure measurement Temperature measurement Fast settling filter option Flow measurement 8 differential/16 pseudo differential input channels Weigh scales RMS noise: 11 nV at 4.7 Hz (gain = 128) Chromatography 15.5 noise-free bits at 2.4 kHz (gain = 128) Medical and scientific instrumentation Up to 22 noise-free bits (gain = 1) Offset drift: ±5 nV/°C GENERAL DESCRIPTION Gain drift: ±1 ppm/°C The AD7194 is a low noise, complete analog front end for high Programmable gain (1 to 128) precision measurement applications. It contains a low noise, Output data rate: 4.7 Hz to 4.8 kHz 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). Internal or external clock The on-chip low noise gain stage means that signals of small Simultaneous 50 Hz/60 Hz rejection amplitude can interface directly to the ADC. 4 general-purpose digital outputs The device can be configured to have eight differential inputs or Power supply sixteen pseudo differential inputs. The on-chip 4.92 MHz clock AV : 3 V to 5.25 V DD can be used as the clock source to the ADC or, alternatively, an DV : 2.7 V to 5.25 V DD external clock or crystal can be used. The output data rate from Current: 4.65 mA the part can be varied from 4.7 Hz to 4.8 kHz. Temperature range: −40°C to +105°C Package: 32-lead LFCSP The device has a very flexible digital filter, including a fast Interface settling option. Variables such as output data rate and settling 3-wire serial time are dependent on the option selected. For applications that SPI, QSPI™, MICROWIRE™, and DSP compatible require all conversions to be settled, the AD7194 includes zero Schmitt trigger on SCLK latency. APPLICATIONS The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 4.65 mA, and it is housed in a 32-lead PLC/DCS analog input modules LFCSP package. Data acquisition Strain gage transducers FUNCTIONAL BLOCK DIAGRAM AV AGND DV DGND REFIN1(+) REFIN1(–) DD DD REFERENCE DETECT AD7194 AIN1/P3 AV DD AIN2/P2 AIN3/P1/REFIN2(+) DOUT/RDY AIN4/P0/REFIN2(–) SERIAL INTERFACE AIN5 MUX DIN Σ-Δ PGA AND ADC CONTROL SCLK LOGIC AIN16 CS AINCOM AGND CLOCK TEMP CIRCUITRY SENSOR MCLK1 MCLK2 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08566-001 AD7194 TABLE OF CONTENTS Features .............................................................................................. 1  Programmable Gain Array (PGA) ........................................... 30  Applications ....................................................................................... 1  Reference ..................................................................................... 30  General Description ......................................................................... 1  Reference Detect ......................................................................... 31  Functional Block Diagram .............................................................. 1  Bipolar/Unipolar Configuration .............................................. 31  Revision History ............................................................................... 2  Data Output Coding .................................................................. 31  Specif ica t ions ..................................................................................... 3  Burnout Currents ....................................................................... 31  Timing Characteristics ................................................................ 7  Digital Interface .......................................................................... 32  Absolute Maximum Ratings ............................................................ 9  Reset ............................................................................................. 36  Thermal Resistance ...................................................................... 9  System Synchronization ............................................................ 36  ESD Caution .................................................................................. 9  Enable Parity ............................................................................... 36  Pin Configuration and Function Descriptions ........................... 10  Clock ............................................................................................ 36  Typical Performance Characteristics ........................................... 12  Temperature Sensor ................................................................... 36  RMS Noise and Resolution ............................................................ 15  Logic Outputs ............................................................................. 37  4 Sinc Chop Disabled ................................................................... 15 Calibration ................................................................................... 37  3 Sinc Chop Disabled ................................................................... 16  Digital Filter .................................................................................... 39  4 Fast Settling ................................................................................. 17  Sinc Filter (Chop Disabled) ..................................................... 39  3 On-Chip Registers .......................................................................... 18  Sinc Filter (Chop Disabled) ..................................................... 41  4 Communications Register ......................................................... 19  Chop Enabled (Sinc Filter) ...................................................... 43  3 Status Register ............................................................................. 20  Chop Enabled (Sinc Filter) ...................................................... 45  4 Mode Register ............................................................................. 21  Fast Settling Mode (Sinc Filter) ............................................... 46  3 Configuration Register .............................................................. 24  Fast Settling Mode (Sinc Filter) ............................................... 48  Data Register ............................................................................... 27  Fast Settling Mode (Chop Enabled) ......................................... 50  ID Register ................................................................................... 27  Summary of Filter Options ....................................................... 51  GPOCON Register ..................................................................... 27  Grounding and Layout .................................................................. 52  Offset Register ............................................................................. 28  Applications Information .............................................................. 53  Full-Scale Register ...................................................................... 28  Flowmeter .................................................................................... 53  ADC Circuit Information .............................................................. 29  Outline Dimensions ....................................................................... 54  Overview ...................................................................................... 29  Ordering Guide .......................................................................... 54  Analog Input Channel ............................................................... 30  REVISION HISTORY 10/09—Revision 0: Initial Version Rev. 0 | Page 2 of 56 AD7194 SPECIFICATIONS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = +2.5 V or AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter Min Typ Max Unit Test Conditions/Comments ADC Output Data Rate 4.7 4800 Hz Chop disabled 4 1.17 1200 Hz Chop enabled, sinc filter 3 1.56 1600 Hz Chop enabled, sinc filter 2 3 4 No Missing Codes 24 Bits FS[9:0] > 1, sinc filter 3 3 24 Bits FS[9:0] > 4, sinc filter Resolution See the RMS Noise and Resolution section RMS Noise and Output See the RMS Noise and Resolution section Data Rates Integral Nonlinearity 2 Gain = 1 ±2 ±10 ppm of FSR AV = 5 V DD ±2 ±15 ppm of FSR AV = 3 V DD Gain > 1 ±5 ±30 ppm of FSR AV = 5 V DD ±15 ±30 ppm of FSR AV = 3 V DD 4 , 5 Offset Error ±150/gain μV Chop disabled ±1 μV Chop enabled, AV = 5 V DD ±0.5 μV Chop enabled, AV = 3 V DD Offset Error Drift vs. ±150/gain nV/°C Gain = 1 to 16; chop disabled Temperature ±5 nV/°C Gain = 32 to 128; chop disabled ±5 nV/°C Chop enabled 4 Gain Error ±0.001 % AVDD = 5 V, gain = 1, TA = 25°C (factory calibration conditions) −0.4 % Gain = 128, before full-scale calibration (see Table 27) ±0.003 % Gain > 1, after internal full-scale calibration, AVDD ≥ 4.75 V ±0.005 % Gain > 1, after internal full-scale calibration, AVDD < 4.75 V Gain Drift vs. ±1 ppm/°C Temperature Power Supply Rejection 90 dB Gain = 1, V = 1 V IN 95 110 dB Gain > 1, V = 1 V/gain IN Common-Mode Rejection @ DC 110 dB Gain = 1, V = 1 V IN @ DC 105 120 dB Gain > 1, V = 1 V/gain IN 2 @ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 2 @ 50 Hz 120 dB 50 Hz output data rate, 50 Hz ± 1 Hz 2 @ 60 Hz 120 dB 60 Hz output data rate, 60 Hz ± 1 Hz 2 3 @ 50 Hz 115 dB Fast settling, FS[9:0] = 6, average by 16, 50 Hz ± 1 Hz 2 3 @ 60 Hz 115 dB Fast settling, FS[9:0] = 5, average by 16, 60 Hz ± 1 Hz Rev. 0 | Page 3 of 56 AD7194 1 Parameter Min Typ Max Unit Test Conditions/Comments 2 Normal Mode Rejection 4 Sinc Filter Internal Clock @ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 6 74 dB 50 Hz output data rate, REJ60 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz 96 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 97 dB 60 Hz output data rate, 60 Hz ± 1 Hz External Clock @ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 6 82 dB 50 Hz output data rate, REJ60 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz 120 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 120 dB 60 Hz output data rate, 60 Hz ± 1 Hz 3 Sinc Filter Internal Clock @ 50 Hz, 60 Hz 75 dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 6 60 dB 50 Hz output data rate, REJ60 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz 70 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 70 dB 60 Hz output data rate, 60 Hz ± 1 Hz External Clock @ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 6 @ 50 Hz 67 dB 50 Hz output data rate, REJ60 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz 95 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 95 dB 60 Hz output data rate, 60 Hz ± 1 Hz Fast Settling Internal Clock 3 @ 50 Hz 26 dB FS[9:0] = 6, average by 16, 50 Hz ± 0.5 Hz 3 @ 60 Hz 26 dB FS[9:0] = 5, average by 16, 60 Hz ± 0.5 Hz External Clock 3 @ 50 Hz 40 dB FS[9:0] = 6, average by 16, 50 Hz ± 0.5 Hz 3 @ 60 Hz 40 dB FS[9:0] = 5, average by 16, 60 Hz ± 0.5 Hz ANALOG INPUTS Differential Input ±VREF/gain V VREF = REFINx(+) − REFINx(−), Voltage Ranges gain = 1 to 128 −(AVDD − 1.25 V)/gain +(AVDD − 1.25 V)/gain V Gain > 1 Absolute AIN Voltage 2 Limits Unbuffered Mode AGND − 0.05 AVDD + 0.05 V Buffered Mode AGND + 0.25 AVDD − 0.25 V Analog Input Current Buffered Mode 2 Input Current −2 +2 nA Gain = 1 −3 +3 nA Gain > 1 Input Current Drift ±5 pA/°C Unbuffered Mode Input Current ±3.5 μA/V Gain = 1, input current varies with input voltage ±1 μA/V Gain > 1 Input Current Drift ±0.05 nA/V/°C External clock ±1.6 nA/V/°C Internal clock Rev. 0 | Page 4 of 56 AD7194 1 Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUT REFIN Voltage 1 AVDD V REFIN = REFINx(+) − REFINx(−), the differential input must be limited to ±(AVDD − 1.25 V)/gain when gain > 1 Absolute REFIN Voltage AGND − 0.05 AVDD + 0.05 V 2 Limits Average Reference Input 4.5 μA/V Current Average Reference Input ±0.03 nA/V/°C External clock Current Drift ±1.3 nA/V/°C Internal clock 2 Normal Mode Rejection Same as for analog inputs Common-Mode 100 dB Rejection Reference Detect Levels 0.3 0.6 V TEMPERATURE SENSOR Accuracy ±2 °C Applies after user calibration at 25°C Sensitivity 2815 Codes/°C Bipolar mode BURNOUT CURRENTS AIN Current 500 nA Analog inputs must be buffered and chop disabled DIGITAL OUTPUTS (P0 to P3) Output High Voltage, V AV − 0.6 V AV = 3 V, I = 100 μA OH DD DD SOURCE 4 V AV = 5 V, I = 200 μA DD SOURCE Output Low Voltage, V 0.4 V AV = 3 V, I = 100 μA OL DD SINK 0.4 V AV = 5 V, I = 800 μA DD SINK Floating-State Leakage −100 +100 nA 2 Current Floating-State Output 10 pF Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency 4.72 5.12 MHz Duty Cycle 50:50 % External Clock/Crystal Frequency 2.4576 4.9152 5.12 MHz Input Low Voltage, V 0.8 V DV = 5 V INL DD 0.4 V DV = 3 V DD Input High Voltage, VINH 2.5 V DVDD = 3 V 3.5 V DVDD = 5 V Input Current −10 +10 μA LOGIC INPUTS 2 Input High Voltage, V 2 V INH 2 Input Low Voltage, V 0.8 V INL 2 Hysteresis 0.1 0.25 V Input Currents −10 +10 μA LOGIC OUTPUT (DOUT/RDY) 2 Output High Voltage, VOH DVDD − 0.6 V DVDD = 3 V, ISOURCE = 100 μA 4 V DV = 5 V, I = 200 μA DD SOURCE 2 Output Low Voltage, V 0.4 V DV = 3 V, I = 100 μA OL DD SINK 0.4 V DV = 5 V, I = 1.6 mA DD SINK Floating-State Leakage −10 +10 μA Current Floating-State Output 10 pF Capacitance Data Output Coding Offset binary Rev. 0 | Page 5 of 56 AD7194 1 Parameter Min Typ Max Unit Test Conditions/Comments 2 SYSTEM CALIBRATION Full-Scale Calibration Limit 1.05 × FS V Zero-Scale Calibration −1.05 × FS V Limit Input Span 0.8 × FS 2.1 × FS V 7 POWER REQUIREMENTS Power Supply Voltage AVDD − AGND 3 5.25 V DVDD − DGND 2.7 5.25 V Power Supply Currents AIDD Current 0.85 1.1 mA Gain = 1, buffer off 1 1.35 mA Gain = 1, buffer on 2.8 3.6 mA Gain = 8, buffer off 3.2 3.85 mA Gain = 8, buffer on 3.8 4.7 mA Gain = 16 to 128, buffer off 4.3 5.3 mA Gain = 16 to 128, buffer on DIDD Current 0.35 0.4 mA DVDD = 3 V 0.5 0.6 mA DVDD = 5 V 1.5 mA External crystal used I 3 μA Power-down mode DD 1 Temperature range: −40°C to +105°C. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5 The analog inputs are configured for differential mode. 6 REJ60 is a bit in the mode register. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz/60 Hz rejection. 7 Digital inputs equal to DVDD or DGND. Rev. 0 | Page 6 of 56 AD7194 TIMING CHARACTERISTICS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2. 1, 2 Parameter Limit at TMIN, TMAX (B Version) Unit Conditions/Comments READ AND WRITE OPERATIONS t3 100 ns min SCLK high pulse width t4 100 ns min SCLK low pulse width READ OPERATION t1 0 ns min CS falling edge to DOUT/RDY active time 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V 3 4 t 0 ns min SCLK active edge to data valid delay 2 60 ns max DV = 4.75 V to 5.25 V DD 80 ns max DVDD = 2.7 V to 3.6 V 5, 6 t5 10 ns min Bus relinquish time after CS inactive edge 80 ns max t 0 ns min SCLK inactive edge to CS inactive edge 6 t 10 ns min SCLK inactive edge to DOUT/RDY high 7 WRITE OPERATION 4 t 0 ns min CS falling edge to SCLK active edge setup time 8 t 30 ns min Data valid to SCLK edge setup time 9 t 25 ns min Data valid to SCLK edge hold time 10 t11 0 ns min CS rising edge to SCLK edge hold time 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. Rev. 0 | Page 7 of 56 AD7194 Circuit and Timing Diagrams I (1.6mA WITH DV = 5V, SINK DD 100µA WITH DV = 3V) DD TO OUTPUT 1.6V PIN 50pF I (200µA WITH DV = 5V, SOURCE DD 100µA WITH DV = 3V) DD Figure 2. Load Circuit for Timing Characterization CS (I) t 6 t 1 t 5 MSB LSB DOUT/RDY (O) t 7 t 2 t 3 SCLK (I) t 4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t t 11 8 SCLK (I) t 9 t 10 DIN (I) MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. 0 | Page 8 of 56 08566-002 08566-004 08566-003 AD7194 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA Table 3. soldered in a circuit board for surface-mount packages. Parameter Rating AV to AGND −0.3 V to +6.5 V DD Table 4. Thermal Resistance DV to AGND −0.3 V to +6.5 V DD Package Type θ θ Unit JA JC AGND to DGND −0.3 V to +0.3 V 32-Lead LFCSP 32.5 32.71 °C/W Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V ESD CAUTION Digital Input Voltage to DGND −0.3 V to DV + 0.3 V DD Digital Output Voltage to DGND −0.3 V to DV + 0.3 V DD AINx/Digital Input Current 10 mA Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature, Soldering Reflow 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 9 of 56 AD7194 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AIN1/P3 1 24 DV DD AIN2/P2 2 23 AV DD AIN3/P1/REFIN2(+) 3 22 DGND AD7194 AIN4/P0/REFIN2(–) 4 21 AGND TOP VIEW AINCOM 5 20 AIN16 (Not to Scale) 6 19 AGND AIN15 AIN5 7 18 REFIN1(–) AIN6 8 17 REFIN1(+) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO AGND. Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 AIN1/P3 Analog Input/Digital Output Pin. This pin can function as an analog input pin. When the GP32EN bit is set to 1, the pin functions as a general-purpose output bit referenced between AVDD and AGND. 2 AIN2/P2 Analog Input/Digital Output Pin. This pin can function as an analog input pin. When the GP32EN bit is set to 1, the pin functions as a general-purpose output bit referenced between AVDD and AGND. 3 AIN3/P1/REFIN2(+) Analog Input/Digital Output Pin/Positive Reference Input. This pin functions as an analog input pin. When the GP10EN bit is set to 1, the pin functions as a general-purpose output bit referenced between AV and DD AGND. When the REFSEL bit in the configuration register is set to 1, this pin functions as REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AVDD and AGND + 1 V. 4 AIN4/P0/REFIN2(−) Analog Input/Digital Output Pin/Positive Reference Input. This pin functions as an analog input pin. When the GP10EN bit is set to 1, the pin functions as a general-purpose output bit referenced between AV and DD AGND. When the REFSEL bit in the configuration register is set to 1, this pin functions as REFIN2(−). An external reference can be applied between REFIN2(+) and REFIN2(−). This reference input can lie anywhere between AGND and AVDD − 1 V. 5 AINCOM Analog Input AIN1 to Analog Input AIN16 are referenced to this input when the bit pseudo is set to 1. 6 AGND Analog Ground Reference Point. 7 AIN5 Analog Input Pin. 8 AIN6 Analog Input Pin. 9 AIN7 Analog Input Pin. 10 AIN8 Analog Input Pin. 11 AIN9 Analog Input Pin. 12 AIN10 Analog Input Pin. 13 AIN11 Analog Input Pin. 14 AIN12 Analog Input Pin. 15 AIN13 Analog Input Pin. 16 AIN14 Analog Input Pin. 17 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between AV and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − DD REFIN1(−)), is AV , but the part functions with a reference from 1 V to AV . DD DD 18 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. 19 AIN15 Analog Input Pin. 20 AIN16 Analog Input Pin. 21 AGND Analog Ground Reference Point. 22 DGND Digital Ground Reference Point. Rev. 0 | Page 10 of 56 AIN7 9 32 CS AIN8 10 31 SCLK AIN9 11 30 MCLK2 AIN10 12 29 MCLK1 AIN11 13 28 DIN AIN12 14 27 DOUT/RDY 15 26 AIN13 NC AIN14 16 25 SYNC 08566-005 AD7194 Pin No. Mnemonic Description 23 AVDD Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with AVDD at 5 V or vice versa. 24 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V with DV at 5 V or vice versa. DD 25 SYNC Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7194 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DV . DD 26 NC This pin should be connected to GND for correct operation. 27 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. 28 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register. 29 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. 30 MCLK2 Master Clock Signal for the Device. The AD7194 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7194 can also be provided externally in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected. 31 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a nonconti- nuous clock with the information transmitted to or from the ADC in smaller batches of data. 32 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. Rev. 0 | Page 11 of 56 AD7194 TYPICAL PERFORMANCE CHARACTERISTICS 8,387,952 50 8,387,950 40 8,387,948 8,387,946 30 8,387,944 8,387,942 20 8,387,940 8,387,938 10 8,387,936 8,387,934 0 0 200 400 600 800 1000 8,388,830 8,388,860 8,388,890 8,388,920 SAMPLE CODE Figure 6. Noise (VREF = AVDD = 5 V, Output Data Rate = 4.7 Hz, Figure 9. Noise Distribution Histogram (V = AV = 5 V, REF DD 4 4 Gain = 128, Chop Disabled, Sinc Filter) Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc Filter) 200 8,388,880 8,388,878 8,388,876 150 8,388,874 8,388,872 100 8,388,870 8,388,868 50 8,388,866 8,388,864 0 0 200 400 600 800 1000 8,387,936 8,387,940 8,387,944 8,387,948 8,387,938 8,387,942 8,387,946 8,387,950 SAMPLE CODE Figure 7. Noise Distribution Histogram (VREF = AVDD = 5 V, Figure 10. Noise (VREF = AVDD = 5 V, Output Data Rate = 42.1 Hz (FS[9:0] = 6, 4 4 Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc Filter) Average by 16), Gain = 1, Chop Disabled, Sinc Filter) 8,388,920 200 8,388,910 8,388,900 150 8,388,890 8,388,880 100 8,388,870 8,388,860 50 8,388,850 8,388,840 0 8,388,830 8,388,864 8,388,868 8,388,872 8,388,876 8,388,880 0 200 400 600 800 1000 CODE SAMPLE Figure 8. Noise (V = AV = 5 V, Output Data Rate = 2400 Hz, Figure 11. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate = REF DD 4 4 Gain = 1, Chop Disabled, Sinc Filter) 42.1 Hz (FS[9:0] = 6, Average by 16), Gain = 1, Chop Disabled, Sinc Filter) Rev. 0 | Page 12 of 56 CODE CODE OCCURRENCE 08566-007 08566-008 08566-006 CODE OCCURRENCE OCCURRENCE 08566-011 08566-009 08566-010 AD7194 5 0.6 4 0.5 3 0.4 2 0.3 1 0.2 0 0.1 –1 –2 0 –60 –40 –20 0 20 40 60 80 100 120 –4 –3 –2 –1 01234 V (V) TEMPERAUTRE (°C) IN Figure 12. INL (Gain = 1) Figure 15. Offset vs. Temperature (Gain = 128, Chop Disabled) 20 1.000008 1.000006 15 1.000004 10 1.000002 5 1.000000 0 0.999998 0.999996 –5 0.999994 –10 0.999992 –15 0.999990 –20 0.999988 –0.03 –0.02 –0.01 0 0.01 0.02 0.03 –60 –40 –20 0 20 40 60 80 100 120 V (V) TEMPERATURE (°C) IN Figure 13. INL (Gain = 128) Figure 16. Gain vs. Temperature (Gain = 1) 128.004 170 128.002 168 128.000 166 127.998 164 162 127.996 160 127.994 158 127.992 156 127.990 127.988 154 –60 –40 –20 0 20 40 60 80 100 120 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. Offset vs. Temperature (Gain = 1, Chop Disabled) Figure 17. Gain vs. Temperature (Gain = 128) Rev. 0 | Page 13 of 56 OFFSET (µV) INL (ppm of FSR) INL (ppm of FSR) 08566-014 08566-012 08566-013 GAIN GAIN OFFSET ERROR (μV) 08566-067 08566-017 08566-016 AD7194 24 23 GAIN = 1 GAIN = 8 GAIN = 16 22 GAIN = 32 22 GAIN = 64 GAIN = 128 21 20 20 19 18 18 GAIN = 1 GAIN = 8 16 GAIN = 16 17 GAIN = 32 GAIN = 64 GAIN = 128 16 14 1 10 100 1k 1 10 100 1k 10k OUTPUT DATA RATE (Hz) OUTPUT DATA RATE (Hz) 4 Figure 20. Noise-Free Resolution in Fast Settling Mode (VREF = 5 V, Figure 18. Noise-Free Resolution (Sinc Filter, Chop Disabled, V = 5 V) REF 4 Averaging by 16, Sinc Filter, Chop Disabled) 24 22 20 18 16 14 GAIN = 1 GAIN = 8 GAIN = 16 12 GAIN = 32 GAIN = 64 GAIN = 128 10 1 10 100 1k 10k OUTPUT DATA RATE (Hz) 3 Figure 19. Noise-Free Resolution (Sinc Filter, Chop Disabled, VREF = 5 V) Rev. 0 | Page 14 of 56 NOISE FREE RESOLUTION (Bits) NOISE FREE RESOLUTION (Bits) 08566-070 08566-069 NOISE FREE RESOLUTION (Bits) 08566-068 AD7194 RMS NOISE AND RESOLUTION The following tables show the rms noise, peak-to-peak noise, is continuously converting on a single channel. It is important effective resolution, and noise-free (peak-to-peak) resolution of to note that the effective resolution is calculated using the rms the AD7194 for various output data rates and gain settings with noise, whereas the peak-to-peak resolution is calculated based 4 3 chop disabled for the sinc and sinc filters and for fast settling on peak-to-peak noise. The peak-to-peak resolution represents mode. The numbers given are for the bipolar input range with the resolution for which there is no code flicker. With chop an external 5 V reference. These numbers are typical and are enabled, the resolution improves by 0.5 bits. generated with a differential input voltage of 0 V when the ADC 4 SINC CHOP DISABLED Table 6. RMS Noise (nV) vs. Gain and Output Data Rate Gain of Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1 8 16 32 64 128 1023 4.7 852.5 370 57 35 18 13 11 640 7.5 533 440 73 41 24 17 13 480 10 400 470 83 45 28 18 16 96 50 80 1100 150 85 52 38 34 80 60 66.7 1200 170 94 56 42 38 32 150 26.7 1800 260 150 86 65 59 16 300 13.3 2500 360 210 130 95 83 5 960 4.17 4500 640 370 230 170 150 2 2400 1.67 7500 1100 600 380 280 240 1 4800 0.83 26,000 3400 1800 940 550 390 Table 7. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Gain of Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1 8 16 32 64 128 1023 4.7 852.5 2200 340 200 120 84 70 640 7.5 533 2700 430 260 150 100 85 480 10 400 3000 480 300 170 120 100 96 50 80 6600 950 540 350 250 210 80 60 66.7 7200 1000 610 370 270 220 32 150 26.7 11,000 1600 970 580 430 370 16 300 13.3 17,000 2400 1400 840 620 530 5 960 4.17 35,000 4800 2500 1500 1100 1000 2 2400 1.67 56,000 7500 4200 2900 1800 1700 1 4800 0.83 175,000 23,000 12,000 7100 3600 2600 Table 8. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate 1 Gain of Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1 8 16 32 64 128 1023 4.7 852.5 24 (22.1) 24 (21.8) 24 (21.6) 24 (21.3) 23.5 (20.8) 22.8 (20.1) 640 7.5 533 24 (21.8) 24 (21.5) 23.9 (21.2) 23.6 (21) 23.1 (20.6) 22.5 (19.8) 480 10 400 24 (21.7) 24 (21.3) 23.7 (21) 23.4 (20.8) 23 (20.3) 22.2 (19.6) 96 50 80 23.1 (20.5) 23 (20.3) 22.8 (20.1) 22.5 (19.8) 22 (19.3) 21.1 (18.5) 80 60 66.7 23 (20.4) 22.9 (20.3) 22.7 (20) 22.4 (19.7) 21.8 (19.1) 21 (18.4) 32 150 26.7 22.4 (19.8) 22.3 (19.6) 22 (19.3) 21.8 (19) 21.2 (18.5) 20.3 (17.7) 16 300 13.3 21.9 (19.2) 21.8 (19) 21.5 (18.8) 21.2 (18.5) 20.7 (17.9) 19.8 (17.2) 5 960 4.17 21.1 (18.4) 21 (18) 20.7 (17.9) 20.4 (17.7) 19.8 (17.1) 19 (16.3) 2 2400 1.67 20.4 (17.6) 20.3 (17.3) 20 (17.2) 19.6 (16.7) 19.1 (16.4) 18.3 (15.5) 1 4800 0.83 18.6 (15.8) 18.5 (15.7) 18.4 (15.7) 18.3 (15.4) 18.1 (15.4) 17.6 (14.9) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. 0 | Page 15 of 56 AD7194 3 SINC CHOP DISABLED Table 9. RMS Noise (nV) vs. Gain and Output Data Rate Gain of Output Data Settling Rate (Hz) Time (ms) Filter Word (Decimal) 1 8 16 32 64 128 1023 4.7 639.4 380 58 35 20 13 11 640 7.5 400 450 73 41 25 17 14 480 10 300 490 90 47 28 19 16 96 50 60 1100 160 92 54 40 36 80 60 50 1200 170 99 59 43 39 32 150 20 1900 280 160 91 72 63 16 300 10 2700 380 210 130 97 87 5 960 3.13 6400 870 490 280 200 170 2 2400 1.25 115,000 14,000 7000 3600 1800 950 1 4800 0.625 860,000 110,000 54,000 28,000 14,000 7000 Table 10. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Gain of Output Data Settling Filter Word (Decimal) Rate (Hz) Time (ms) 1 8 16 32 64 128 1023 4.7 639.4 2300 350 220 130 84 70 640 7.5 400 2700 450 270 160 110 88 480 10 300 3100 520 310 180 120 100 96 50 60 7200 990 560 370 260 230 80 60 50 7800 1100 630 390 270 250 32 150 20 13,000 1800 1000 580 480 400 16 300 10 19,000 2500 1400 860 640 560 5 960 3.13 410,000 5700 3200 1800 1300 1100 2 2400 1.25 730,000 93,000 47,000 24,000 12,000 6100 1 4800 0.625 5,700,000 730,000 360,000 180,000 93,000 45,000 Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate 1 Gain of Output Data Settling Filter Word (Decimal) Rate (Hz) Time (ms) 1 8 16 32 64 128 1023 4.7 639.4 24 (22.1) 24 (21.8) 24 (21.4) 23.9 (21.2) 23.5 (20.8) 22.8 (20.1) 640 7.5 400 24 (21.8) 24 (21.4) 23.9 (21.1) 23.6 (20.9) 23.1 (20.4) 22.4 (19.8) 480 10 300 24 (21.6) 23.8 (21.2) 23.7 (20.9) 23.4 (20.7) 23 (20.3) 22.2 (19.6) 96 50 60 23.1 (20.4) 22.9 (20.3) 22.7 (20.1) 22.5 (19.7) 21.9 (19.2) 21 (18.4) 80 60 50 23 (20.3) 22.8 (20.1) 22.6 (19.9) 22.3 (19.6) 21.8 (19.1) 20.9 (18.3) 32 150 20 22.3 (19.6) 22.1 (19.4) 21.9 (19.3) 21.7 (19) 21 (18.3) 20.2 (17.6) 16 300 10 21.8 (19) 21.6 (18.9) 21.56 (18.8) 21.2 (18.5) 20.6 (17.9) 19.8 (17.1) 5 960 3.13 20.6 (17.9) 20.5 (17.7) 20.3 (17.6) 20.1 (17.4) 19.6 (16.9) 18.8 (16.1) 2 2400 1.25 16.5 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.6) 1 4800 0.625 13.5 (10.8) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. 0 | Page 16 of 56 AD7194 FAST SETTLING Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Gain of Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) Average 1 8 16 32 64 128 96 16 2.63 380 410 87 52 33 15 12 30 16 8.4 118.75 700 140 71 43 30 21 6 16 42.10 23.75 1500 270 150 82 56 47 5 16 50.53 19.79 1600 280 160 88 61 52 2 16 126.32 7.92 2700 380 210 130 94 85 1 16 252.63 3.96 3700 540 300 190 140 120 Table 13. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Gain of Filter Word Output Data Settling (Decimal) Average Rate (Hz) Time (ms) 1 8 16 32 64 128 96 16 2.63 380 2500 450 260 180 100 70 30 16 8.4 118.75 4200 900 470 280 190 130 6 16 42.10 23.75 10,000 1800 950 540 360 300 5 16 50.53 19.79 11,000 1900 1000 580 390 330 2 16 126.32 7.92 16,000 2800 1500 850 580 510 1 16 252.63 3.96 23,000 4500 2000 1200 850 740 Table 14. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate 1 Gain of Filter Word Output Data Settling (Decimal) Average Rate (Hz) Time (ms) 1 8 16 32 64 128 96 16 2.63 380 24 (21.9) 23.8 (21.4) 23.5 (21.2) 23.2 (20.7) 23.3 (20.6) 22.6 (20.1) 30 16 8.4 118.75 23.8 (21.2) 23.1 (20.4) 23.1 (20.3) 22.8 (20.1) 22.3 (19.6) 21.8 (19.2) 6 16 42.10 23.75 22.7 (19.9) 22.1 (19.4) 22 (19.3) 21.9 (19.1) 21.4 (18.7) 20.7 (18) 5 16 50.53 19.79 22.6 (19.8) 22.1 (19.3) 21.9 (19.3) 21.8 (19) 21.3 (18.6) 20.5 (17.9) 2 16 126.32 7.92 21.8 (19.3) 21.6 (18.8) 21.5 (18.7) 21.2 (18.5) 20.7 (18) 19.8 (17.2) 1 16 252.63 3.96 21.4 (18.7) 21.1 (18.1) 21 (18.3) 20.6 (18) 20.1 (17.5) 19.3 (16.7) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. 0 | Page 17 of 56 AD7194 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term, set, implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. Table 15. Register Summary Register Addr. Dir. Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Communications 00 W 00 0 R/W Register address CREAD 0 0 Status 00 R 80 RDY ERR NOREF Parity CHD3 CHD2 CHD1 CHD0 Mode 01 R/W 080060 Mode select DAT_STA CLK1 CLK0 AVG1 AVG0 SINC3 0 ENPAR CLK_DIV Single REJ60 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB) Configuration 02 R/W 000117 Chop (MSB) 0 0 REFSEL 0 Pseudo 0 TEMP CH7( CH6 CH5 CH4 CH3 CH2 CH1 CH0 Burn REFDET 0 BUF U/B G2 G1 G0 (LSB) Data 03 R 000000 D23 (MSB) D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) ID 04 R X3 X X X X 0 0 1 1 GPOCON 05 R/W 00 0 0 GP32EN GP10EN P3DAT P2DAT P1DAT P0DAT Offset 06 R/W 800000 OF23 (MSB) OF22 OF21 OF20 OF19 OF18 OF17 OF16 OF15 OF14 OF13 OF12 OF11 OF10 OF9 OF8 OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 (LSB) Full Scale 07 R/W 5XXXX0 FS23 (MSB) FS22 FS21 FS20 FS19 FS18 FS17 FS16 FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB) Rev. 0 | Page 18 of 56 AD7194 a reset, the ADC is in this default state waiting for a write COMMUNICATIONS REGISTER operation to the communications register. In situations where the RS2, RS1, RS0 = 000 interface sequence is lost, a write operation of at least 40 serial The communications register is an 8-bit write-only register. All clock cycles with DIN high returns the ADC to this default state communications to the part must start with a write operation to by resetting the entire part. Table 16 outlines the bit designations the communications register. The data written to the communi- for the communications register. CR0 through CR7 indicate the cations register determine whether the next operation is a read bit location, CR denoting that the bits are in the communications or write operation and in which register this operation occurs. For register. CR7 denotes the first bit of the data stream. The number read or write operations, when the subsequent read or write oper- in parentheses indicates the power-on/reset default status of ation to the selected register is complete, the interface returns to that bit. where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN(0) R/W(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0) Table 16. Communications Register (CR) Bit Designations Bit Location Bit Name Description CR7 WEN Write enable bit. For a write to the communications register to occur, 0 must be written to this bit. If a 1 is the first bit written, the part does not clock onto subsequent bits in the register; rather, it stays at this bit location until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. Idling the DIN pin high between data transfers minimizes the effects of spurious SCLK pulses on the serial interface. CR6 R/W 0 in this bit location indicates that the next operation is a write to a specified register. 1 in this bit position indicates that the next operation is a read from the designated register. CR5 to CR3 RS2 to RS0 Register address bits. These address bits are used to select which registers of the ADC are selected during the serial interface communication (see Table 17). CR2 CREAD Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, Instruction 01011100 must be written to the communications register. To disable continuous read, Instruction 01011000 must be written to the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 40 consecutive 1s occur on DIN; therefore, hold DIN low until an instruction is written to the device. CR1 to CR0 0 These bits must be programmed to Logic 0 for correct operation. Table 17. Register Selection RS2 RS1 RS0 Register Register Size 0 0 0 Communications register during a write operation 8 bits 0 0 0 Status register during a read operation 8 bits 0 0 1 Mode register 24 bits 0 1 0 Configuration register 24 bits 0 1 1 Data register/data register plus status information 24 bits/32 bits 1 0 0 ID register 8 bits 1 0 1 GPOCON register 8 bits 1 1 0 Offset register 24 bits 1 1 1 Full-scale register 24 bits Rev. 0 | Page 19 of 56 AD7194 load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 18 outlines the bit STATUS REGISTER designations for the status register. SR0 through SR7 indicate the RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 bit locations, SR denoting that the bits are in the status register. The status register is an 8-bit read-only register. To access the SR7 denotes the first bit of the data stream. The number in paren- ADC status register, the user must write to the communications theses indicates the power-on/reset default status of that bit. register, select the next operation to be a read operation, and SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY(1) ERR(0) NOREF(0) Parity(0) CHD3(0) CHD2(0) CHD1(0) CHD0(0) Table 18. Status Register (SR) Bit Designations Bit Location Bit Name Description SR7 RDY Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register is read, or a period of time before the data register is updated, with a new conversion result to indicate to the user that the conversion data should not be read. It is also set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC error bit. This bit is written to at the same time as the RDY bit. This bit is set to indicate that the result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange, underrange, or the absence of a reference voltage. This bit is cleared when the result written to the data register returns to within the allowed analog input range. The ERR bit is also set during calibrations if the reference source is invalid or if the applied analog input voltages are outside range during system calibrations. SR5 NOREF No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled by setting the REFDET bit in the configuration register to 1. SR4 Parity Parity check of the data register. If the ENPAR bit in the mode register is set, the parity bit is set if there is an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. SR3 to SR0 CHD3 to CHD0 These bits indicate which channel corresponds to the data register contents. They do not indicate which channel is presently being converted, but indicate which channel was selected when the conversion contained in the data register was generated. Rev. 0 | Page 20 of 56 AD7194 register. MR0 through MR23 indicate the bit locations, MR MODE REGISTER denoting that the bits are in the mode register. MR23 denotes RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060 the first bit of the data stream. The number in parentheses The mode register is a 24-bit register from which data can be indicates the power-on/reset default status of that bit. Any write read or to which data can be written. This register is used to to the mode register resets the modulator and filter and sets the select the operating mode, the output data rate, and the clock RDY bit. source. Table 19 outlines the bit designations for the mode MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16 MD2(0) MD1(0) MD0(0) DAT_STA(0) CLK1(1) CLK0(0) AVG1(0) AVG0(0) MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 SINC3(0) 0 ENPAR(0) CLK_DIV(0) Single(0) REJ60(0) FS9(0) FS8(0) MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 FS7(0) FS6(1) FS5(1) FS4(0) FS3(0) FS2(0) FS1(0) FS0(0) Table 19. Mode Register (MR) Bit Designations Bit Location Bit Name Description MR23 to MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7194 (see Table 20). MR21 MR20 DAT_STA This bit enables the transmission of status register contents after each data register read. When DAT_STA is set, the contents of the status register are transmitted along with each data register read. This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds. MR19, MR18 CLK1, CLK0 These bits select the clock source for the AD7194. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7194 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7194. CLK1 CLK0 ADC Clock Source 0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2. 0 1 External clock. The external clock is applied to the MCLK2 pin. 1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated. 1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2. MR17, MR16 AVG1, AVG0 Fast settling filter. When this option is selected, the settling time equals one conversion time. In fast settling mode, a first-order average and decimate block is included after the sinc filter. The data from the sinc filter is averaged by 2, 8, or 16. The averaging reduces the output data rate for a given FS word; however, the rms noise improves. The AVG1 and AVG0 bits select the amount of averaging. Fast settling 3 mode can be used for FS words less than 512 only. When the sinc filter is selected, the FS word must be less than 256 when averaging by 16. AVG1 AVG0 Average 0 0 No averaging (fast settling mode disabled) 0 1 Average by 2 1 0 Average by 8 1 1 Average by 16 3 4 MR15 SINC3 Sinc filter select bit. When this bit is cleared, the sinc filter is used (default value). When this bit is set, 3 3 4 the sinc filter is used. The benefit of the sinc filter compared to the sinc filter is its lower settling time. 3 4 For a given output data rate, fADC, the sinc filter has a settling time of 3/fADC whereas the sinc filter has 4 a settling time of 4/fADC when chop is disabled. The sinc filter, due to its deeper notches, gives better 50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing 4 codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc filter gives 3 better performance than the sinc filter for rms noise and no missing codes. MR14 0 This bit must be programmed with a Logic 0 for correct operation. MR13 ENPAR Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. Rev. 0 | Page 21 of 56 AD7194 Bit Location Bit Name Description MR12 CLK_DIV Clock divide-by-2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, set this bit to 0. When performing internal full-scale calibrations, this bit must be set when AVDD is less than 4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data rate is used while performing the calibration. When AV is greater than or equal to 4.75 V, it is not compulsory to set DD the CLK_DIV bit when performing internal full-scale calibrations. MR11 Single Single cycle conversion enable bit. When this bit is set, the AD7194 settles in one conversion cycle so that it functions as a zero latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected. If the fast-settling filter is enabled, this bit (single) does not have an effect on the conversions unless chopping is also enabled. MR10 REJ60 This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/ 60 Hz rejection. MR9 to MR0 FS9 to FS0 Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter cutoff frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, they also determine the output noise and, therefore, the effective resolution of the device (see Table 6 through Table 11). When chop is disabled, fast settling mode is disabled and continuous conversion mode is selected Output Data Rate = (MCLK/1024)/FS where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop disabled and fast settling mode disabled, the first notch frequency is equal to the output data rate when converting on a single channel. When chop is enabled (fast settling mode disabled) Output Data Rate = (MCLK/1024)/(N × FS) where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The first notch frequency of the sinc filter is equal to N × Output Data Rate The chopping introduces notches at odd integer multiples of Output Data Rate/2 Rev. 0 | Page 22 of 56 AD7194 Table 20. Operating Modes (MD) MD2 MD1 MD0 Mode 0 0 0 Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the communications register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each conversion by writing to the communications register. After power-on, a reset, or a recon- figuration of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are available at the selected output data rate, which is dependent on filter choice. 0 0 1 Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The internal clock requires 200 μs typically to power up and settle. The ADC then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in the data register. RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register until another conversion is performed. RDY remains active (low) until the data is read or another conversion is performed. 0 1 0 Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks continue to be provided. 0 1 1 Power-down mode. In power-down mode, all AD7194 circuitry is powered down. The external crystal, if selected, remains active. 1 0 0 Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. 1 0 1 Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is recommended each time that the gain of a channel is changed to minimize the full-scale error. When AVDD is less than 4.75 V, the CLK_DIV bit must be set when performing the internal full-scale calibration. 1 1 0 System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is recommended each time that the gain of a channel is changed. 1 1 1 System full-scale calibration. The user should connect the system full-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is recommended each time the gain of a channel is changed. Rev. 0 | Page 23 of 56 AD7194 Table 21 outlines the bit designations for the configuration register. CONFIGURATION REGISTER CON0 through CON23 indicate the bit locations. CON denotes RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 that the bits are in the configuration register. CON23 denotes The configuration register is a 24-bit register from which data the first bit of the data stream. The number in parentheses can be read or to which data can be written. This register is indicates the power-on/reset default status of that bit. used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel. CON23 CON22 CON21 CON20 CON19 CON18 CON17 CON16 Chop(0) 0(0) 0(0) REFSEL(0) 0(0) Pseudo(0) 0(0) Temp(0) CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8 CH7(0) CH6(0) CH5(0) CH4(0) CH3(0) CH2(0) CH1(0) CH0(1) CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0 Burn(0) REFDET(0) 0(0) BUF(1) U/B (0) G2(1) G1(1) G0(1) Rev. 0 | Page 24 of 56 AD7194 Table 21. Configuration Register Bit Designations Bit Location Bit Name Description CON23 Chop Chop enable bit. When the chop bit is cleared, chop is disabled. With chop disabled, higher conversion rates are allowed. 4 For an FS word of 96 decimal and the sinc filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. When the chop bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed. However, this increases the conversion time and settling time of the ADC. 4 For example, when FS = 96 decimal and the sinc filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. CON22, CON21 0 These bits must be programmed with a Logic 0 for correct operation. CON20 REFSEL Reference select bits. The reference source for the ADC is selected using these bits. REFSEL Reference Voltage 0 External reference applied between REFIN1(+) and REFIN1(−). 1 External reference applied between the AIN3/P1/REFIN2(+) and AIN4/P0/REFIN2(−) pins. CON19 0 This bit must be programmed with a Logic 0 for correct operation. CON18 Pseudo Pseudo differential analog inputs. When the pseudo bit is set to 1, the AD7194 is configured to have 16 pseudo differential analog inputs with AINCOM as the common negative terminal. Bits CH7 to CH4 select the positive input terminal while bits CH3 to CH0 have no effect. When the pseudo bit is set to 0, channel selection is controlled using the CH7 to CH0 bits. CON17 0 This bit must be programmed with a Logic 0 for correct operation. CON16 Temp Temperature sensor select bit. When the Temp bit is set to 1, the internal temperature sensor is selected. When the Temp bit is low, the analog input channel as determined by the Pseudo bit and the CH7 to CH0 bits is selected. The temperature sensor does not have a unique code in bits CHD3 to CHD0 of the status register. CON16 to CON8 CH7 to CH0 Channel select bits. These bits select which channel is enabled on the AD7194 (see Table 22 to Table 24). The conversion on each channel requires the complete settling time. The four LSBs of the status register indicate the channel corresponding to the conversion in the data register. The four LSBs correspond to bits CH7 to CH3, that is, the positive analog input terminal. CON7 Burn When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When Burn = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and when chop is disabled. CON6 REFDET Enables the reference detect function. When set, the NOREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference detect circuitry operates only when the ADC is active. CON5 0 This bit must be programmed with a Logic 0 for correct operation. CON4 BUF Enables the buffer on the analog inputs. If BUF is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. When the buffer is enabled, it requires some head- room; therefore, the voltage on any input pin must be limited to 250 mV within the power supply rails. If cleared, the analog inputs are unbuffered, lowering the power consumption of the device. With the buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AVDD. CON3 U/B Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar operation is selected. CON2 to CON0 G2 to G0 Gain select bits. These bits are written by the user to select the ADC input range as follows: G2 G1 G0 Gain ADC Input Range (5 V Reference) 0 0 0 1 ±2.5 V 0 0 1 Reserved 0 1 0 Reserved 0 1 1 8 ±312.5 mV 1 0 0 16 ±156.2 mV 1 0 1 32 ±78.125 mV 1 1 0 64 ±39.06 mV 1 1 1 128 ±19.53 mV Rev. 0 | Page 25 of 56 AD7194 Channel Selection (Pseudo Bit = 0) Table 22. Positive Input Selection Table 23. Negative Input Selection Positive Input Enable Bits in Negative Input Enable Bits in the Positive Status Negative the Configuration Register Input Enabled Configuration Register Register Bits Input Enabled CH7 CH6 CH5 CH4 AIN(+) CHD[3:0] CH3 CH2 CH1 CH0 AIN(−) 0 0 0 0 AIN1 0000 0 0 0 0 AIN1 0 0 0 1 AIN2 0001 0 0 0 1 AIN2 0 0 1 0 AIN3 0010 0 0 1 0 AIN3 0 0 1 1 AIN4 0011 0 0 1 1 AIN4 0 1 0 0 AIN5 0100 0 1 0 0 AIN5 0 1 0 1 AIN6 0101 0 1 0 1 AIN6 0 1 1 0 AIN7 0110 0 1 1 0 AIN7 0 1 1 1 AIN8 0111 0 1 1 1 AIN8 1 0 0 0 AIN9 1000 1 0 0 0 AIN9 1 0 0 1 AIN10 1001 1 0 0 1 AIN10 1010 1 0 1 0 AIN11 1 0 1 0 AIN11 1 0 1 1 1011 1 0 1 1 AIN12 AIN12 1 1 0 0 1100 AIN13 1 1 0 0 AIN13 1 1 0 1 1101 1 1 0 1 AIN14 AIN14 1 1 1 0 1110 1 1 1 0 AIN15 AIN15 1 1 1 1 1 1 1 1 AIN16 1111 AIN16 Table 24. Channel Selection (Pseudo Bit = 1) Channel Enable Bits in the Configuration Register Channel Enabled Status Register CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Positive Input AIN(+) Negative Input AIN(−) Bits CHD[3:0] 0 0 0 0 X X X X AIN1 AINCOM 0000 0 0 0 1 X X X X AIN2 AINCOM 0001 0 0 1 0 X X X X AIN3 AINCOM 0010 0 0 1 1 X X X X AIN4 AINCOM 0011 0 1 0 0 X X X X AIN5 AINCOM 0100 0 1 0 1 X X X X AIN6 AINCOM 0101 0 1 1 0 X X X X AIN7 AINCOM 0110 0 1 1 1 X X X X AIN8 AINCOM 0111 1 0 0 0 X X X X AIN9 AINCOM 1000 1 0 0 1 X X X X AIN10 AINCOM 1001 1 0 1 0 X X X X AIN11 AINCOM 1010 1 0 1 1 X X X X AIN12 AINCOM 1011 1 1 0 0 X X X X AIN13 AINCOM 1100 1 1 0 1 X X X X AIN14 AINCOM 1101 1 1 1 0 X X X X AIN15 AINCOM 1110 1 1 1 1 X X X X AIN16 AINCOM 1111 Rev. 0 | Page 26 of 56 AD7194 GPOCON REGISTER DATA REGISTER RS2, RS1, RS0 = 101; Power-On/Reset = 0x00 RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000 The GPOCON register is an 8-bit register from which data can The conversion result from the ADC is stored in this data register. be read or to which data can be written. This register is used to This is a read-only, 24-bit register. Upon completion of a read enable the general-purpose digital outputs. RDY operation from this register, the pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the Table 25 outlines the bit designations for the GPOCON register. status register are appended to each 24-bit conversion. This is GP0 through GP7 indicate the bit locations. GP denotes that the advisable when several analog input channels are enabled because bits are in the GPOCON register. GP7 denotes the first bit of the four LSBs of the status register (CHD3 to CHD0) identify the data stream. The number in parentheses indicates the the channel from which the conversion originated. power-on/reset default status of that bit. ID REGISTER RS2, RS1, RS0 = 100; Power-On/Reset = 0xX3 The identification number for the AD7194 is stored in the ID register. This is a read-only register. GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0(0) 0(0) GP32EN(0) GP10EN(0) P3DAT(0) P2DAT(0) P1DAT(0) P0DAT(0) Table 25. Register Bit Designations Bit Location Bit Name Description GP7, GP6 0 These bits must be programmed with a Logic 0 for proper operation. GP5 GP32EN Digital Output P3 and Digital Output P2 enable. When GP32EN is set, the P3 and P2 digital outputs are active. When GP32EN is cleared, Pin P3 functions as analog input Pin AIN1 and Pin P2 functions as analog input Pin AIN2. GP4 GP10EN Digital Output P1 and Digital Output P0 enable. When GP10EN is set, the P1 and P0 digital outputs are active. When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are ignored. The P1 and P0 pins can be used as a reference input, REFIN2, when the REFSEL bit in the configuration register is set to 1. When GP10EN is cleared and Bit REFSEL is cleared, Pin P1 functions as analog input Pin AIN3 while Pin P0 functions as analog input Pin AIN4. GP3 P3DAT Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin. When P3DAT is high, the P3 output pin is high. When P3DAT is low, the P3 output pin is low. When the GPOCON register is read, the P3DAT bit reflects the status of the P3 pin if GP32EN is set. GP2 P2DAT Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin. When P2DAT is high, the P2 output pin is high. When P2DAT is low, the P2 output pin is low. When the GPOCON register is read, the P2DAT bit reflects the status of the P2 pin if GP32EN is set. GP1 P1DAT Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin. When P1DAT is high, the P1 output pin is high. When P1DAT is low, the P1 output pin is low. When the GPOCON register is read, the P1DAT bit reflects the status of the P1 pin if GP10EN is set. GP0 P0DAT Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin. When P0DAT is high, the P0 output pin is high. When P0DAT is low, the P0 output pin is low. When the GPOCON register is read, the P0DAT bit reflects the status of the P0 pin if GP10EN is set. Rev. 0 | Page 27 of 56 AD7194 OFFSET REGISTER FULL-SCALE REGISTER RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000) RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0 The offset register holds the offset calibration coefficient for the The full-scale register is a 24-bit register that holds the full-scale ADC. The power-on reset value of the offset register is 0x800000. calibration coefficient for the ADC. The full-scale register is The register is a 24-bit read/write register. It is used in conjunc- a read/write register. However, when writing to the full-scale tion with the full-scale register to form a register pair. The register, the ADC must be placed in power-down mode or idle power-on reset value is automatically overwritten if an internal mode. The register is configured at power-on with a factory or system zero-scale calibration is initiated by the user. The calibrated full-scale calibration coefficient, the calibration being AD7194 must be placed in power-down mode or idle mode performed at gain = 1. Therefore, every device has different when writing to the offset register. default coefficients. The default value is automatically over- written if an internal or system full-scale calibration is initiated by the user or if the full-scale register is written to. Rev. 0 | Page 28 of 56 AD7194 ADC CIRCUIT INFORMATION AV AGND DV DGND REFIN1(+) REFIN1(–) DD DD REFERENCE DETECT AD7194 AIN1/P3 V DD AIN2/P2 AIN3/P1/REFIN2(+) AIN4/P0/REFIN2(–) DOUT/RDY SERIAL INTERFACE AIN5 MUX Σ-Δ DIN PGA AND ADC CONTROL SCLK LOGIC AIN16 CS AINCOM AGND CLOCK TEMP CIRCUITRY SENSOR MCLK1 MCLK2 Figure 21. Basic Connection Diagram Σ-Δ ADC and Filter OVERVIEW The AD7194 contains a fourth-order Σ-Δ modulator followed The AD7194 is an ultralow noise ADC that incorporates a by a digital filter. sigma-delta (Σ-Δ) modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range The device has several filter options: signals such as those in pressure transducers, weigh scales, and 4 • Sinc strain gage applications. Figure 21 shows the basic connections 3 • Sinc required to operate the part. • Chop enabled/disabled Analog Inputs • Fast settling The device can be configured to have four differential or eight • Zero latency pseudo differential analog inputs. The analog inputs can be Serial Interface buffered or unbuffered. The AD7194 uses flexible multiplexing, thus any analog input pin can be selected as a positive input The AD7194 has a 4-wire SPI. The on-chip registers are and any analog input pin can be selected as a negative input. accessed via the serial interface. Multiplexer Clock The on-chip multiplexer increases the channel count of the The AD7194 has an internal 4.92 MHz clock. Either this clock device. Because the multiplexer is included on chip, any channel or an external clock can be used as the clock source to the AD7194. changes are synchronized with the conversion process. The internal clock can also be made available on a pin if a clock source is required for external circuitry. PGA Temperature Sensor The analog input signal can be amplified using the PGA. The PGA allows gains of 1, 8, 16, 32, 64, and 128. The on-chip temperature sensor monitors the die temperature. Reference Detect Digital Outputs The AD7194 is capable of monitoring the external reference. If The AD7194 has four general-purpose digital outputs. These the reference is not present, a flag is set in the status register of can be used for driving external circuitry. For example, an the device. external multiplexer can be controlled by these outputs. Burnout Currents Calibration Two 500 nA burnout currents are included on-chip to detect Both internal and system calibration are included on chip; the presence of the external sensor. therefore, the user has the option of removing offset/gain errors internal to the AD7194 only, or removing the offset/gain errors of the complete end system. Rev. 0 | Page 29 of 56 08566-021 AD7194 The absolute input voltage range in buffered mode is restricted ANALOG INPUT CHANNEL to a range between AGND + 250 mV and AV − 250 mV. Care DD The AD7194 uses flexible multiplexing so any of the analog must be taken in setting up the common-mode voltage to not input pins AIN1 to AIN16 can be selected as a positive input or exceed these limits; otherwise, linearity and noise performance a negative input (see Table 22 and Table 23). The AINCOM pin degrade. can be a negative analog input pin only. The absolute input voltage in unbuffered mode includes the AVDD range between AGND − 50 mV and AVDD + 50 mV. The AIN1 negative absolute input voltage limit allows the possibility of monitoring small true bipolar signals with respect to AGND. AVDD PROGRAMMABLE GAIN ARRAY (PGA) AVDD AIN2 BURNOUT When the gain stage is enabled, the output from the buffer is CURRENTS applied to the input of the PGA. The presence of the PGA PGA TO ADC means that signals of small amplitude can be gained within the AVDD AD7194 and still maintain excellent noise performance. For example, when the gain is set to 128, the rms noise is 11 nV, AIN15 typically, when the output data rate is 4.7 Hz, which is equivalent to 22.7 bits of effective resolution or 20 bits of noise-free AVDD resolution. AIN16 The AD7194 can be programmed to have a gain of 1, 8, 16, 32, 64, and 128 by using Bit G2 to Bit G0 in the configuration AVDD register. Therefore, with an external 2.5 V reference, the unipolar ranges are from 0 mV to 19.53 mV to 0 V to 2.5 V, AINCOM and the bipolar ranges are from ±19.53 mV to ±2.5 V. The analog input range must be limited to ±(AVDD − 1.25 V)/gain Figure 22. Analog Input Multiplexer Circuit because the PGA requires some headroom. Therefore, if VREF = The channels are configured using bits CH7 to CH0 and bit AVDD = 5 V, the maximum analog input that can be applied to the Pseudo in the configuration register (See Table 22 to Table 24). AD7194 is 0 V to 3.75 V/gain in unipolar mode or ±3.75 V/gain The device can be configured to have eight differential inputs, in bipolar mode. sixteen pseudo-differential inputs or a combination of both. The REFERENCE inputs can be buffered or unbuffered. In the buffered mode (the The ADC has a fully differential input capability for the BUF bit in the configuration register is set to 1), the input channel reference channel. In addition, the user has the option of feeds into a high impedance input stage of the buffer amplifier. selecting one of two external reference options (REFIN1(±) Therefore, the input can tolerate significant source impedances and or REFIN2(±)). The reference source for the AD7194 is is tailored for direct connection to external resistive type sensors selected using the REFSEL bit in the configuration register. such as strain gages or resistance temperature detectors (RTDs). The REFIN2(±) pins are dual purpose: they can function as When BUF = 0, the part is operated in the unbuffered mode. two general-purpose output pins or as reference pins. When This results in a higher analog input current. Note that this the REFSEL bit is set to 1, these pins automatically function as unbuffered input path provides a dynamic load to the driving reference pins. source. Therefore, resistor/capacitor combinations on the input The common-mode range for these differential inputs is from pins can cause gain errors, depending on the output impedance AGND to AV . The reference voltage REFIN (REFINx(+) − DD of the source that is driving the ADC input. Table 26 shows the REFINx(−)) is AV nominal, but the AD7194 is functional DD allowable external resistance/capacitance values for unbuffered with reference voltages from 1 V to AV . In applications where DD mode at a gain of 1 such that no gain error at the 18-bit level is the excitation (voltage or current) for the transducer on the introduced. analog input also drives the reference voltage for the part, the Table 26. External R-C Combination for No 18-Bit Gain Error effect of the low frequency noise in the excitation source is removed C (pF) R (Ω) because the application is ratiometric. If the AD7194 is used in a 50 1.4 k nonratiometric application, a low noise reference should be used. 100 850 The reference input is unbuffered; therefore, excessive R-C 500 300 source impedances introduce gain errors. R-C values similar to 1000 230 those in Table 26 are recommended for the reference inputs. 5000 30 Deriving the reference input voltage across an external resistor means that the reference input sees significant external source Rev. 0 | Page 30 of 56 08566-071 AD7194 impedance. External decoupling on the REFINx pins is not input is configured for unipolar mode with a gain of 2, the input recommended in this type of circuit configuration. Conversely, voltage range on the AIN1 pin is 2.5 V to 3.75 V when a 2.5 V if large decoupling capacitors are used on the reference inputs, reference is used. there should be no resistors in series with the reference inputs. If AINCOM is 2.5 V and the AD7194 AIN1 analog input is Recommended 2.5 V reference voltage sources for the AD7194 configured for bipolar mode with a gain of 2, the analog input include the ADR421 and ADR431, which are low noise references. range on AIN1 is 1.25 V to 3.75 V. The bipolar/unipolar option These references tolerate decoupling capacitors on REFINx(+) is chosen by programming the U/B bit in the configuration without introducing gain errors in the system. Figure 23 shows the register. recommended connections between the ADR421 and the AD7194. DATA OUTPUT CODING ADR421 AD7194 AVDD When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input 2 6 V V REFINx(+) IN OUT voltage resulting in a code of 00...00, a midscale voltage resulting 0.1µF 10µF 4.7µF in a code of 100...000, and a full-scale input voltage resulting in 4 GND TRIM 5 REFINx(–) a code of 111...111. The output code for any analog input voltage can be represented as Figure 23. ADR421 to AD7194 Connections Code = (2N × AIN × Gain)/VREF REFERENCE DETECT When the ADC is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting The AD7194 includes on-chip circuitry to detect whether the in a code of 000...000, a zero differential input voltage resulting part has a valid reference for conversions or calibrations. This in a code of 100...000, and a positive full-scale input voltage feature is enabled when the REFDET bit in the configuration resulting in a code of 111...111. The output code for any analog register is set to 1. If the voltage between the selected REFINx(+) input voltage can be represented as and REFINx(−) pins is less than 0.3 V, the AD7194 detects that it no longer has a valid reference. In this case, the NOREF bit Code = 2N – 1 × [(AIN × Gain/VREF) + 1] of the status register is set to 1. When the voltage between the where: selected REFINx(+) and REFINx(−) pins is greater than 0.6 V, AIN is the analog input voltage. the AD7194 detects a valid reference; thus, the NOREF bit is set Gain is the PGA setting (1 to 128). to 0. The operation of the NOREF bit is undefined when the N = 24. voltage between the selected REFINx(+) and REFINx(−) pins BURNOUT CURRENTS is between 0.3 V and 0.6 V. The AD7194 contains two 500 nA constant current generators, If the AD7194 is performing normal conversions and the one sourcing current from AV to AIN(+) and one sinking DD NOREF bit becomes active, the conversion result is all 1s. current from AIN(−) to AGND. The currents are switched to Therefore, it is not necessary to continuously monitor the the selected analog input pair. Both currents are either on or off, status of the NOREF bit when performing conversions. It is depending on the burnout current enable (burn) bit in the only necessary to verify its status if the conversion result read configuration register. from the ADC data register is all 1s. These currents can be used to verify that an external transducer If the AD7194 is performing either an offset or full-scale cali- remains operational before attempting to take measurements on bration and the NOREF bit becomes active, the updating of the that channel. After the burnout currents are turned on, they respective calibration registers is inhibited to avoid loading flow in the external transducer circuit, and a measurement of incorrect coefficients to these registers, and the ERR bit in the the input voltage on the analog input channel can be taken. It status register is set. If the user is concerned about verifying that takes some time for the burnout currents to detect an open a valid reference is in place every time a calibration is performed, circuit condition because the currents must charge any external the status of the ERR bit should be checked at the end of the capacitors. calibration cycle. There are several reasons that a fault condition is detected: the BIPOLAR/UNIPOLAR CONFIGURATION front-end sensor may be either open circuit or overloaded, or The analog input to the AD7194 can accept either unipolar or the reference may be absent and the NOREF bit in the status bipolar input voltage ranges. A bipolar input range does not register is set, thus clamping the data to all 1s. The user must imply that the part can tolerate negative voltages with respect check these three cases before making a determination. to system AGND. In pseudo differential mode, signals are If the voltage measured is 0 V, it may indicate that the transducer referenced to AINCOM, whereas in differential mode, signals has short circuited. The current sources work over the normal are referenced to the negative input of the differential pair. For example, if AINCOM is 2.5 V and the AD7194 AIN1 analog Rev. 0 | Page 31 of 56 08566-022 AD7194 absolute input voltage range specifications when the analog Figure 3 and Figure 4 show timing diagrams for interfacing to inputs are buffered and chop is disabled. CS the AD7194 using to decode the part. Figure 3 shows the timing for a read operation from the output shift register of the DIGITAL INTERFACE AD7194, and Figure 4 shows the timing for a write operation to As indicated in the On-Chip Registers section, the program- the input shift register. It is possible to read the same word from mable functions of the AD7194 are controlled using a set of the data register several times even though the DOUT/RDY line on-chip registers. Data is written to these registers via the serial returns high after the first read operation. However, care must interface of the part. Read access to the on-chip registers is also be taken to ensure that the read operations are completed provided by this interface. before the next output update occurs. In continuous read mode, All communication with the part must start with a write to the the data register can be read only once. communications register. After power-on or reset, the device CS The serial interface can operate in 3-wire mode by tying low. expects a write to its communications register. The data written In this case, the SCLK, DIN, and DOUT/RDY lines are used to to this register determines whether the next operation is a read communicate with the AD7194. The end of the conversion can operation or a write operation, and it determines to which be monitored using the RDY bit or pin. This scheme is suitable register this read or write operation occurs. Therefore, write CS is required as a decoding for interfacing to microcontrollers. If access to any of the other registers on the part begins with a signal, it can be generated from a port pin. For microcontroller write operation to the communications register, followed by a interfaces, it is recommended that SCLK idle high between data write to the selected register. A read operation from any other transfers. register (except when continuous read mode is selected) starts with a write to the communications register, followed by a read The AD7194 can be operated with CS used as a frame synchro- operation from the selected register. nization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS because CS The serial interface of the AD7194 consists of four signals: , CS normally occurs after the falling edge of SCLK in DSPs. The RDY DIN, SCLK, and DOUT/ . The DIN line is used to transfer SCLK can continue to run between data transfers, provided the data into the on-chip registers and DOUT/RDY is used for timing numbers are obeyed. accessing data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN The serial interface can be reset by writing a series of 1s to the or DOUT/RDY) occur with respect to the SCLK signal. DIN input. If a Logic 1 is written to the AD7194 DIN line for at least 40 serial clock cycles, the serial interface is reset. This RDY The DOUT/ pin functions as a data ready signal also, the ensures that the interface can be reset to a known state if the line going low when a new data-word is available in the output interface is lost due to a software error or a glitch in the system. register. It is reset high when a read operation from the data Reset returns the interface to the state in which it expects a write register is complete. It also goes high prior to the updating of to the communications register. This operation resets the the data register to indicate when not to read from the device, to contents of all registers to their power-on values. Following a ensure that a data read is not attempted while the register is reset, the user should allow a period of 200 μs before addressing being updated. CS is used to select a device. It can be used to the serial interface. decode the AD7194 in systems where several components are The AD7194 can be configured to continuously convert or to connected to the serial bus. perform a single conversion (see Figure 24 through Figure 26). Rev. 0 | Page 32 of 56 AD7194 Single Conversion Mode RDY CS RDY DOUT/ goes high. If is low, DOUT/ remains high until another conversion is initiated and completed. The data In single conversion mode, the AD7194 is placed in power- register can be read several times, if required, even when down mode after conversions. When a single conversion is DOUT/RDY has gone high. initiated by setting MD2 to 0, MD1 to 0, and MD0 to 1 in the mode register, the AD7194 powers up, performs a single If the DAT_STA bit in the mode register is set to 1, the contents conversion, and then returns to power-down mode. The on- of the status register are output along with the conversion each chip oscillator requires 200 μs, approximately, to power up. time that the data read is performed. The four LSBs of the status register indicate the channel to which the conversion corresponds. RDY DOUT/ goes low to indicate the completion of a conver- sion. When the data-word has been read from the data register, CS 0x08 0x280060 0x58 DIN DATA DOUT/RDY SCLK Figure 24. Single Conversion Rev. 0 | Page 33 of 56 08566-023 AD7194 Continuous Conversion Mode register additional times, if required. However, the user must ensure that the data register is not being accessed at the com- Continuous conversion is the default power-up mode. The pletion of the next conversion or else the new conversion word AD7194 converts continuously, and the RDY bit in the status is lost. register goes low each time a conversion is complete. If CS is If the DAT_STA bit in the mode register is set to 1, the contents low, the DOUT/RDY line also goes low when a conversion is of the status register are output along with the conversion each completed. To read a conversion, the user writes to the commu- time that the data read is performed. The status register indi- nications register, indicating that the next operation is a read of cates the channel to which the conversion corresponds. the data register. When the data-word has been read from the RDY data register, DOUT/ goes high. The user can read this CS 0x58 0x58 DIN DATA DATA DOUT/RDY SCLK Figure 25. Continuous Conversion Rev. 0 | Page 34 of 56 08566-024 AD7194 Continuous Read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion, Rather than write to the communications register each time a or if insufficient serial clocks are applied to the AD7194 to conversion is complete to access the data, the AD7194 can be read the word, the serial output register is reset when the next configured so that the conversions are placed on the DOUT/ conversion is complete, and the new conversion is placed in the RDY line automatically. By writing 01011100 to the communi- output serial register. cations register, the user need only apply the appropriate number of SCLK cycles to the ADC, and the conversion word is auto- To exit the continuous read mode, Instruction 01011000 must RDY RDY matically placed on the DOUT/ line when a conversion is be written to the communications register while the pin is complete. The ADC should be configured for continuous low. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to conversion mode. exit the continuous read mode. Additionally, a reset occurs if 40 When DOUT/RDY goes low to indicate the end of a conversion, consecutive 1s are seen on DIN. Therefore, DIN should be held sufficient SCLK cycles must be applied to the ADC; the data low in continuous read mode until an instruction is to be written to RDY conversion is then placed on the DOUT/ line. When the the device. RDY conversion is read, DOUT/ returns high until the next conversion is available. In this mode, the data can be read only once. The user must also ensure that the data-word is read CS 0x5C DIN DATA DATA DATA DOUT/RDY SCLK Figure 26. Continuous Read Rev. 0 | Page 35 of 56 08566-025 AD7194 RESET ENABLE PARITY The circuitry and serial interface of the AD7194 can be reset When the ENPAR bit in the mode register is set to 1, parity is by writing consecutive 1s to the device; 40 consecutive 1s are enabled. The contents of the status register must be transmitted required to perform the reset. This resets the logic, the digital along with each 24-bit conversion when the parity function is filter, and the analog modulator, whereas all on-chip registers enabled. To append the contents of the status register to each are reset to their default values. conversion read, the DAT_STA bit in the mode register should be set to 1. For each conversion read, the parity bit in the status A reset is automatically performed on power-up. When a reset is register is programmed so that the overall number of 1s trans- initiated, the user must allow a period of 200 μs before acces- mitted in the 24-bit data-word is even. Therefore, for example, sing any of the on-chip registers. A reset is useful if the serial if the 24-bit conversion contains 11 ones (binary format), the interface loses synchronization due to noise on the SCLK line. parity bit is set to 1 so that the total number of ones in the serial SYSTEM SYNCHRONIZATION transmission is even. If the microprocessor receives an odd number of 1s, it knows that the data received has been corrupted. The SYNC input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the The parity function does not ensure that all errors are detected. part. This allows the user to start gathering samples of the analog For example, two bits of corrupt data can result in the micro- input from a known point in time, that is, the rising edge of processor receiving an even number of ones. Therefore, an error SYNC SYNC . needs to be taken low for at least four master condition is not detected. clock cycles to implement the synchronization function. CLOCK If multiple AD7194 devices are operated from a common The AD7194 includes an internal 4.92 MHz clock on-chip. This master clock, they can be synchronized so that their data internal clock has a tolerance of ±4%. Either the internal clock registers are updated simultaneously. A falling edge on the or an external crystal/clock can be used as the clock source to SYNC pin resets the digital filter and the analog modulator and the AD7194. The clock source is selected using the CLK1 and places the AD7194 into a consistent, known state. While the CLK0 bits in the mode register. When an external crystal is SYNC pin is low, the AD7194 is maintained in this state. On the used, it must be connected across the MCLK1 and MCLK2 SYNC rising edge, the modulator and filter are taken out of this pins. The crystal manufacturer recommends the load capa- reset state and, on the next clock edge, the part starts to gather citances required for the crystal. The MCLK1 and MCLK2 input samples again. In a system using multiple AD7194 devices, pins of the AD7194 have a capacitance of 15 pF, typically. If a common signal to their SYNC pins synchronizes their opera- an external clock source is used, the clock source must be tion. This is normally done after each AD7194 has performed connected to the MCLK2 pin, and the MCLK1 pin can remain its own calibration or has calibration coefficients loaded into its floating. calibration registers. The conversions from the AD7194s are The internal clock can also be made available at the MCLK2 then synchronized. pin. This is useful when several ADCs are used in an appli- The part is taken out of reset on the master clock falling edge cation and the devices must be synchronized. The internal clock SYNC following the low to high transition. Therefore, when from one device can be used as the clock source for all ADCs in SYNC multiple devices are being synchronized, the pin should the system. Using a common clock, the devices can be synchro- be taken high on the master clock rising edge to ensure that all nized by applying a common reset to all devices, or the SYNC devices begin sampling on the master clock falling edge. If the pin can be pulsed. SYNC pin is not taken high in sufficient time, it is possible to TEMPERATURE SENSOR have a difference of one master clock cycle between the devices; Embedded in the AD7194 is a temperature sensor. This is that is, the instant at which conversions are available differs selected using the TEMP bit in the configuration register. When from part to part by a maximum of one master clock cycle. the TEMP bit is set to 1, the temperature sensor is enabled. SYNC The pin can also be used as a start conversion command. When the temperature sensor is selected and bipolar mode is SYNC In this mode, the rising edge of starts conversion, and the selected, the device should return a code of 0x800000 when the falling edge of RDY indicates when the conversion is complete. temperature is 0 Kelvin, theoretically. A one-point calibration is The settling time of the filter has to be allowed for each data needed to obtain the optimum performance from the sensor. register update. For example, if the ADC is configured to use Therefore, a conversion at 25°C should be recorded and the 4 the sinc filter, zero latency is disabled, and chop is disabled, the sensitivity calculated. The sensitivity is 2815 codes/°C, settling time equals 4/f where f is the output data rate ADC ADC approximately. The equation for the temperature sensor is when continuously converting on a single channel. Temperature (K) = (Conversion − 0x800000)/2815 K Temperature (°C) = Temperature (K) − 273 Rev. 0 | Page 36 of 56 AD7194 Following the one-point calibration, the internal temperature During an internal zero-scale or full-scale calibration, the respec- sensor has an accuracy of ±2°C, typically. tive zero input and full-scale input are automatically connected internally to the ADC input pins. A system calibration, LOGIC OUTPUTS however, expects the system zero-scale and system full-scale The AD7194 has four general-purpose digital outputs: P0, P1, voltages to be applied to the ADC pins before initiating the P2, and P3. These are enabled using the GP32EN and GP10EN calibration mode. In this way, errors external to the ADC are bits in the GPOCON register. The pins can be pulled high or removed. low using the P0DAT to P3DAT bits in the GPOCON register; From an operational point of view, treat a calibration like that is, the value at the pin is determined by the setting of the another ADC conversion. A zero-scale calibration, if required, P0DAT to P3DAT bits. The logic levels for these pins are must always be performed before a full-scale calibration. Set the determined by AVDD rather than by DVDD. When the GPOCON RDY system software to monitor the bit in the status register or register is read, Bit P0DAT to Bit P3DAT reflect the actual value the DOUT/RDY pin to determine the end of calibration via a at the pins; this is useful for short-circuit detection. polling sequence or an interrupt-driven routine. These pins can be used to drive external circuitry, for example, With chop disabled, both an internal zero-scale calibration and an external multiplexer. If an external multiplexer is used to a system zero-scale calibration require a time equal to the settling increase the channel count, the multiplexer logic pins can be 4 3 time, t (4/f for the sinc filter and 3/f for the sinc SETTLE ADC ADC controlled via the AD7194 general-purpose output pins. The filter). general-purpose output pins can be used to select the active multiplexer pin. Because the operation of the multiplexer is With chop enabled, an internal zero-scale calibration is not independent of the AD7194, the AD7194 modulator and filter needed because the ADC itself minimizes the offset continuously. SYNC should be reset using the pin or by a write to the mode or However, if an internal zero-scale calibration is performed, the configuration register each time that the multiplexer channel is settling time, tSETTLE (2/fADC), is required to perform the calibra- changed. tion. Similarly, a system zero-scale calibration requires a time of tSETTLE to complete. CALIBRATION To perform an internal full-scale calibration, a full-scale input The AD7194 provides four calibration modes that can be pro- voltage is automatically connected to the selected analog input grammed via the mode bits in the mode register. These modes for this calibration. For a gain of 1, the time required for an are internal zero-scale calibration, internal full-scale calibration, internal full-scale calibration is equal to tSETTLE. For higher gains, system zero-scale calibration, and system full-scale calibration. the internal full-scale calibration requires a time of 2 × tSETTLE. A calibration can be performed at any time by setting the MD2 A full-scale calibration is recommended each time the gain of a to MD0 bits in the mode register appropriately. A calibration channel is changed to minimize the full-scale error. should be performed when the gain is changed. After each conversion, the ADC conversion result is scaled using the ADC A system full-scale calibration requires a time of t . With SETTLE calibration registers before being written to the data register. chop disabled, the zero-scale calibration (internal or system The offset calibration coefficient is subtracted from the result zero-scale) should be performed before the system full-scale prior to multiplication by the full-scale coefficient. calibration is initiated. To start a calibration, write the relevant value to the MD2 to MD0 bits. The DOUT/RDY pin and the RDY bit in the status register go high when the calibration initiates. When the calibration is complete, the contents of the corresponding RDY calibration registers are updated, the bit in the status RDY CS register is reset, the DOUT/ pin returns low (if is low), and the AD7194 reverts to idle mode. Rev. 0 | Page 37 of 56 AD7194 An internal zero-scale calibration, system zero-scale calibration, An internal full-scale calibration reduces the gain error to and system full-scale calibration can be performed at any ±0.001%, typically, when the gain is equal to 1. For higher gains, output data rate. An internal full-scale calibration can be the gain error post internal full-scale calibration is ±0.003%, performed at any output data rate for which the filter word, typically when AVDD is equal to or higher than 4.75 V. When FS[9:0], is divisible by 16, FS[9:0] being the decimal equivalent AVDD is less than 4.75 V, the gain error post internal full-scale of the 10-bit word written to Bit FS9 to Bit FS0 in the mode calibration is ±0.005%, typically. register. Therefore, internal full-scale calibrations can be When AVDD is less than 4.75 V, the CLK_DIV bit must be set performed at output data rates such as 10 Hz or 50 Hz when when performing internal full-scale calibrations. This increases chop is disabled. Using these lower output data rates results in the calibration time by a factor of 2. The accuracy of the internal better calibration accuracy. full-scale calibration is further increased if chop is enabled and The offset error is, typically, ±150 μV/gain. If the gain is changed, it a low output data rate is used while performing the calibration. is advisable to perform a calibration. A zero-scale calibration (an A system full-scale calibration reduces the gain error to the internal zero-scale calibration or a system zero-scale calibration) order of the noise irrespective of the analog power supply reduces the offset error to the order of the noise. voltage. The gain error of the AD7194 is factory calibrated at a gain of 1 The AD7194 gives the user access to the on-chip calibration with a 5 V power supply at ambient temperature. Following this registers, allowing the microprocessor to read the calibration calibration, the gain error is ±0.001%, typically, at 5 V. Table 27 coefficients of the device and also to write its own calibration shows the typical uncalibrated gain error for the different gain coefficients from prestored values in the EEPROM. A read of settings. the registers can be performed at any time. However, the ADC must be placed in power-down or idle mode when writing to Table 27. Typical Precalibration Gain Error vs. Gain the registers. The values in the calibration registers are 24 bits Gain Precalibration Gain Error (%) wide. The span and offset of the part can also be manipulated 8 −0.11 using the registers. 16 −0.20 32 −0.23 64 −0.29 128 −0.4 Rev. 0 | Page 38 of 56 AD7194 DIGITAL FILTER The AD7194 offers a lot of flexibility in the digital filter. The When conversions are performed on a single channel and a device has five filter options. The device can be operated with step change occurs, the ADC does not detect the change in 3 4 a sinc or sinc filter, chop can be enabled or disabled, and zero analog input. Therefore, it continues to output conversions latency can be enabled. Finally, an averaging block can be at the programmed output data rate. However, it is at least four included after the sinc filter, which gives a fast settling mode. conversions later before the output data accurately reflect the The option selected affects the output data rate, settling time, analog input. If the step change occurs while the ADC is and 50 Hz/60 Hz rejection. The following sections describe processing a conversion, then the ADC takes five conversions each filter type, indicating the available output data rates for after the step change to generate a fully settled result. each filter option. The filter response along with the settling ANALOG INPUT time and 50 Hz/60 Hz rejection is also discussed. FULLY SETTLED 4 SINC FILTER (CHOP DISABLED) ADC OUTPUT 4 When the AD7194 is powered up, the sinc filter is selected by default and chop is disabled. This filter gives excellent noise 1/f ADC performance over the complete range of output data rates. It Figure 29. Asynchronous Step Change in Analog Input also gives the best 50 Hz/60 Hz rejection, but it has a long 4 The 3 dB frequency for the sinc filter is equal to settling time. ADC f = 0.23 × f 3dB ADC Table 28 gives some examples of the relationship between the 3 4 CHOP MODULATOR SINC /SINC POST FILTER values in Bits FS[9:0] and the corresponding output data rate and settling time. 4 Figure 27. Sinc Filter (Chop Disabled) Table 28. Examples of Output Data Rates and the 4 Corresponding Settling Time Sinc Output Data Rate/Settling Time FS[9:0] Output Data Rate (Hz) Settling Time (ms) The output data rate (the rate at which conversions are available 480 10 400 on a single channel when the ADC is continuously converting) 96 50 80 is equal to 80 60 66.6 fADC = fCLK/(1024 × FS[9:0]) 4 Sinc Zero Latency where: Zero latency is enabled by setting the single bit (Bit 11) in the fADC is the output data rate. mode register to 1. With zero latency, the complete settling time f is the master clock (4.92 MHz nominal). CLK is allowed for each conversion. Therefore, the conversion time FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the when converting on a single channel or when converting on mode register. several channels is constant. The user does not need to consider The output data rate can be programmed from 4.7 Hz to the effects of channel changes on the output data rate. 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. The output data rate equals 4 The settling time for the sinc filter is equal to fADC = 1/tSETTLE = fCLK/(4 × 1024 × FS[9:0]) tSETTLE = 4/fADC where: When a channel change occurs, the modulator and filter are fADC is the output data rate. reset. The settling time is allowed to generate the first conver- f is the master clock (4.92 MHz nominal). CLK sion after the channel change. Subsequent conversions on this FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the channel occur at 1/f . ADC mode register. CHANNEL A CHANNEL B CHANNEL CONVERSIONS CH A CH A CH A CH B CH B CH B 1/f ADC 4 Figure 28. Sinc Channel Change Rev. 0 | Page 39 of 56 08566-026 08566-027 08566-028 AD7194 When the analog input is constant or a channel change occurs, Figure 32 shows the frequency response when FS[9:0] is valid conversions are available at a constant output data rate. programmed to 80 and the master clock is equal to 4.92 MHz. When conversions are being performed on a single channel and The output data rate is 60 Hz when zero latency is disabled and 4 a step change occurs on the analog input, the ADC continues to 15 Hz when zero latency is enabled. The sinc filter provides output fully settled conversions if the step change is synchronized 60 Hz (±1 Hz) rejection of 120 dB minimum, assuming a stable with the conversion process. If the step change is asynchronous, master clock. one conversion is output from the ADC, which is not completely 0 settled (see Figure 30). –10 –20 ANALOG INPUT –30 FULLY SETTLED –40 ADC OUTPUT –50 –60 –70 1/f ADC –80 4 Figure 30. Sinc Zero Latency Operation –90 –100 Table 29 shows examples of output data rate and the corres- –110 ponding FS values. –120 Table 29. Examples of Output Data Rates and the FREQUENCY (Hz) Corresponding Settling Time (Zero Latency) 4 Figure 32. Sinc Filter Response (FS[9:0] = 80) FS[9:0] Output Data Rate (Hz) Settling Time (ms) Simultaneous 50 Hz and 60 Hz rejection is obtained when 480 2.5 400 FS[9:0] is programmed to 480 and the master clock equals 96 12.5 80 4.92 MHz. The output data rate is 10 Hz when zero latency is 80 15 66.6 4 disabled and 2.5 Hz when zero latency is enabled. The sinc 4 Sinc 50 Hz/60 Hz Rejection filter provides 50 Hz (±1 Hz) and 60 Hz (±1 Hz) rejection of 4 Figure 31 shows the frequency response of the sinc filter when 120 dB minimum, assuming a stable master clock. FS[9:0] is set to 96 and the master clock is 4.92 MHz. With zero 0 latency disabled, the output data rate is equal to 50 Hz. With –10 4 zero latency enabled, the output data rate is 12.5 Hz. The sinc –20 filter provides 50 Hz (±1 Hz) rejection in excess of 120 dB –30 minimum, assuming a stable master clock. –40 0 –50 –10 –60 –20 –70 –30 –80 –40 –90 –50 –100 –60 –110 –70 –120 0 30 60 90 120 150 –80 FREQUENCY (Hz) –90 4 Figure 33. Sinc Filter Response (FS[9:0] = 480) –100 Simultaneous 50 Hz/60 Hz rejection can also be achieved using –110 the REJ60 bit in the mode register. When FS[9:0] is set to 96 –120 and REJ60 is set to 1, notches are placed at 50 Hz and 60 Hz. FREQUENCY (Hz) 4 Figure 31. Sinc Filter Response (FS[9:0] = 96) Rev. 0 | Page 40 of 56 0 30 60 90 120 150 0 25 50 75 100 125 150 FILTER GAIN (dB) 08566-030 08566-029 FILTER GAIN (dB) FILTER GAIN (dB) 08566-032 08566-031 AD7194 The output data rate is 50 Hz when zero latency is disabled and The 3 dB frequency is equal to 12.5 Hz when zero latency is enabled. Figure 34 shows the f = 0.272 × f 3dB ADC 4 frequency response of the sinc filter. The filter provides 50 Hz Table 30 gives some examples of FS settings and the corres- ±1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming ponding output data rates and settling times. a stable 4.92 MHz master clock. 0 Table 30. Examples of Output Data Rates and the –10 Corresponding Settling Time –20 FS[9:0] Output Data Rate (Hz) Settling Time (ms) –30 480 10 300 –40 96 50 60 –50 80 60 50 –60 When a channel change occurs, the modulator and filter reset. –70 The complete settling time is allowed to generate the first –80 conversion after the channel change (see Figure 36). Subsequent –90 –100 conversions on this channel are available at 1/fADC. –110 CHANNEL B CHANNEL A CHANNEL –120 0 25 50 75 100 125 150 CONVERSIONS CH A CH A CH A CH B CH B CH B CH B FREQUENCY (Hz) 4 Figure 34. Sinc Filter Response (FS[9:0] = 96, REJ60 = 1) 1/f ADC 3 SINC FILTER (CHOP DISABLED) 3 Figure 36. Sinc Channel Change 3 4 A sinc filter can be used instead of the sinc filter. The filter is When conversions are performed on a single channel and a step 3 selected using the SINC3 bit in the mode register. The sinc change occurs, the ADC does not detect the change in analog filter is selected when the SINC3 bit is set to 1. input. Therefore, it continues to output conversions at the This filter has good noise performance when operating with programmed output data rate. However, it is at least three output data rates up to 1 kHz. It has moderate settling time and conversions later before the output data accurately reflects the moderate 50 Hz/60 Hz (±1 Hz) rejection. analog input. If the step change occurs while the ADC is processing a conversion, the ADC takes four conversions after ADC the step change to generate a fully settled result. ANALOG 3 4 CHOP MODULATOR SINC /SINC POST FILTER INPUT FULLY SETTLED ADC 3 OUTPUT Figure 35. Sinc Filter (Chop Disabled) 3 Sinc Output Data Rate and Settling Time 1/f ADC The output data rate (the rate at which conversions are available Figure 37. Asynchronous Step Change in Analog Input on a single channel when the ADC is continuously converting) 3 is equal to Sinc Zero Latency f = f /(1024 × FS[9:0]) Zero latency is enabled by setting the single bit (Bit 11) in the ADC CLK mode register to 1. With zero latency, the complete settling time where: is allowed for each conversion. Therefore, the conversion time f is the output data rate. ADC when converting on a single channel or when converting on fCLK is the master clock (4.92 MHz nominal). several channels is constant. The user does not need to consider FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the the effects of channel changes on the output data rate. mode register. The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. The settling time is equal to t = 3/f SETTLE ADC Rev. 0 | Page 41 of 56 FILTER GAIN (dB) 08566-034 08566-033 08566-036 08566-035 AD7194 3 The output data rate equals Sinc 50 Hz/60 Hz Rejection 3 f = 1/t = f /(3 × 1024 × FS[9:0]) Figure 39 show the frequency response of the sinc filter when ADC SETTLE CLK FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The where: output data rate is equal to 50 Hz when zero latency is disabled fADC is the output data rate. 3 and 16.7 Hz when zero latency is enabled. The sinc filter gives fCLK is the master clock (4.92 MHz nominal). 50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock. FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the 0 mode register. –10 When the analog input is constant or a channel change occurs, –20 valid conversions are available at a constant output data rate. –30 When conversions are being performed on a single channel and –40 a step change occurs on the analog input, the ADC continues to –50 output fully settled conversions if the step change is synchronized –60 with the conversion process. If the step change is asynchronous, –70 one conversion is output from the ADC that is not completely –80 settled (see Figure 38). –90 –100 ANALOG INPUT –110 FULLY SETTLED –120 ADC 0 25 50 75 100 125 150 OUTPUT FREQUENCY (Hz) 3 Figure 39. Sinc Filter Response (FS[9:0] = 96) 1/f ADC When FS[9:0] is set to 80 and the master clock equals 3 Figure 38. Sinc Zero Latency Operation 4.92 MHz, 60 Hz rejection is achieved (see Figure 40). The output data rate is equal to 60 Hz when zero latency is disabled Table 31 provides examples of output data rates and the corres- 3 and 20 Hz when zero latency is enabled. The sinc filter has ponding FS values. rejection of 95 dB minimum at 60 Hz ± 1 Hz, assuming a stable Table 31. Examples of Output Data Rates and the master clock. Corresponding Settling Time (Zero Latency) 0 FS[9:0] Output Data Rate (Hz) Settling Time (ms) –10 –20 480 3.3 300 –30 96 16.7 60 –40 80 20 50 –50 –60 –70 –80 –90 –100 –110 –120 0 30 60 90 120 150 FREQUENCY (Hz) 3 Figure 40. Sinc Filter Response (FS[9:0] = 80) Rev. 0 | Page 42 of 56 08566-037 FILTER GAIN (dB) FILTER GAIN (dB) 08566-039 08566-038 AD7194 4 Simultaneous 50 Hz and 60 Hz rejection is obtained when CHOP ENABLED (SINC FILTER) FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in With chop enabled, the ADC offset and offset drift are minimized. Figure 41. The output data rate is 10 Hz when zero latency is The analog input pins are continuously swapped. With the 3 disabled and 3.3 Hz when zero latency is enabled. The sinc analog input pins connected in one direction, the settling time filter has rejection of 100 dB minimum at 50 Hz ± 1 Hz and of the sinc filter is allowed and a conversion is recorded. The 60 Hz ± 1 Hz. analog input pins are then inverted, and another settled conver- sion is obtained. Subsequent conversions are averaged to 0 minimize the offset. This continuous swapping of the analog –10 input pins and the averaging of subsequent conversions means –20 that the offset drift is also minimized. With chop enabled, the –30 resolution increases by 0.5 bits. –40 ADC –50 –60 3 4 CHOP MODULATOR SINC /SINC POST FILTER –70 –80 –90 Figure 43. Chop Enabled –100 4 Output Data Rate and Settling Time (Sinc Chop –110 Enabled) –120 0 306090 120 150 4 For the sinc filter, the output data rate is equal to FREQUENCY (Hz) 3 Figure 41. Sinc Filter Response (FS[9:0] = 480) fADC = fCLK/(4 × 1024 × FS[9:0]) where: Simultaneous 50 Hz/60 Hz rejection is also achieved using the fADC is the output data rate. REJ60 bit in the mode register. When FS[9:0] is programmed to f is the master clock (4.92 MHz nominal). 96 and the REJ60 bit is set to 1, notches are placed at both 50 Hz CLK FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the and 60 Hz for a stable 4.92 MHz master clock. Figure 42 shows 3 mode register. the frequency response of the sinc filter with this configuration. Assuming a stable clock, the rejection at 50 Hz/60 Hz (±1 Hz) The value of FS[9:0] can be varied from 1 to 1023. This results is in excess of 67 dB minimum. in an output data rate of 1.17 Hz to 1200 Hz. The settling time is 0 equal to –10 tSETTLE = 2/fADC –20 Table 32 gives some examples of FS[9:0] values and the corres- –30 ponding output data rates and settling times. –40 –50 Table 32. Examples of Output Data Rates and the –60 Corresponding Settling Time –70 FS[9:0] Output Data Rate (Hz) Settling Time (ms) –80 96 12.5 160 –90 80 15 133 –100 –110 –120 0 25 50 75 100 125 150 FREQUENCY (Hz) 3 Figure 42. Sinc Filter Response (FS[9:0] = 96, REJ60 = 1) Rev. 0 | Page 43 of 56 FILTER GAIN (dB) FILTER GAIN (dB) 08566-041 08566-040 08566-042 AD7194 0 When a channel change occurs, the modulator and filter reset. –10 The complete settling time is required to generate the first –20 conversion after the channel change. Subsequent conversions –30 on this channel occur at 1/f . ADC –40 –50 CHANNEL A CHANNEL B CHANNEL –60 CONVERSIONS CH A CH A CH A CH B CH B CH B CH B CH B –70 –80 1/f –90 ADC 4 –100 Figure 44. Channel Change (Sinc Chop Enabled) –110 When conversions are performed on a single channel and a –120 0 25 50 75 100 125 150 step change occurs, the ADC does not detect the change in FREQUENCY (Hz) analog input; therefore, it continues to output conversions at 4 the programmed output data rate. However, it is at least two Figure 46. Sinc Filter Response (FS[9:0] = 96, Chop Enabled) conversions later before the output data accurately reflects the The 50 Hz/60 Hz rejection can be improved by setting the analog input. If the step change occurs while the ADC is REJ60 bit in the mode register to 1. With FS[9:0] set to 96 processing a conversion, the ADC takes three conversions after and REJ60 set to 1, the filter response shown in Figure 47 the step change to generate a fully settled result. is achieved. The output data rate is unchanged but the 50 Hz/ ANALOG 60 Hz (± 1 Hz) rejection is increased to 83 dB typically. INPUT FULLY 0 SETTLED –10 ADC OUTPUT –20 –30 1/f ADC –40 4 Figure 45. Asynchronous Step Change in Analog Input (Sinc Chop Enabled) –50 –60 The cutoff frequency f3dB is equal to –70 f = 0.24 × f 3dB ADC –80 4 –90 50 Hz/60 Hz Rejection (Sinc Chop Enabled) –100 When FS[9:0] is set to 96 and chopping is enabled, the output –110 data rate is equal to 12.5 Hz for a 4.92 MHz master clock. The –120 filter response shown in Figure 46 is obtained. The chopping 0 25 50 75 100 125 150 FREQUENCY (Hz) introduces notches at odd integer multiples of fADC/2. The 4 notches due to the sinc filter in addition to the notches intro- Figure 47. Sinc Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1) duced by the chopping mean that simultaneous 50 Hz and 60 Hz rejection is achieved for an output data rate of 12.5 Hz. The rejection at 50 Hz/60 Hz ± 1 Hz is typically 63 dB, assuming a stable master clock. Rev. 0 | Page 44 of 56 08566-044 08566-043 FILTER GAIN (dB) FILTER GAIN (dB) 08566-045 08566-046 AD7194 3 If conversions are performed on a single channel and a step CHOP ENABLED (SINC FILTER) change occurs, the ADC does not detect the change in analog With chop enabled, the ADC offset and offset drift are input; therefore, it continues to output conversions at the minimized. The analog input pins are continuously swapped. programmed output data rate. However, it is at least two With the analog input pins connected in one direction, the conversions later before the output data accurately reflects settling time of the sinc filter is allowed and a conversion is the analog input. If the step change occurs while the ADC is recorded. The analog input pins invert and another settled processing a conversion, then the ADC takes three conversions conversion is obtained. Subsequent conversions are averaged after the step change to generate a fully settled result. to minimize the offset. This continuous swapping of the analog ANALOG input pins and the averaging of subsequent conversions means INPUT that the offset drift is also minimized. With chop enabled, the FULLY SETTLED 3 resolution increases by 0.5 bits. Using the sinc filter with chop ADC OUTPUT enabled is suitable for output data rates up to 320 Hz. ADC 1/f ADC 3 Figure 50. Asynchronous Step Change in Analog Input (Sinc Chop Enabled) 3 4 CHOP MODULATOR SINC /SINC POST FILTER The cutoff frequency f is equal to 3dB 3 f3dB = 0.24 × fADC Figure 48. Chop Enabled (Sinc Chop Enabled) 3 50 Hz/60 Hz Rejection (Sinc Chop Enabled) 3 Output Data Rate and Settling Time (Sinc Chop Enabled) When FS[9:0] is set to 96 and chopping is enabled, the filter 3 response shown in Figure 51 is obtained. The output data rate For the sinc filter, the output data rate is equal to is equal to 16.7 Hz for a 4.92 MHz master clock. The chopping fADC = fCLK/(3 × 1024 × FS[9:0]) introduces notches at odd integer multiples of f /2. The ADC where: notches due to the sinc filter is addition to the notches intro- f is the output data rate. ADC duced by the chopping means that simultaneous 50 Hz and f is the master clock (4.92 MHz nominal). CLK 60 Hz rejection is achieved for an output data rate of 16.7 Hz. FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the The rejection at 50 Hz/60 Hz ± 1 Hz is typically 53 dB, mode register. assuming a stable master clock. 0 The value of FS[9:0] can be varied from 1 to 1023. This results –10 in an output data rate of 1.56 Hz to 1600 Hz. The settling time –20 is equal to –30 t = 2/f SETTLE ADC –40 –50 Table 33. Examples of Output Data Rates and the –60 3 Corresponding Settling Time (Chop Enabled, Sinc Filter) –70 FS[9:0] Output Data Rate (Hz) Settling Time (ms) –80 96 16.7 120 –90 80 20 100 –100 When a channel change occurs, the modulator and filter are –110 reset. The complete settling time is required to generate the first –120 0 25 50 75 100 125 150 conversion after the channel change. Subsequent conversions on FREQUENCY (Hz) this channel occur at 1/f . ADC 3 Figure 51. Sinc Filter Response (FS[9:0] = 96, Chop Enabled) CHANNEL A CHANNEL B CHANNEL CONVERSIONS CH A CH A CH A CH B CH B CH B CH B CH B 1/f ADC 3 Figure 49. Channel Change (Sinc Chop Enable) Rev. 0 | Page 45 of 56 08566-047 08566-048 FILTER GAIN (dB) 08566-049 08566-050 AD7194 The 50 Hz/60 Hz rejection can be improved by setting the The settling time is equal to REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and t = 1/f SETTLE ADC REJ60 set to 1, the filter response shown in Figure 52 is achieved. Table 34 lists sample FS words and the corresponding output The output data rate is unchanged but the 50 Hz/60 Hz ± 1 Hz data rates and settling times. rejection improves to 73 dB typically. 0 Table 34. Examples of Output Data Rates and the –10 4 Corresponding Settling Time (Fast Settling Mode, Sinc ) –20 Output Data Settling –30 FS[9:0] Average Rate (Hz) Time (ms) –40 96 16 2.63 380 –50 30 16 8.4 118.75 –60 6 16 42.1 23.75 –70 5 16 50.53 19.79 –80 When the analog input channel is changed, there is no –90 additional delay in generating valid conversions—the device –100 functions as a zero latency ADC. –110 CHANNEL B –120 CHANNEL A CHANNEL 0 25 50 75 100 125 150 FREQUENCY (Hz) CONVERSIONS CH A CH A CH A CH B CH B CH B CH B CH B CH B 3 Figure 52. Sinc Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1) 1/f ADC 4 4 FAST SETTLING MODE (SINC FILTER) Figure 54. Fast Settling, Sinc Filter In fast settling mode, the settling time is close to the inverse of When the device is converting on a single channel and a step the first filter notch; therefore, the user can achieve 50 Hz and/or change occurs on the analog input, the ADC does not detect the 60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz. change and continues to output conversions. If the step change The settling time is equal to 1/output data rate. Therefore, the is synchronized with the conversion, only fully settled results conversion time is constant when converting on a single channel are output from the ADC. However, if the step change is asyn- or when converting on several channels. There is no added chronous to the conversion process, there is one intermediate latency when switching channels. result, which is not completely settled (see Figure 55). Enable the fast settling mode using Bit AVG1 and Bit AVG0 in ANALOG INPUT the mode register. In fast settling mode, a postfilter is included 4 VALID after the sinc filter. The postfilter averages by 2, 8, or 16, ADC OUTPUT depending on the settings of the AVG1 and AVG0 bits. ADC 1/f ADC 4 3 4 Figure 55. Step Change on Analog Input, Sinc Filter CHOP MODULATOR SINC /SINC POST FILTER The output data rate is the same for chop enabled and chop disabled in fast settling mode. However, when chop is enabled, 4 Figure 53. Fast Settling Mode, Sinc Filter the settling time equals 4 Output Data Rate and Settling Time, Sinc Filter tSETTLE = 2/fADC With chop disabled, the output data rate is 4 Therefore, if chop is enabled, the sinc filter is selected, FS[9:0] fADC = fCLK/((4 + Avg − 1)× 1024 × FS[9:0]) (1) is set to 6, and averaging by 16 is enabled. The output data rate where: is equal to 42.1 Hz when the master clock equals 4.92 MHz. Therefore, the conversion time equals 1/42.10 Hz or 23.75 ms and f is the output data rate. ADC the settling time is equal to 47.5 ms. f is the master clock (4.92 MHz nominal). CLK 4 Avg is the average. 50 Hz/60 Hz Rejection, Sinc Filter FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the Figure 56 shows the frequency response when FS[9:0] is set to 6 mode register. and the postfilter averages by 16. This gives an output data rate If AVG1 = AVG0 = 0, the fast settling mode is not enabled. In this case, Equation 1 is not relevant. Rev. 0 | Page 46 of 56 FILTER GAIN (dB) 08566-052 08566-051 08566-053 08566-054 AD7194 of 42.10 Hz when the master clock equals 4.92 MHz. The sinc Simultaneous 50 Hz/60 Hz rejection is achieved when FS[9:0] is filter places the first notch at set to 30 and the postfilter averages by 16. The output data rate is equal to 8.4 Hz whereas the rejection at 50 Hz ± 0.5 Hz and f = f /(1024 × FS[9:0]) NOTCH CLK 60 Hz ± 0.5 Hz is 44 dB typically. The postfiltering places notches at fNOTCH/Avg (Avg is the 0 amount of averaging) and multiples of this frequency; therefore, –10 when FS[9:0] is set to 6 and the postfilter averaging is 16, a –20 notch is placed at 800 Hz due to the sinc filter and notches are –30 placed at 50 Hz and multiples of 50 Hz due to the postfilter. The –40 notch at 50 Hz is a first-order notch; therefore, the notch is not –50 wide. This means that the rejection at 50 Hz exactly is good, –60 assuming a stable 4.92 MHz master clock. However, in a band –70 of 50 Hz ± 1 Hz, the rejection degrades significantly. The –80 rejection at 50 Hz ± 0.5 Hz is 40 dB minimum, assuming a –90 stable clock; therefore, a good master clock source is –100 recommended when using fast settling mode. –110 0 –120 0 30 60 90 120 150 –10 FREQUENCY (Hz) –20 Figure 58. Filter Response for Average + Decimate Filter –30 4 (Sinc Filter, FS[9:0] = 30, Average by 16) –40 Simultaneous 50 Hz and 60 Hz rejection is also achieved by –50 using an FS word of 96 and averaging by 16; this places a notch –60 at 50 Hz. Setting the REJ60 bit to 1 places a notch at 60 Hz (see –70 Figure 59). The output data rate is reduced to 2.63 Hz with this –80 configuration but the rejection is improved to 100 dB typically –90 at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz. –100 –110 0 –120 –10 0 306090 120 150 –20 FREQUENCY (Hz) –30 Figure 56. Filter Response for Average + Decimate Filter 4 –40 (Sinc Filter, FS[9:0] = 6, Average by 16) –50 Figure 57 shows the filter response when FS[9:0] is set to 5 and –60 the postfilter averages by 16. In this case, the output data rate is –70 equal to 50.53 Hz (4.92 MHz master clock) while the first filter –80 notch is placed at 60 Hz. The rejection at 60 Hz ± 0.5 Hz is –90 equal to 40 dB minimum. –100 0 –110 –10 –120 –20 0 30 60 90 120 150 FREQUENCY (Hz) –30 Figure 59. Filter Response for Average + Decimate Filter –40 4 (Sinc Filter, FS[9:0] = 96, Average by 16) –50 –60 –70 –80 –90 –100 –110 –120 0 30 60 90 120 150 FREQUENCY (Hz) Figure 57. Filter Response for Average + Decimate Filter 4 (Sinc Filter, FS[9:0] = 5, Average by 16) Rev. 0 | Page 47 of 56 FILTER GAIN (dB) FILTER GAIN (dB) 08566-056 08566-055 FILTER GAIN (dB) FILTER GAIN (dB) 08566-057 08566-058 AD7194 3 FAST SETTLING MODE (SINC FILTER) If the analog input channel is changed, there is no additional delay in generating valid conversions and the device functions In fast settling mode, the settling time is close to the inverse of as a zero latency ADC. the first filter notch. Therefore, the user can achieve 50 Hz and/or 60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz. CHANNEL B CHANNEL A CHANNEL The settling time is equal to 1/output data rate. Therefore, the CONVERSIONS CH A CH A CH A CH B CH B CH B CH B CH B CH B conversion time is constant when converting on a single channel or when converting on several channels. There is no added latency when switching channels. 1/f ADC 3 Figure 61. Fast Settling, Sinc Filter The fast settling mode is enabled using Bit AVG1 and Bit AVG0 4 in the mode register. A postfilter is included after the sinc filter. When the device is converting on a single channel and a step The postfilter averages by 2, 8, or 16, depending on the settings change occurs on the analog input, the ADC does not detect of the AVG1 and AVG0 bits. the change and continues to output conversions. When the step ADC change is synchronized with the conversion, only fully settled results are output from the ADC. However, if the step change is asynchronous to the conversion process, one intermediate result 3 4 CHOP MODULATOR SINC /SINC POST FILTER is not completely settled (see Figure 62). ANALOG 3 INPUT Figure 60. Fast Settling Mode, Sinc Filter VALID 3 Output Data Rate and Settling Time, Sinc Filter ADC OUTPUT With chop disabled, the output data rate is f = f /((3 + Avg – 1)× 1024 × FS[9:0]) ADC CLK 1/f ADC 3 fADC is the output data rate. Figure 62. Step Change on Analog Input, Sinc Filter fCLK is master clock (4.92 MHz nominal). 3 50 Hz/60 Hz Rejection, Sinc Filter Avg is the average. Figure 63 shows the frequency response when FS[9:0] is set to 6 FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the and the postfilter averages by 16. This gives an output data rate mode register. of 44.44 Hz when the master clock is 4.92 MHz. The sinc filter If AVG1 = AVG0 = 0, the fast settling mode is not enabled. In places the first notch at this case, the preceding equation is not relevant. fNOTCH = fCLK/(1024 × FS[9:0]) The settling time is equal to The postfiltering places notches at fNOTCH/Avg (Avg is the tSETTLE = 1/fADC amount of averaging) and multiples of this frequency. There- Table 35 lists some sample FS words and the corresponding fore, when FS[9:0] is set to 6 and the postfilter averaging is 16, output data rates and settling times. a notch is placed at 800 Hz due to the sinc filter and notches are placed at 50 Hz and multiples of 50 Hz due to the postfilter. Table 35. Examples of Output Data Rates and the 3 The notch at 50 Hz is a first-order notch. Therefore, the notch is Corresponding Settling Time (Fast Settling Mode, Sinc ) not wide. This means that the rejection at 50 Hz exactly is good, Output Data Settling assuming a stable 4.92 MHz master clock. However, in a band of FS[9:0] Average Rate (Hz) Time (ms) 50 Hz ± 1 Hz, the rejection degrades significantly. The rejection at 96 16 2.78 Hz 360 ms 50 Hz ± 0.5 Hz is 40 dB minimum, assuming a stable clock; there- 30 16 8.9 Hz 112.5 ms fore, a good master clock source is recommended when using fast 6 16 44.44 Hz 22.5 ms settling mode. 5 16 53.3 Hz 18.75 ms Rev. 0 | Page 48 of 56 08566-059 08566-060 08566-061 AD7194 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 0 306090 120 150 0 306090 120 150 FREQUENCY (Hz) FREQUENCY (Hz) Figure 63. Filter Response for Average + Decimate Filter Figure 65. Filter Response for Average + Decimate Filter 3 3 (Sinc Filter, FS[9:0] = 6, Average by 16) (Sinc Filter, FS[9:0] = 30, Average by 16) Figure 64 shows the filter response when FS[9:0] is set to 5 and Simultaneous 50 Hz and 60 Hz rejection is also achieved by the post filter averages by 16. In this case, the output data rate is using an FS word of 96 and averaging by 16, which places a equal to 53.33 Hz when the first filter notch is placed at 60 Hz. notch at 50 Hz. Setting the REJ60 bit to 1 places a notch at The rejection at 60 Hz ± 0.5 Hz is equal to 40 dB minimum. 60 Hz (see Figure 66). The output data rate is reduced to 2.78 Hz with this configuration, but the rejection is improved 0 to 94 dB typically at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz. –10 –20 0 –30 –10 –40 –20 –50 –30 –60 –40 –70 –50 –80 –60 –90 –70 –100 –80 –110 –90 –120 –100 0 30 60 90 120 150 –110 FREQUENCY (Hz) –120 Figure 64. Filter Response for Average + Decimate Filter 0 30 60 90 120 150 3 (Sinc Filter, FS[9:0] = 5, Average by 16) FREQUENCY (Hz) Simultaneous 50 Hz/60 Hz rejection is achieved when FS[9:0] is Figure 66. Filter Response for Average + Decimate Filter 3 (Sinc Filter, FS[9:0] = 96, Average by 16) set to 30 and the postfilter averages by 16. The output data rate is equal to 8.9 Hz, whereas the rejection at 50 Hz ± 0.5 Hz and 60 Hz ± 0.5 Hz is 42 dB typically. Rev. 0 | Page 49 of 56 FILTER GAIN (dB) FILTER GAIN (dB) 08566-063 08566-062 FILTER GAIN (dB) FILTER GAIN (dB) 08566-064 08566-065 AD7194 input pins and the averaging of subsequent conversions means FAST SETTLING MODE (CHOP ENABLED) that the offset drift is also minimized. Chop can be enabled in the fast settling mode. With chop Chopping does not change the output data rate. However, the enabled, the ADC offset and offset drift are minimized. The settling time equals analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the tSETTLE = 2/fADC sinc filter is allowed and a conversion is recorded. The analog 4 Consequently, if chop is enabled, the sinc filter is selected, FS[9:0] input pins are then inverted, and another settled conversion is set to 6 and averaging by 16 is enabled, and the output data is obtained. Subsequent conversions are averaged so that the rate is equal to 42.1 Hz. Therefore, the conversion time equals offset is minimized. This continuous swapping of the analog 1/42.10 Hz or 23.75 ms and the settling time is equal to 47.5 ms. Rev. 0 | Page 50 of 56 AD7194 Table 36 shows some sample configurations and the SUMMARY OF FILTER OPTIONS corresponding performance in terms of throughput, settling The AD7194 has several filter options. The filter that is chosen time and 50 Hz/60 Hz rejection. affects the output data rate, settling time, the rms noise, the stop band attenuation, and the 50 Hz/60 Hz rejection. 1 Table 36. Filter Summary Output Data Settling 2 3 Filter FS[9:0] Rate (Hz) Time (ms) Throughput (Hz) REJ60 50 Hz Rejection (dB) 4 4 Sinc , Chop Disabled 1 4800 0.83 1200 0 No 50 Hz or 60 Hz rejection 4 Sinc , Chop Disabled 5 960 4.17 240 0 No 50 Hz or 60 Hz rejection 3 Sinc , Chop Disabled 5 960 3.125 320 0 No 50 Hz or 60 Hz rejection 4 Sinc , Chop Disabled 480 10 400 2.5 0 120 dB ( 50 Hz and 60 Hz) 3 Sinc , Chop Disabled 480 10 300 3.33 0 100 dB (50 Hz and 60 Hz) 4 Sinc , Chop Disabled 96 50 80 12.5 0 120 dB (50 Hz only) 4 Sinc , Chop Disabled 96 50 80 12.5 1 82 dB ( 50 Hz and 60 Hz) 3 Sinc , Chop Disabled 96 50 60 16.7 0 95 dB (50 Hz only) 3 Sinc , Chop Disabled 96 50 60 16.7 1 67 dB ( 50 Hz and 60 Hz) 4 Sinc , Chop Disabled 80 60 66.67 15 0 120 dB (60 Hz only) 3 Sinc , Chop Disabled 80 60 50 20 0 95 dB (60 Hz only) 4 Sinc , Chop Disabled, Zero 96 12.5 80 12.5 0 120 dB (50 Hz only) Latency 4 Sinc , Chop Disabled, Zero 96 12.5 80 12.5 1 82 dB ( 50 Hz and 60 Hz) Latency 4 Sinc , Chop Disabled, Zero 80 15 66.67 15 0 120 dB (60 Hz only) Latency 4 Sinc , Chop Enabled 96 12.5 160 6.25 1 80 dB (50 Hz and 60 Hz) 3 Sinc , Chop Enabled 96 16.7 120 8.33 1 67 dB (50 Hz and 60 Hz) 4 96 2.63 380 2.63 1 100 dB (50 Hz and 60 Hz) Fast Settling (Sinc , Chop Disabled, Average by 16) 4 Fast Settling (Sinc , Chop 96 2.78 360 2.78 1 94 dB (50 Hz and 60 Hz) Disabled, Average by 16) 4 Fast Settling (Sinc , Chop 5 50.53 19.79 50.53 0 40 dB (60 Hz only) Disabled, Average by 16) 3 Fast Settling (Sinc , Chop 5 53.33 18.75 53.33 0 40 dB (60 Hz only) Disabled, Average by 16) 4 Fast Settling (Sinc , Chop 6 42.10 23.75 42.1 0 40 dB (50 Hz only) Disabled, Average by 16) 3 Fast Settling (Sinc , Chop 6 44.44 22.5 44.44 0 40 dB (50 Hz only) Disabled, Average by 16) 1 These calculations assume a 4.92 MHz stable master clock. 2 Throughput is the rate at which conversions are available when several channels are enabled. In zero latency mode, the output data rate and throughput are equal. 3 For fast settling mode, the 50 Hz/60 Hz rejection is measured in a band of ±0.5 Hz around 50 Hz and/or 60 Hz. For all other modes, a region of ±1 Hz around 50 Hz and/or 60 Hz is used. 4 4 For output dates rates greater than 1 kHz, the sinc filter is recommended. Rev. 0 | Page 51 of 56 AD7194 GROUNDING AND LAYOUT because a ground loop results. In these situations, it is recom- Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are common- mended that the ground pins of the AD7194 be tied to the mode voltages. The high common-mode rejection of the part AGND plane. removes common-mode noise on these inputs. The analog and In any layout, the user must keep in mind the flow of currents digital supplies to the AD7194 are independent and separately in the system, ensuring that the paths for all currents are as close as pinned out to minimize coupling between the analog and possible to the paths the currents took to reach their destinations. digital sections of the device. The digital filter provides rejection Avoid forcing digital currents to flow through the AGND. of broadband noise on the power supplies, except at integer Avoid running digital lines under the device because this multiples of the modulator sampling frequency. couples noise onto the die, and allows the analog ground plane Connect an R-C filter to each analog input pin to provide rejection to run under the AD7194 to prevent noise coupling. The power at the modulator sampling frequency. A 100 Ω resistor in series supply lines to the AD7194 must use as wide a trace as possible with each analog input, a 0.1 μF capacitor between the analog to provide low impedance paths and reduce the effects of input pins, and a 0.01 μF capacitor from each analog input to glitches on the power supply line. Shield fast switching signals, AGND are advised. like clocks, with digital ground to prevent radiating noise to The digital filter also removes noise from the analog and other sections of the board, and never run clock signals near the reference inputs provided that these noise sources do not analog inputs. Avoid crossover of digital and analog signals. saturate the analog modulator. As a result, the AD7194 is Run traces on opposite sides of the board at right angles to each more immune to noise interference than a conventional high other. This reduces the effects of feedthrough through the resolution converter. However, because the resolution of the board. A microstrip technique is by far the best, but is not AD7194 is so high and the noise levels from the converter so always possible with a double-sided board. In this technique, low, care must be taken with regard to grounding and layout. the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side. The printed circuit board (PCB) that houses the ADC must be designed so that the analog and digital sections are separated Good decoupling is important when using high resolution ADCs. Decouple all analog supplies with 10 μF tantalum and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum capacitors in parallel with 0.1 μF capacitors to AGND. To etch technique is generally best for ground planes because it achieve the best results from these decoupling components, gives the best shielding. place them as close as possible to the device, ideally right up against the device. Decouple all logic chips with 0.1 μF ceramic Although the AD7194 has separate pins for analog and digital capacitors to DGND. In systems in which a common supply ground, the AGND and DGND pins are tied together internally voltage is used to drive both the AV and DV of the AD7194, DD DD via the substrate. Therefore, the user must not tie these two pins it is recommended that the system AV supply be used. For DD to separate ground planes unless the ground planes are connected this supply, place the recommended analog supply decoupling together near the AD7194. capacitors between the AVDD pin of the AD7194 and AGND In systems in which the AGND and DGND are connected and the recommended digital supply decoupling capacitor somewhere else in the system (that is, the power supply of the between the DVDD pin of the AD7194 and DGND. system), they should not be connected again at the AD7194 Rev. 0 | Page 52 of 56 AD7194 APPLICATIONS INFORMATION The AD7194 provides a low cost, high resolution analog-to- In Figure 67, temperature compensation is performed using digital function. Because the analog-to-digital function is a thermistor. In addition, the reference voltage for the temperature provided by a Σ-Δ architecture, the part is more immune to noisy measurement is derived from a precision resistor in series with environments, making it ideal for use in sensor measurement and the thermistor. This allows a ratiometric measurement so that industrial and process control applications. variation of the excitation voltage has no affect on the measurement (it is the ratio of the precision reference resistance to the thermistor FLOWMETER resistance that is measured). Figure 67 shows the AD7194 being used in a flowmeter application For simplicity, external filters are not shown in Figure 67; that consists of two pressure transducers with the rate of flow however, an R-C antialias filter must be included on each analog being equal to the pressure difference. The pressure transducers input. This is required because the on-chip digital filter does are arranged in a bridge network and give a differential output not provide any rejection around the modulator sampling voltage between its OUT+ and OUT− terminals. With rated frequency or multiples of this frequency. Suitable values are a full-scale pressure (in this case 300 mmHg) on the transducer, 100 Ω resistor in series with each analog input, a 0.1 μF capacitor the differential output voltage is 3 mV/V of the input voltage between the analog input pins, and a 0.01 μF capacitor from (that is, the voltage between the IN+ and IN− terminals). each analog input pin to AGND. Assuming a 5 V excitation voltage, the full-scale output range from the transducer is 15 mV. The excitation voltage for the bridge can be used to directly provide the reference for the ADC, as the reference input range includes the supply voltage. 5V AGND AV DV DGND DD DD REFIN1(+) REFERENCE IN+ DETECT AV AIN1 DD OUT+ OUT– AIN2 IN+ DOUT/RDY SERIAL IN– INTERFACE OUT+ MUX DIN OUT– AIN5 PGA Σ-Δ ADC AND AIN6 CONTROL SCLK LOGIC AIN7 CS IN– AIN8 SYNC AGND REFIN2(+) R REF REFIN2(–) REFIN1(–) CLOCK CIRCUITRY AD7194 MCLK1 MCLK2 Figure 67. Typical Application (Flowmeter) Rev. 0 | Page 53 of 56 08566-066 AD7194 OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 4.90 0.18 PIN 1 INDICATOR 25 32 24 1 0.50 BSC 3.65 EXPOSED PAD 3.50 SQ 3.45 8 17 16 9 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.75 0.05 MAX FUNCTION DESCRIPTIONS 0.70 SECTION OF THIS DATA SHEET. 0.02 NOM COPLANARITY 0.08 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. Figure 68. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 × 5 mm Body, Very, Very Thin Quad (CP-32-11) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD7194BCPZ −40°C to +105°C 32-Lead LFCSP_WQ CP-32-11 1 AD7194BCPZ-REEL −40°C to +105°C 32-Lead LFCSP_WQ CP-32-11 1 AD7194BCPZ-REEL7 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-11 1 Z = RoHS Compliant Part. Rev. 0 | Page 54 of 56 PIN 1 INDICATOR 112408-A AD7194 NOTES Rev. 0 | Page 55 of 56 AD7194 NOTES ©2009 Analo ©2009 Analog g Devi Devices, Inc. All rights ces, Inc. All rights reserve reserved d. Tra . Trad dem emar arks and ks and registered tra registered trad demar emarks are the prop ks are the property erty of their respective o of their respective owners. wners. D08566-0-10/09(0) Rev. 0 | Page 56 of 56