ANALOG DEVICES AD7193

4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA Data Sheet AD7193 FEATURES Pressure measurement Temperature measurement Fast settling filter option Flow measurement 4 differential/8 pseudo differential input channels Weigh scales RMS noise: 11 nV @ 4.7 Hz (gain = 128) Chromatography 15.5 noise-free bits @ 2.4 kHz (gain = 128) Medical and scientific instrumentation Up to 22 noise-free bits (gain = 1) Offset drift: ±5 nV/°C GENERAL DESCRIPTION Gain drift: ±1 ppm/°C The AD7193 is a low noise, complete analog front end for high Specified drift over time precision measurement applications. It contains a low noise, Automatic channel sequencer 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). Programmable gain (1 to 128) The on-chip low noise gain stage means that signals of small Output data rate: 4.7 Hz to 4.8 kHz amplitude can interface directly to the ADC. Internal or external clock The device can be configured to have four differential inputs or Simultaneous 50 Hz/60 Hz rejection eight pseudo differential inputs. The on-chip channel sequencer 4 general-purpose digital outputs allows several channels to be enabled simultaneously, and the Power supply AD7193 sequentially converts on each enabled channel, simplifying AV : 3 V to 5.25 V DD DV : 2.7 V to 5.25 V communication with the part. The on-chip 4.92 MHz clock can DD Current: 4.65 mA be used as the clock source to the ADC or, alternatively, an external Temperature range: −40°C to +105°C clock or crystal can be used. The output data rate from the part 28-lead TSSOP and 32-lead LFCSP packages can be varied from 4.7 Hz to 4.8 kHz. Interface The device has a very flexible digital filter, including a fast 3-wire serial settling option. Variables such as output data rate and settling SPI, QSPI™, MICROWIRE™, and DSP compatible time are dependent on the option selected. The AD7193 also Schmitt trigger on SCLK includes a zero latency option. APPLICATIONS The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 4.65 mA, and it is available in a 28-lead PLC/DCS analog input modules TSSOP package and a 32-lead LFCSP package. Data acquisition Strain gage transducers FUNCTIONAL BLOCK DIAGRAM AV AGND DV DGND REFIN1(+) REFIN1(–) DD DD AD7193 AIN1 AIN2 AIN3 DOUT/RDY AIN4 SERIAL AIN5 INTERFACE MUX DIN Σ-Δ PGA AND AIN6 ADC CONTROL SCLK AIN7 LOGIC AIN8 CS AINCOM SYNC TEMP P3 SENSOR P2 BPDSW CLOCK CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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All rights reserved. 08367-001 AD7193 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Reference ..................................................................................... 32 Applications ....................................................................................... 1 Reference Detect ......................................................................... 33 General Description ......................................................................... 1 Bipolar/Unipolar Configuration .............................................. 33 Functional Block Diagram .............................................................. 1 Data Output Coding .................................................................. 33 Revision History ............................................................................... 3 Burnout Currents ....................................................................... 33 Specifications ..................................................................................... 4 Channel Sequencer .................................................................... 33 Timing Characteristics ................................................................ 8 Digital Interface .......................................................................... 34 Absolute Maximum Ratings .......................................................... 10 Reset ............................................................................................. 38 Thermal Resistance .................................................................... 10 System Synchronization ............................................................ 38 ESD Caution ................................................................................ 10 Enable Parity ............................................................................... 38 Pin Configurations and Function Descriptions ......................... 11 Clock ............................................................................................ 38 Typical Performance Characteristics ........................................... 15 Bridge Power-Down Switch ...................................................... 38 RMS Noise and Resolution............................................................ 18 Temperature Sensor ................................................................... 39 4 Sinc Chop Disabled ................................................................... 18 Logic Outputs ............................................................................. 39 3 Sinc Chop Disabled ................................................................... 19 Calibration................................................................................... 39 Fast Settling ................................................................................. 20 Digital Filter .................................................................................... 41 4 On-Chip Registers .......................................................................... 21 Sinc Filter (Chop Disabled) ..................................................... 41 3 Communications Register ......................................................... 22 Sinc Filter (Chop Disabled) ..................................................... 43 4 Status Register ............................................................................. 23 Chop Enabled (Sinc Filter) ...................................................... 45 3 Mode Register ............................................................................. 24 Chop Enabled (Sinc Filter) ...................................................... 47 4 Configuration Register .............................................................. 27 Fast Settling Mode (Sinc Filter) ............................................... 48 3 Data Register ............................................................................... 29 Fast Settling Mode (Sinc Filter) ............................................... 50 ID Register ................................................................................... 29 Fast Settling Mode (Chop Enabled) ......................................... 51 GPOCON Register ..................................................................... 29 Summary of Filter Options ....................................................... 52 Offset Register ............................................................................. 30 Grounding and Layout .................................................................. 53 Full-Scale Register ...................................................................... 30 Applications Information .............................................................. 54 ADC Circuit Information .............................................................. 31 Flowmeter .................................................................................... 54 Overview ...................................................................................... 31 Outline Dimensions ....................................................................... 55 Analog Input Channel ............................................................... 32 Ordering Guide .......................................................................... 55 Programmable Gain Array (PGA) ........................................... 32 Rev. C | Page 2 of 56 Data Sheet AD7193 REVISION HISTORY 12/11—Rev. B to Rev. C Changes to Table 6 .......................................................................... 17 Moved Revision History Section ..................................................... 3 Changes to Table 9 .......................................................................... 18 Changes to Table 6 .......................................................................... 13 Changes to Table 12, Table 13, and Table 14 ............................... 19 4/10—Rev. A to Rev. B Changes to Table 19 ........................................................................ 24 Added 32-Lead LFCSP ...................................................... Universal Changes to Table 22 and Table 23 ................................................. 27 Changes to Offset Register and Full-Scale Register Sections .... 29 Changes to Table 7 .......................................................................... 17 Changes to Communications Register, Table 16 ......................... 20 Changes to Reference Section ....................................................... 31 Updated Outline Dimensions ........................................................ 54 Changes to Data Output Coding Section .................................... 32 4 Changes to Ordering Guide ........................................................... 54 Changes to Sinc 50 Hz/60 Hz Rejection Section ....................... 41 3 9/09—Rev. 0 to Rev. A Changes to Sinc 50 Hz/60 Hz Rejection Section ....................... 43 4 Changes to Internal/External Clock, Internal Clock Frequency Changes to 50 Hz/60 Hz Rejection, Sinc Filter Section ............ 47 Parameter, Table 1 ............................................................................. 5 Changes to Summary of Filter Options Section and Table 35 .. 52 Changes to Figure 7 and Figure 8 .................................................. 14 7/09—Revision 0: Initial Version Rev. C | Page 3 of 56 AD7193 Data Sheet SPECIFICATIONS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = 2.5 V or AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter Min Typ Max Unit Test Conditions/Comments ADC Output Data Rate 4.7 4800 Hz Chop disabled 4 1.17 1200 Hz Chop enabled, sinc filter 3 1.56 1600 Hz Chop enabled, sinc filter 2 3 4 No Missing Codes 24 Bits FS[9:0] > 1, sinc filter 3 3 24 Bits FS[9:0] > 4, sinc filter Resolution See the RMS Noise and Resolution section RMS Noise and Output See the RMS Noise and Resolution section Data Rates Integral Nonlinearity 2 Gain = 1 ±2 ±10 ppm of FSR AVDD = 5 V ±2 ±15 ppm of FSR AVDD = 3 V Gain > 1 ±5 ±30 ppm of FSR AV = 5 V DD ±15 ±30 ppm of FSR AV = 3 V DD 4, 5 Offset Error ±150/gain µV Chop disabled ±1 µV Chop enabled, AV = 5 V DD ±0.5 µV Chop enabled, AV = 3 V DD Offset Error Drift vs. ±150/gain nV/°C Gain = 1 to 16; chop disabled Temperature ±5 nV/°C Gain = 32 to 128; chop disabled ±5 nV/°C Chop enabled Offset Error Drift vs. Time 25 nV/1000 Gain > 32 hours 4 AV = 5 V, gain = 1, T = 25°C Gain Error ±0.001 % DD A (factory calibration conditions) −0.39 % Gain = 128, before full-scale calibration (see Table 27) ±0.003 % Gain > 1, after internal full-scale calibration, AVDD ≥ 4.75 V ±0.005 % Gain > 1, after internal full-scale calibration, AVDD < 4.75 V Gain Drift vs. ±1 ppm/°C Temperature Gain Drift vs. Time 10 ppm/ Gain = 1 1000 hours Power Supply Rejection 90 dB Gain = 1, V = 1 V IN 95 110 dB Gain > 1, V = 1 V/gain IN Common-Mode Rejection @ DC 110 dB Gain = 1, V = 1 V IN @ DC 105 dB Gain > 1, V = 1 V/gain IN 2 @ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 2 @ 50 Hz 120 dB 50 Hz output data rate, 50 Hz ± 1 Hz 2 @ 60 Hz 120 dB 60 Hz output data rate, 60 Hz ± 1 Hz 3 2 Fast settling, FS[9:0] = 6, average by 16, @ 50 Hz 115 dB 50 Hz ± 1 Hz 3 2 Fast settling, FS[9:0] = 5, average by 16, @ 60 Hz 115 dB 60 Hz ± 1 Hz Rev. C | Page 4 of 56 Data Sheet AD7193 1 Parameter Min Typ Max Unit Test Conditions/Comments 2 Normal-Mode Rejection 4 Sinc Filter Internal Clock @ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 6 74 dB 50 Hz output data rate, REJ60 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz 96 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 97 dB 60 Hz output data rate, 60 Hz ± 1 Hz External Clock @ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 6 82 dB 50 Hz output data rate, REJ60 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz 120 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 120 dB 60 Hz output data rate, 60 Hz ± 1 Hz 3 Sinc Filter Internal Clock 10 Hz output data rate, 50 Hz ± 1 Hz, @ 50 Hz, 60 Hz 75 dB 60 Hz ± 1 Hz 6 50 Hz output data rate, REJ60 = 1, 60 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz 70 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 70 dB 60 Hz output data rate, 60 Hz ± 1 Hz External Clock @ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 6 @ 50 Hz 67 dB 50 Hz output data rate, REJ60 = 1, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz 95 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 95 dB 60 Hz output data rate, 60 Hz ± 1 Hz Fast Settling Internal Clock 3 @ 50 Hz 26 dB FS[9:0] = 6, average by 16, 50 Hz ± 0.5 Hz 3 @ 60 Hz 26 dB FS[9:0] = 5, average by 16, 60 Hz ± 0.5 Hz External Clock 3 @ 50 Hz 40 dB FS[9:0] = 6, average by 16, 50 Hz ± 0.5 Hz 3 @ 60 Hz 40 dB FS[9:0] = 5, average by 16, 60 Hz ± 0.5 Hz ANALOG INPUTS Differential Input ±V /gain V V = REFINx(+) − REFINx(−), gain = 1 to 128 REF REF Voltage Ranges −(AV − 1.25 V)/gain +(AV − 1.25 V)/gain V Gain > 1 DD DD Absolute AIN Voltage 2 Limits Unbuffered Mode AGND − 0.05 AV + 0.05 V DD Buffered Mode AGND + 0.25 AV − 0.25 V DD Analog Input Current Buffered Mode 2 Input Current −2 +2 nA Gain = 1 −3 +3 nA Gain > 1 Input Current Drift ±5 pA/°C Unbuffered Mode Gain = 1, input current varies with input Input Current ±3.5 µA/V voltage ±1 µA/V Gain > 1 Input Current Drift ±0.05 nA/V/°C External clock ±1.6 nA/V/°C Internal clock Rev. C | Page 5 of 56 AD7193 Data Sheet 1 Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUT REFIN Voltage 1 AVDD V REFIN = REFINx(+) − REFINx(−), the differential input must be limited to ±(AVDD − 1.25 V)/gain when gain > 1 Absolute REFIN Voltage AGND − 0.05 AVDD + 0.05 V 2 Limits Average Reference Input 4.5 µA/V Current Average Reference Input ±0.03 nA/V/°C External clock Current Drift ±1.3 nA/V/°C Internal clock 2 Normal Mode Rejection Same as for analog inputs Common-Mode 100 dB Rejection Reference Detect Levels 0.3 0.6 V TEMPERATURE SENSOR Accuracy ±2 °C Applies after user calibration at 25°C Sensitivity 2815 Codes/°C Bipolar mode BRIDGE POWER-DOWN SWITCH RON 10 Ω 2 Allowable Current 30 mA Continuous current BURNOUT CURRENTS AIN Current 500 nA Analog inputs must be buffered and chop disabled DIGITAL OUTPUTS (P0 to P3) Output High Voltage, VOH AVDD − 0.6 V AVDD = 3 V, ISOURCE = 100 μA 4 V AVDD = 5 V, ISOURCE = 200 μA Output Low Voltage, V 0.4 V AV = 3 V, I = 100 μA OL DD SINK 0.4 V AV = 5 V, I = 800 μA DD SINK Floating-State Leakage −100 +100 nA 2 Current Floating-State Output 10 pF Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency 4.72 4.92 5.12 MHz Duty Cycle 50:50 % External Clock/Crystal Frequency 2.4576 4.9152 5.12 MHz Input Low Voltage, V 0.8 V DV = 5 V INL DD 0.4 V DV = 3 V DD Input High Voltage, V 2.5 V DV = 3 V INH DD 3.5 V DV = 5 V DD Input Current −10 +10 µA LOGIC INPUTS 2 Input High Voltage, VINH 2 V 2 Input Low Voltage, VINL 0.8 V 2 Hysteresis 0.1 0.25 V Input Currents −10 +10 µA LOGIC OUTPUT (DOUT/RDY) 2 Output High Voltage, VOH DVDD − 0.6 V DVDD = 3 V, ISOURCE = 100 µA 4 V DVDD = 5 V, ISOURCE = 200 µA 2 Output Low Voltage, VOL 0.4 V DVDD = 3 V, ISINK = 100 µA 0.4 V DVDD = 5 V, ISINK = 1.6 mA Floating-State Leakage −10 +10 µA Current Floating-State Output 10 pF Capacitance Data Output Coding Offset binary Rev. C | Page 6 of 56 Data Sheet AD7193 1 Parameter Min Typ Max Unit Test Conditions/Comments 2 SYSTEM CALIBRATION Full-Scale Calibration Limit 1.05 × FS V Zero-Scale Calibration −1.05 × FS V Limit Input Span 0.8 × FS 2.1 × FS V 7 POWER REQUIREMENTS Power Supply Voltage AV − AGND 3 5.25 V DD DV − DGND 2.7 5.25 V DD Power Supply Currents AIDD Current 0.85 1 mA Gain = 1, buffer off 1 1.25 mA Gain = 1, buffer on 2.8 3.6 mA Gain = 8, buffer off 3.2 3.9 mA Gain = 8, buffer on 3.8 4.7 mA Gain = 16 to 128, buffer off 4.3 5.3 mA Gain = 16 to 128, buffer on DIDD Current 0.35 0.4 mA DVDD = 3 V 0.5 0.6 mA DVDD = 5 V 1.5 mA External crystal used I 3 µA Power-down mode DD 1 Temperature range: −40°C to +105°C. 2 Specification is not production tested but is supported by characterization data at initial product release. 3 FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full- scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5 The analog inputs are configured for differential mode. 6 REJ60 is a bit in the mode register. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz/60 Hz rejection. 7 Digital inputs equal to DV or DGND. DD Rev. C | Page 7 of 56 AD7193 Data Sheet TIMING CHARACTERISTICS AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2. 1, 2 Parameter Limit at TMIN, TMAX (B Version) Unit Conditions/Comments READ AND WRITE OPERATIONS t3 100 ns min SCLK high pulse width t4 100 ns min SCLK low pulse width READ OPERATION t1 0 ns min CS falling edge to DOUT/RDY active time 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DV = 2.7 V to 3.6 V DD 3 4 t 0 ns min SCLK active edge to data valid delay 2 60 ns max DV = 4.75 V to 5.25 V DD 80 ns max DVDD = 2.7 V to 3.6 V 5, 6 t5 10 ns min Bus relinquish time after CS inactive edge 80 ns max t 0 ns min SCLK inactive edge to CS inactive edge 6 t 10 ns min SCLK inactive edge to DOUT/RDY high 7 WRITE OPERATION 4 t 0 ns min CS falling edge to SCLK active edge setup time 8 t 30 ns min Data valid to SCLK edge setup time 9 t10 25 ns min Data valid to SCLK edge hold time t11 0 ns min CS rising edge to SCLK edge hold time 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V or V limits. OL OH 4 The SCLK active edge is the falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. Circuit and Timing Diagrams I (1.6mA WITH DV = 5V, SINK DD 100µA WITH DV = 3V) DD TO OUTPUT 1.6V PIN 50pF I (200µA WITH DV = 5V, SOURCE DD 100µA WITH DV = 3V) DD Figure 2. Load Circuit for Timing Characterization Rev. C | Page 8 of 56 08367-002 Data Sheet AD7193 CS (I) t 6 t 1 t 5 MSB LSB DOUT/RDY (O) t 7 t 2 t 3 SCLK (I) t 4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t t 11 8 SCLK (I) t 9 t 10 DIN (I) MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. C | Page 9 of 56 08367-004 08367-003 AD7193 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA Table 3. soldered in a circuit board for the surface-mount packages. Parameter Rating AV to AGND −0.3 V to +6.5 V DD Table 4. Thermal Resistance DVDD to AGND −0.3 V to +6.5 V Package Type θ θ Unit JA JC AGND to DGND −0.3 V to +0.3 V 28-Lead TSSOP 97.9 14 °C/W Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V 32-Lead LFCSP 32.5 32.71 °C/W Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND −0.3 V to DV + 0.3 V DD ESD CAUTION Digital Output Voltage to DGND −0.3 V to DV + 0.3 V DD AINx/Digital Input Current 10 mA Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature, Soldering Reflow 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 10 of 56 Data Sheet AD7193 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS MCLK1 1 28 DIN MCLK2 2 27 DOUT/RDY SCLK 3 26 SYNC CS 4 25 DV DD P3 5 24 AV DD 6 23 DGND P2 AD7193 7 22 P1/REFIN2(+) AGND TOP VIEW 8 21 P0/REFIN2(–) BPDSW (Not to Scale) 20 NC 9 REFIN1(–) 10 19 AINCOM REFIN1(+) 11 18 AIN1 AIN8 12 AIN2 17 AIN7 AIN3 13 16 AIN6 AIN4 14 15 AIN5 NC = NO CONNECT Figure 5. 28-lead TSSOP Pin Configuration Table 5. 28-lead TSSOP Pin Function Descriptions Pin No. Mnemonic Description 1 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. 2 MCLK2 Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected. 3 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data. 4 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 5 P3 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AV and DD AGND. 6 P2 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. 7 P1/REFIN2(+) Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced between AV and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as DD REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. 8 P0/REFIN2(−) Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced between AV and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as DD REFIN2(−). This reference input can lie anywhere between AGND and AV − 1 V. DD 9 NC No Connect. Tie this pin to AGND. 10 AINCOM Analog Input AIN1 to Analog Input AIN8 are referenced to this input when configured for pseudo differential operation. 11 AIN1 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN2 or as a pseudo differential input when used with AINCOM. 12 AIN2 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN1 or as a pseudo differential input when used with AINCOM. 13 AIN3 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudo differential input when used with AINCOM. Rev. C | Page 11 of 56 08367-005 AD7193 Data Sheet Pin No. Mnemonic Description 14 AIN4 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudo differential input when used with AINCOM. 15 AIN5 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN6 or as a pseudo differential input when used with AINCOM. 16 AIN6 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN5 or as a pseudo differential input when used with AINCOM. 17 AIN7 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN8 or as a pseudo differential input when used with AINCOM. 18 AIN8 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN7 or as a pseudo differential input when used with AINCOM. 19 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. 20 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. 21 BPDSW Bridge Power-Down Switch to AGND. 22 AGND Analog Ground Reference Point. 23 DGND Digital Ground Reference Point. 24 AVDD Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with AVDD at 5 V or vice versa. 25 DV Digital Supply Voltage, 2.7 V to 5.25 V. DV is independent of AV . Therefore, AV can be operated at 3 V DD DD DD DD with DV at 5 V or vice versa. DD 26 SYNC Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7193 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DVDD. 27 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. 28 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register. Rev. C | Page 12 of 56 Data Sheet AD7193 P3 1 24 DV DD 2 23 AV P2 DD P1/REFIN2(+) 3 22 DGND AD7193 P0/REFIN2(–) 4 21 AGND TOP VIEW NC 5 20 BPDSW (Not to Scale) NC 6 19 NC NC 7 18 REFIN1(–) AINCOM 8 17 REFIN1(+) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO AGND. Figure 6. 32-Lead LFCSP Pin Configuration Table 6. 32-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1 P3 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. 2 P2 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AV and DD AGND. 3 P1/REFIN2(+) Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AVDD, but the part functions with a reference from 1 V to AV . DD 4 P0/REFIN2(−) Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced between AV and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as DD REFIN2(−). This reference input can lie anywhere between AGND and AVDD − 1 V. 5, 6, 7, 19, NC No Connect. Tie these pins to AGND. 26 8 AINCOM Analog Input AIN1 to Analog Input AIN8 are referenced to this input when configured for pseudo differential operation. 9 AIN1 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN2 or as a pseudo differential input when used with AINCOM. 10 AIN2 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN1 or as a pseudo differential input when used with AINCOM. 11 AIN3 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudo differential input when used with AINCOM. 12 AIN4 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudo differential input when used with AINCOM. 13 AIN5 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN6 or as a pseudo differential input when used with AINCOM. 14 AIN6 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN5 or as a pseudo differential input when used with AINCOM. 15 AIN7 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN8 or as a pseudo differential input when used with AINCOM. 16 AIN8 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN7 or as a pseudo differential input when used with AINCOM. 17 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. 18 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. 20 BPDSW Bridge Power-Down Switch to AGND. Rev. C | Page 13 of 56 AIN1 9 32 CS AIN2 10 31 SCLK AIN3 11 30 MCLK2 AIN4 MCLK1 12 29 AIN5 13 28 DIN AIN6 14 27 DOUT/RDY AIN7 15 26 NC AIN8 16 25 SYNC 08367-065 AD7193 Data Sheet Pin No. Mnemonic Description 21 AGND Analog Ground Reference Point. 22 DGND Digital Ground Reference Point. 23 AVDD Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with AV at 5 V or vice versa. DD 24 DV Digital Supply Voltage, 2.7 V to 5.25 V. DV is independent of AV . Therefore, AV can be operated at 3 V DD DD DD DD with DVDD at 5 V or vice versa. 25 SYNC Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7193 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DV . DD 27 DOUT/ Serial Data Output/Data Ready Output. DOUT/ serves a dual purpose. It functions as a serial data output RDY RDY pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. 28 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register. 29 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. 30 MCLK2 Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected. 31 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data. 32 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. EPAD The exposed pad must be connected to AGND. Rev. C | Page 14 of 56 Data Sheet AD7193 TYPICAL PERFORMANCE CHARACTERISTICS 8,387,486 50 8,387,484 40 8,387,482 8,387,480 30 8,387,478 8,387,476 20 8,387,474 8,387,472 10 8,387,470 8,387,468 0 0 200 400 600 800 1000 8,388,830 8,388,860 8,388,890 8,388,920 SAMPLE CODE Figure 10. Noise Distribution Histogram (V = AV = 5 V, Figure 7. Noise (VREF = AVDD = 5 V, Output Data Rate = 4.7 Hz, REF DD 4 4 Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc Filter) Gain = 128, Chop Disabled, Sinc Filter) 200 8,388,880 8,388,878 8,388,876 150 8,388,874 8,388,872 100 8,388,870 8,388,868 50 8,388,866 8,388,864 0 0 200 400 600 800 1000 8,387,470 8,387,474 8,387,478 8,387,482 8,387,472 8,387,476 8,387,480 8,387,484 SAMPLE CODE Figure 8. Noise Distribution Histogram (VREF = AVDD = 5 V, Figure 11. Noise (VREF = AVDD = 5 V, Output Data Rate = 42.1 Hz (FS[9:0] = 6, 4 4 Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc Filter) Average by 16), Gain = 1, Chop Disabled, Sinc Filter) 8,388,920 200 8,388,910 8,388,900 150 8,388,890 8,388,880 100 8,388,870 8,388,860 50 8,388,850 8,388,840 8,388,830 0 8,388,864 8,388,868 8,388,872 8,388,876 8,388,880 0 200 400 600 800 1000 CODE SAMPLE Figure 9. Noise (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Figure 12. Noise Distribution Histogram (V = AV = 5 V, Output Data Rate = REF DD 4 4 Gain = 1, Chop Disabled, Sinc Filter) 42.1 Hz (FS[9:0] = 6, Average by 16), Gain = 1, Chop Disabled, Sinc Filter) Rev. C | Page 15 of 56 CODE CODE OCCURRENCE 08367-007 08367-008 08367-006 CODE OCCURRENCE OCCURRENCE 08367-011 08367-009 08367-010 AD7193 Data Sheet 5 0.4 0.2 4 0 3 –0.2 2 –0.4 –0.6 1 –0.8 0 –1.0 –1 –1.2 –2 –1.4 –4 –3 –2 –1 0 1 2 3 4 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) V (V) IN Figure 13. INL (Gain = 1) Figure 16. Offset vs. Temperature (Gain = 128, Chop Disabled) 20 1.000008 1.000006 15 1.000004 10 1.000002 5 1.000000 0.999998 0 0.999996 –5 0.999994 –10 0.999992 –15 0.999990 –20 0.999988 –60 –40 –20 0 20 40 60 80 100 120 –0.03 –0.02 –0.01 0 0.01 0.02 0.03 V (V) TEMPERATURE (°C) IN Figure 14. INL (Gain = 128) Figure 17. Gain vs. Temperature (Gain = 1) 170 128.004 168 128.002 166 128.000 164 127.998 162 127.996 160 127.994 158 127.992 156 127.990 154 127.988 –60 –40 –20 0 20 40 60 80 100 120 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Offset vs. Temperature (Gain = 1, Chop Disabled) Figure 18. Gain vs. Temperature (Gain = 128) Rev. C | Page 16 of 56 INL (ppm of FSR) OFFSET (µV) INL (ppm of FSR) 08367-012 08367-014 08367-013 GAIN GAIN OFFSET (µV) 08367-015 08367-017 08367-016 Data Sheet AD7193 24 23 GAIN = 1 GAIN = 1 GAIN = 8 GAIN = 8 GAIN = 16 GAIN = 16 22 GAIN = 32 GAIN = 32 22 GAIN = 64 GAIN = 64 GAIN = 128 GAIN = 128 21 20 20 19 18 18 16 17 16 14 1 10 100 1k 1 10 100 1k 10k OUTPUT DATA RATE (Hz) OUTPUT DATA RATE (Hz) 4 Figure 21. Noise Free Resolution in Fast Settling Mode Figure 19. Noise Free Resolution (Sinc Filter, Chop Disabled, VREF = 5 V) 4 (V = 5 V, Averaging by 16, Sinc Filter, Chop Disabled) REF 24 GAIN = 1 GAIN = 8 GAIN = 16 22 GAIN = 32 GAIN = 64 GAIN = 128 20 18 16 14 12 10 1 10 100 1k 10k OUTPUT DATA RATE (Hz) 3 Figure 20. Noise Free Resolution (Sinc Filter, Chop Disabled, VREF = 5 V) Rev. C | Page 17 of 56 NOISE FREE RESOLUTION (Bits) NOISE FREE RESOLUTION (Bits) 08367-019 08367-018 NOISE FREE RESOLUTION (Bits) 08367-022 AD7193 Data Sheet RMS NOISE AND RESOLUTION The following tables show the rms noise, peak-to-peak noise, is continuously converting on a single channel. It is important effective resolution, and noise free (peak-to-peak) resolution of to note that the effective resolution is calculated using the rms the AD7193 for various output data rates and gain settings with noise, whereas the peak-to-peak resolution is calculated based 4 3 chop disabled for the sinc and sinc filters and for fast settling on peak-to-peak noise. The peak-to-peak resolution represents mode. The numbers given are for the bipolar input range with the resolution for which there is no code flicker. With chop an external 5 V reference. These numbers are typical and are enabled, the resolution improves by 0.5 bits. generated with a differential input voltage of 0 V when the ADC 4 SINC CHOP DISABLED Table 7. RMS Noise (nV) vs. Gain and Output Data Rate Gain of Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1 8 16 32 64 128 1023 4.7 852.5 340 53 34 18 12 11 640 7.5 533 410 67 40 24 14 13 480 10 400 460 76 45 28 16 15 96 50 80 950 150 80 50 37 31 80 60 66.7 1000 160 90 54 40 35 32 150 26.7 1600 250 140 83 63 55 16 300 13.3 2300 340 190 120 90 79 5 960 4.17 4200 610 350 210 160 140 2 2400 1.67 7100 1000 570 350 260 230 1 4800 0.83 26,000 3400 1700 910 530 380 Table 8. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Gain of Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1 8 16 32 64 128 1023 4.7 852.5 2200 340 190 110 70 65 640 7.5 533 2700 410 230 130 90 85 480 10 400 3000 450 260 150 100 95 96 50 80 6000 890 500 320 230 200 80 60 66.7 6600 1000 560 350 250 220 32 150 26.7 10,000 1500 920 540 400 370 16 300 13.3 14,000 2200 1300 800 600 530 5 960 4.17 28,000 4100 2400 1400 1000 900 2 2400 1.67 49,000 7000 3800 2400 1800 1700 1 4800 0.83 175,000 23,000 12,000 6100 3500 2600 Table 9. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate 1 Gain of Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1 8 16 32 64 128 1023 4.7 852.5 24 (22.1) 24 (21.8) 24 (21.6) 24 (21.4) 23.6 (21.1) 22.8 (20.2) 640 7.5 533 24 (21.8) 24 (21.5) 23.9 (21.4) 23.6 (21.2) 23.4 (20.7) 22.5 (19.8) 480 10 400 24 (21.7) 24 (21.4) 23.7 (21.2) 23.4 (21) 23.2 (20.6) 22.3 (19.6) 96 50 80 23.3 (20.7) 23 (20.4) 22.9 (20.3) 22.6 (19.9) 22 (19.4) 21.3 (18.6) 80 60 66.7 23.3 (20.5) 22.9 (20.3) 22.8 (20.1) 22.5 (19.8) 21.9 (19.3) 21.1 (18.4) 32 150 26.7 22.6 (19.9) 22.3 (19.7) 22.1 (19.4) 21.8 (19.1) 21.2 (18.6) 20.4 (17.7) 16 300 13.3 22.1 (19.4) 21.8 (19.1) 21.6 (18.9) 21.3 (18.6) 20.7 (18) 19.9 (17.2) 5 960 4.17 21.2 (18.4) 21 (18.2) 20.8 (18) 20.5 (17.8) 19.9 (17.3) 19.1 (16.4) 2 2400 1.67 20.4 (17.6) 20.3 (17.4) 20.1 (17.3) 19.8 (17) 19.2 (16.4) 18.4 (15.5) 1 4800 0.83 18.6 (15.8) 18.5 (15.7) 18.5 (15.7) 18.4 (15.6) 18.2 (15.4) 17.6 (14.9) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. C | Page 18 of 56 Data Sheet AD7193 3 SINC CHOP DISABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Gain of Output Data Settling Filter Word (Decimal) Rate (Hz) Time (ms) 1 8 16 32 64 128 1023 4.7 639.4 340 58 35 20 13 11 640 7.5 400 410 72 41 25 16 14 480 10 300 490 90 45 28 18 16 96 50 60 1000 160 85 54 38 34 80 60 50 1100 170 95 59 41 37 32 150 20 1700 260 150 88 66 59 16 300 10 2400 350 200 130 94 85 5 960 3.13 6400 870 470 270 190 160 2 2400 1.25 115,000 14,000 7000 3600 1800 950 1 4800 0.625 860,000 110,000 54,000 27,000 14,000 7000 Table 11. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Gain of Output Data Settling Filter Word (Decimal) Rate (Hz) Time (ms) 1 8 16 32 64 128 1023 4.7 639.4 2200 350 220 130 80 65 640 7.5 400 2700 450 270 160 100 88 480 10 300 3000 520 310 180 120 100 96 50 60 6400 990 540 370 250 230 80 60 50 7000 1100 610 390 270 250 32 150 20 11,000 1700 980 580 440 390 16 300 10 16,000 2300 1400 860 630 560 5 960 3.13 40,000 5700 3100 1800 1300 1100 2 2400 1.25 730,000 93,000 47,000 24,000 12,000 6100 1 4800 0.625 5,700,000 730,000 360,000 180,000 93,000 45,000 Table 12. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate 1 Gain of Output Data Settling Filter Word (Decimal) Rate (Hz) Time (ms) 1 8 16 32 64 128 1023 4.7 639.4 24 (22.1) 24 (21.8) 24 (21.4) 23.9 (21.2) 23.5 (20.9) 22.8 (20.2) 640 7.5 400 24 (21.8) 24 (21.4) 23.9 (21.1) 23.6 (20.9) 23.2 (20.6) 22.4 (19.8) 480 10 300 24 (21.7) 23.8 (21.2) 23.7 (20.9) 23.4 (20.7) 23 (20.3) 22.2 (19.6) 96 50 60 23.3 (20.6) 22.9 (20.3) 22.9 (20.1) 22.5 (19.7) 22 (19.3) 21.1 (18.4) 80 60 50 23.1 (20.4) 22.8 (20.1) 22.7 (20) 22.3 (19.6) 21.9 (19.1) 21 (18.3) 32 150 20 22.5 (19.8) 22.2 (19.5) 22 (19.3) 21.8 (19) 21.2 (18.4) 20.3 (17.6) 16 300 10 22 (19.3) 21.8 (19.1) 21.6 (18.8) 21.2 (18.5) 20.7 (17.9) 19.8 (17.1) 5 960 3.13 20.6 (17.9) 20.5 (17.7) 20.3 (17.6) 20.1 (17.4) 19.6 (16.9) 18.9 (16.1) 2 2400 1.25 16.5 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.6) 1 4800 0.625 13.5 (10.8) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. C | Page 19 of 56 AD7193 Data Sheet FAST SETTLING Table 13. RMS Noise (nV) vs. Gain and Output Data Rate Gain of Filter Word Output Data Settling (Decimal) Average Rate (Hz) Time (ms) 1 8 16 32 64 128 96 16 2.63 380 380 87 52 33 15 11 30 16 8.4 118.75 620 140 71 43 30 21 6 16 42.10 23.75 1300 270 150 82 56 47 5 16 50.53 19.79 1500 280 160 88 61 50 2 16 126.32 7.92 2300 380 210 130 88 77 1 16 252.63 3.96 3400 520 290 180 130 110 Table 14. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Gain of Filter Word Output Data Settling (Decimal) Average Rate (Hz) Time (ms) 1 8 16 32 64 128 96 16 2.63 380 2500 450 260 180 100 70 30 16 8.4 118.75 4000 900 470 280 190 130 6 16 42.10 23.75 8500 1800 950 540 360 300 5 16 50.53 19.79 9500 1900 1000 580 390 330 2 16 126.32 7.92 14,000 2800 1500 850 580 510 1 16 252.63 3.96 22,000 3800 2000 1200 820 740 Table 15. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate 1 Gain of Filter Word Output Data Settling (Decimal) Average Rate (Hz) Time (ms) 1 8 16 32 64 128 96 16 2.63 380 24 (21.9) 23.8 (21.4) 23.5 (21.2) 23.2 (20.7) 23.2 (20.6) 22.8 (20.1) 30 16 8.4 118.75 23.9 (21.3) 23.6 (20.4) 23.1 (20.3) 22.8 (20.1) 22.3 (19.6) 21.8 (19.2) 6 16 42.10 23.75 22.9 (20.2) 22.1 (19.4) 22 (19.3) 21.9 (19.1) 21.4 (18.7) 20.7 (18) 5 16 50.53 19.79 22.7 (20) 22.1 (19.3) 21.9 (19.3) 21.8 (19) 21.3 (18.6) 20.6 (17.9) 2 16 126.32 7.92 22.1 (19.4) 21.6 (18.8) 21.5 (18.7) 21.2 (18.5) 20.8 (18) 20 (17.2) 1 16 252.63 3.96 21.5 (18.8) 21.2 (18.3) 21 (18.3) 20.7 (18) 20.2 (17.5) 19.4 (16.7) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. C | Page 20 of 56 Data Sheet AD7193 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term set implies a Logic 1 state and the term cleared implies a Logic 0 state, unless otherwise noted. Table 16. Register Summary Register Addr. Dir. Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Communications 00 W 00 WEN R/W Register address CREAD 0 0 Status 00 R 80 RDY ERR NOREF Parity CHD3 CHD2 CHD1 CHD0 Mode 01 R/W 080060 Mode select DAT_STA CLK1 CLK0 AVG1 AVG0 SINC3 0 ENPAR CLK_DIV Single REJ60 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB) Configuration 02 R/W 000117 Chop (MSB) 0 0 REFSEL 0 Pseudo Short TEMP CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Burn REFDET 0 BUF U/B G2 G1 G0 (LSB) Data 03 R 000000 D23 (MSB) D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) ID 04 R X2 X X X X 0 0 1 0 GPOCON 05 R/W 00 0 BPDSW GP32EN GP10EN P3DAT P2DAT P1DAT P0DAT Offset 06 R/W 800000 OF23 (MSB) OF22 OF21 OF20 OF19 OF18 OF17 OF16 OF15 OF14 OF13 OF12 OF11 OF10 OF9 OF8 OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 (LSB) Full Scale 07 R/W 5XXXX0 FS23 (MSB) FS22 FS21 FS20 FS19 FS18 FS17 FS16 FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB) Rev. C | Page 21 of 56 AD7193 Data Sheet a reset, the ADC is in this default state waiting for a write COMMUNICATIONS REGISTER operation to the communications register. In situations where the RS2, RS1, RS0 = 000 interface sequence is lost, a write operation of at least 40 serial The communications register is an 8-bit write-only register. All clock cycles with DIN high returns the ADC to this default state communications to the part must start with a write operation to by resetting the entire part. Table 17 outlines the bit designations the communications register. The data written to the communi- for the communications register. CR0 through CR7 indicate the cations register determine whether the next operation is a read bit location, CR denoting that the bits are in the communications or write operation and in which register this operation occurs. For register. CR7 denotes the first bit of the data stream. The number read or write operations, when the subsequent read or write oper- in parentheses indicates the power-on/reset default status of ation to the selected register is complete, the interface returns to that bit. where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN(0) R/W(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0) Table 17. Communications Register (CR) Bit Designations Bit Location Bit Name Description CR7 WEN Write enable bit. For a write to the communications register to occur, 0 must be written to this bit. If a 1 is the first bit written, the part does not clock onto subsequent bits in the register; rather, it stays at this bit location until a 0 is written to this bit. After a 0 is written to the bit, the next seven bits are loaded to WEN the communications register. Idling the DIN pin high between data transfers minimizes the effects of spurious SCLK pulses on the serial interface. CR6 R/W 0 in this bit location indicates that the next operation is a write to a specified register. 1 in this bit position indicates that the next operation is a read from the designated register. CR5 to CR3 RS2 to RS0 Register address bits. These address bits are used to select which registers of the ADC are selected during the serial interface communication (see Table 18). CR2 CREAD Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, Instruction 01011100 must be written to the communications register. To disable continuous read, Instruction 01011000 must be written to the communica- tions register while the RDY pin is low. While continuous read is enabled, the ADC monitors activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 40 consecutive 1s occur on DIN; therefore, hold DIN low until an instruction is written to the device. CR1 to CR0 0 These bits must be programmed to Logic 0 for correct operation. Table 18. Register Selection RS2 RS1 RS0 Register Register Size 0 0 0 Communications register during a write operation 8 bits 0 0 0 Status register during a read operation 8 bits 0 0 1 Mode register 24 bits 0 1 0 Configuration register 24 bits 0 1 1 Data register/data register plus status information 24 bits/32 bits 1 0 0 ID register 8 bits 1 0 1 GPOCON register 8 bits 1 1 0 Offset register 24 bits 1 1 1 Full-scale register 24 bits Rev. C | Page 22 of 56 Data Sheet AD7193 load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 19 outlines the bit STATUS REGISTER designations for the status register. SR0 through SR7 indicate the RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 bit locations, SR denoting that the bits are in the status register. The status register is an 8-bit read-only register. To access the SR7 denotes the first bit of the data stream. The number in paren- ADC status register, the user must write to the communications theses indicates the power-on/reset default status of that bit. register, select the next operation to be a read operation, and SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY(1) ERR(0) NOREF(0) Parity(0) CHD3(0) CHD2(0) CHD1(0) CHD0(0) Table 19. Status Register (SR) Bit Designations Bit Location Bit Name Description SR7 RDY Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register is read, or a period of time before the data register is updated, with a new conversion result to indicate to the user that the conversion data should not be read. It is also set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC error bit. This bit is written to at the same time as the RDY bit. This bit is set to indicate that the result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange, underrange, or the absence of a reference voltage. This bit is cleared when the result written to the data register returns to within the allowed analog input range. The ERR bit is also set during calibrations if the reference source is invalid or if the applied analog input voltages are outside range during system calibrations. SR5 NOREF No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled by setting the REFDET bit in the configuration register to 1. SR4 Parity Parity check of the data register. If the ENPAR bit in the mode register is set and there is an odd number of 1s in the data register, the parity bit is set. It is cleared if there is an even number of 1s in the data register. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. SR3 to SR0 CHD3 to CHD0 These bits indicate which channel corresponds to the data register contents. They do not indicate which channel is presently being converted but indicate which channel was selected when the conversion contained in the data register was generated. Rev. C | Page 23 of 56 AD7193 Data Sheet register. MR0 through MR23 indicate the bit locations, MR MODE REGISTER denoting that the bits are in the mode register. MR23 denotes RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060 the first bit of the data stream. The number in parentheses The mode register is a 24-bit register from which data can be indicates the power-on/reset default status of that bit. Any write read or to which data can be written. This register is used to to the mode register resets the modulator and filter and sets the select the operating mode, the output data rate, and the clock RDY bit. source. Table 20 outlines the bit designations for the mode MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16 MD2(0) MD1(0) MD0(0) DAT_STA(0) CLK1(1) CLK0(0) AVG1(0) AVG0(0) MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 SINC3(0) 0 ENPAR(0) CLK_DIV(0) Single(0) REJ60(0) FS9(0) FS8(0) MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 FS7(0) FS6(1) FS5(1) FS4(0) FS3(0) FS2(0) FS1(0) FS0(0) Table 20. Mode Register (MR) Bit Designations Bit Location Bit Name Description MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7193 (see Table 21). MR20 DAT_STA This bit enables the transmission of status register contents after each data register read. When DAT_STA is set, the contents of the status register are transmitted along with each data register read. This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds. MR19, MR18 CLK1, CLK0 These bits select the clock source for the AD7193. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7193 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7193. CLK1 CLK0 ADC Clock Source 0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2. 0 1 External clock. The external clock is applied to the MCLK2 pin. 1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated. 1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2. MR17, MR16 AVG1, AVG0 Fast settling filter. When this option is selected, the settling time equals one conversion time. In fast settling mode, a first-order average and decimate block is included after the sinc filter. The data from the sinc filter is averaged by 2, 8, or 16. The averaging reduces the output data rate for a given FS word; however, the rms noise improves. The AVG1 and AVG0 bits select the amount of averaging. Fast settling 3 mode can be used for FS words less than 512 only. When the sinc filter is selected, the FS word must be less than 256 when averaging by 16. AVG1 AVG0 Average 0 0 No averaging (fast settling mode disabled) 0 1 Average by 2 1 0 Average by 8 1 1 Average by 16 3 4 MR15 SINC3 Sinc filter select bit. When this bit is cleared, the sinc filter is used (default value). When this bit is set, 3 3 4 the sinc filter is used. The benefit of the sinc filter compared to the sinc filter is its lower settling time. 3 4 For a given output data rate, f , the sinc filter has a settling time of 3/f whereas the sinc filter has ADC ADC 4 a settling time of 4/fADC when chop is disabled. The sinc filter, due to its deeper notches, gives better 50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing 4 codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc filter gives 3 better performance than the sinc filter for rms noise and no missing codes. MR14 0 This bit must be programmed with a Logic 0 for correct operation. MR13 ENPAR Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. Rev. C | Page 24 of 56 Data Sheet AD7193 Bit Location Bit Name Description MR12 CLK_DIV Clock divide-by-2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, set this bit to 0. When performing internal full-scale calibrations, this bit must be set when AVDD is less than 4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data rate is used while performing the calibration. When AV is greater than or equal to 4.75 V, it is not compulsory to set DD the CLK_DIV bit when performing internal full-scale calibrations. MR11 Single Single cycle conversion enable bit. When this bit is set, the AD7193 settles in one conversion cycle so that it functions as a zero latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected. If the average + decimate filter is enabled, this bit (single) does not have an effect on the conversions unless chopping is also enabled. MR10 REJ60 This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/ 60 Hz rejection. MR9 to MR0 FS9 to FS0 Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter cutoff frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, they also determine the output noise and, therefore, the effective resolution of the device (see Table 7 through Table 15). When chop is disabled, fast settling mode is disabled and continuous conversion mode is selected. Output Data Rate = (MCLK/1024)/FS where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop disabled and fast settling mode disabled, the first notch frequency is equal to the output data rate when converting on a single channel. When chop is enabled (fast settling mode disabled) Output Data Rate = (MCLK/1024)/(N × FS) where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The first notch frequency of the sinc filter is equal to N × Output Data Rate The chopping introduces notches at odd integer multiples of Output Data Rate/2 Table 21. Operating Modes (MD) MD2 MD1 MD0 Mode 0 0 0 Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the commun- ications register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are available at the selected output data rate, which is dependent on filter choice. 0 0 1 Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in the data register. RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register until another conversion is performed. remains active (low) until the data is read or another conversion RDY is performed. 0 1 0 Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks continue to be provided. 0 1 1 Power-down mode. In power-down mode, all AD7193 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7193 for settling reasons. The external crystal, if selected, remains active. Rev. C | Page 25 of 56 AD7193 Data Sheet MD2 MD1 MD0 Mode 1 0 0 Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. 1 0 1 Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is recommended each time that the gain of a channel is changed to minimize the full-scale error. When AV is less than 4.75 V, the CLK_DIV bit must be set when performing the DD internal full-scale calibration. 1 1 0 System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. goes high when the calibration is initiated and RDY returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is recommended each time that the gain of a channel is changed. 1 1 1 System full-scale calibration. The user should connect the system full-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is recommended each time the gain of a channel is changed. Rev. C | Page 26 of 56 Data Sheet AD7193 Table 22 outlines the bit designations for the configuration register. CONFIGURATION REGISTER CON0 through CON23 indicate the bit locations. CON denotes RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 that the bits are in the configuration register. CON23 denotes The configuration register is a 24-bit register from which data the first bit of the data stream. The number in parentheses can be read or to which data can be written. This register is indicates the power-on/reset default status of that bit. used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel. CON23 CON22 CON21 CON20 CON19 CON18 CON17 CON16 Chop(0) 0(0) 0(0) REFSEL(0) 0(0) Pseudo(0) Short(0) TEMP(0) CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8 CH7(0) CH6(0) CH5(0) CH4(0) CH3(0) CH2(0) CH1(0) CH0(1) CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0 Burn(0) REFDET(0) 0(0) BUF(1) U/B(0) G2(1) G1(1) G0(1) Table 22. Configuration Register (CON) Bit Designations Bit Location Bit Name Description CON23 Chop Chop enable bit. When the chop bit is cleared, chop is disabled. With chop disabled, higher conversion rates are allowed. 4 For an FS word of 96 decimal and the sinc filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. When the chop bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed. However, this increases the conversion time and settling time of the ADC. 4 For example, when FS = 96 decimal and the sinc filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. CON22, CON21 0 These bits must be programmed with a Logic 0 for correct operation. CON20 REFSEL Reference select bits. The reference source for the ADC is selected using these bits. REFSEL Reference Voltage 0 External reference applied between REFIN1(+) and REFIN1(−). 1 External reference applied between the P1/REFIN2(+) and P0/REFIN2(−) pins. CON19 0 This bit must be programmed with a Logic 0 for correct operation. CON18 Pseudo Pseudo differential analog inputs. The analog inputs can be configured as differential inputs or pseudo differential analog inputs. When the pseudo bit is set to 1, the AD7193 is configured to have eight pseudo differential analog inputs. When pseudo bit is set to 0, the AD7193 is configured to have four differential analog inputs. CON17 to CON8 Short, TEMP, Channel select bits. These bits select which channels are enabled on the AD7193 (see Table 23 and Table 24). CH7 to CH0 Several channels can be selected, and the AD7193 automatically sequences them. The conversion on each channel requires the complete settling time. When performing calibrations or when accessing the calibration registers, only one channel can be selected. CON7 Burn When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When burn = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and when chop is disabled. CON6 REFDET Enables the reference detect function. When set, the NOREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference detect circuitry operates only when the ADC is active. CON5 0 This bit must be programmed with a Logic 0 for correct operation. Rev. C | Page 27 of 56 AD7193 Data Sheet Bit Location Bit Name Description CON4 BUF Enables the buffer on the analog inputs. If BUF is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. When the buffer is enabled, it requires some head- room; therefore, the voltage on any input pin must be limited to 250 mV within the power supply rails. If cleared, the analog inputs are unbuffered, lowering the power consumption of the device. With the buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AVDD. CON3 U/B Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar operation is selected. CON2 to CON0 G2 to G0 Gain select bits. These bits are written by the user to select the ADC input range as follows: G2 G1 G0 Gain ADC Input Range (5 V Reference) 0 0 0 1 ±2.5 V 0 0 1 Reserved 0 1 0 Reserved 0 1 1 8 ±312.5 mV 1 0 0 16 ±156.2 mV 1 0 1 32 ±78.125 mV 1 1 0 64 ±39.06 mV 1 1 1 128 ±19.53 mV Table 23. Channel Selection (Pseudo Bit = 0) Channel Enable Bits in the Configuration Register Channel Enabled Status Calibration Positive Negative Register Register Short TEMP CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Input AIN(+) Input AIN(−) Bits CHD[3:0] Pair 1 AIN1 AIN2 0000 0 1 AIN3 AIN4 0001 1 1 AIN5 AIN6 0010 2 1 AIN7 AIN8 0011 3 1 AIN1 AIN2 0100 0 1 AIN3 AIN4 0101 1 1 AIN5 AIN6 0110 2 1 AIN7 AIN8 0111 3 1 Temperature sensor 1000 1 AIN2 AIN2 1001 0 Table 24. Channel Selection (Pseudo Bit = 1) Channel Enable Bits in the Configuration Register Channel Enabled Status Positive Negative Register Calibration Short TEMP CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Input AIN(+) Input AIN(−) Bits CHD[3:0] Register Pair 1 AIN1 AINCOM 0000 0 1 AIN2 AINCOM 0001 1 1 AIN3 AINCOM 0010 2 1 AIN4 AINCOM 0011 3 1 AIN5 AINCOM 0100 4 1 AIN6 AINCOM 0101 4 1 AIN7 AINCOM 0110 4 1 AIN8 AINCOM 0111 4 1 Temperature sensor 1000 1 AINCOM AINCOM 1001 0 Rev. C | Page 28 of 56 Data Sheet AD7193 DATA REGISTER GPOCON REGISTER RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000 RS2, RS1, RS0 = 101; Power-On/Reset = 0x00 The conversion result from the ADC is stored in this data register. The GPOCON register is an 8-bit register from which data can This is a read-only, 24-bit register. Upon completion of a read be read or to which data can be written. This register is used to enable the general-purpose digital outputs. operation from this register, the RDY pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the Table 25 outlines the bit designations for the GPOCON register. status register are appended to each 24-bit conversion. This is GP0 through GP7 indicate the bit locations. GP denotes that the advisable when several analog input channels are enabled because bits are in the GPOCON register. GP7 denotes the first bit of the four LSBs of the status register (CHD3 to CHD0) identify the data stream. The number in parentheses indicates the the channel from which the conversion originated. power-on/reset default status of that bit. ID REGISTER RS2, RS1, RS0 = 100; Power-On/Reset = 0xX2 The identification number for the AD7193 is stored in the ID register. This is a read-only register. GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0(0) BPDSW(0) GP32EN(0) GP10EN(0) P3DAT(0) P2DAT(0) P1DAT(0) P0DAT(0) Table 25. GPOCON Register (GP) Bit Designations Bit Location Bit Name Description GP7 0 This bit must be programmed with a Logic 0 for proper operation. GP6 BPDSW Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge power-down switch. When the ADC is placed in power- down mode, the bridge power-down switch remains active. GP5 GP32EN Digital Output P3 and Digital Output P2 enable. When GP32EN is set, the P3 and P2 digital outputs are active. When GP32EN is cleared, the P3 and P2 pins are tristated, and the P3DAT and P2DAT bits are ignored. GP4 GP10EN Digital Output P1 and Digital Output P0 enable. When GP10EN is set, the P1 and P0 digital outputs are active. The P1 and P0 pins can be used as a reference input to REFIN2 when the REFSEL bit in the configuration register is set to 1. When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are ignored. GP3 P3DAT Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin. When P3DAT is high, the P3 output pin is high. When P3DAT is low, the P3 output pin is low. When the GPOCON register is read, the P3DAT bit reflects the status of the P3 pin if GP32EN is set. GP2 P2DAT Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin. When P2DAT is high, the P2 output pin is high. When P2DAT is low, the P2 output pin is low. When the GPOCON register is read, the P2DAT bit reflects the status of the P2 pin if GP32EN is set. GP1 P1DAT Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin. When P1DAT is high, the P1 output pin is high. When P1DAT is low, the P1 output pin is low. When the GPOCON register is read, the P1DAT bit reflects the status of the P1 pin if GP10EN is set. GP0 P0DAT Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin. When P0DAT is high, the P0 output pin is high. When P0DAT is low, the P0 output pin is low. When the GPOCON register is read, the P0DAT bit reflects the status of the P0 pin if GP10EN is set. Rev. C | Page 29 of 56 AD7193 Data Sheet OFFSET REGISTER FULL-SCALE REGISTER RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000) RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0 The offset register holds the offset calibration coefficient for the The full-scale register is a 24-bit register that holds the full-scale ADC. The power-on reset value of the offset register is 0x800000. calibration coefficient for the ADC. The AD7193 has five full- The AD7193 has five offset registers. In differential mode, each scale registers. In differential mode, each channel has a dedicated channel has a dedicated offset register. In pseudo differential full-scale register. In pseudo differential mode, the AIN1, AIN2, mode, Channel AIN1, Channel AIN2, Channel AIN3, and AIN3, and AIN4 channels have dedicated registers whereas the Channel AIN4 have dedicated registers whereas the remaining remaining channels share a full-scale register (see Table 23 and channels share an offset register (see Table 23 and Table 24). Table 24). Each of these registers is a 24-bit read/write register. This register The full-scale registers are read/write registers. However, when is used in conjunction with its associated full-scale register to writing to the full-scale registers, the ADC must be placed in form a register pair. The power-on reset value is automatically power-down mode or idle mode. These registers are configured overwritten if an internal or system zero-scale calibration is at power-on with factory calibrated full-scale calibration coeffi- initiated by the user. The AD7193 must be placed in power- cients, the calibration being performed at gain = 1. Therefore, down mode or idle mode when writing to the offset register. every device has different default coefficients. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or if the full-scale register is written to. Rev. C | Page 30 of 56 Data Sheet AD7193 ADC CIRCUIT INFORMATION 5V AGND AV DV DGND DD DD REFIN1(+) REFERENCE DETECT IN+ AV AIN1 DD AIN2 OUT+ OUT– AIN3 DOUT/RDY AIN4 SERIAL INTERFACE AIN5 MUX DIN MODULATOR PGA IN– AND AIN6 AND FILTER CONTROL SCLK AIN7 LOGIC CS AIN8 Σ-Δ ADC AINCOM SYNC CALIBRATION AGND TEMP P3 SENSOR REFIN1(–) P2 BPDSW CLOCK AD7193 CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) Figure 22. Basic Connection Diagram Sigma-Delta (Σ-Δ) ADC and Filter OVERVIEW The AD7193 contains a fourth-order Σ-Δ modulator followed The AD7193 is an ultralow noise ADC that incorporates a Σ-Δ by a digital filter. The device has several filter options modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals such as 4 • Sinc those in pressure transducers, weigh scales, and strain gage 3 • Sinc applications. Figure 22 shows the basic connections required • Chop enabled/disabled to operate the part. • Fast settling Analog Inputs • Zero latency The device can be configured to have four differential or eight Serial Interface pseudo differential analog inputs. The analog inputs can be The AD7193 has a 4-wire SPI interface. The on-chip registers buffered or unbuffered. are accessed via the serial interface. Multiplexer Clock The on-chip multiplexer increases the channel count of the device. The AD7193 has an internal 4.92 MHz clock. Either this clock Because the multiplexer is included on chip, any channel changes or an external clock can be used as the clock source to the AD7193. are synchronized with the conversion process. The internal clock can also be made available on a pin if a clock PGA source is required for external circuitry. The analog input signal can be amplified using the PGA. The Bridge Power-Down Switch PGA allows gains of 1, 8, 16, 32, 64, and 128. External circuitry such as strain gages or bridges can be Reference Detect powered up/down using the bridge power-down switch. The AD7193 is capable of monitoring the external reference. If Temperature Sensor the reference is not present, a flag is set in the status register of The on-chip temperature sensor monitors the die temperature. the device. Digital Outputs Burnout Currents The AD7193 has four general-purpose digital outputs. These Two 500 nA burnout currents are included on-chip to detect can be used for driving external circuitry. For example, an the presence of the external sensor. external multiplexer can be controlled by these outputs. Calibration Both internal and system calibration are included on chip; therefore, the user has the option of removing offset/gain errors internal to the AD7193 only, or removing the offset/gain errors of the complete end system. Rev. C | Page 31 of 56 08367-023 AD7193 Data Sheet The analog input range must be limited to ±(AV − 1.25 V)/gain ANALOG INPUT CHANNEL DD because the PGA requires some headroom. Therefore, if V = REF The AD7193 has four differential/eight pseudo differential analog AV = 5 V, the maximum analog input that can be applied to the DD input channels that can be buffered or unbuffered. In buffered AD7193 is 0 V to 3.75 V/gain in unipolar mode or ±3.75 V/gain mode (the BUF bit in the configuration register is set to 1), the in bipolar mode. input channel feeds into a high impedance input stage of the buffer amplifier. Therefore, the input can tolerate significant REFERENCE source impedances and is tailored for direct connection to The ADC has a fully differential input capability for the refer- external resistive type sensors such as strain gages or resistance ence channel. In addition, the user has the option of selecting temperature detectors (RTDs). one of two external reference options (REFIN1(±) or REFIN2(±)). When BUF = 0, the part operates in unbuffered mode. This The reference source for the AD7193 is selected using the REFSEL results in a higher analog input current. Note that this unbuffered bit in the configuration register. The REFIN2(±) pins are dual input path provides a dynamic load to the driving source. purpose: they can function as two general-purpose output pins Therefore, resistor/capacitor combinations on the input pins or as reference pins. When the REFSEL bit is set to 1, these pins can cause gain errors, depending on the output impedance of automatically function as reference pins. the source that is driving the ADC input. Table 26 shows the The common-mode range for these differential inputs is from allowable external resistance/capacitance values for unbuffered AGND to AVDD. The reference voltage REFIN (REFINx(+) − mode at a gain of 1 such that no gain error at the 20-bit level is REFINx(−)) is AVDD nominal, but the AD7193 is functional introduced. with reference voltages from 1 V to AVDD. In applications where the excitation (voltage or current) for the transducer on the Table 26. External RC Combination for No 20-Bit Gain Error analog input also drives the reference voltage for the part, the C (pF) R (Ω) effect of the low frequency noise in the excitation source is removed 50 1.4 k because the application is ratiometric. If the AD7193 is used in a 100 850 nonratiometric application, a low noise reference should be used. 500 300 The reference input is unbuffered; therefore, excessive RC 1000 230 source impedances introduce gain errors. RC values similar to 5000 30 those in Table 26 are recommended for the reference inputs. The absolute input voltage range in buffered mode is restricted Deriving the reference input voltage from an external resistor to a range between AGND + 250 mV and AVDD − 250 mV. Care means that the reference input sees significant external source must be taken in setting up the common-mode voltage to not impedance. External decoupling on the REFINx pins is not exceed these limits; otherwise, linearity and noise performance recommended in this type of circuit configuration. Conversely, degrade. if large decoupling capacitors are used on the reference inputs, The absolute input voltage in unbuffered mode includes the there should be no resistors in series with the reference inputs. range between AGND − 50 mV and AVDD + 50 mV. The Recommended 2.5 V reference voltage sources for the AD7193 negative absolute input voltage limit allows the possibility of include the ADR421 and ADR431, which are low noise references. monitoring small true bipolar signals with respect to AGND. These references tolerate decoupling capacitors on REFINx(+) PROGRAMMABLE GAIN ARRAY (PGA) without introducing gain errors in the system. Figure 23 shows the recommended connections between the ADR421 and the AD7193. When the gain stage is enabled, the output from the buffer is ADR421 AD7193 applied to the input of the PGA. The presence of the PGA means AVDD that signals of small amplitude can be gained within the AD7193 2 6 V V REFINx(+) and still maintain excellent noise performance. For example, when IN OUT 0.1µF 10µF 4.7µF the gain is set to 128, the rms noise is 11 nV, typically, when the output data rate is 4.7 Hz, which is equivalent to 22.7 bits of 4 GND TRIM 5 REFINx(–) effective resolution or 20 bits of noise free resolution. The AD7193 can be programmed to have a gain of 1, 8, 16, 32, Figure 23. ADR421 to AD7193 Connections 64, or 128 by using Bit G2 to Bit G0 in the configuration register. Therefore, with an external 2.5 V reference, the unipolar ranges are from 0 mV to 19.53 mV to 0 V to 2.5 V, and the bipolar ranges are from ±19.53 mV to ±2.5 V. Rev. C | Page 32 of 56 08367-124 Data Sheet AD7193 When the ADC is configured for bipolar operation, the output REFERENCE DETECT code is offset binary with a negative full-scale voltage resulting The AD7193 includes on-chip circuitry to detect whether the in a code of 000…000, a zero differential input voltage resulting part has a valid reference for conversions or calibrations. This in a code of 100…000, and a positive full-scale input voltage feature is enabled when the REFDET bit in the configuration resulting in a code of 111…111. The output code for any analog register is set to 1. If the voltage between the selected REFINx(+) input voltage can be represented as and REFINx(−) pins is less than 0.3 V, the AD7193 detects that it no longer has a valid reference. In this case, the NOREF bit Code = 2N – 1 × [(AIN × Gain/VREF) + 1] of the status register is set to 1. When the voltage between the where: selected REFINx(+) and REFINx(−) pins is greater than 0.6 V, AIN is the analog input voltage. the AD7193 detects a valid reference so the NOREF bit is set Gain is the PGA setting (1 to 128). to 0. The operation of the NOREF bit is undefined when the N = 24. voltage between the selected REFINx(+) and REFINx(−) pins BURNOUT CURRENTS is between 0.3 V and 0.6 V. The AD7193 contains two 500 nA constant current generators, If the AD7193 is performing normal conversions and the NOREF one sourcing current from AV to AIN(+) and one sinking DD bit becomes active, the conversion result is all 1s. Therefore, it is current from AIN(−) to AGND. The currents are switched to not necessary to continuously monitor the status of the NOREF the selected analog input pair. Both currents are either on or off, bit when performing conversions. It is only necessary to verify depending on the burnout current enable (burn) bit in the its status if the conversion result read from the ADC data register configuration register. is all 1s. These currents can be used to verify that an external transducer If the AD7193 is performing either an offset or full-scale calibration remains operational before attempting to take measurements on and the NOREF bit becomes active, the updating of the respective that channel. After the burnout currents are turned on, they calibration registers is inhibited to avoid loading incorrect flow in the external transducer circuit, and a measurement of coefficients to these registers, and the ERR bit in the status the input voltage on the analog input channel can be taken. It register is set. If the user is concerned about verifying that a takes some time for the burnout currents to detect an open valid reference is in place every time a calibration is performed, circuit condition because the currents must charge any external the status of the ERR bit should be checked at the end of the capacitors. calibration cycle. There are several reasons that a fault condition is detected: the BIPOLAR/UNIPOLAR CONFIGURATION front-end sensor may be either open circuit or overloaded, or The analog input to the AD7193 can accept either unipolar or the reference may be absent and the NOREF bit in the status bipolar input voltage ranges. A bipolar input range does not register is set, thus clamping the data to all 1s. The user must imply that the part can tolerate negative voltages with respect check these three cases before making a determination. to system AGND. In pseudo differential mode, signals are If the voltage measured is 0 V, it may indicate that the transducer referenced to AINCOM, whereas in differential mode, signals has short circuited. The current sources work over the normal are referenced to the negative input of the differential pair. For absolute input voltage range specifications when the analog example, if AINCOM is 2.5 V and the AD7193 AIN1 analog inputs are buffered and chop is disabled. input is configured for unipolar mode with a gain of 2, the input voltage range on the AIN1 pin is 2.5 V to 3.75 V when a 2.5 V CHANNEL SEQUENCER reference is used. The AD7193 includes a channel sequencer, which simplifies If AINCOM is 2.5 V and the AD7193 AIN1 analog input is communications with the device in multichannel applications. configured for bipolar mode with a gain of 2, the analog input The sequencer also optimizes the channel throughput of the range on AIN1 is 1.25 V to 3.75 V. The bipolar/unipolar option device because the sequencer switches channels at the optimum rate rather than waiting for instructions via the SPI interface. is chosen by programming the U/B bit in the configuration register. Bit CH0 to Bit CH7 in the configuration register are used to enable the required analog input channels. The analog inputs must be DATA OUTPUT CODING configured for differential mode or pseudo differential mode When the ADC is configured for unipolar operation, the output using the pseudo bit in the configuration register. The tempera- code is natural (straight) binary with a zero differential input ture sensor is enabled using the TEMP bit in the configuration. voltage resulting in a code of 000…000, a midscale voltage resulting An internal short can also be selected using the short bit in the in a code of 100…000, and a full-scale input voltage resulting in configuration register. a code of 111…111. The output code for any analog input voltage can be represented as Code = (2N × AIN × Gain)/V REF Rev. C | Page 33 of 56 AD7193 Data Sheet In continuous conversion mode, the ADC selects each of the DIGITAL INTERFACE enabled channels in sequence and performs a conversion on the As indicated in the On-Chip Registers section, the programmable channel. The DOUT/RDY pin indicates when a valid conversion is functions of the AD7193 are controlled using a set of on-chip available on each channel. When several channels are enabled, registers. Data is written to these registers via the serial interface the contents of the status register should be attached to the 24-bit of the part. Read access to the on-chip registers is also provided word allowing the user to identify the channel that corresponds by this interface. to each conversion. The four LSBs of the status register indicate All communication with the part must start with a write to the the channel to which the conversion corresponds. Table 23 and communications register. After power-on or reset, the device Table 24 show the channel options for differential mode and expects a write to its communications register. The data written pseudo differential mode with the corresponding channel ID to this register determines whether the next operation is a read values in the status register. To attach the status register value operation or a write operation, and it determines to which to the conversion, Bit DAT_STA in the mode register should register this read or write operation occurs. Therefore, write be set to 1. access to any of the other registers on the part begins with a When several channels are enabled, the ADC allows the complete write operation to the communications register, followed by a filter settling time to generate a valid conversion each time the write to the selected register. A read operation from any other channel is changed. The AD7193 automatically takes care of this register (except when continuous read mode is selected) starts through the following sequence: with a write to the communications register, followed by a read 1. When a channel is selected, the modulator and filter are operation from the selected register. reset. CS The serial interface of the AD7193 consists of four signals: , 2. The AD7193 allows the complete settling time to generate RDY DIN, SCLK, and DOUT/ . The DIN line is used to transfer a valid conversion. RDY data into the on-chip registers and DOUT/ is used for RDY 3. DOUT/ indicates when a valid conversion is available. accessing data from the on-chip registers. SCLK is the serial 4. The AD7193 selects the next enabled channel and converts clock input for the device, and all data transfers (either on DIN on that channel. or DOUT/RDY) occur with respect to the SCLK signal. 5. The user can read the data register while the ADC is The DOUT/RDY pin also functions as a data-ready signal, the performing the conversion on the next channel. line going low when a new data-word is available in the output The time required to read a valid conversion from all enabled register. It is reset high when a read operation from the data channels is equal to register is complete. It also goes high prior to the updating of tSETTLE × Number of Enabled Channels the data register to indicate when not to read from the device, 4 to ensure that a data read is not attempted while the register is For example, if the sinc filter is selected, chop is disabled, and being updated. CS is used to select a device. It can be used to zero latency is disabled, the settling time for each channel equals decode the AD7193 in systems where several components are t = 4/f SETTLE ADC connected to the serial bus. where f is the output data rate when continuously converting ADC Figure 3 and Figure 4 show timing diagrams for interfacing to on a single channel. CS the AD7193 using to decode the part. Figure 3 shows the Therefore, the time required to read all enabled channels is timing for a read operation from the output shift register of the AD7193, and Figure 4 shows the timing for a write operation to (4× Number of Enabled Channels)/fADC the input shift register. It is possible to read the same word from RDY the data register several times even though the DOUT/RDY line CONVERSIONS returns high after the first read operation. However, care must CHANNEL A CHANNEL B CHANNEL C be taken to ensure that the read operations are completed before 1/f ADC the next output update occurs. In continuous read mode, the Figure 24. Channel Sequencer data register can be read only once. CS The serial interface can operate in 3-wire mode by tying low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD7193. The end of the conversion can be monitored using the RDY bit or pin. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers. Rev. C | Page 34 of 56 08367-060 Data Sheet AD7193 CS RDY The AD7193 can be operated with used as a frame synchro- DOUT/ goes low to indicate the completion of a conversion. nization signal. This scheme is useful for DSP interfaces. In this When the data-word has been read from the data register, case, the first bit (MSB) is effectively clocked out by CS because DOUT/RDY goes high. If CS is low, DOUT/RDY remains high CS normally occurs after the falling edge of SCLK in DSPs. The until another conversion is initiated and completed. The data register can be read several times, if required, even when SCLK can continue to run between data transfers, provided the DOUT/RDY has gone high. timing numbers are obeyed. The serial interface can be reset by writing a series of 1s to the If several channels are enabled, the ADC sequences through the DIN input. If a Logic 1 is written to the AD7193 DIN line for enabled channels and performs a conversion on each channel. at least 40 serial clock cycles, the serial interface is reset. This RDY When a conversion is started, DOUT/ goes high and remains ensures that the interface can be reset to a known state if the high until a valid conversion is available. As soon as the conversion interface is lost due to a software error or a glitch in the system. is available, DOUT/RDY goes low. The ADC then selects the Reset returns the interface to the state in which it expects a write to next channel and begins a conversion. The user can read the the communications register. This operation resets the contents present conversion while the next conversion is being performed. of all registers to their power-on values. Following a reset, the As soon as the next conversion is complete, the data register is user should allow a period of 500 µs before addressing the serial updated; therefore, the user has a limited period in which to interface. read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to power- The AD7193 can be configured to continuously convert or to down mode. perform a single conversion (see Figure 25 through Figure 27). If the DAT_STA bit in the mode register is set to 1, the contents Single Conversion Mode of the status register are output along with the conversion each In single conversion mode, the AD7193 is placed in power- time that the data read is performed. The four LSBs of the status down mode after conversions. When a single conversion is register indicate the channel to which the conversion corresponds. initiated by setting MD2 to 0, MD1 to 0, and MD0 to 1 in the mode register, the AD7193 powers up, performs a single conversion, and then returns to power-down mode. The on- chip oscillator requires 1 ms, approximately, to power up. CS 0x08 0x280060 0x58 DIN DATA DOUT/RDY SCLK Figure 25. Single Conversion Rev. C | Page 35 of 56 08367-061 AD7193 Data Sheet Continuous Conversion Mode When several channels are enabled, the ADC continuously loops through the enabled channels, performing one conversion Continuous conversion is the default power-up mode. The on each channel per loop. The data register is updated as soon AD7193 converts continuously, and the RDY bit in the status as each conversion is available. The DOUT/RDY pin pulses low register goes low each time a conversion is complete. If CS is each time a conversion is available. The user can then read the RDY low, the DOUT/ line also goes low when a conversion is conversion while the ADC converts on the next enabled channel. completed. To read a conversion, the user writes to the commu- If the DAT_STA bit in the mode register is set to 1, the contents nications register, indicating that the next operation is a read of of the status register are output along with the conversion each the data register. When the data-word has been read from the time that the data read is performed. The status register indicates data register, DOUT/RDY goes high. The user can read this the channel to which the conversion corresponds. register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion or else the new conversion word is lost. CS 0x58 0x58 DIN DATA DATA DOUT/RDY SCLK Figure 26. Continuous Conversion Rev. C | Page 36 of 56 08367-062 Data Sheet AD7193 Continuous Read To exit the continuous read mode, Instruction 01011000 must RDY be written to the communications register while the pin Rather than write to the communications register each time a is low. While in the continuous read mode, the ADC monitors conversion is complete to access the data, the AD7193 can be activity on the DIN line so that it can receive the instruction to configured so that the conversions are placed on the DOUT/ exit the continuous read mode. Additionally, a reset occurs if RDY line automatically. By writing 01011100 to the communi- 40 consecutive 1s are seen on DIN. Therefore, DIN should be cations register, the user need only apply the appropriate number held low in continuous read mode until an instruction is to be of SCLK cycles to the ADC, and the conversion word is auto- written to the device. RDY matically placed on the DOUT/ line when a conversion is complete. The ADC should be configured for continuous When several channels are enabled, the ADC continuously steps through the enabled channels and performs one conversion conversion mode. on each channel each time that it is selected. DOUT/RDY pulses When DOUT/RDY goes low to indicate the end of a conversion, low when a conversion is available. When the user applies sufficient sufficient SCLK cycles must be applied to the ADC; the data SCLK pulses, the data is automatically placed on the DOUT/RDY RDY conversion is then placed on the DOUT/ line. When the pin. If the DAT_STA bit in the mode register is set to 1, the RDY conversion is read, DOUT/ returns high until the next contents of the status register are output along with the conversion. conversion is available. In this mode, the data can be read only The status register indicates the channel to which the conversion once. The user must also ensure that the data-word is read corresponds. before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the AD7193 to read the word, the serial output register is reset when the next conversion is complete, and the new conversion is placed in the output serial register. CS 0x5C DIN DATA DATA DATA DOUT/RDY SCLK Figure 27. Continuous Read Rev. C | Page 37 of 56 08367-063 AD7193 Data Sheet RESET ENABLE PARITY The circuitry and serial interface of the AD7193 can be reset When the ENPAR bit in the mode register is set to 1, parity is by writing consecutive 1s to the device; 40 consecutive 1s are enabled. The contents of the status register must be transmitted required to perform the reset. This resets the logic, the digital along with each 24-bit conversion when the parity function is filter, and the analog modulator, whereas all on-chip registers enabled. To append the contents of the status register to each are reset to their default values. A reset is automatically performed conversion read, the DAT_STA bit in the mode register should on power-up. When a reset is initiated, the user must allow a be set to 1. For each conversion read, the parity bit in the status period of 500 µs before accessing any of the on-chip registers. A register is programmed so that the overall number of 1s trans- reset is useful if the serial interface loses synchronization due to mitted in the 24-bit data-word is even. Therefore, for example, noise on the SCLK line. if the 24-bit conversion contains 11 ones (binary format), the parity bit is set to 1 so that the total number of 1s in the serial SYSTEM SYNCHRONIZATION transmission is even. If the microprocessor receives an odd The SYNC input allows the user to reset the modulator and the number of 1s, it knows that the data received has been corrupted. digital filter without affecting any of the setup conditions on the The parity function does not ensure that all errors are detected. part. This allows the user to start gathering samples of the analog For example, two bits of corrupt data can result in the micro- input from a known point in time, that is, the rising edge of processor receiving an even number of 1s. Therefore, an error SYNC SYNC . needs to be taken low for at least four master condition is not detected. clock cycles to implement the synchronization function. CLOCK If multiple AD7193 devices are operated from a common master The AD7193 includes an internal 4.92 MHz clock on chip. This clock, they can be synchronized so that their data registers are internal clock has a tolerance of ±4%. Either the internal clock updated simultaneously. A falling edge on the SYNC pin resets or an external crystal/clock can be used as the clock source to the digital filter and the analog modulator and places the AD7193 the AD7193. The clock source is selected using the CLK1 and into a consistent, known state. While the SYNC pin is low, the CLK0 bits in the mode register. When an external crystal is used, SYNC AD7193 is maintained in this state. On the rising edge, it must be connected across the MCLK1 and MCLK2 pins. the modulator and filter are taken out of this reset state and, The crystal manufacturer recommends the load capacitances on the next clock edge, the part starts to gather input samples required for the crystal. The MCLK1 and MCLK2 pins of the again. In a system using multiple AD7193 devices, a common AD7193 have a capacitance of 15 pF, typically. If an external signal to their SYNC pins synchronizes their operation. This clock source is used, the clock source must be connected to the is normally done after each AD7193 has performed its own MCLK2 pin, and the MCLK1 pin can remain floating. calibration or has calibration coefficients loaded into its The internal clock can also be made available at the MCLK2 calibration registers. The conversions from the AD7193s pin. This is useful when several ADCs are used in an application are then synchronized. and the devices must be synchronized. The internal clock from The part is taken out of reset on the master clock falling edge one device can be used as the clock source for all ADCs in the following the SYNC low-to-high transition. Therefore, when system. Using a common clock, the devices can be synchronized multiple devices are being synchronized, the SYNC pin should by applying a common reset to all devices, or the SYNC pin can be taken high on the master clock rising edge to ensure that all be pulsed. devices begin sampling on the master clock falling edge. If the BRIDGE POWER-DOWN SWITCH SYNC pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle between the devices; In bridge applications such as strain gages and load cells, the that is, the instant at which conversions are available differs bridge itself consumes the majority of the current in the system. from part to part by a maximum of one master clock cycle. For example, a 350 Ω load cell requires 15 mA of current when excited with a 5 V supply. To minimize the current consumption The SYNC pin can also be used as a start conversion command. of the system, the bridge can be disconnected (when it is not In this mode, the rising edge of SYNC starts conversion, and the being used) using the bridge power-down switch. Figure 22 falling edge of RDY indicates when the conversion is complete. shows how the bridge power-down switch is used. The switch The settling time of the filter has to be allowed for each data can withstand 30 mA of continuous current, and it has an on register update. For example, if the ADC is configured to use the resistance of 10 Ω maximum. 4 sinc filter, zero latency is disabled, and chop is disabled, the settling time equals 4/f , where f is the output data rate ADC ADC when continuously converting on a single channel. Rev. C | Page 38 of 56 Data Sheet AD7193 To start a calibration, write the relevant value to the MD2 to TEMPERATURE SENSOR RDY RDY MD0 bits. The DOUT/ pin and the bit in the status Embedded in the AD7193 is a temperature sensor. This is selected register go high when the calibration initiates. When the using the TEMP bit in the configuration register. When the calibration is complete, the contents of the corresponding TEMP bit is set to 1, the temperature sensor is enabled. When calibration registers are updated, the RDY bit in the status the temperature sensor is selected and bipolar mode is selected, register is reset, the DOUT/RDY pin returns low (if CS is low), the device should return a code of 0x800000 when the temperature and the AD7193 reverts to idle mode. is 0 Kelvin, theoretically. A one-point calibration is needed to obtain the optimum performance from the sensor. Therefore, a During an internal zero-scale or full-scale calibration, the conversion at 25°C should be recorded and the sensitivity respective zero input and full-scale input are automatically calculated. The sensitivity is 2815 codes/°C, approximately. connected internally to the ADC input pins. A system calibration, The equation for the temperature sensor is however, expects the system zero-scale and system full-scale voltages to be applied to the ADC pins before initiating the Temperature (K) = (Conversion − 0x800000)/2815 K calibration mode. In this way, errors external to the ADC Temperature (°C) = Temperature (K) − 273 are removed. Following the one-point calibration, the internal temperature From an operational point of view, treat a calibration like another sensor has an accuracy of ±2°C, typically. ADC conversion. A zero-scale calibration, if required, must LOGIC OUTPUTS always be performed before a full-scale calibration. Set the system software to monitor the RDY bit in the status register or The AD7193 has four general-purpose digital outputs: P0, P1, P2, and P3. These are enabled using the GP32EN and GP10EN the DOUT/RDY pin to determine the end of calibration via a bits in the GPOCON register. The pins can be pulled high or polling sequence or an interrupt-driven routine. low using the P0DAT to P3DAT bits in the GPOCON register; With chop disabled, both an internal zero-scale calibration and that is, the value at the pin is determined by the setting of the a system zero-scale calibration require a time equal to the settling P0DAT to P3DAT bits. The logic levels for these pins are deter- 4 3 time, t (4/f for the sinc filter and 3/f for the sinc filter). SETTLE ADC ADC mined by AV rather than by DV . When the GPOCON DD DD With chop enabled, an internal zero-scale calibration is not register is read, Bit P0DAT to Bit P3DAT reflect the actual needed because the ADC itself minimizes the offset continuously. value at the pins; this is useful for short-circuit detection. However, if an internal zero-scale calibration is performed, the These pins can be used to drive external circuitry, for example, settling time, tSETTLE (2/fADC), is required to perform the calibration. an external multiplexer. If an external multiplexer is used to Similarly, a system zero-scale calibration requires a time of tSETTLE increase the channel count, the multiplexer logic pins can be to complete. controlled via the AD7193 general-purpose output pins. The To perform an internal full-scale calibration, a full-scale input general-purpose output pins can be used to select the active voltage is automatically connected to the selected analog input multiplexer pin. Because the operation of the multiplexer is for this calibration. For a gain of 1, the time required for an independent of the AD7193, the AD7193 modulator and filter internal full-scale calibration is equal to t . For higher gains, SETTLE should be reset using the SYNC pin or by a write to the mode or the internal full-scale calibration requires a time of 2 × t . SETTLE configuration register each time that the multiplexer channel is A full-scale calibration is recommended each time the gain of a changed. channel is changed to minimize the full-scale error. CALIBRATION A system full-scale calibration requires a time of tSETTLE. With The AD7193 provides four calibration modes that can be chop disabled, the zero-scale calibration (internal or system programmed via the mode bits in the mode register. These zero-scale) should be performed before the system full-scale modes are internal zero-scale calibration, internal full-scale calibration is initiated. calibration, system zero-scale calibration, and system full-scale An internal zero-scale calibration, system zero-scale calibration, calibration. A calibration can be performed at any time by setting and system full-scale calibration can be performed at any output the MD2 to MD0 bits in the mode register appropriately. A data rate. An internal full-scale calibration can be performed at calibration should be performed when the gain is changed. any output data rate for which the filter word, FS[9:0], is divisible After each conversion, the ADC conversion result is scaled by 16, FS[9:0] being the decimal equivalent of the 10-bit word using the ADC calibration registers before being written to the written to Bit FS9 to Bit FS0 in the mode register. Therefore, data register. The offset calibration coefficient is subtracted from internal full-scale calibrations can be performed at output data the result prior to multiplication by the full-scale coefficient. rates such as 10 Hz or 50 Hz when chop is disabled. Using these lower output data rates, results in better calibration accuracy. Rev. C | Page 39 of 56 AD7193 Data Sheet The offset error is, typically, ±150 µV/gain. If the gain is changed, An internal full-scale calibration reduces the gain error to it is advisable to perform a calibration. A zero-scale calibration ±0.001%, typically, when the gain is equal to 1. For higher gains, (an internal zero-scale calibration or a system zero-scale calibration) the gain error postinternal full-scale calibration is ±0.003%, reduces the offset error to the order of the noise. typically, when AVDD is equal to or higher than 4.75 V. When The gain error of the AD7193 is factory calibrated at a gain of 1 AVDD is less than 4.75 V, the gain error after internal full-scale with a 5 V power supply at ambient temperature. Following this calibration is ±0.005%, typically. calibration, the gain error is, typically, ±0.001% at 5 V. Table 27 When AVDD is less than 4.75 V, the CLK_DIV bit must be set shows the typical uncalibrated gain error for the different gain when performing internal full-scale calibrations. This increases settings. the calibration time by a factor of 2. The accuracy of the internal full-scale calibration is further increased if chop is enabled and Table 27. Typical Precalibration Gain Error vs. Gain a low output data rate is used while performing the calibration. Gain Precalibration Gain Error (%) A system full-scale calibration reduces the gain error to the 8 −0.11 order of the noise irrespective of the analog power supply 16 −0.20 voltage. 32 −0.23 64 −0.29 The AD7193 gives the user access to the on-chip calibration 128 −0.39 registers, allowing the microprocessor to read the calibration coefficients of the device and also to write its own calibration coefficients from prestored values in the EEPROM. A read of the registers can be performed at any time. However, the ADC must be placed in power-down or idle mode when writing to the registers. The values in the calibration registers are 24 bits wide. The span and offset of the part can also be manipulated using the registers. Rev. C | Page 40 of 56 Data Sheet AD7193 DIGITAL FILTER The AD7193 offers a lot of flexibility in the digital filter. The When conversions are performed on a single channel and a step device has five filter options. The device can be operated with change occurs, the ADC does not detect the change in analog 3 4 a sinc or sinc filter, chop can be enabled or disabled, and zero input. Therefore, it continues to output conversions at the pro- latency can be enabled. Finally, an averaging block can be grammed output data rate. However, it is at least four conversions included after the sinc filter, which gives a fast settling mode. later before the output data accurately reflect the analog input. The option selected affects the output data rate, settling time, If the step change occurs while the ADC is processing a conver- and 50 Hz/60 Hz rejection. The following sections describe sion, then the ADC takes five conversions after the step change each filter type, indicating the available output data rates for to generate a fully settled result. each filter option. The filter response, along with the settling ANALOG INPUT time and 50 Hz/60 Hz rejection, is also discussed. FULLY SETTLED 4 ADC SINC FILTER (CHOP DISABLED) OUTPUT 4 When the AD7193 is powered up, the sinc filter is selected by default and chop is disabled. This filter gives excellent noise 1/f ADC performance over the complete range of output data rates. It Figure 30. Asynchronous Step Change in Analog Input also gives the best 50 Hz/60 Hz rejection, but it has a long 4 The 3 dB frequency for the sinc filter is equal to settling time. ADC f = 0.23 × f 3dB ADC Table 28 gives some examples of the relationship between the 3 4 CHOP MODULATOR SINC /SINC POST FILTER values in Bits FS[9:0] and the corresponding output data rate and settling time. 4 Figure 28. Sinc Filter (Chop Disabled) Table 28. Examples of Output Data Rates and the 4 Corresponding Settling Time Sinc Output Data Rate/Settling Time FS[9:0] Output Data Rate (Hz) Settling Time (ms) The output data rate (the rate at which conversions are available 480 10 400 on a single channel when the ADC is continuously converting) 96 50 80 is equal to 80 60 66.6 fADC = fCLK/(1024 × FS[9:0]) 4 Sinc Zero Latency where: Zero latency is enabled by setting the single bit (Bit 11) in the fADC is the output data rate. mode register to 1. With zero latency, the complete settling time f is the master clock (4.92 MHz nominal). CLK is allowed for each conversion. Therefore, the conversion time FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the when converting on a single channel or when converting on mode register. several channels is constant. The user does not need to consider The output data rate can be programmed from 4.7 Hz to the effects of channel changes on the output data rate. When the 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. channel sequencer is enabled, the AD7193 automatically 4 The settling time for the sinc filter is equal to operates in zero latency mode. tSETTLE = 4/fADC The output data rate equals When a channel change occurs, the modulator and filter are fADC = 1/tSETTLE = fCLK/(4 × 1024 × FS[9:0]) reset. The settling time is allowed to generate the first conver- where: sion after the channel change. Subsequent conversions on this f is the output data rate. ADC channel occur at 1/f . ADC f is the master clock (4.92 MHz nominal). CLK CHANNEL A CHANNEL B FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the CHANNEL mode register. CONVERSIONS CH A CH A CH A CH B CH B CH B 1/f ADC 4 Figure 29. Sinc Channel Change Rev. C | Page 41 of 56 08367-024 08367-025 08367-026 AD7193 Data Sheet When the analog input is constant or a channel change occurs, Figure 33 shows the frequency response when FS[9:0] is valid conversions are available at a constant output data rate. programmed to 80 and the master clock is equal to 4.92 MHz. When conversions are being performed on a single channel and The output data rate is 60 Hz when zero latency is disabled and 4 a step change occurs on the analog input, the ADC continues to 15 Hz when zero latency is enabled. The sinc filter provides output fully settled conversions if the step change is synchronized 60 Hz (±1 Hz) rejection of 120 dB minimum, assuming a stable with the conversion process. If the step change is asynchronous, master clock. one conversion is output from the ADC, which is not completely 0 settled (see Figure 31). –10 –20 ANALOG INPUT –30 FULLY SETTLED –40 ADC –50 OUTPUT –60 –70 1/f ADC –80 4 Figure 31. Sinc Zero Latency Operation –90 –100 Table 29 shows examples of output data rate and the corresponding –110 FS values. –120 Table 29. Examples of Output Data Rates and the FREQUENCY (Hz) Corresponding Settling Time (Zero Latency) 4 Figure 33. Sinc Filter Response (FS[9:0] = 80) FS[9:0] Output Data Rate (Hz) Settling Time (ms) Simultaneous 50 Hz and 60 Hz rejection is obtained when 480 2.5 400 FS[9:0] is programmed to 480 and the master clock equals 96 12.5 80 4.92 MHz. The output data rate is 10 Hz when zero latency is 80 15 66.6 4 disabled and 2.5 Hz when zero latency is enabled. The sinc 4 Sinc 50 Hz/60 Hz Rejection filter provides 50 Hz (±1 Hz) and 60 Hz (±1 Hz) rejection of 4 120 dB minimum, assuming a stable master clock. Figure 32 shows the frequency response of the sinc filter when FS[9:0] is set to 96 and the master clock is 4.92 MHz. With zero 0 latency disabled, the output data rate is equal to 50 Hz. With –10 4 –20 zero latency enabled, the output data rate is 12.5 Hz. The sinc –30 filter provides 50 Hz (±1 Hz) rejection in excess of 120 dB –40 minimum, assuming a stable master clock. –50 0 –60 –10 –70 –20 –80 –30 –90 –40 –100 –50 –110 –60 –120 –70 0 30 60 90 120 150 –80 FREQUENCY (Hz) –90 4 Figure 34. Sinc Filter Response (FS[9:0] = 480) –100 –110 –120 FREQUENCY (Hz) 4 Figure 32. Sinc Filter Response (FS[9:0] = 96) Rev. C | Page 42 of 56 0 30 60 90 120 150 0 25 50 75 100 125 150 FILTER GAIN (dB) 08367-028 08367-027 FILTER GAIN (dB) FILTER GAIN (dB) 08367-030 08367-029 Data Sheet AD7193 Simultaneous 50 Hz/60 Hz rejection can also be achieved using The settling time is equal to the REJ60 bit in the mode register. When FS[9:0] is set to 96 t = 3/f SETTLE ADC and REJ60 is set to 1, notches are placed at 50 Hz and 60 Hz. The 3 dB frequency is equal to The output data rate is 50 Hz when zero latency is disabled and f3dB = 0.272 × fADC 12.5 Hz when zero latency is enabled. Figure 35 shows the 4 frequency response of the sinc filter. The filter provides 50 Hz Table 30 gives some examples of FS settings and the corresponding ± 1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, output data rates and settling times. assuming a stable 4.92 MHz master clock. Table 30. Examples of Output Data Rates and the 0 Corresponding Settling Time –10 FS[9:0] Output Data Rate (Hz) Settling Time (ms) –20 480 10 300 –30 96 50 60 –40 80 60 50 –50 –60 When a channel change occurs, the modulator and filter reset. The –70 complete settling time is allowed to generate the first conversion –80 after the channel change (see Figure 37). Subsequent conversions –90 on this channel are available at 1/fADC. –100 CHANNEL B CHANNEL A –110 CHANNEL –120 CONVERSIONS 0 25 50 75 100 125 150 CH A CH A CH A CH B CH B CH B CH B FREQUENCY (Hz) 4 Figure 35. Sinc Filter Response (FS[9:0] = 96, REJ60 = 1) 1/f ADC 3 3 Figure 37. Sinc Channel Change SINC FILTER (CHOP DISABLED) 3 4 When conversions are performed on a single channel and a A sinc filter can be used instead of the sinc filter. The filter is 3 step change occurs, the ADC does not detect the change in selected using the SINC3 bit in the mode register. The sinc analog input. Therefore, it continues to output conversions at filter is selected when the SINC3 bit is set to 1. the programmed output data rate. However, it is at least three This filter has good noise performance when operating with conversions later before the output data accurately reflects the output data rates up to 1 kHz. It has moderate settling time and analog input. If the step change occurs while the ADC is processing moderate 50 Hz/60 Hz (±1 Hz) rejection. a conversion, the ADC takes four conversions after the step change ADC to generate a fully settled result. ANALOG INPUT 3 4 CHOP MODULATOR SINC /SINC POST FILTER FULLY SETTLED ADC OUTPUT 3 Filter (Chop Disabled) Figure 36. Sinc 3 Sinc Output Data Rate and Settling Time 1/f ADC The output data rate (the rate at which conversions are available Figure 38. Asynchronous Step Change in Analog Input on a single channel when the ADC is continuously converting) is equal to f = f /(1024 × FS[9:0]) ADC CLK where: f is the output data rate. ADC fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. Rev. C | Page 43 of 56 FILTER GAIN (dB) 08367-032 08367-031 08367-034 08367-033 AD7193 Data Sheet 3 Sinc Zero Latency 3 Sinc 50 Hz/60 Hz Rejection 3 Zero latency is enabled by setting the single bit (Bit 11) in the Figure 40 show the frequency response of the sinc filter when mode register to 1. With zero latency, the complete settling time FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The is allowed for each conversion. Therefore, the conversion time output data rate is equal to 50 Hz when zero latency is disabled 3 when converting on a single channel or when converting on and 16.7 Hz when zero latency is enabled. The sinc filter gives several channels is constant. The user does not need to consider 50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock. the effects of channel changes on the output data rate. When the 0 channel sequencer is enabled, the AD7193 automatically operates –10 in zero latency mode. –20 –30 The output data rate equals –40 fADC = 1/ tSETTLE = fCLK/(3 × 1024 × FS[9:0]) –50 where: –60 fADC is the output data rate. –70 f is the master clock (4.92 MHz nominal). CLK –80 FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the –90 mode register. –100 –110 When the analog input is constant or a channel change occurs, –120 valid conversions are available at a constant output data rate. 0 25 50 75 100 125 150 When conversions are being performed on a single channel and FREQUENCY (Hz) 3 a step change occurs on the analog input, the ADC continues to Figure 40. Sinc Filter Response (FS[9:0] = 96) output fully settled conversions if the step change is synchronized When FS[9:0] is set to 80 and the master clock equals 4.92 MHz, with the conversion process. If the step change is asynchronous, 60 Hz rejection is achieved (see Figure 41). The output data rate one conversion is output from the ADC that is not completely is equal to 60 Hz when zero latency is disabled and 20 Hz when settled (see Figure 39). 3 zero latency is enabled. The sinc filter has rejection of 95 dB ANALOG minimum at 60 Hz ± 1 Hz, assuming a stable master clock. INPUT FULLY 0 SETTLED ADC –10 OUTPUT –20 –30 –40 1/f ADC –50 3 Figure 39. Sinc Zero Latency Operation –60 Table 31 provides examples of output data rates and the –70 corresponding FS values. –80 –90 Table 31. Examples of Output Data Rates and the –100 Corresponding Settling Time (Zero Latency) –110 FS[9:0] Output Data Rate (Hz) Settling Time (ms) –120 0 30 60 90 120 150 480 3.3 300 FREQUENCY (Hz) 96 16.7 60 3 Figure 41. Sinc Filter Response (FS[9:0] = 80) 80 20 50 Rev. C | Page 44 of 56 08367-035 FILTER GAIN (dB) FILTER GAIN (dB) 08367-037 08367-036 Data Sheet AD7193 4 Simultaneous 50 Hz and 60 Hz rejection is obtained when CHOP ENABLED (SINC FILTER) FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in With chop enabled, the ADC offset and offset drift are minimized. Figure 42. The output data rate is 10 Hz when zero latency is The analog input pins are continuously swapped. With the analog 3 disabled and 3.3 Hz when zero latency is enabled. The sinc input pins connected in one direction, the settling time of the filter has rejection of 100 dB minimum at 50 Hz ± 1 Hz and sinc filter is allowed and a conversion is recorded. The analog 60 Hz ± 1 Hz. input pins are then inverted, and another settled conversion is obtained. Subsequent conversions are averaged to minimize the 0 offset. This continuous swapping of the analog input pins and –10 the averaging of subsequent conversions means that the offset –20 drift is also minimized. With chop enabled, the resolution –30 increases by 0.5 bits. –40 ADC –50 –60 3 4 CHOP MODULATOR SINC /SINC POST FILTER –70 –80 –90 Figure 44. Chop Enabled –100 4 –110 Output Data Rate and Settling Time (Sinc Chop Enabled) –120 4 For the sinc filter, the output data rate is equal to 0 30 60 90 120 150 FREQUENCY (Hz) f = f /(4 × 1024 × FS[9:0]) ADC CLK 3 Figure 42. Sinc Filter Response (FS[9:0] = 480) where: Simultaneous 50 Hz/60 Hz rejection is also achieved using the fADC is the output data rate. REJ60 bit in the mode register. When FS[9:0] is programmed to fCLK is the master clock (4.92 MHz nominal). 96 and the REJ60 bit is set to 1, notches are placed at both 50 Hz FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the and 60 Hz for a stable 4.92 MHz master clock. Figure 43 shows mode register. 3 the frequency response of the sinc filter with this configuration. The value of FS[9:0] can be varied from 1 to 1023. This results Assuming a stable clock, the rejection at 50 Hz/60 Hz (±1 Hz) is in an output data rate of 1.17 Hz to 1200 Hz. The settling time is in excess of 67 dB minimum. equal to 0 tSETTLE = 2/fADC –10 –20 Table 32 gives some examples of FS[9:0] values and the –30 corresponding output data rates and settling times. –40 Table 32. Examples of Output Data Rates and the –50 Corresponding Settling Time –60 FS[9:0] Output Data Rate (Hz) Settling Time (ms) –70 96 12.5 160 –80 –90 80 15 133 –100 –110 –120 0 25 50 75 100 125 150 FREQUENCY (Hz) 3 Figure 43. Sinc Filter Response (FS[9:0] = 96, REJ60 = 1) Rev. C | Page 45 of 56 FILTER GAIN (dB) FILTER GAIN (dB) 08367-039 08367-038 08367-040 AD7193 Data Sheet 0 When a channel change occurs, the modulator and filter reset. –10 The complete settling time is required to generate the first –20 conversion after the channel change. Subsequent conversions on –30 this channel occur at 1/fADC. –40 –50 CHANNEL A CHANNEL B CHANNEL –60 CONVERSIONS CH A CH A CH A CH B CH B CH B CH B CH B –70 –80 1/f ADC –90 4 –100 Figure 45. Channel Change (Sinc Chop Enabled) –110 When conversions are performed on a single channel and a –120 0 25 50 75 100 125 150 step change occurs, the ADC does not detect the change in FREQUENCY (Hz) analog input; therefore, it continues to output conversions 4 Figure 47. Sinc Filter Response (FS[9:0] = 96, Chop Enabled) at the programmed output data rate. However, it is at least two conversions later before the output data accurately reflects The 50 Hz/60 Hz rejection can be improved by setting the the analog input. If the step change occurs while the ADC is REJ60 bit in the mode register to 1. With FS[9:0] set to 96 processing a conversion, the ADC takes three conversions after and REJ60 set to 1, the filter response shown in Figure 48 the step change to generate a fully settled result. is achieved. The output data rate is unchanged but the 50 Hz/ ANALOG 60 Hz (±1 Hz) rejection is increased to 83 dB typically. INPUT FULLY 0 SETTLED –10 ADC OUTPUT –20 –30 1/f ADC –40 4 –50 Figure 46. Asynchronous Step Change in Analog Input (Sinc Chop Enabled) –60 The cutoff frequency f3dB is equal to –70 f = 0.24 × f 3dB ADC –80 4 –90 50 Hz/60 Hz Rejection (Sinc Chop Enabled) –100 When FS[9:0] is set to 96 and chopping is enabled, the output –110 data rate is equal to 12.5 Hz for a 4.92 MHz master clock. The –120 0 25 50 75 100 125 150 filter response shown in Figure 47 is obtained. The chopping FREQUENCY (Hz) introduces notches at odd integer multiples of f /2. The notches ADC 4 Figure 48. Sinc Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1) due to the sinc filter in addition to the notches introduced by the chopping mean that simultaneous 50 Hz and 60 Hz rejection is achieved for an output data rate of 12.5 Hz. The rejection at 50 Hz/60 Hz ± 1 Hz is typically 63 dB, assuming a stable master clock. Rev. C | Page 46 of 56 08367-042 08367-041 FILTER GAIN (dB) FILTER GAIN (dB) 08367-044 08367-043 Data Sheet AD7193 3 If conversions are performed on a single channel and a step CHOP ENABLED (SINC FILTER) change occurs, the ADC does not detect the change in analog With chop enabled, the ADC offset and offset drift are minimized. input; therefore, it continues to output conversions at the The analog input pins are continuously swapped. With the analog programmed output data rate. However, it is at least two input pins connected in one direction, the settling time of the conversions later before the output data accurately reflects sinc filter is allowed and a conversion is recorded. The analog the analog input. If the step change occurs while the ADC is input pins invert and another settled conversion is obtained. processing a conversion, then the ADC takes three conversions Subsequent conversions are averaged to minimize the offset. after the step change to generate a fully settled result. This continuous swapping of the analog input pins and the ANALOG averaging of subsequent conversions means that the offset drift INPUT is also minimized. With chop enabled, the resolution increases FULLY SETTLED 3 by 0.5 bits. Using the sinc filter with chop enabled is suitable ADC OUTPUT for output data rates up to 320 Hz. ADC 1/f ADC 3 Figure 51. Asynchronous Step Change in Analog Input (Sinc Chop Enabled) 3 4 CHOP MODULATOR SINC /SINC POST FILTER The cutoff frequency f3dB is equal to 3 f3dB = 0.24 × fADC Figure 49. Chop Enabled (Sinc Chop Enabled) 3 50 Hz/60 Hz Rejection (Sinc Chop Enabled) 3 Output Data Rate and Settling Time (Sinc Chop Enabled) When FS[9:0] is set to 96 and chopping is enabled, the filter 3 For the sinc filter, the output data rate is equal to response shown in Figure 52 is obtained. The output data rate fADC = fCLK/(3 × 1024 × FS[9:0]) is equal to 16.7 Hz for a 4.92 MHz master clock. The chopping where: introduces notches at odd integer multiples of fADC/2. The notches fADC is the output data rate. due to the sinc filter in addition to the notches introduced by fCLK is the master clock (4.92 MHz nominal). the chopping means that simultaneous 50 Hz and 60 Hz rejection FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the is achieved for an output data rate of 16.7 Hz. The rejection at mode register. 50 Hz/60 Hz ± 1 Hz is typically 53 dB, assuming a stable master clock. The value of FS[9:0] can be varied from 1 to 1023. This results 0 in an output data rate of 1.56 Hz to 1600 Hz. The settling time is –10 equal to –20 tSETTLE = 2/fADC –30 –40 Table 33. Examples of Output Data Rates and the –50 3 Corresponding Settling Time (Chop Enabled, Sinc Filter) –60 FS[9:0] Output Data Rate (Hz) Settling Time (ms) –70 96 16.7 120 –80 80 20 100 –90 When a channel change occurs, the modulator and filter are reset. –100 –110 The complete settling time is required to generate the first –120 conversion after the channel change. Subsequent conversions 0 25 50 75 100 125 150 on this channel occur at 1/fADC. FREQUENCY (Hz) 3 CHANNEL A CHANNEL B Figure 52. Sinc Filter Response (FS[9:0] = 96, Chop Enabled) CHANNEL CONVERSIONS CH A CH A CH A CH B CH B CH B CH B CH B 1/f ADC 3 Figure 50. Channel Change (Sinc Chop Enable) Rev. C | Page 47 of 56 08367-045 08367-046 FILTER GAIN (dB) 08367-047 08367-048 AD7193 Data Sheet The 50 Hz/60 Hz rejection can be improved by setting the The settling time is equal to REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and t = 1/f SETTLE ADC REJ60 set to 1, the filter response shown in Figure 53 is achieved. Table 34 lists sample FS words and the corresponding output The output data rate is unchanged but the 50 Hz/60 Hz ± 1 Hz data rates and settling times. rejection improves to 73 dB typically. 0 Table 34. Examples of Output Data Rates and the –10 4 Corresponding Settling Time (Fast Settling Mode, Sinc ) –20 FS[9:0] Average Output Data Rate (Hz) Settling Time (ms) –30 96 16 2.63 380 –40 30 16 8.4 118.75 –50 6 16 42.1 23.75 –60 5 16 50.53 19.79 –70 When the analog input channel is changed, there is no additional –80 delay in generating valid conversions—the device functions as a –90 zero latency ADC. –100 –110 CHANNEL B CHANNEL A CHANNEL –120 0 25 50 75 100 125 150 CONVERSIONS CH A CH A CH A CH B CH B CH B CH B CH B CH B FREQUENCY (Hz) 3 Figure 53. Sinc Filter Response 1/f ADC (FS[9:0] = 96, Chop Enabled, REJ60 = 1) 4 Figure 55. Fast Settling, Sinc Filter 4 FAST SETTLING MODE (SINC FILTER) When the device is converting on a single channel and a step In fast settling mode, the settling time is close to the inverse of change occurs on the analog input, the ADC does not detect the the first filter notch; therefore, the user can achieve 50 Hz and/or change and continues to output conversions. If the step change 60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz. is synchronized with the conversion, only fully settled results The settling time is equal to 1/output data rate. Therefore, the are output from the ADC. However, if the step change is asyn- conversion time is constant when converting on a single channel chronous to the conversion process, there is one intermediate or when converting on several channels. There is no added result, which is not completely settled (see Figure 56). latency when switching channels. ANALOG INPUT Enable the fast settling mode using Bit AVG1 and Bit AVG0 in the mode register. In fast settling mode, a postfilter is included VALID ADC 4 after the sinc filter. The postfilter averages by 2, 8, or 16, OUTPUT depending on the settings of the AVG1 and AVG0 bits. ADC 1/f ADC 4 Figure 56. Step Change on Analog Input, Sinc Filter 3 4 CHOP MODULATOR SINC /SINC POST FILTER The output data rate is the same for chop enabled and chop disabled in fast settling mode. However, when chop is enabled, 4 the settling time equals Figure 54. Fast Settling Mode, Sinc Filter 4 tSETTLE = 2/fADC Output Data Rate and Settling Time, Sinc Filter 4 Therefore, if chop is enabled, the sinc filter is selected, FS[9:0] With chop disabled, the output data rate is is set to 6, and averaging by 16 is enabled. The output data rate f = f /((4 + Avg − 1) × 1024 × FS[9:0]) (1) ADC CLK is equal to 42.1 Hz when the master clock equals 4.92 MHz. f is the output data rate. ADC Therefore, the conversion time equals 1/42.10 Hz or 23.75 ms and f is the master clock (4.92 MHz nominal). CLK the settling time is equal to 47.5 ms. Avg is the average. FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. If AVG1 = AVG0 = 0, the fast settling mode is not enabled. In this case, Equation 1 is not relevant. Rev. C | Page 48 of 56 FILTER GAIN (dB) 08367-050 08367-049 08367-051 08367-052 Data Sheet AD7193 4 50 Hz/60 Hz Rejection, Sinc Filter Simultaneous 50 Hz/60 Hz rejection is achieved when FS[9:0] is set to 30 and the postfilter averages by 16. The output data rate Figure 57 shows the frequency response when FS[9:0] is set to 6 is equal to 8.4 Hz, whereas the rejection at 50 Hz ± 0.5 Hz and and the postfilter averages by 16. This gives an output data rate 60 Hz ± 0.5 Hz is typically 44 dB. of 42.10 Hz when the master clock equals 4.92 MHz. The sinc 0 filter places the first notch at –10 f = f /(1024 × FS[9:0]) NOTCH CLK –20 The postfiltering places notches at f /Avg (Avg is the amount of –30 NOTCH averaging) and multiples of this frequency; therefore, when FS[9:0] –40 –50 is set to 6 and the postfilter averaging is 16, a notch is placed at –60 800 Hz due to the sinc filter and notches are placed at 50 Hz –70 and multiples of 50 Hz due to the postfilter. The notch at 50 Hz –80 is a first-order notch; therefore, the notch is not wide. This means –90 that the rejection at 50 Hz exactly is good, assuming a stable –100 4.92 MHz master clock. However, in a band of 50 Hz ± 1 Hz, the –110 rejection degrades significantly. The rejection at 50 Hz ± 0.5 Hz is –120 40 dB minimum, assuming a stable clock; therefore, a good master 0 30 60 90 120 150 clock source is recommended when using fast settling mode. FREQUENCY (Hz) 0 Figure 59. Filter Response for Average + Decimate Filter 4 –10 (Sinc Filter, FS[9:0] = 30, Average by 16) –20 Simultaneous 50 Hz and 60 Hz rejection is also achieved by –30 using an FS word of 96 and averaging by 16; this places a notch –40 at 50 Hz. Setting the REJ60 bit to 1 places a notch at 60 Hz (see –50 Figure 60). The output data rate is reduced to 2.63 Hz with this –60 configuration but the rejection is improved to typically 100 dB –70 at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz. –80 0 –90 –10 –100 –20 –110 –30 –120 0 30 60 90 120 150 –40 FREQUENCY (Hz) –50 Figure 57. Filter Response for Average + Decimate Filter –60 4 (Sinc Filter, FS[9:0] = 6, Average by 16) –70 –80 Figure 58 shows the filter response when FS[9:0] is set to 5 and –90 the postfilter averages by 16. In this case, the output data rate is –100 equal to 50.53 Hz (4.92 MHz master clock) while the first filter –110 notch is placed at 60 Hz. The rejection at 60 Hz ± 0.5 Hz is equal to –120 40 dB minimum. 0 30 60 90 120 150 0 FREQUENCY (Hz) –10 Figure 60. Filter Response for Average + Decimate Filter 4 –20 (Sinc Filter, FS[9:0] = 96, Average by 16) –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 30 60 90 120 150 FREQUENCY (Hz) Figure 58. Filter Response for Average + Decimate Filter 4 (Sinc Filter, FS[9:0] = 5, Average by 16) Rev. C | Page 49 of 56 FILTER GAIN (dB) FILTER GAIN (dB) 08367-058 08367-053 FILTER GAIN (dB) FILTER GAIN (dB) 08367-157 08367-059 AD7193 Data Sheet 3 When the device is converting on a single channel and a step FAST SETTLING MODE (SINC FILTER) change occurs on the analog input, the ADC does not detect In fast settling mode, the settling time is close to the inverse of the change and continues to output conversions. When the step the first filter notch. Therefore, the user can achieve 50 Hz and/or change is synchronized with the conversion, only fully settled 60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz. results are output from the ADC. However, if the step change is The settling time is equal to 1/output data rate. Therefore, the asynchronous to the conversion process, one intermediate result conversion time is constant when converting on a single channel is not completely settled (see Figure 63). or when converting on several channels. There is no added ANALOG latency when switching channels. INPUT The fast settling mode is enabled using Bit AVG1 and Bit AVG0 VALID 4 ADC in the mode register. A postfilter is included after the sinc filter. OUTPUT The postfilter averages by 2, 8, or 16, depending on the settings of the AVG1 and AVG0 bits. 1/f ADC ADC 3 Figure 63. Step Change on Analog Input, Sinc Filter 3 50 Hz/60 Hz Rejection, Sinc Filter 3 4 CHOP MODULATOR SINC /SINC POST FILTER Figure 64 shows the frequency response when FS[9:0] is set to 6 and the postfilter averages by 16. This gives an output data rate 3 Figure 61. Fast Settling Mode, Sinc Filter of 44.44 Hz when the master clock is 4.92 MHz. The sinc filter 3 places the first notch at Output Data Rate and Settling Time, Sinc Filter f = f /(1024 × FS[9:0]) With chop disabled, the output data rate is NOTCH CLK The postfiltering places notches at fNOTCH/Avg (Avg is the amount fADC = fCLK/((3 + Avg – 1) × 1024 × FS[9:0]) of averaging) and multiples of this frequency. Therefore, when fADC is the output data rate. FS[9:0] is set to 6 and the postfilter averaging is 16, a notch is fCLK is master clock (4.92 MHz nominal). placed at 800 Hz due to the sinc filter and notches are placed at Avg is the average. 50 Hz and multiples of 50 Hz due to the postfilter. FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the The notch at 50 Hz is a first-order notch. Therefore, the notch is mode register. not wide. This means that the rejection at 50 Hz exactly is good, If AVG1 = AVG0 = 0, the fast settling mode is not enabled. assuming a stable 4.92 MHz master clock. However, in a band of In this case, the preceding equation is not relevant. 50 Hz ± 1 Hz, the rejection degrades significantly. The rejection at The settling time is equal to 50 Hz ± 0.5 Hz is 40 dB minimum, assuming a stable clock; there- fore, a good master clock source is recommended when using fast tSETTLE = 1/fADC settling mode. Table 35 lists some sample FS words and the corresponding 0 output data rates and settling times. –10 –20 Table 35. Examples of Output Data Rates and the 3 –30 Corresponding Settling Time (Fast Settling Mode, Sinc ) –40 FS[9:0] Average Output Data Rate (Hz) Settling Time (ms) –50 96 16 2.78 360 –60 30 16 8.9 112.5 –70 6 16 44.44 22.5 –80 5 16 53.3 18.75 –90 If the analog input channel is changed, there is no additional –100 delay in generating valid conversions and the device functions –110 as a zero latency ADC. –120 0 30 60 90 120 150 CHANNEL B CHANNEL A CHANNEL FREQUENCY (Hz) Figure 64. Filter Response for Average + Decimate Filter CONVERSIONS CH A CH A CH A CH B CH B CH B CH B CH B CH B 3 (Sinc Filter, FS[9:0] = 6, Average by 16) 1/f ADC 3 Figure 62. Fast Settling, Sinc Filter Rev. C | Page 50 of 56 08367-055 08367-056 FILTER GAIN (dB) 08367-053 08367-057 Data Sheet AD7193 Figure 65 shows the filter response when FS[9:0] is set to 5 and Simultaneous 50 Hz and 60 Hz rejection is also achieved by using the post filter averages by 16. In this case, the output data rate is an FS word of 96 and averaging by 16, which places a notch at equal to 53.33 Hz when the first filter notch is placed at 60 Hz. 50 Hz. Setting the REJ60 bit to 1 places a notch at 60 Hz (see The rejection at 60 Hz ± 0.5 Hz is equal to 40 dB minimum. Figure 67). The output data rate is reduced to 2.78 Hz with this 0 configuration, but the rejection is improved to 94 dB typically at –10 50 Hz ± 1 Hz and 60 Hz ± 1 Hz. –20 0 –30 –10 –40 –20 –50 –30 –60 –40 –70 –50 –80 –60 –90 –70 –100 –80 –110 –90 –120 –100 0 30 60 90 120 150 –110 FREQUENCY (Hz) –120 Figure 65. Filter Response for Average + Decimate Filter 0 30 60 90 120 150 3 (Sinc Filter, FS[9:0] = 5, Average by 16) FREQUENCY (Hz) Figure 67. Filter Response for Average + Decimate Filter Simultaneous 50 Hz/60 Hz rejection is achieved when FS[9:0] is 3 (Sinc Filter, FS[9:0] = 96, Average by 16) set to 30 and the postfilter averages by 16. The output data rate is equal to 8.9 Hz whereas the rejection at 50 Hz ± 0.5 Hz and FAST SETTLING MODE (CHOP ENABLED) 60 Hz ± 0.5 Hz is typically 42 dB. Chop can be enabled in the fast settling mode. With chop 0 enabled, the ADC offset and offset drift are minimized. The –10 analog input pins are continuously swapped. With the analog –20 input pins connected in one direction, the settling time of the –30 sinc filter is allowed and a conversion is recorded. The analog –40 input pins are then inverted, and another settled conversion is –50 obtained. Subsequent conversions are averaged so that the offset –60 is minimized. This continuous swapping of the analog input –70 pins and the averaging of subsequent conversions means that –80 the offset drift is also minimized. –90 Chopping does not change the output data rate. However, the –100 settling time equals –110 –120 tSETTLE = 2/fADC 0 30 60 90 120 150 4 FREQUENCY (Hz) Consequently, if chop is enabled, the sinc filter is selected, FS[9:0] Figure 66. Filter Response for Average + Decimate Filter is set to 6, averaging by 16 is enabled, and the output data rate is 3 (Sinc Filter, FS[9:0] = 30, Average by 16) equal to 42.1 Hz. Therefore, the conversion time equals 1/42.10 Hz or 23.75 ms, and the settling time is equal to 47.5 ms. Rev. C | Page 51 of 56 FILTER GAIN (dB) FILTER GAIN (dB) 08367-054 08367-058 FILTER GAIN (dB) 08367-164 AD7193 Data Sheet Table 36 shows some sample configurations and the corresponding SUMMARY OF FILTER OPTIONS performance in terms of throughput, settling time, and 50 Hz/ The AD7193 has several filter options. The filter that is chosen 60 Hz rejection. affects the output data rate, settling time, the rms noise, and the 50 Hz/60 Hz rejection. 1 Table 36. Filter Summary Output Data Settling 2 3 Filter FS[9:0] Rate (Hz) Time (ms) Throughput (Hz) REJ60 50 Hz Rejection (dB) 4 4 Sinc , Chop Disabled 1 4800 0.83 1200 0 No 50 Hz or 60 Hz rejection 4 Sinc , Chop Disabled 5 960 4.17 240 0 No 50 Hz or 60 Hz rejection 3 Sinc , Chop Disabled 5 960 3.125 320 0 No 50 Hz or 60 Hz rejection 4 Sinc , Chop Disabled 480 10 400 2.5 0 120 dB (50 Hz and 60 Hz) 3 Sinc , Chop Disabled 480 10 300 3.33 0 100 dB (50 Hz and 60 Hz) 4 Sinc , Chop Disabled 96 50 80 12.5 0 120 dB (50 Hz only) 4 Sinc , Chop Disabled 96 50 80 12.5 1 82 dB (50 Hz and 60 Hz) 3 Sinc , Chop Disabled 96 50 60 16.7 0 95 dB (50 Hz only) 3 Sinc , Chop Disabled 96 50 60 16.7 1 67 dB (50 Hz and 60 Hz) 4 Sinc , Chop Disabled 80 60 66.67 15 0 120 dB (60 Hz only) 3 Sinc , Chop Disabled 80 60 50 20 0 95 dB (60 Hz only) 4 Sinc , Chop Disabled, 96 12.5 80 12.5 0 120 dB (50 Hz only) Zero Latency 4 Sinc , Chop Disabled, 96 12.5 80 12.5 1 82 dB (50 Hz and 60 Hz) Zero Latency 4 Sinc , Chop Disabled, 80 15 66.67 15 0 120 dB (60 Hz only) Zero Latency 4 Sinc , Chop Enabled 96 12.5 160 6.25 1 80 dB (50 Hz and 60 Hz) 3 Sinc , Chop Enabled 96 16.7 120 8.33 1 67 dB (50 Hz and 60 Hz) 4 Fast Settling (Sinc , Chop 96 2.63 380 2.63 1 100 dB (50 Hz and 60 Hz) Disabled, Average by 16) 4 Fast Settling (Sinc , Chop 96 2.78 360 2.78 1 94 dB (50 Hz and 60 Hz) Disabled, Average by 16) 4 Fast Settling (Sinc , Chop 5 50.53 19.79 50.53 0 40 dB (60 Hz only) Disabled, Average by 16) 3 Fast Settling (Sinc , Chop 5 53.33 18.75 53.33 0 40 dB (60 Hz only) Disabled, Average by 16) 4 Fast Settling (Sinc , Chop 6 42.10 23.75 42.1 0 40 dB (50 Hz only) Disabled, Average by 16) 3 Fast Settling (Sinc , Chop 6 44.44 22.5 44.44 0 40 dB (50 Hz only) Disabled, Average by 16) 1 These calculations assume a 4.92 MHz stable master clock. 2 Throughput is the rate at which conversions are available when several channels are enabled. In zero latency mode, the output data rate and throughput are equal. 3 For fast settling mode, the 50 Hz/60 Hz rejection is measured in a band of ±0.5 Hz around 50 Hz and/or 60 Hz. For all other modes, a region of ±1 Hz around 50 Hz and/or 60 Hz is used. 4 4 For output dates rates greater than 1 kHz, the sinc filter is recommended. Rev. C | Page 52 of 56 Data Sheet AD7193 GROUNDING AND LAYOUT Because the analog inputs and reference inputs are differential, In systems in which the AGND and DGND are connected some- most of the voltages in the analog modulator are common-mode where else in the system (that is, the power supply of the system), voltages. The high common-mode rejection of the part removes they should not be connected again at the AD7193 because a common-mode noise on these inputs. The analog and digital ground loop results. In these situations, it is recommended that supplies to the AD7193 are independent and separately pinned the ground pins of the AD7193 be tied to the AGND plane. out to minimize coupling between the analog and digital sections In any layout, the user must keep in mind the flow of currents of the device. The digital filter provides rejection of broadband in the system, ensuring that the paths for all currents are as close as noise on the power supplies, except at integer multiples of the possible to the paths the currents took to reach their destinations. modulator sampling frequency. Avoid forcing digital currents to flow through the AGND. Connect an RC filter to each analog input pin to provide rejection Avoid running digital lines under the device because this couples at the modulator sampling frequency. A 100 Ω resistor in series noise onto the die and allows the analog ground plane to run with each analog input, a 0.1 µF capacitor between the analog under the AD7193 to prevent noise coupling. The power supply input pins, and a 0.01 µF capacitor from each analog input to lines to the AD7193 must use as wide a trace as possible to AGND are advised. provide low impedance paths and reduce the effects of glitches The digital filter also removes noise from the analog and on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections reference inputs provided that these noise sources do not saturate the analog modulator. As a result, the AD7193 is of the board and never run clock signals near the analog inputs. more immune to noise interference than a conventional high Avoid crossover of digital and analog signals. Run traces on resolution converter. However, because the resolution of the opposite sides of the board at right angles to each other. This AD7193 is so high and the noise levels from the converter so reduces the effects of feedthrough through the board. A microstrip low, care must be taken with regard to grounding and layout. technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of The printed circuit board (PCB) that houses the ADC must be the board is dedicated to ground planes, whereas signals are designed so that the analog and digital sections are separated placed on the solder side. and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum Good decoupling is important when using high resolution ADCs. etch technique is generally best for ground planes because it Decouple all analog supplies with 10 µF tantalum capacitors in gives the best shielding. parallel with 0.1 µF capacitors to AGND. To achieve the best results from these decoupling components, place them as close Although the AD7193 has separate pins for analog and digital as possible to the device, ideally right up against the device. ground, the AGND and DGND pins are tied together internally Decouple all logic chips with 0.1 µF ceramic capacitors to DGND. via the substrate. Therefore, the user must not tie these two pins In systems in which a common supply voltage is used to drive to separate ground planes unless the ground planes are connected both the AV DD and DVDD of the AD7193, it is recommended together near the AD7193. that the system AVDD supply be used. For this supply, place the recommended analog supply decoupling capacitors between the AV pin of the AD7193 and AGND and the recommended DD digital supply decoupling capacitor between the DV pin of the DD AD7193 and DGND. Rev. C | Page 53 of 56 AD7193 Data Sheet APPLICATIONS INFORMATION The AD7193 provides a low cost, high resolution analog-to-digital power consumed in the application. In addition, the bridge function. Because the analog-to-digital function is provided by a power-down switch can be opened while the AD7193 is in power- Σ-∆ architecture, the part is more immune to noisy environments, down mode, thus avoiding unnecessary power consumption making it ideal for use in sensor measurement and industrial and by the front-end transducers. When the parts are taken out of process control applications. power-down mode and the bridge power-down switch is closed, the user should ensure that the front-end circuitry is fully settled FLOWMETER before attempting a read from the AD7193. Figure 68 shows the AD7193 being used in a flowmeter application In Figure 68, temperature compensation is performed using that consists of two pressure transducers with the rate of flow a thermistor. In addition, the reference voltage for the temperature being equal to the pressure difference. The pressure transducers measurement is derived from a precision resistor in series with are arranged in a bridge network and give a differential output the thermistor. This allows a ratiometric measurement so that voltage between its OUT+ and OUT− terminals. With rated variation of the excitation voltage has no affect on the measurement full-scale pressure (in this case 300 mmHg) on the transducer, (it is the ratio of the precision reference resistance to the thermistor the differential output voltage is 3 mV/V of the input voltage resistance that is measured) (that is, the voltage between the IN+ and IN– terminals). For simplicity, external filters are not shown in Figure 68; however, Assuming a 5 V excitation voltage, the full-scale output range an RC antialias filter must be included on each analog input. from the transducer is 15 mV. The excitation voltage for the This is required because the on-chip digital filter does not bridge can be used to directly provide the reference for the ADC, provide any rejection around the modulator sampling frequency or because the reference input range includes the supply voltage. multiples of this frequency. Suitable values are a 100 Ω resistor A second advantage of using the AD7193 in transducer-based in series with each analog input, a 0.1 µF capacitor between the applications is that the bridge power-down switch can be fully analog input pins, and a 0.01 µF capacitor from each analog utilized in low power applications. The bridge power-down switch input pin to AGND. is connected in series with the cold side of the bridges. In normal operation, the switch is closed and measurements are taken. In applications where power is of concern, the AD7193 can be placed in power-down mode, thus significantly reducing the 5V AGND AV DV DGND DD DD REFIN1(+) REFERENCE IN+ DETECT AV AIN1 DD OUT+ OUT– AIN2 IN+ DOUT/RDY SERIAL IN– INTERFACE OUT+ MUX DIN OUT– AIN3 PGA Σ-Δ ADC AND AIN4 CONTROL SCLK AIN5 LOGIC CS IN– AIN6 SYNC AGND REFIN2(+) REFIN2(–) REFIN1(–) AD7193 BPDSW CLOCK CIRCUITRY AGND MCLK1 MCLK2 Figure 68. Typical Application (Flowmeter) Rev. C | Page 54 of 56 08367-064 Data Sheet AD7193 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 0.19 SEATING COPLANARITY 0.09 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 69. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 5.10 0.30 5.00 SQ 0.25 4.90 0.18 PIN 1 INDICATOR 25 32 24 1 0.50 BSC EXPOSED 3.65 PAD 3.50 SQ 3.45 8 17 16 9 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.75 0.05 MAX FUNCTION DESCRIPTIONS 0.70 SECTION OF THIS DATA SHEET. 0.02 NOM COPLANARITY 0.08 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. Figure 70. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very, Very Thin Quad (CP-32-11) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD7193BRUZ −40°C to +105°C 28-Lead TSSOP RU-28 AD7193BRUZ-REEL −40°C to +105°C 28-Lead TSSOP RU-28 AD7193BCPZ −40°C to +105°C 32-Lead LFCSP_WQ CP-32-11 AD7193BCPZ-RL −40°C to +105°C 32-Lead LFCSP_WQ CP-32-11 AD7193BCPZ-RL7 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-11 EVAL-AD7193EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. C | Page 55 of 56 PIN 1 INDICATOR 112408-A AD7193 Data Sheet NOTES ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08367-0-12/11(C) Rev. C | Page 56 of 56