ANALOG DEVICES AD7190

4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA AD7190 FEATURES Chromatography PLC/DCS analog input modules RMS noise: 8.5 nV @ 4.7 Hz (gain = 128) Data acquisition 16 noise free bits @ 2.4 kHz (gain = 128) Medical and scientific instrumentation Up to 22.5 noise free bits (gain = 1) Offset drift: 5 nV/°C GENERAL DESCRIPTION Gain drift: 1 ppm/°C The AD7190 is a low noise, complete analog front end for high Specified drift over time precision measurement applications. It contains a low noise, 2 differential/4 pseudo differential input channels 24-bit sigma-delta (∑-Δ) analog-to-digital converter (ADC). Automatic channel sequencer The on-chip low noise gain stage means that signals of small Programmable gain (1 to 128) amplitude can be interfaced directly to the ADC. Output data rate: 4.7 Hz to 4.8 kHz The device can be configured to have two differential inputs or Internal or external clock four pseudo differential inputs. The on-chip channel sequencer Simultaneous 50 Hz/60 Hz rejection allows several channels to be enabled, and the AD7190 4 general-purpose digital outputs sequentially converts on each enabled channel. This simplifies Power supply AV : 4.75 V to 5.25 V communication with the part. The on-chip 4.92 MHz clock can DD DV : 2.7 V to 5.25 V be used as the clock source to the ADC or, alternatively, an DD Current: 6 mA external clock or crystal can be used. The output data rate from Temperature range: –40°C to +105°C the part can be varied from 4.7 Hz to 4.8 kHz. Interface The device has two digital filter options. The choice of filter 3-wire serial affects the rms noise/noise-free resolution at the programmed SPI, QSPI™, MICROWIRE™, and DSP compatible output data rate, the settling time, and the 50 Hz/60 Hz Schmitt trigger on SCLK rejection. For applications that require all conversions to be settled, the AD7190 includes a zero latency feature. APPLICATIONS The part operates with 5 V analog power supply and a digital Weigh scales power supply from 2.7 V to 5.25 V. It consumes a current of Strain gauge transducers 6 mA. It is housed in a 24-lead TSSOP package. Pressure measurement Temperature measurement FUNCTIONAL BLOCK DIAGRAM AGND AV DV DGND REFIN1(+) REFIN1(–) DD DD REFERENCE DETECT AD7190 AIN1 AIN2 AIN3 DOUT/RDY SERIAL AIN4 INTERFACE MUX DIN Σ-Δ AINCOM PGA AND ADC CONTROL SCLK LOGIC CS SYNC TEMP P3 SENSOR P2 BPDSW CLOCK CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 07640-001 AD7190 TABLE OF CONTENTS Features .............................................................................................. 1 Full-Scale Register ...................................................................... 25 Applications ....................................................................................... 1 ADC Circuit Information .............................................................. 26 General Description ......................................................................... 1 Overview ..................................................................................... 26 Functional Block Diagram .............................................................. 1 Filter, Output Data Rate, Settling Time ................................... 26 Revision History ............................................................................... 2 Digital Interface .......................................................................... 29 Specif ica t ions ..................................................................................... 3 Circuit Description......................................................................... 33 Timing Characteristics ................................................................ 7 Analog Input Channel ............................................................... 33 Circuit and Timing Diagrams ..................................................... 7 PGA .............................................................................................. 33 Absolute Maximum Ratings ............................................................ 9 Bipolar/Unipolar Configuration .............................................. 33 Thermal Resistance ...................................................................... 9 Data Output Coding .................................................................. 33 ESD Caution .................................................................................. 9 Clock ............................................................................................ 33 Pin Configuration and Function Descriptions ........................... 10 Burnout Currents ....................................................................... 34 Typical Performance Characteristics ........................................... 12 Reference ..................................................................................... 34 RMS Noise and Resolution ............................................................ 15 Reference Detect ......................................................................... 34 4 Sinc Chop Disabled ................................................................... 15 Reset ............................................................................................. 34 3 Sinc Chop Disabled ................................................................... 16 System Synchronization ............................................................ 35 4 Sinc Chop Enabled .................................................................... 17 Temperature Sensor ................................................................... 35 3 Sinc Chop Enabled .................................................................... 18 Bridge Power-Down Switch ...................................................... 35 On-Chip Registers .......................................................................... 19 Logic Outputs ............................................................................. 35 Communications Register ......................................................... 19 Enable Parity ............................................................................... 36 Status Register ............................................................................. 20 Calibration ................................................................................... 36 Mode Register ............................................................................. 20 Grounding and Layout .............................................................. 37 Configuration Register .............................................................. 22 Applications Information .............................................................. 38 Data Register ............................................................................... 24 Weigh Scales ................................................................................ 38 ID Register ................................................................................... 24 Outline Dimensions ....................................................................... 39 GPOCON Register ..................................................................... 24 Ordering Guide .......................................................................... 39 Offset Register ............................................................................. 25 REVISION HISTORY Changes to Table 21 ....................................................................... 25 5/09—Rev. A to Rev. B Changes to Filter, Output Data Rate, Settling Time Section .... 26 Changes to Table 3 ............................................................................ 9 Changes to Continuous Conversion Mode Section ................... 31 5/09—Rev. 0 to Rev. A Changes to Analog Input Channel and Bipolar/Unipolar Configuration Sections .................................................................. 33 Changes to Table 1 ............................................................................ 3 Changes to Burnout Currents, Reference, Reference Detect, and Changes to Table 3 and Table 4 ....................................................... 9 Reset Sections .................................................................................. 34 Changes to Table 5 .......................................................................... 10 Changes to Table 6 and Table 7 ..................................................... 15 Changes to Temperature Sensor Section ..................................... 35 Changes to Calibration Section .................................................... 36 Changes to Status Register Section .............................................. 20 Changes to Grounding and Layout Section ................................ 37 Changes to Table 17 ........................................................................ 21 Changes to Weigh Scales Section ................................................. 38 Changes to Table 19 ........................................................................ 23 Changes to Ordering Guide .......................................................... 39 Changes to Table 20 ........................................................................ 24 Added ID Register Section ............................................................ 24 10/08—Revision 0—Initial Version Rev. B | Page 2 of 40 AD7190 SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, REFINx(+) = AVDD , REFINx(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter AD7190B Unit Test Conditions/Comments ADC Output Data Rate 4.7 to 4800 Hz nom Chop disabled. 4 1.17 to 1200 Hz nom Chop enabled, sinc filter. 3 1.56 to 1600 Hz nom Chop enabled, sinc filter. 2 4 3 No Missing Codes 24 Bits min FS > 1, sinc filter . 3 3 24 Bits min FS > 4, sinc filter . Resolution See the RMS Noise and Resolution section RMS Noise and Output Data Rates See the RMS Noise and Resolution section Integral Nonlinearity ±5 ppm of FSR max ±1 ppm typical, gain = 1. ±15 ppm of FSR max ±5 ppm typical, gain > 1. 4, 5 Offset Error ±75/gain μV typ Chop disabled. ±0.5 μV typ Chop enabled. 5 Offset Error Drift vs. Temperature ±100/gain nV/°C typ Gain = 1 to 16. chop disabled. ±5 nV/°C typ Gain = 32 to 128. chop disabled. ±5 nV/°C typ Chop enabled. Offset Error Drift vs. Time 25 nV/1000 hours typ Gain ≥ 32. 4 6 Gain Error ±0.005 % max ±0.001 % typical, gain = 1, AVDD = 5 V . ±0.0075 % typ Gain > 1, post internal full-scale calibration. Gain Drift vs. Temperature ±1 ppm/°C typ Gain Drift vs. Time 10 ppm/1000 hours typ Gain = 1. Power Supply Rejection 95 dB typ Gain = 1, V = 1 V. IN 100 dB min Gain > 1, V = 1 V/gain. 110 dB typical. IN Common-Mode Rejection 2 @ DC 100 dB min Gain = 1, VIN = 1 V . 110 dB min Gain > 1, VIN = 1 V/gain. 2 @ 50 Hz, 60 Hz 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 2 @ 50 Hz, 60 Hz 120 dB min 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz (60 Hz output data rate). 2 Normal Mode Rejection 4 Sinc Filter Internal Clock @ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 7 74 dB min 50 Hz output data rate, REJ60 = 1, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz 96 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 97 dB min 60 Hz output data rate, 60 ± 1 Hz. Rev. B | Page 3 of 40 AD7190 1 Parameter AD7190B Unit Test Conditions/Comments External Clock @ 50 Hz, 60 Hz 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 7 82 dB min 50 Hz output data rate, REJ60 = 1, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz 120 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 120 dB min 60 Hz output data rate, 60 ± 1 Hz. 3 Sinc Filter Internal Clock @ 50 Hz, 60 Hz 75 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 60 dB min 50 Hz output data rate, REJ60 = 1, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz 70 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 70 dB min 60 Hz output data rate, 60 ± 1 Hz. External Clock @ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 7 67 dB min 50 Hz output data rate, REJ60 = 1, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz 95 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 95 dB min 60 Hz output data rate, 60 ± 1 Hz. ANALOG INPUTS Differential Input Voltage Ranges ±VREF/gain V nom VREF = REFINx(+) − REFINx(−), gain = 1 to 128. ±(AVDD – 1.25 V)/gain V min/max Gain > 1. 2 Absolute AIN Voltage Limits Unbuffered Mode AGND − 50 mV V min AVDD + 50 mV V max Buffered Mode AGND + 250 mV V min AVDD − 250 mV V max Analog Input Current Buffered Mode 2 Input Current ±2 nA max Gain = 1. ±3 nA max Gain > 1. Input Current Drift ±5 pA/°C typ Unbuffered Mode Input Current ±5 μA/V typ Gain = 1, input current varies with input voltage. ±1 μA/V typ Gain > 1. Input Current Drift ±0.05 nA/V/°C typ External clock. ±1.6 nA/V/°C typ Internal clock. REFERENCE INPUT REFIN Voltage AVDD V nom REFIN = REFINx(+) − REFINx(−). 2 Reference Voltage Range 1 V min AV V max The differential input must be limited to DD ± (AV – 1.25 V)/gain when gain > 1. DD 2 Absolute REFIN Voltage Limits AGND – 50 mV V min AVDD + 50 mV V max Average Reference Input Current 7 μA/V typ Average Reference Input Current ±0.03 nA/V/°C typ External clock. Drift 1.3 nA/V/°C typ Internal clock. Rev. B | Page 4 of 40 AD7190 1 Parameter AD7190B Unit Test Conditions/Comments 2 Normal Mode Rejection Same as for analog inputs Common-Mode Rejection 95 dB typ Reference Detect Levels 0.3 V min 0.6 V max TEMPERATURE SENSOR Accuracy ±2 °C typ Applies after user calibration at 25°C. Sensitivity 2815 Codes/°C typ Bipolar mode. BRIDGE POWER-DOWN SWITCH RON 10 Ω max 2 Allowable Current 30 mA max Continuous current. BURNOUT CURRENTS AIN Current 500 nA nom Analog inputs must be buffered and chop disabled. DIGITAL OUTPUTS (P0 to P3) 2 Output High Voltage, V 4 V min AV = 5V, I = 200 μA. OH DD SOURCE 2 Output Low Voltage, V 0.4 V max AV = 5V, I = 800 μA. OL DD SINK Floating-State Leakage Current ±100 nA max Floating-State Output 10 pF typ Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency 4.92 ± 4% MHz min/max Duty Cycle 50:50 % typ 2 External Clock/Crystal Frequency 4.9152 MHz nom 2.4576/5.12 MHz min/max Input Low Voltage, VINL 0.8 V max DVDD = 5 V. 0.4 V max DVDD = 3 V. Input High Voltage, V 2.5 V min DV = 3 V. INH DD 3.5 V min DV = 5 V. DD Input Current ±10 μA max LOGIC INPUTS 2 Input High Voltage, V 2 V min INH 2 Input Low Voltage, VINL 0.8 V max 2 Hysteresis 0.1/0.25 V min/V max Input Currents ±10 μA max LOGIC OUTPUT (DOUT/RDY) 2 Output High Voltage, VOH DVDD − 0.6 V min DVDD = 3 V, ISOURCE = 100 μA. 2 Output Low Voltage, VOL 0.4 V max DVDD = 3 V, ISINK = 100 μA. 2 Output High Voltage, V 4 V min DV = 5 V, I = 200 μA. OH DD SOURCE 2 Output Low Voltage, V 0.4 V max DV = 5 V, I = 1.6 mA. OL DD SINK Floating-State Leakage Current ±10 μA max Floating-State Output 10 pF typ Capacitance Data Output Coding Offset binary 2 SYSTEM CALIBRATION Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max Rev. B | Page 5 of 40 AD7190 1 Parameter AD7190B Unit Test Conditions/Comments 8 POWER REQUIREMENTS Power Supply Voltage AVDD − AGND 4.75/5.25 V min/max DV − DGND 2.7/5.25 V min/max DD Power Supply Currents AI Current 1 mA max 0.85 mA typical, gain = 1, buffer off. DD 1.3 mA max 1.1 mA typical, gain = 1, buffer on. 4.5 mA max 3.5 mA typical, gain = 8, buffer off. 4.75 mA max 4 mA typical, gain = 8, buffer on. 6.2 mA max 5 mA typical, gain = 16 to 128, buffer off. 6.75 mA max 5.5 mA typical, gain = 16 to 128, buffer on. DIDD Current 0.4 mA max 0.35 mA typical, DVDD = 3 V. 0.6 mA max 0.5 mA typical, DVDD = 5 V. 1.5 mA typ External crystal used. I (Power-Down Mode) 2 μA max DD 1 Temperature range: TMIN = −40°C, TMAX = +105°C. 2 Specification is not production tested but is supported by characterization data at initial product release. 3 FS = decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full- scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5 The analog inputs are configured for differential mode. 6 Applies at the factory calibration conditions (AVDD = 5 V, gain = 1, TA = 25°C). 7 REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection. 8 Digital inputs equal to DVDD or DGND. Rev. B | Page 6 of 40 AD7190 TIMING CHARACTERISTICS AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2. 1, 2 Parameter Limit at TMIN, TMAX (B Version) Unit Conditions/Comments t3 100 ns min SCLK high pulse width t4 100 ns min SCLK low pulse width READ OPERATION t1 0 ns min CS falling edge to DOUT/RDY active time 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V 3 4 t 0 ns min SCLK active edge to data valid delay 2 60 ns max DV = 4.75 V to 5.25 V DD 80 ns max DVDD = 2.7 V to 3.6 V 5, 6 t5 10 ns min Bus relinquish time after CS inactive edge 80 ns max t 0 ns min SCLK inactive edge to CS inactive edge 6 t 10 ns min SCLK inactive edge to DOUT/RDY high 7 WRITE OPERATION 4 t 0 ns min CS falling edge to SCLK active edge setup time 8 t 30 ns min Data valid to SCLK edge setup time 9 t 25 ns min Data valid to SCLK edge hold time 10 t11 0 ns min CS rising edge to SCLK edge hold time 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. CIRCUIT AND TIMING DIAGRAMS I (1.6mA WITH DV = 5V, SINK DD 100µA WITH DV = 3V) DD TO OUTPUT 1.6V PIN 50pF I (200µA WITH DV = 5V, SOURCE DD 100µA WITH DV = 3V) DD Figure 2. Load Circuit for Timing Characterization Rev. B | Page 7 of 40 07640-002 AD7190 CS (I) t 6 t 1 t 5 DOUT/RDY (O) MSB LSB t 7 t 2 t 3 SCLK (I) t 4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t t 8 11 SCLK (I) t 9 t 10 DIN (I) MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. B | Page 8 of 40 07640-004 07640-003 AD7190 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE TA = 25°C, unless otherwise noted. θ is specified for the worst-case conditions, that is, a device JA Table 3. soldered in a circuit board for surface-mount packages. Parameter Rating Table 4. Thermal Resistance AV to AGND DD −0.3 V to +6.5 V Package Type θ θ Unit JA JC DVDD to AGND −0.3 V to +6.5 V 24-Lead TSSOP 128 42 °C/W AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND −0.3 V to AV + 0.3 V DD ESD CAUTION Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND −0.3 V to DV + 0.3 V DD Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V AIN/Digital Input Current 10 mA Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature, Soldering Reflow 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 9 of 40 AD7190 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS MCLK1 1 24 DIN MCLK2 2 23 DOUT/RDY SCLK 3 22 SYNC CS 4 21 DV AD7190 DD TOP VIEW P3 5 20 AV DD (Not to Scale) P2 6 19 DGND 18 P1/REFIN2(+) 7 AGND 8 17 P0/REFIN2(–) BPDSW 9 NC 16 REFIN1(–) 10 15 AINCOM REFIN1(+) AIN1 11 14 AIN4 AIN2 12 13 AIN3 NC = NO CONNECT Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. 2 MCLK2 Master Clock Signal for the Device. The AD7190 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7190 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected. 3 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncon- tinuous clock with the information transmitted to or from the ADC in smaller batches of data. 4 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 5 P3 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AV and AGND. DD 6 P2 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and AGND. 7 P1/REFIN2(+) Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced between AV and AGND. When REFSEL = 1, this pin functions as REFIN2(+). An external reference can be DD applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AV and AGND + 1 V. The DD nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AV , but the part functions with a reference from DD 1 V to AVDD. 8 P0/REFIN2(−) Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced between AVDD and AGND. When REFSEL = 1, this pin functions as REFIN2(−). This reference input can lie anywhere between AGND and AV − 1 V. DD 9 NC No Connect. This pin should be tied to AGND. 10 AINCOM Analog Input AIN1 to Analog Input AIN4 are referenced to this input when configured for pseudo differential operation. 11 AIN1 Analog Input. It can be configured as the positive input of a fully differential input pair when used with AIN2 or as a pseudo differential input when used with AINCOM. 12 AIN2 Analog Input. It can be configured as the negative input of a fully differential input pair when used with AIN1 or as a pseudo differential input when used with AINCOM. Rev. B | Page 10 of 40 07640-005 AD7190 Pin No. Mnemonic Description 13 AIN3 Analog Input. It can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudo differential input when used with AINCOM. 14 AIN4 Analog Input. It can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudo differential input when used with AINCOM. 15 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(+) can lie anywhere between AVDD REFIN1(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. 16 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. 17 BPDSW Bridge Power-Down Switch to AGND. 18 AGND Analog Ground Reference Point. 19 DGND Digital Ground Reference Point. 20 AVDD Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD. 21 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. 22 SYNC Logic input that allows for synchronization of the digital filters and analog modulators when using multiple AD7190 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset and the analog modulator is held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DVDD. 23 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. 24 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register. Rev. B | Page 11 of 40 AD7190 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,760 8,388,950 8,388,900 8,388,758 8,388,850 8,388,756 8,388,800 8,388,750 8,388,754 8,388,700 8,388,752 8,388,650 8,388,750 8,388,600 8,388,550 8,388,748 8,388,500 8,388,746 8,388,450 0 200 400 600 800 1000 0 100 200 300 400 500 600 700 800 900 1000 SAMPLE SAMPLES Figure 6. Noise (V = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop Figure 8. Noise (V = 5 V, Output Data Rate = 4800 Hz, Gain = 128, Chop REF REF 4 4 Disabled, Sinc Filter) Disabled, Sinc Filter) 250 30 25 200 20 150 15 100 10 50 5 0 0 CODE CODE Figure 9. Noise Distribution Histogram (V = 5 V, Figure 7. Noise Distribution Histogram (V = 5 V, REF REF 4 4 Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc Filter) Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc Filter) Rev. B | Page 12 of 40 CODE FREQUENCY 8,388,746 8,388,748 8,388,750 8,388,752 8,388,754 8,388,756 8,388,758 8,388,760 07640-107 07640-106 CODE FREQUENCY 8,388,490 8,388,576 8,388,662 8,388,748 8,388,834 8,388,920 07640-109 07640-108 AD7190 3.0 8,388,820 8,388,800 2.0 8,388,780 1.0 8,388,760 8,388,740 0 8,388,720 8,388,700 –1.0 8,388,680 –2.0 8,388,660 8,388,640 –3.0 8,388,620 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 0 100 200 300 400 500 600 700 800 900 1000 V (V) IN SAMPLES Figure 10. Noise (V = 5 V, Output Data Rate = 4800 Hz, Gain = 1, Chop Figure 12. INL (Gain = 1) REF 4 Disabled, Sinc Filter) 80 70 6 60 4 50 2 40 30 0 20 –2 10 –4 0 –6 –0.020 –0.015 –0.010 –0.005 0 0.005 0.010 0.015 0.020 V (V) CODE IN Figure 11. Noise Distribution Histogram (V = 5 V, REF Figure 13. INL (Gain = 128) 4 Output Data Rate = 4800 Hz, Gain = 1, Chop Disabled, Sinc Filter) Rev. B | Page 13 of 40 CODE FREQUENCY 8,388,620 8,388,660 8,388,700 8,388,740 8,388,780 8,388,820 07640-111 07640-110 INL (ppm of FSR) INL (ppm of FSR) 07640-112 07640-113 AD7190 66 1.000008 1.000007 64 1.000006 62 1.000005 60 1.000004 1.000003 58 1.000002 56 1.000001 54 1.000000 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. Offset Error (Gain = 1, Chop Disabled) Figure 16. Gain Error (Gain = 1, Chop Disabled) 0 128.003 –0.1 128.002 –0.2 128.001 –0.3 128.000 –0.4 127.999 –0.5 127.998 –0.6 127.997 –0.7 127.996 –60 –40 –20 0 20 40 60 80 100 120 –60 –40 –20 0 20 40 60 80 100 120 TEMERATURE (°C) TEMPERATURE (°C) Figure 15. Offset Error (Gain = 128, Chop Disabled) Figure 17. Gain Error (Gain = 128, Chop Disabled) Rev. B | Page 14 of 40 OFFSET (µV) OUTPUT VOLTAGE (µV) 07640-114 07640-115 GAIN GAIN 07640-116 07640-117 AD7190 RMS NOISE AND RESOLUTION 4 3 The AD7190 has a choice of two filter types: sinc and sinc . on a single channel. The effective resolution is also shown, and In addition, the AD7190 can be operated with chop enabled the output peak-to-peak (p-p) resolution, or noise-free resol- or chop disabled. ution, is listed in parentheses. It is important to note that the effective resolution is calculated using the rms noise, wheras the The following tables show the rms noise of the AD7190 for some p-p resolution is calculated based on peak-to-peak noise. The of the output data rates and gain settings with chop disabled p-p resolution represents the resolution for which there is no 4 3 and enabled for the sinc and sinc filters. The numbers given code flicker. These numbers are typical and are rounded to the are for the bipolar input range with the external 5 V reference. nearest ½ LSB. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting 4 SINC CHOP DISABLED Table 6. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 4.7 852.5 250 38 21 12 10 8.5 640 7.5 533 310 45 25 16 12 10.5 480 10 400 330 50 30 18 14 11.5 96 50 80 900 125 78 45 33 28 80 60 66.7 970 140 88 52 36 31 32 150 26.7 1460 215 125 75 55 48 16 300 13.3 1900 285 170 100 75 67 5 960 4.17 3000 480 280 175 140 121 2 2400 1.67 5000 780 440 280 220 198 1 4800 0.83 14,300 1920 1000 550 380 295 Table 7. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word Output Data Settling 1 1 1 1 1 1 (Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 4.7 852.5 24 (22.5) 24 (22) 24 (22) 24 (22) 24 (21) 23 (20.5) 640 7.5 533 24 (22) 24 (22) 24 (22) 24 (21.5) 23.5 (21) 23 (20) 480 10 400 24 (22) 24 (22) 24 (21.5) 24 (21.5) 23.5 (20.5) 22.5 (20) 96 50 80 23.5 (20.5) 23.5 (20.5) 23 (20) 22.5 (20) 22 (19.5) 21.5 (18.5) 80 60 66.7 23.5 (20.5) 23 (20.5) 22.5 (20) 22.5 (20) 22 (19.5) 21.5 (18.5) 32 150 26.7 22.5 (20) 22.5 (19.5) 22.5 (19.5) 22 (19.5) 21.5 (18.5) 20.5 (18) 16 300 13.3 22.5 (19.5) 22 (19.5) 22 (19) 21.5 (19) 21 (18.5) 20 (17.5) 5 960 4.17 21.5 (19) 21.5 (18.5) 21 (18.5) 21 (18) 20 (17.5) 19.5 (16.5) 2 2400 1.67 21 (18) 20.5 (18) 20.5 (17.5) 20 (17.5) 19.5 (16.5) 18.5 (16) 1 4800 0.83 19.5 (16.5) 19.5 (16.5) 19.5 (16.5) 19 (16.5) 18.5 (16) 18 (15.5) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. B | Page 15 of 40 AD7190 3 SINC CHOP DISABLED Table 8. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 4.7 639.4 270 42 23 13.5 10.5 9 640 7.5 400 320 50 27 17 13 11.5 480 10 300 350 60 35 19 15 12.5 96 50 60 1000 134 86 50 35 29 80 60 50 1050 145 95 55 40 32 32 150 20 1500 225 130 80 58 50 16 300 10 1950 308 175 110 83 73 5 960 3.125 4000 590 330 200 150 133 2 2400 1.25 56,600 7000 3500 1800 900 490 1 4800 0.625 442,000 55,000 28,000 14,000 7000 3450 Table 9. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word Output Data Settling 1 1 1 1 1 1 (Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 4.7 639.4 24 (22.5) 24 (22) 24 (22) 24 (21.5) 24 (21) 23 (20.5) 640 7.5 400 24 (22) 24 (22) 24 (21.5) 24 (21.5) 23.5 (21) 22.5 (20) 480 10 300 24 (22) 24 (21.5) 24 (21.5) 24 (21) 23.5 (20.5) 22.5 (20) 96 50 60 23.5 (20.5) 23 (20.5) 23 (20) 22.5 (20) 22 (19.5) 21.5 (18.5) 80 60 50 23 (20.5) 23 (20.5) 22.5 (20) 22.5 (19.5) 22 (19) 21 (18.5) 32 150 20 22.5 (20) 22.5 (19.5) 22 (19.5) 22 (19) 21.5 (18.5) 20.5 (18) 16 300 10 22.5 (19.5) 22 (19) 22 (19) 21.5 (18.5) 21 (18) 20 (17.5) 5 960 3.125 21.5 (18.5) 21 (18.5) 21 (18) 20.5 (18) 20 (17.5) 19 (16.5) 2 2400 1.25 17.5 (14.5) 17.5 (14.5) 17.5 (14.5) 17.5 (14.5) 17.5 (14.5) 17.5 (14.5) 1 4800 0.625 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. B | Page 16 of 40 AD7190 4 SINC CHOP ENABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 1.175 1702 177 27 15 8.5 7 6 640 1.875 1067 219 32 18 11.5 8.5 7.5 480 2.5 800 234 36 21 13 10 8.5 96 12.5 160 637 89 55 32 24 20 80 15 133 686 99 63 37 26 22 32 37.5 53 1033 152 89 53 39 34 16 75 26.7 1343 202 120 71 53 48 5 240 8.33 2121 340 198 124 99 86 2 600 3.33 3536 552 311 198 156 140 1 1200 1.67 10,200 1360 707 389 26 209 Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word Output Data Settling 1 1 1 1 1 1 (Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 1.175 1702 24 (23) 24 (22.5) 24 (22.5) 24 (22.5) 24 (21.5) 23.5 (21) 640 1.875 1067 24 (22.5) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23.5 (20.5) 480 2.5 800 24 (22.5) 24 (22.5) 24 (22) 24 (22) 24 (21) 23 (20.5) 96 12.5 160 24 (21) 24 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 80 15 133 24 (21) 23.5 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 32 37.5 53 23 (20.5) 23 (20) 23 (20) 22.5 (20) 22 (19) 21 (18.5) 16 75 26.7 23 (20) 22.5 (20) 22.5 (19.5) 22 (19.5) 21.5 (19) 20.5 (18) 5 240 8.33 22 (19.5) 22 (19) 21.5 (19) 21.5 (18.5) 20.5 (18) 20 (17) 2 600 3.33 21.5 (18.5) 21 (18.5) 21 (18) 20.5 (18) 20 (17) 19 (16.5) 1 1200 1.67 20 (17) 20 (17) 20 (17) 19.5 (17) 19 (16.5) 18.5 (16) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. B | Page 17 of 40 AD7190 3 SINC CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 1.56 1282 191 30 16.5 10 8 6.5 640 2.5 800 226 36 19 12 9 8.5 480 3.33 600 248 43 25 14 11 9 96 16.6 120 708 95 61 36 25 21 80 20 100 743 103 68 39 29 23 32 50 40 1061 159 92 57 41 36 16 100 20 1380 218 124 78 59 52 5 320 6.25 2829 418 234 142 106 94 2 800 2.5 40,100 4950 2475 1273 637 347 1 1600 1.25 312,550 38,540 19,800 9900 4950 2440 Table 13. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word Output Data Settling 1 1 1 1 1 1 (Decimal) Rate (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 1.56 1282 24 (23) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23.5 (21) 640 2.5 800 24 (22.5) 24 (22.5) 24 (22) 24 (22) 24 (21.5) 23 (20.5) 480 3.33 600 24 (22.5) 24 (22) 24 (22) 24 (21.5) 24 (21) 23 (20.5) 96 16.6 120 24 (21) 23.5 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 80 20 100 23.5 (21) 23.5 (21) 23 (20.5) 23 (20) 22.5 (19.5) 21.5 (19) 32 50 40 23 (20.5) 23 (20) 22.5 (20) 22.5 (19.5) 22 (19) 21 (18.5) 16 100 20 23 (20) 22.5 (19.5) 22.5 (19.5) 22 (19) 21.5 (18.5) 20.5 (18) 5 320 6.25 22 (19) 21.5 (19) 21.5 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 2 800 2.5 18 (15) 18 (15) 18 (15) 18 (15) 18 (15) 18 (15) 1 1600 1.25 15 (12) 15 (12.5) 15 (12) 15 (12) 15 (12) 15 (12) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. B | Page 18 of 40 AD7190 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip interface returns to where it expects a write operation to registers, which are described in the following sections. In the the communications register. This is the default state of the descriptions, set implies a Logic 1 state and cleared implies a interface and, on power-up or after a reset, the ADC is in this Logic 0 state, unless otherwise noted. default state waiting for a write operation to the communi- cations register. In situations where the interface sequence is COMMUNICATIONS REGISTER lost, a write operation of at least 40 serial clock cycles with DIN (RS2, RS1, RS0 = 0, 0, 0) high returns the ADC to this default state by resetting the entire The communications register is an 8-bit write-only register. All part. Table 14 outlines the bit designations for the communications to the part must start with a write operation to communications register. CR0 through CR7 indicate the bit the communications register. The data written to the communi- locations, CR denoting that the bits are in the communications cations register determines whether the next operation is a read register. CR7 denotes the first bit of the data stream. The or write operation and in which register this operation takes number in parentheses indicates the power-on/reset default place. For read or write operations, when the subsequent read status of that bit. or write operation to the selected register is complete, the CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN(0) R/W(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0) Table 14. Communications Register Bit Designations Bit Location Bit Name Description CR7 WEN Write enable bit. A 0 must be written to this bit for a write to the communications register to occur. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. CR6 R/W A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a read from the designated register. CR5 to CR3 RS2 to RS0 Register address bits. These address bits are used to select which registers of the ADC are selected during the serial interface communication. See Table 15. CR2 CREAD Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, the instruction 01011100 must be written to the communications register. To disable continuous read, the instruction 01011000 must be written to the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low until an instruction is to be written to the device. CR1 to CR0 These bits must be programmed to Logic 0 for correct operation. Table 15. Register Selection RS2 RS1 RS0 Register Register Size 0 0 0 Communications register during a write operation 8 bits 0 0 0 Status register during a read operation 8 bits 0 0 1 Mode register 24 bits 0 1 0 Configuration register 24 bits 0 1 1 Data register/data register plus status information 24 bits/32 bits 1 0 0 ID register 8 bits 1 0 1 GPOCON register 8 bits 1 1 0 Offset register 24 bits 1 1 1 Full-scale register 24 bits Rev. B | Page 19 of 40 AD7190 STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80) The status register is an 8-bit, read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 16 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY(1) ERR(0) NOREF(0) Parity(0) 0(0) CHD2(0) CHD1(0) CHD0(0) Table 16. Status Register Bit Designations Bit Location Bit Name Description SR7 RDY Ready bit for the ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register is read, or a period of time before the data register is updated with a new conversion result, to indicate to the user that the conversion data should not be read. It is also set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC error bit. This bit is written to at the same time as the RDY bit. The ERR bit is set to indicate that the result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange or underrange or the absence of a reference voltage. The bit is cleared by a write operation to start a conversion. SR5 NOREF No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled by setting the REFDET bit in the configuration register to 1. SR4 Parity Parity check of the data register. If the ENPAR bit in the mode register is set, the parity bit is set if there is an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. SR3 0 This bit will be set to 0. SR2 to SR0 CHD2 to These bits indicate which channel corresponds to the data register contents. They do not indicate which CHD0 channel is presently being converted but indicate which channel was selected when the conversion contained in the data register was generated. MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060) The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the output data rate, and the clock source. Table 17 outlines the bit designations for the mode register. MR0 through MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and RDY filter and sets the bit. MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16 MD2(0) MD1(0) MD0(0) DAT_STA(0) CLK1(1) CLK0(0) 0 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 Sinc3(0) 0 ENPAR(0) 0 Single(0) REJ60(0) FS9(0) FS8(0) MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 FS7(0) FS6(1) FS5(1) FS4(0) FS3(0) FS2(0) FS1(0) FS0(0) Rev. B | Page 20 of 40 AD7190 Table 17. Mode Register Bit Designations Bit Location Bit Name Description MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7190 (see Table 18). MR20 DAT_STA This bit enables the transmission of status register contents after each data register read. When DAT_STA is set, the contents of the status register are transmitted along with each data register read. This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds. MR19 to MR18 CLK1 to CLK0 These bits are used to select the clock source for the AD7190. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7190 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7190. CLK1 CLK0 ADC Clock Source 0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2. 0 1 External clock. The external clock is applied to the MCLK2 pin. 1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated. 1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2. MR17 to MR16 These bits must be programmed with a Logic 0 for correct operation. 3 4 MR15 SINC3 Sinc filter select bit. When this bit is cleared, the sinc filter is used (default value). When this bit is set, 3 3 4 the sinc filter is used. The benefit of the sinc filter compared to the sinc filter is its lower settling time 3 when chop is disabled. For a given output data rate, f , the sinc filter has a settling time of 3/f ADC ADC 4 4 while the sinc filter has a settling time of 4/fADC. The sinc filter, due to its deeper notches, gives better 50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no 4 missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc 3 filter gives better performance than the sinc filter for rms noise and no missing codes. MR14 This bit must be programmed with a Logic 0 for correct operation. MR13 ENPAR Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. MR12 This bit must be programmed with a Logic 0 for correct operation. MR11 Single Single cycle conversion enable bit. When this bit is set, the AD7190 settles in one conversion cycle so that it functions as a zero latency ADC. This bit has no affect when multiple analog input channels are enabled or when the single conversion mode is selected. MR10 REJ60 This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/60 Hz rejection. MR9 to MR0 FS9 to FS0 Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter cutoff frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, it also determines the output noise (and, therefore, the effective resolution) of the device. (see Table 6 through Table 13) When chop is disabled and continuous conversion mode is selected, the output data rate equals Output Data Rate = (fmod/64)/FS where FS is the decimal equivalent of the code in bits FS0 to FS9 and is in the range 1 to 1023, and fmod is the modulator frequency, which is equal to MCLK/16. With a nominal MCLK of 4.92 MHz, this results in a output data rate from 4.69 Hz to 4.8 kHz. With chop disabled, the filter first notch frequency is equal to the output data rate when converting on a single channel. When chop is enabled, the output data rate equals Output Data Rate = (fmod/64)/(N × FS) where: FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023. fmod is the modulator frequency, which is equal to MCLK/16. With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The sinc filter’s first notch frequency is equal to N × Output Data Rate. The chopping introduces notches at odd integer multiples of (Output Data Rate/2). Rev. B | Page 21 of 40 AD7190 Table 18. Operating Modes MD2 MD1 MD0 Mode 0 0 0 Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/ RDY pin and the RDY bit in the status register go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the communications register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are available at the selected output data rate, which is dependent on filter choice. 0 0 1 Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed. 0 1 0 Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are still provided. 0 1 1 Power-down mode. In power-down mode, all AD7190 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7190 for settling reasons. The external crystal, if selected, remains active. 1 0 0 Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. 1 0 1 Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the full- scale error. 1 1 0 System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required each time the gain of a channel is changed. 1 1 1 System full-scale calibration. The user should connect the system full-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed. CONFIGURATION REGISTER (RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117) The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel. Table 19 outlines the bit designations for the configuration register. CON0 through CON23 indicate the bit locations. CON denotes that the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power- on/reset default status of that bit. Rev. B | Page 22 of 40 AD7190 CON23 CON22 CON21 CON20 CON19 CON18 CON17 CON16 Chop(0) 0(0) 0(0) REFSEL(0) 0(0) 0(0) 0(0) (0) CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8 CH7(0) CH6(0) CH5(0) CH4(0) CH3(0) CH2(0) CH1(0) CH0(1) CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0 Burn(0) REFDET(0) 0(0) BUF(1) U/B (0) G2(1) G1(1) G0(1) Table 19. Configuration Register Bit Designations Bit Location Bit Name Description CON23 Chop Chop enable bit. When the chop bit is cleared, chop is disabled. When the chop bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously minimized. However, this increases the conversion time and settling time of the ADC. For example, when FS = 96 4 decimal and the sinc filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of 4 96 decimal and the sinc filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. CON22, CON21 These bits must be programmed with a Logic 0 for correct operation. CON20 REFSEL Reference select bits. The reference source for the ADC is selected using these bits. REFSEL Reference Voltage 0 External reference applied between REFIN1(+) and REFIN1(−). 1 External reference applied between the P1/REFIN2(+) and P0/REFIN2(-) pins. CON19 to CON16 These bits must be programmed with a Logic 0 for correct operation. CON15 to CON8 CH7 to CH0 Channel select bits. These bits are used to select which channels are enabled on the AD7190. See Table 20. Several channels can be selected, and the AD7190 automatically sequences them. The conversion on each channel requires the complete settling time. CON7 Burn When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When burn = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and when chop is disabled. CON6 REFDET Enables the reference detect function. When set, the NOREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference detect circuitry only operates when the ADC is active. CON5 This bit must be programmed with a Logic 0 for correct operation. CON4 BUF Enables the buffer on the analog inputs. If cleared, the analog inputs are unbuffered, lowering the power consumption of the device. If set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. With the buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AV . DD When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin must be limited to 250 mV within the power supply rails. CON3 U/B Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar operation is selected. CON2 to CON0 G2 to G0 Gain select bits. Written by the user to select the ADC input range as follows: G2 G1 G0 Gain ADC Input Range (5 V Reference, Bipolar Mode) 0 0 0 1 ±5 V 0 0 1 Reserved 0 1 0 Reserved 0 1 1 8 ±625 mV 1 0 0 16 ±312.5 mV 1 0 1 32 ±156.2 mV 1 1 0 64 ±78.125 mV 1 1 1 128 ±39.06 mV Rev. B | Page 23 of 40 AD7190 Table 20. Channel Selection Channel Enable Bits in the Configuration Register Channel Enabled Positive Input Negative Input Status Register Calibration CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 AIN(+) AIN(−) Bits CHD[2:0] Register Pair 1 AIN1 AIN2 000 0 1 AIN3 AIN4 001 1 1 Temperature sensor 010 None 1 AIN2 AIN2 011 0 1 AIN1 AINCOM 100 0 1 AIN2 AINCOM 101 1 1 AIN3 AINCOM 110 2 1 AIN4 AINCOM 111 3 ID REGISTER DATA REGISTER RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xX4 (RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000) The identification number for the AD7190 is stored in the ID The conversion result from the ADC is stored in this data register. This is a read-only register. register. This is a read-only, 24-bit register. On completion of a read operation from this register, the RDY pin/bit is set. When GPOCON REGISTER the DAT_STA bit in the mode register is set to 1, the contents of (RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00) the status register are appended to each 24-bit conversion. This The GPOCON register is an 8-bit register from which data can is advisable when several analog input channels are enabled be read or to which data can be written. This register is used to because the three LSBs of the status register (CHD2 to CHD0) enable the general-purpose digital outputs. identify the channel from which the conversion originated. Table 21 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are in the GPOCON register. GP7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Rev. B | Page 24 of 40 AD7190 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0(0) BPDSW(0) GP32EN(0) GP10EN(0) P3DAT(0) P2DAT(0) P1DAT(0) P0DAT(0) Table 21. Register Bit Designations Bit Location Bit Name Description GP7 0 This bit must be programmed with a Logic 0 for correct operation. GP 6 BPDSW Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge power- down switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active. GP5 GP32EN Digital Output P3 and Digital Output P2 enable. When GP32EN is set, the digital outputs, P3 and P2, are active. When GP32EN is cleared, the P3 and P2 pins are tristated, and the P3DAT and P2DAT bits are ignored. GP4 GP10EN Digital Output P1 and Digital Output P0 enable. When GP10EN is set, the digital outputs, P1 and P0, are active. When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are ignored. The P1 and P0 pins can be used as a reference input REFIN2 when the REFSEL bit in the configuration register is set to 1. GP3 P3DAT Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin. When P3DAT is high, the P3 output pin is high. When P3DAT is low, the P3 output pin is low. When the GPOCON register is read, the P3DAT bit reflects the status of the P3 pin if GP32EN is set. GP2 P2DAT Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin. When P2DAT is high, the P2 output pin is high. When P2DAT is low, the P2 output pin is low. When the GPOCON register is read, the P2DAT bit reflects the status of the P2 pin if GP32EN is set. GP1 P1DAT Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin. When P1DAT is high, the P1 output pin is high. When P1DAT is low, the P1 output pin is low. When the GPOCON register is read, the P1DAT bit reflects the status of the P1 pin if GP10EN is set. GP0 P0DAT Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin. When P0DAT is high, the P0 output pin is high. When P0DAT is low, the P0 output pin is low. When the GPOCON register is read, the P0DAT bit reflects the status of the P0 pin if GP10EN is set. OFFSET REGISTER FULL-SCALE REGISTER (RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000) (RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0) The offset register holds the offset calibration coefficient for the The full-scale register is a 24-bit register that holds the full-scale ADC. The power-on reset value of the offset register is 0x800000. calibration coefficient for the ADC. The AD7190 has four full- The AD7190 has four offset registers; therefore, each channel scale registers; therefore, each channel has a dedicated full-scale has a dedicated offset register. Each of these registers is a 24-bit register. The full-scale registers are read/write registers. However, read/write register. This register is used in conjunction with its when writing to the full-scale registers, the ADC must be placed associated full-scale register to form a register pair. The power- in power-down mode or idle mode. These registers are configured on reset value is automatically overwritten if an internal or at power-on with factory-calibrated, full-scale calibration coef- system zero-scale calibration is initiated by the user. The AD7190 ficients, the calibration being performed at gain = 1. Therefore, must be placed in power-down mode or idle mode when writing every device has different default coefficients. The default value to the offset register. is automatically overwritten if an internal or system full-scale calibration is initiated by the user or if the full-scale register is written to. Rev. B | Page 25 of 40 AD7190 ADC CIRCUIT INFORMATION 5V AGND AV DV DGND DD DD REFIN1(+) REFERENCE DETECT IN+ AV AIN1 DD AIN2 OUT+ OUT– AIN3 DOUT/RDY AIN4 SERIAL INTERFACE AINCOM MUX DIN Σ-Δ PGA AND IN– ADC CONTROL SCLK LOGIC CS SYNC AGND TEMP P3 REFIN1(–) SENSOR P2 BPDSW CLOCK AD7190 CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) Figure 18. Basic Connection Diagram where: OVERVIEW f is the output data rate. ADC The AD7190 is an ultralow noise ADC that incorporates a fCLK = master clock (4.92 MHz nominal). ∑-Δ modulator, a buffer, PGA, and on-chip digital filtering FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the intended for the measurement of wide dynamic range signals mode register. such as those in pressure transducers, weigh scales, and strain gauge applications. The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. The part can be configured to have two differential inputs or four 3 4 The previous equation is valid for both the sinc and sinc pseudo differential inputs that can be buffered or unbuffered. 4 filters. The settling time for the sinc filter is equal to Figure 18 shows the basic connections required to operate the part. = 4/f tSETTLE ADC FILTER, OUTPUT DATA RATE, SETTLING TIME 3 A ∑-Δ ADC consists of a modulator followed by a digital filter. Whereas the settling time for the sinc filter is equal to 3 4 The AD7190 has two filter options: a sinc filter and a sinc tSETTLE = 3/fADC filter. The filter is selected using the SINC3 bit in the mode 4 Figure 19 and Figure 20 show the frequency response of the sinc 4 register. When SINC3 is set to 0 (default value), the sinc filter is 3 and sinc filters, respectively, for an output data rate of 50 Hz. 3 selected. The sinc filter is selected when SINC3 is set to 1. 0 At low output data rates (<1 kHz), the noise-free resolution is –10 comparable for the two filter types. However, at the higher –20 4 output data rates, the sinc filter gives better noise free –30 resolution. 4 –40 The sinc filter also leads to better 50 Hz and 60 Hz rejection. –50 While the notch positions are not affected by the order of the filter, the higher order filter has wider notches, which leads to –60 better rejection in the band (±1 Hz) around the notches. It also –70 3 gives better stop-band attenuation. The benefit of the sinc filter –80 is its lower settling time for the same output data rate. –90 Chop Disabled –100 0 255075 100 125 150 The output data rate (the rate at which conversions are available FREQUENCY (Hz) on a single channel when the ADC is continuously converting) 4 Figure 19. Sinc Filter Response (50 Hz Output Data Rate) is equal to f = f /(1024 × FS[9:0]) ADC CLK Rev. B | Page 26 of 40 FILTER GAIN (dB) 07640-012 07640-013 AD7190 0 The value of FS[9:0] can be varied from 1 to 1023. This results 4 –10 in an output data rate of 1.173 Hz to 1200 Hz for the sinc filter 3 and 1.56 Hz to 1600 Hz for the sinc filter. The settling time for –20 3 4 the sinc or sinc filter is equal to –30 tSETTLE = 2/fADC –40 –50 Therefore, with chop enabled, the settling time is reduced for a given output data rate compared to the chop disabled mode. –60 However, for a given FS[9:0] value, the output data rate is less –70 with chop enabled compared with the chop disabled mode. –80 3 4 For either the sinc or the sinc filter, the cutoff frequency f is 3dB –90 equal to –100 0 255075 100 125 150 f3dB = 0.24 × fADC FREQUENCY (Hz) 4 3 Figure 21 and Figure 22 show the filter response for the sinc Figure 20. Sinc Filter Response (50 Hz Output Data Rate) 3 and sinc filters, respectively, when chop is enabled. As shown 4 The sinc filter provides 50 Hz (±1 Hz) rejection in excess of in the plots, the stop-band attenuation is less compared with the 3 120 dB, assuming a stable master clock, while the sinc filter chop disabled modes. gives a rejection of 100 dB. The stop-band attenuation is 0 4 typically 53 dB for the sinc filter but equal to 40 dB for the –10 3 sinc filter. –20 4 The 3 dB frequency for the sinc filter is equal to –30 f = 0.23 × f 3dB ADC –40 3 and for the sinc filter is equal to –50 f = 0.272 × f 3dB ADC –60 Chop Enabled –70 –80 With chop enabled, the ADC offset and offset drift are minimized. When chop is enabled, the analog input pins are –90 continuously swapped. Therefore, with the analog input pins –100 0 255075 100 125 150 connected in one direction, the settling time of the sinc filter is FREQUENCY (Hz) allowed to elapse until a valid conversion is available. The analog 4 Figure 21. Sinc Filter Response (Output Data Rate = 12.5 Hz, Chop Enabled) input pins are then inverted and another valid conversion is 0 obtained. Subsequent conversions are then averaged so that the –10 offset is minimized. This continuous swapping of the analog input pins and the averaging of subsequent conversions means –20 that the offset drift is also minimized. –30 Chopping affects the output data rate and settling time of the –40 4 ADC. For the sinc filter, the output data rate is equal to –50 fADC = fCLK/(4 × 1024 × FS[9:0]) –60 3 For sinc filter, the output data rate is equal to –70 –80 fADC = fCLK/(3 × 1024 × FS[9:0]) –90 where: –100 f is the output data rate. ADC 0 255075 100 125 150 f = master clock (4.92 MHz nominal). CLK FREQUENCY (Hz) FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the 3 Figure 22. Sinc Filter Response (Output Data Rate = 16.6 Hz, Chop Enabled) mode register. Rev. B | Page 27 of 40 FILTER GAIN (dB) 07640-014 FILTER GAIN (dB) FILTER GAIN (dB) 07640-016 07640-015 AD7190 50 Hz/60 Hz Rejection filter is used. Figure 25 and Figure 26 show the filter response for both output data rates when REJ60 is set to 1. Normal mode rejection is one of the main functions of the 0 digital filter. With chop disabled, 50 Hz rejection is obtained –10 when the output data rate is set to 50 Hz, whereas 60 Hz rejection is achieved when the output data rate is set to 60 Hz. –20 Simultaneous 50 Hz/60 Hz rejection is obtained when the –30 output data rate is set to 10 Hz. Simultaneous 50 Hz/60 Hz –40 rejection can also be achieved using the REJ60 bit in the mode –50 register. When the output data rate is programmed to 50 Hz and –60 the REJ60 bit is set to 1, notches are placed at both 50 Hz and 60 Hz. –70 –80 Figure 23 and Figure 24 show the frequency response of the 4 3 sinc and sinc filters, respectively, when the output data rate is –90 programmed to 50 Hz and REJ60 is set to 1. –100 0 255075 100 125 150 0 FREQUENCY (Hz) –10 4 Figure 25. Sinc Filter Response (12.5 Hz Output Data Rate, –20 Chop Enabled, REJ60 = 1) 0 –30 –10 –40 –20 –50 –30 –60 –40 –70 –50 –80 –60 –90 –70 –100 0 255075 100 125 150 –80 FREQUENCY (Hz) 4 –90 Figure 23. Sinc Filter Response (50 Hz Output Data Rate, REJ60 = 1) –100 0 0 255075 100 125 150 –10 FREQUENCY (Hz) 3 Figure 26. Sinc Filter Response (16.7 Hz Output Data Rate, –20 Chop Enabled, REJ60 = 1) –30 Zero Latency –40 Zero latency is enabled by setting the SINGLE bit in the mode –50 register to 1. With zero latency, the complete settling time is –60 allowed for each conversion. Therefore, –70 fADC = 1/tSETTLE –80 Zero latency means that the output data rate is constant –90 irrespective of the number of analog input channels enabled; –100 0 255075 100 125 150 the user does not need to consider the effects of channel FREQUENCY (Hz) changes on the output data rate. The disadvantages of zero 3 Figure 24. Sinc Filter Response (50 Hz Output Data Rate, REJ60 = 1) latency are the increased noise for a given output data rate 4 compared with the nonzero latency mode. For example, when Again, the sinc filter provides better 50 Hz/60 Hz rejection 3 zero latency is not enabled, the AD7190 has a noise-free than the sinc filter. In addition, better stop-band attenuation is 4 resolution of 18.5 bits when the output data rate is 50 Hz and achieved with the sinc filter. the gain is set to 128. When zero latency is enabled, the ADC When chop is enabled, lower output data rates must be used to has a resolution of 17.5 bits peak-to-peak when the output data achieve 50 Hz and 60 Hz rejection. With REJ60 set to 1, an output rate is 50 Hz. The filter response also changes. Figure 19 shows data rate of 12.5 Hz gives simultaneous 50 Hz/60 Hz rejection 4 the filter response for the sinc filter when the output data rate 4 when the sinc filter is selected, whereas an output data rate of is 50 Hz (zero latency disabled). Figure 27 shows the filter 3 16.7 Hz gives simultaneous 50 Hz/ 60 Hz rejection when the sinc response when zero latency is enabled and the output data rate Rev. B | Page 28 of 40 FILTER GAIN (dB) FILTER GAIN (dB) 07640-018 07640-017 FILTER GAIN (dB) FILTER GAIN (dB) 07640-126 07640-125 AD7190 4 4 is 50 Hz (sinc filter); 50 Hz rejection is no longer achieved. The For example, if the sinc filter is selected, chop is disabled and ADC needs to operate with an output data rate of 12.5 Hz to zero latency is disabled, conversions are available at 1/f when ADC obtain 50 Hz rejection when zero latency is enabled. To obtain converting on a single channel, where f is equal to the output ADC data rate. The settling time is equal to simultaneous 50 Hz/60 Hz rejection, the REJ60 bit in the mode register can be set when the output data rate is equal to 12.5 Hz. tSETTLE = 4/fADC The stop-band attenuation is considerably reduced also (3 dB The time required to sample N channels is compared with 53 dB in the nonzero latency mode). 4/(fADC × N) 0 –10 –20 RDY –30 CONVERSIONS CHANNEL A CHANNEL B CHANNEL C –40 1/f ADC –50 Figure 28. Channel Sequencer –60 –70 DIGITAL INTERFACE –80 As indicated in the On-Chip Registers section, the programmable –90 functions of the AD7190 are controlled using a set of on-chip –100 registers. Data is written to these registers via the serial interface 01 5000 150 200 250 300 350 400 450 500 550 600 of the part. Read access to the on-chip registers is also provided FREQUENCY (Hz) 4 by this interface. All communication with the part must start with Figure 27. Sinc Filter Response (50 Hz Output Data Rate, Zero Latency) a write to the communications register. After power-on or reset, Channel Sequencer the device expects a write to its communications register. The data The AD7190 includes a channel sequencer, which simplifies written to this register determines whether the next operation is a communications with the device in multichannel applications. read operation or a write operation and also determines which The sequencer also optimizes the channel throughput of the register this read or write operation affects. Therefore, write device as the sequencer switches channels at the optimum rate access to any of the other registers on the part begins with a write rather than waiting for instructions via the SPI interface. operation to the communications register, followed by a write to the selected register. A read operation from any other register Bits CH0 to Bit CH7 in the configuration register are used to (except when continuous read mode is selected) starts with a write enable the required channels. In continuous conversion mode, to the communications register, followed by a read operation from the ADC selects each of the enabled channels in sequence and the selected register. performs a conversion on the channel. The RDY pin goes low when a valid conversion is available on each channel. When CS The serial interface of the AD7190 consists of four signals: , several channels are enabled, the contents of the status register DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer should be attached to the 24-bit word so that the user can data into the on-chip registers, whereas DOUT/RDY is used for identify the channel that corresponds to each conversion. To accessing data from the on-chip registers. SCLK is the serial clock attach the status register value to the conversion, Bit DAT_STA input for the device, and all data transfers (either on DIN or in the mode register should be set to 1. RDY DOUT/ ) occur with respect to the SCLK signal. When several channels are enabled, the ADC must allow the RDY The DOUT/ pin functions as a data ready signal also, the complete settling time to generate a valid conversion each time line going low when a new data-word is available in the output that the channel is changed. The AD7190 takes care of this: register. It is reset high when a read operation from the data when a channel is selected, the modulator and filter are reset register is complete. It also goes high prior to the updating of the and the pin is taken high. The AD7190 then allows the RDY data register to indicate when not to read from the device, to complete settling time to generate the first conversion. ensure that a data read is not attempted while the register is being CS only goes low when a valid conversion is available. The updated. is used to select a device. It can be used to decode the RDY AD7190 in systems where several components are connected to AD7190 then selects the next enabled channel and converts on the serial bus. that channel. The user can then read the data register while the ADC is performing the conversion on the next channel. The time required to read a valid conversion from all enabled channels is equal to t × Number of Enabled Channels SETTLE Rev. B | Page 29 of 40 FILTER GAIN (dB) 07640-020 07640-019 AD7190 Figure 3 and Figure 4 show timing diagrams for interfacing to the The AD7190 can be configured to continuously convert or to CS perform a single conversion. See Figure 29 through Figure 31. AD7190, with being used to decode the part. Figure 3 shows the timing for a read operation from the output shift register of Single Conversion Mode the AD7190, and Figure 4 shows the timing for a write operation In single conversion mode, the AD7190 is placed in power- to the input shift register. It is possible to read the same word down mode after conversions. When a single conversion is from the data register several times even though the DOUT/RDY initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively, line returns high after the first read operation. However, care in the mode register, the AD7190 powers up, performs a single must be taken to ensure that the read operations have been com- conversion, and then returns to power-down mode. The pleted before the next output update occurs. In continuous read on-chip oscillator requires 1 ms approximately to power up. mode, the data register can be read only once. DOUT/RDY goes low to indicate the completion of a conversion. CS The serial interface can operate in 3-wire mode by tying low. When the data word has been read from the data register, In this case, the SCLK, DIN, and DOUT/RDY lines are used to DOUT/RDY goes high. If CS is low, DOUT/RDY remains high communicate with the AD7190. The end of the conversion can be until another conversion is initiated and completed. The data monitored using the RDY bit or pin. This scheme is suitable for register can be read several times, if required, even when interfacing to microcontrollers. RDY DOUT/ has gone high. CS If is required as a decoding signal, it can be generated from a If several channels are enabled, the ADC sequences through the port pin. For microcontroller interfaces, it is recommended that enabled channels and performs a conversion on each channel. SCLK idle high between data transfers. When a conversion is started, DOUT/RDY goes high and CS The AD7190 can be operated with used as a frame synchron- remains high until a valid conversion is available. As soon as the ization signal. This scheme is useful for DSP interfaces. In this conversion is available, DOUT/ goes low. The ADC then RDY case, the first bit (MSB) is effectively clocked out by CS because selects the next channel and begins a conversion. The user can CS normally occurs after the falling edge of SCLK in DSPs. The read the present conversion while the next conversion is being SCLK can continue to run between data transfers, provided the performed. As soon as the next conversion is complete, the data timing numbers are obeyed. register is updated; therefore, the user has a limited period in which to read the conversion. When the ADC has performed a The serial interface can be reset by writing a series of 1s to the single conversion on each of the selected channels, it returns to DIN input. If a Logic 1 is written to the AD7190 DIN line for at power-down mode. least 40 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets If the DAT_STA bit in the mode register is set to 1, the contents lost due to a software error or some glitch in the system. Reset of the status register are output along with the conversion each returns the interface to the state in which it is expecting a write to time that the data read is performed. The four LSBs of the status the communications register. This operation resets the contents of register indicate the channel to which the conversion corresponds. all registers to their power-on values. Following a reset, the user should allow a period of 500 μs before addressing the serial interface. CS 0x08 0x280060 0x58 DIN DATA DOUT/RDY SCLK Figure 29. Single Conversion Rev. B | Page 30 of 40 07640-021 AD7190 Continuous Conversion Mode When several channels are enabled, the ADC continuously loops through the enabled channels, performing one conversion Continuous conversion is the default power-up mode. The on each channel per loop. The data register is updated as soon AD7190 converts continuously, the RDY bit in the status as each conversion is available. The DOUT/RDY pin pulses low register going low each time a conversion is complete. If CS is each time a conversion is available. The user can then read the low, the DOUT/RDY line also goes low when a conversion is conversion while the ADC converts on the next enabled channel. completed. To read a conversion, the user writes to the com- If the DAT_STA bit in the mode register is set to 1, the contents munications register, indicating that the next operation is a read of the status register are output along with the conversion each of the data register. When the data word has been read from the time that the data read is performed. The status register indicates RDY data register, DOUT/ goes high. The user can read this the channel to which the conversion corresponds. register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion or else the new conversion word is lost. CS 0x58 0x58 DIN DATA DATA DOUT/RDY SCLK Figure 30. Continuous Conversion Rev. B | Page 31 of 40 07640-022 AD7190 Continuous Read conversion is complete and the new conversion is placed in the output serial register. Rather than write to the communications register each time a conversion is complete to access the data, the AD7190 can be To exit the continuous read mode, the instruction 01011000 configured so that the conversions are placed on the DOUT/ must be written to the communications register while the RDY line automatically. By writing 01011100 to the commun- RDY pin is low. While in the continuous read mode, the ADC ications register, the user need only apply the appropriate monitors activity on the DIN line so that it can receive the number of SCLK cycles to the ADC, and the conversion word instruction to exit the continuous read mode. Additionally, a RDY is automatically placed on the DOUT/ line when a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, conversion is complete. The ADC should be configured for DIN should be held low in continuous read mode until an instruction is to be written to the device. continuous conversion mode. When several channels are enabled, the ADC continuously When DOUT/RDY goes low to indicate the end of a conversion, steps through the enabled channels and performs one con- sufficient SCLK cycles must be applied to the ADC; the data version on each channel each time that it is selected. DOUT/ RDY conversion is then placed on the DOUT/ line. When the RDY pulses low when a conversion is available. When the user RDY conversion is read, DOUT/ returns high until the next applies sufficient SCLK pulses, the data is automatically placed conversion is available. In this mode, the data can be read only RDY on the DOUT/ pin. If the DAT_STA bit in the mode once. Also, the user must ensure that the data-word is read register is set to 1, the contents of the status register are output before the next conversion is complete. If the user has not read along with the conversion. The status register indicates the the conversion before the completion of the next conversion, channel to which the conversion corresponds. or if insufficient serial clocks are applied to the AD7190 to read the word, the serial output register is reset when the next CS 0x5C DIN DATA DATA DATA DOUT/RDY SCLK Figure 31. Continuous Read Rev. B | Page 32 of 40 07640-023 AD7190 CIRCUIT DESCRIPTION The analog input range must be limited to (AVDD − 1.25 V)/gain ANALOG INPUT CHANNEL because the PGA requires some headroom. Therefore, if AVDD = The AD7190 has two differential/four pseudo differential analog 5 V, the maximum analog input that can be applied to the input channels which can be buffered or unbuffered. In buffered AD7190 is 0 to 3.75 V/gain in unipolar mode or ±3.75 V/ gain mode (the BUF bit in the configuration register is set to 1), the in bipolar mode. input channel feeds into a high impedance input stage of the BIPOLAR/UNIPOLAR CONFIGURATION buffer amplifier. Therefore, the input can tolerate significant The analog input to the AD7190 can accept either unipolar or source impedances and is tailored for direct connection to bipolar input voltage ranges. A bipolar input range does not external resistive-type sensors such as strain gauges or resistance imply that the part can tolerate negative voltages with respect temperature detectors (RTDs). to system AGND. In pseudo-differential mode, signals are When BUF = 0, the part is operated in unbuffered mode. This referenced to AINCOM while in differential mode, signals are results in a higher analog input current. Note that this unbuffered referenced to the negative input of the differential pair. For input path provides a dynamic load to the driving source. example, if AINCOM is 2.5 V and the AD7190 AIN1 analog Therefore, resistor/capacitor combinations on the input pins input is configured for unipolar mode with a gain of 2, the input can cause gain errors, depending on the output impedance of voltage range on the AIN1 pin is 2.5 V to 3.75 V when a 2.5 V the source that is driving the ADC input. Table 22 shows the reference is used. If AINCOM is 2.5 V and the AD7190 AIN1 allowable external resistance/capacitance values for unbuffered analog input is configured for bipolar mode with a gain of 2, the mode at a gain of 1 such that no gain error at the 20-bit level is analog input range on AIN1 is 1.25 V to 3.75 V. introduced. B The bipolar/unipolar option is chosen by programming the U/ Table 22. External R-C Combination for No 20-Bit Gain Error bit in the configuration register. C (pF) R (Ω) DATA OUTPUT CODING 50 1.4 k 100 850 When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input 500 300 1000 230 voltage resulting in a code of 00...00, a midscale voltage resulting 5000 30 in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage The absolute input voltage range in buffered mode is restricted can be represented as to a range between AGND + 250 mV and AVDD – 250 mV. Care N Code = (2 × AIN × gain)/V must be taken in setting up the common-mode voltage so that REF these limits are not exceeded. Otherwise, there is degradation in When the ADC is configured for bipolar operation, the output linearity and noise performance. code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting The absolute input voltage in unbuffered mode includes the range between AGND – 50 mV and AV + 50 mV. The in a code of 100...000, and a positive full-scale input voltage DD resulting in a code of 111...111. The output code for any analog negative absolute input voltage limit does allow the possibility input voltage can be represented as of monitoring small true bipolar signals with respect to AGND. N – 1 Code = 2 × [(AIN × gain/VREF) + 1] PGA where: When the gain stage is enabled, the output from the buffer is AIN is the analog input voltage. applied to the input of the programmable gain array (PGA). gain is the PGA setting (1 to 128). The presence of the PGA means that signals of small amplitude N = 24. can be gained within the AD7190 while still maintaining excel- lent noise performance. For example, when the gain is set to CLOCK 128, the rms noise is 8.5 nV, typically, when the output data rate The AD7190 includes an internal 4.92 MHz clock on-chip. This is 4.7 Hz, which is equivalent to 23 bits of effective resolution or internal clock has a tolerance of ±4%. Either the internal clock 20.5 bits of noise-free resolution. or an external crystal/clock can be used as the clock source to The AD7190 can be programmed to have a gain of 1, 8, 16, 32, the AD7190. The clock source is selected using the CLK1 and 64, and 128 using Bit G2 to Bit G0 in the configuration register. CLK0 bits in the mode register. When an external crystal is Therefore, with an external 2.5 V reference, the unipolar ranges used, it must be connected across the MCLK1 and MCLK2 are from 0 mV to 19.53 mV to 0 V to 2.5 V, and the bipolar pins. The crystal manufacturer recommends the load capaci- ranges are from ±19.53 mV to ±2.5 V. tances required for the crystal. The MCLK1 and MCLK2 pins of the AD7190 have a capacitance of 15 pF, typically. If an external Rev. B | Page 33 of 40 AD7190 clock source is used, the clock source must be connected to the or current) for the transducer on the analog input also drives MCLK2 pin and the MCLK1 pin must be left floating. the reference voltage for the part, the effect of the low frequency noise in the excitation source is removed because the application is The internal clock can also be made available at the MCLK2 ratiometric. If the AD7190 is used in a nonratiometric applica- pin. This is useful when several ADCs are used in an application tion, use a low noise reference. and the devices need to be synchronized. The internal clock from one device can be used as the clock source for all ADCs Recommended 2.5 V reference voltage sources for the AD7190 in the system. Using a common clock, the devices can be syn- include the ADR421 and ADR431, which are low noise chronized by applying a common reset to all devices, or the references. Also note that the reference inputs provide a high pin can be pulsed. impedance, dynamic load. Because the input impedance of each SYNC reference input is dynamic, resistor/capacitor combinations on BURNOUT CURRENTS these inputs can cause dc gain errors, depending on the output The AD7190 contains two 500 nA constant current generators, impedance of the source driving the reference inputs. one sourcing current from AV to AIN(+) and one sinking DD Reference voltage sources like those previously recommended current from AIN(−) to AGND, where AIN(+) is the positive (for example, ADR431) typically have low output impedances analog input terminal and AIN(−) is the negative analog input and are, therefore, tolerant to having decoupling capacitors on terminal in differential mode and AINCOM in pseudo- REFINx(+) without introducing gain errors in the system. differential mode. The currents are switched to the selected Deriving the reference input voltage across an external resistor analog input pair. Both currents are either on or off, depending means that the reference input sees a significant external source on the burnout current enable (burn) bit in the configuration impedance. External decoupling on the REFINx pins is not register. These currents can be used to verify that an external recommended in this type of circuit configuration. transducer remains operational before attempting to take REFERENCE DETECT measurements on that channel. After the burnout currents are turned on, they flow in the external transducer circuit, and a The AD7190 includes on-chip circuitry to detect whether the measurement of the input voltage on the analog input channel part has a valid reference for conversions or calibrations. This can be taken. It will take some time for the burnout currents to feature is enabled when the REFDET bit in the configuration detect an open circuit condition as the currents will need to register is set to 1. If the voltage between the selected REFINx(+) charge any external capacitors and REFINx(–) pins is between 0.3 V and 0.6 V, the AD7190 detects that it no longer has a valid reference. In this case, the There are several reasons why a fault condition can be detected. NOREF bit of the status register is set to 1. If the AD7190 is The front-end sensor may be open circuit. It could also mean performing normal conversions and the NOREF bit becomes that the front-end sensor is overloaded, or the reference may be active, the conversion result is all 1s. Therefore, it is not absent and the NOREF bit in the status register is set, thus necessary to continuously monitor the status of the NOREF bit clamping the data to all 1s. The user needs to check these three when performing conversions. It is only necessary to verify its cases before making a judgment. If the voltage measured is 0 V, status if the conversion result read from the ADC data register it may indicate that the transducer has short circuited. The is all 1s. If the AD7190 is performing either an offset or full- current sources work over the normal absolute input voltage scale calibration and the NOREF bit becomes active, the range specifications when the analog inputs are buffered and updating of the respective calibration registers is inhibited to chop is disabled. avoid loading incorrect coefficients to these registers, and the REFERENCE ERR bit in the status register is set. If the user is concerned The ADC has a fully differential input capability for the refer- about verifying that a valid reference is in place every time a ence channel. In addition, the user has the option of selecting calibration is performed, check the status of the ERR bit at the one of two external reference options (REFIN1(x) or REFIN2(x)). end of the calibration cycle. The reference source for the AD7190 is selected using the RESET REFSEL bit in the configuration register. The REFIN2(x) pins The circuitry and serial interface of the AD7190 can be reset are dual purpose: they can function as two general-purpose by writing consecutive 1s to the device; 40 consecutive 1s are output pins or as reference pins. When the REFSEL bit is set required to perform the reset. This resets the logic, the digital to 1, these pins automatically function as reference pins. filter, and the analog modulator, whereas all on-chip registers The common-mode range for these differential inputs is from are reset to their default values. A reset is automatically AGND to AVDD. The reference input is unbuffered; therefore, performed on power-up. When a reset is initiated, the user excessive R-C source impedances introduce gain errors. The must allow a period of 500 μs before accessing any of the reference voltage REFIN (REFINx(+) − REFINx(−)) is AVDD on-chip registers. A reset is useful if the serial interface loses nominal, but the AD7190 is functional with reference voltages synchronization due to noise on the SCLK line. from 1 V to AV . In applications where the excitation (voltage DD Rev. B | Page 34 of 40 AD7190 SYSTEM SYNCHRONIZATION TEMPERATURE SENSOR The SYNC input allows the user to reset the modulator and the Embedded in the AD7190 is a temperature sensor. This is selected using the CH2 bit in the configuration register. When digital filter without affecting any of the setup conditions on the the CH2 bit is set to 1, the temperature sensor is enabled. When part. This allows the user to start gathering samples of the analog the temperature sensor is selected and bipolar mode is selected, input from a known point in time, that is, the rising edge of the device should return a code of 0x800000 when the temper- SYNC SYNC . needs to be taken low for four master clock cycles ature is 0 K. A one-point calibration is needed to get the optimum to implement the synchronization function. performance from the sensor. Therefore, a conversion at 25°C If multiple AD7190 devices are operated from a common master should be recorded and the sensitivity calculated. The sensitivity clock, they can be synchronized so that their data registers are is approximately 2815 codes/°C. The equation for the temperature updated simultaneously. A falling edge on the SYNC pin resets sensor is the digital filter and the analog modulator and places the AD7190 Temp (K) = (Conversion – 0x800000)/2815 K SYNC into a consistent, known state. While the pin is low, the SYNC Temp (°C) = Temp (K) – 273 AD7190 is maintained in this state. On the rising edge, the modulator and filter are taken out of this reset state and, on Following the one point calibration, the internal temperature the next clock edge, the part starts to gather input samples again. sensor has an accuracy of ±2 °C, typically. In a system using multiple AD7190 devices, a common signal to BRIDGE POWER-DOWN SWITCH their SYNC pins synchronizes their operation. This is normally In bridge applications such as strain gauges and load cells, the done after each AD7190 has performed its own calibration or bridge itself consumes the majority of the current in the system. has had calibration coefficients loaded into its calibration For example, a 350 Ω load cell requires 15 mA of current when registers. The conversions from the AD7190s are then excited with a 5 V supply. To minimize the current consumption synchronized. of the system, the bridge can be disconnected (when it is not The part is taken out of reset on the master clock falling edge being used) using the bridge power-down switch. Figure 18 following the SYNC low-to-high transition. Therefore, when shows how the bridge power-down switch is used. The switch multiple devices are being synchronized, the SYNC pin should can withstand 30 mA of continuous current, and it has an on be taken high on the master clock rising edge to ensure that all resistance of 10 Ω maximum. devices begin sampling on the master clock falling edge. If the LOGIC OUTPUTS SYNC pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle between the devices; The AD7190 has four general-purpose digital outputs, P0, P1, that is, the instant at which conversions are available differs P2, and P3. These are enabled using the GP32EN and GP10EN from part to part by a maximum of one master clock cycle. bits in the GPOCON register. The pins can be pulled high or low using the P0DAT to P3DAT bits in the GPOCON register; The SYNC pin can also be used as a start conversion command. that is, the value at the pin is determined by the setting of the In this mode, the rising edge of SYNC starts conversion, and the P0DAT to P3DAT bits. The logic levels for these pins are falling edge of RDY indicates when the conversion is complete. determined by AVDD rather than by DVDD. When the GPOCON The disadvantage of this scheme is that the settling time of the register is read, the P0DAT to P3DAT bits reflect the actual filter has to be allowed for each data register update. This means value at the pins. This is useful for short-circuit detection. that the rate at which the data register is updated is reduced. For 4 These pins can be used to drive external circuitry, for example, example, if the ADC is configured to use the sinc filter, zero an external multiplexer. If an external multiplexer is used to latency is disabled and chop is disabled, the data register update increase the channel count, the multiplexer logic pins can be takes four times longer. controlled via the AD7190 general-purpose output pins. The general-purpose output pins can be used to select the active multiplexer pin. Because the operation of the multiplexer is independent of the AD7190, the AD7190 modulator and filter SYNC should be reset using the pin each time that the multi- plexer channel is changed. Rev. B | Page 35 of 40 AD7190 With chop disabled, both an internal zero-scale calibration and ENABLE PARITY a system zero-scale calibration require a time equal to the The AD7190 also has a parity check function on-chip that 4 settling time, t , (4/f for the sinc filter and 3/f for the SETTLE ADC ADC detects 1-bit errors in the serial communications between the 3 sinc filter). ADC and the microprocessor. When the ENPAR bit in the mode register is set to 1, parity is enabled. The contents of the With chop enabled, an internal zero-scale calibration is not status register must be transmitted along with each 24-bit needed because the ADC itself minimizes the offset continuously. conversion when the parity function is enabled. To append the However, if an internal zero-scale calibration is performed, the settling time, t (2/f ) is required to perform the calibra- contents of the status register to each conversion read, the SETTLE, ADC tion. Similarly, a system zero-scale calibration requires a time of DAT_STA bit in the mode register should be set to 1. For each t to complete. conversion read, the parity bit in the status register is SETTLE programmed so that the overall number of 1s transmitted in the To perform an internal full-scale calibration, a full-scale input 24-bit data-word is even. Therefore, for example, if the 24-bit voltage is automatically connected to the selected analog input conversion contains eleven 1s (binary format), the parity bit is for this calibration. For a gain of 1, the time required for an set to 1 so that the total number of 1s in the serial transmission is internal full-scale calibration is equal to tSETTLE. For higher gains, even. If the microprocessor receives an odd number of 1s, it the internal full-scale calibration requires a time of 2 × tSETTLE. knows that the data received has been corrupted. A full-scale calibration is recommended each time the gain of a channel is changed to minimize the full-scale error. The parity function only detects 1-bit errors. For example, two bits of corrupt data can result in the microprocessor receiving an A system full-scale calibration requires a time of t . With SETTLE even number of 1s. Therefore, an error condition is not detected. chop disabled, the zero-scale calibration (internal or system zero-scale) should be performed before the system full-scale CALIBRATION calibration is initiated. The AD7190 provides four calibration modes that can be pro- An internal zero-scale calibration, system zero-scale calibration grammed via the mode bits in the mode register. These modes and system full-scale calibration can be performed at any output are internal zero-scale calibration, internal full-scale calibration, data rate. An internal full-scale calibration can be performed at system zero-scale calibration, and system full-scale calibration. any output data rate for which the filter word FS[9:0] is divisible A calibration can be performed at any time by setting the MD2 by 16, FS[9:0] being the decimal equivalent of the 10-bit word to MD0 bits in the mode register appropriately. A calibration written to Bit FS9 to Bit FS0 in the mode register. Therefore, should be performed when the gain is changed. After each internal full-scale calibrations can be performed at output data conversion, the ADC conversion result is scaled using the ADC rates such as 10 Hz or 50 Hz when chop is disabled. Using these calibration registers before being written to the data register. lower output data rates results in better calibration accuracy. The offset calibration coefficient is subtracted from the result prior to multiplication by the full-scale coefficient. The offset error is, typically, 100 μV/gain. If the gain is changed, it is advisable to perform a calibration. A zero-scale calibration To start a calibration, write the relevant value to the MD2 to (an internal zero-scale calibration or system zero-scale RDY RDY MD0 bits. The DOUT/ pin and the bit in the status calibration) reduces the offset error to the order of the noise. register go high when the calibration is initiated. When the calibration is complete, the contents of the corresponding The gain error of the AD7190 is factory calibrated at a gain of 1 calibration registers are updated, the RDY bit in the status with a 5 V power supply at ambient temperature. Following this register is reset, the DOUT/ RDY pin returns low (if CS is low), calibration, the gain error is 0.001%, typically, at 5 V. Table 23 and the AD7190 reverts to idle mode. shows the typical uncalibrated gain error for the different gain settings. An internal full-scale calibration reduces the gain error During an internal zero-scale or full-scale calibration, the res- to 0.001%, typically, when the gain is equal to 1. For higher pective zero input and full-scale input are automatically connected gains, the gain error post internal full-scale calibration is internally to the ADC input pins. A system calibration, however, 0.0075%, typically. A system full-sale calibration reduces the expects the system zero-scale and system full-scale voltages to gain error to the order of the noise. be applied to the ADC pins before initiating the calibration mode. In this way, errors external to the ADC are removed. Table 23. Typical Precalibration Gain Error vs. Gain From an operational point of view, treat a calibration like Gain Precalibration Gain Error (%) another ADC conversion. A zero-scale calibration, if required, 8 −0.11 must always be performed before a full-scale calibration. Set the 16 −0.20 RDY system software to monitor the bit in the status register or 32 −0.23 RDY the DOUT/ pin to determine the end of calibration via a 64 −0.29 polling sequence or an interrupt-driven routine. 128 −0.39 Rev. B | Page 36 of 40 AD7190 The AD7190 gives the user access to the on-chip calibration pins to separate ground planes unless the ground planes are registers, allowing the microprocessor to read the calibration connected together near the AD7190. coefficients of the device and also to write its own calibration In systems in which the AGND and DGND are connected coefficients from prestored values in the EEPROM. A read of somewhere else in the system (that is, the power supply of the the registers can be performed at any time. However, the ADC system), they should not be connected again at the AD7190 must be placed in power-down or idle mode when writing to because a ground loop results. In these situations, it is the registers. The values in the calibration registers are 24-bits recommended that ground pins of the AD7190 be tied to the wide. The span and offset of the part can also be manipulated AGND plane. using the registers. In any layout, the user must keep in mind the flow of currents GROUNDING AND LAYOUT in the system, ensuring that the paths for all currents are as close as possible to the paths the currents took to reach their destin- Because the analog inputs and reference inputs are differential, ations. Avoid forcing digital currents to flow through the AGND. most of the voltages in the analog modulator are common- mode voltages. The high common-mode rejection of the part Avoid running digital lines under the device because this removes common-mode noise on these inputs. The analog and couples noise onto the die and allow the analog ground plane to digital supplies to the AD7190 are independent and separately run under the AD7190 to prevent noise coupling. The power pinned out to minimize coupling between the analog and supply lines to the AD7190 must use as wide a trace as possible digital sections of the device. The digital filter provides to provide low impedance paths and reduce the effects of rejection of broadband noise on the power supplies, except at glitches on the power supply line. Shield fast switching signals integer multiples of the modulator sampling frequency. like clocks with digital ground to prevent radiating noise to Connect an R-C filter to each analog input pin to provide other sections of the board, and never run clock signals near the rejection at the modulator sampling frequency. A 100 Ω analog inputs. Avoid crossover of digital and analog signals. resistor in series with each analog input, a 0.1 μF capacitor Run traces on opposite sides of the board at right angles to each between the analog inputs along with a 0.01 μF capacitor from other. This reduces the effects of feedthrough through the each analog input to AGND is advised. The digital filter also board. A microstrip technique is by far the best but is not removes noise from the analog and reference inputs provided always possible with a double-sided board. In this technique, these noise sources do not saturate the analog modulator. As a the component side of the board is dedicated to ground planes, result, the AD7190 is more immune to noise interference than a whereas signals are placed on the solder side. conventional high resolution converter. However, because the Good decoupling is important when using high resolution ADCs. resolution of the AD7190 is so high and the noise levels from Decouple all analog supplies with 10 μF tantalum in parallel with the converter so low, care must be taken with regard to grounding 0.1 μF capacitors to AGND. To achieve the best from these and layout. decoupling components, place them as close as possible to the The printed circuit board (PCB) that houses the ADC must be device, ideally right up against the device. Decouple all logic chips designed so that the analog and digital sections are separated with 0.1 μF ceramic capacitors to DGND. In systems in which a and confined to certain areas of the board. This facilitates the common supply voltage is used to drive both the AV and DV DD DD use of ground planes that can be easily separated. A minimum of the AD7190, it is recommended that the system AVDD supply etch technique is generally best for ground planes because it be used. For this supply, place the recommended analog supply gives the best shielding. decoupling capacitors between the AVDD pin of the AD7190 and Although the AD7190 has separate pins for analog and digital AGND and the recommended digital supply decoupling capacitor between the DV pin of the AD7190 and DGND. ground, the AGND and DGND pins are tied together internally DD via the substrate. Therefore, the user must not tie these two Rev. B | Page 37 of 40 AD7190 APPLICATIONS INFORMATION The AD7190 provides a low-cost, high resolution analog-to- bridge power-down switch is connected in series with the cold digital function. Because the analog-to-digital function is side of the bridge. In normal operation, the switch is closed and provided by a ∑-Δ architecture, it makes the part more measurements can be taken. In applications in which current immune to noisy environments, making it ideal for use in consumption is being minimized, the AD7190 can be placed in sensor measurement and industrial and process control standby mode, thus significantly reducing the power consumed applications. in the application. In addition, the bridge power-down switch can be opened while in standby mode, thus avoiding unnecessary WEIGH SCALES power consumption by the front-end transducer. When the part Figure 32 shows the AD7190 being used in a weigh scale is taken out of standby mode and the bridge power-down switch application. The load cell is arranged in a bridge network and is closed, the user should ensure that the front-end circuitry is gives a differential output voltage between its OUT+ and OUT– fully settled before attempting a read from the AD7190. terminals. Assuming a 5 V excitation voltage, the full-scale For simplicity, external filters are not included in Figure 32. output range from the transducer is 10 mV when the sensitivity However, an R-C antialias filter should be included on each is 2 mV/V. The excitation voltage for the bridge can be used to analog input. This is required because the on-chip digital filter directly provide the reference for the ADC because the reference does not provide any rejection around the modulator sampling input range includes the supply voltage. frequency or multiples of this frequency. Suitable values are a A second advantage of using the AD7190 in transducer-based 100 Ω resistor in series with each analog input, a 0.1 μF capa- applications is that the bridge power-down switch can be fully citor between the analog inputs and 0.01 μF capacitors from utilized to minimize the power consumption of the system. The each analog input pin to AGND. 5V AGND AV DV DGND DD DD REFIN1(+) REFERENCE DETECT IN+ AV AIN1 DD AIN2 OUT+ OUT– AIN3 DOUT/RDY AIN4 SERIAL INTERFACE AINCOM MUX Σ-Δ DIN PGA AND IN– ADC CONTROL SCLK LOGIC CS SYNC AGND TEMP P3 REFIN1(–) SENSOR P2 BPDSW CLOCK AD7190 CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) Figure 32. Typical Application (Weigh Scale) Rev. B | Page 38 of 40 07640-024 AD7190 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0° 0.30 0.60 0.20 SEATING 0.19 0.45 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Models Temperature Range Package Description Package Option 1 AD7190BRUZ –40°C to +105°C 24-Lead TSSOP RU-24 1 AD7190BRUZ-REEL –40°C to +105°C 24-Lead TSSOP RU-24 1 EVAL-AD7190EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 39 of 40 AD7190 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07640-0-5/09(B) Rev. B | Page 40 of 40