ANALOG DEVICES AD7171

16-Bit Low Power Sigma-Delta ADC AD7171 FEATURES FUNCTIONAL BLOCK DIAGRAM Output data rate: 125 Hz GND V REFIN(+) REFIN(–) DD Pin-programmable power-down and reset Status function AIN(+) DOUT/RDY 16-BIT Σ-Δ Internal clock oscillator ADC AIN(–) SCLK Current: 135 μA PDRST Power supply: 2.7 V to 5.25 V INTERNAL AD7171 CLOCK –40°C to +105°C temperature range Package: 10-lead 3 mm x 3 mm LFCSP Figure 1. INTERFACE Table 1. 2-wire serial (read-only device) P-P SPI compatible VREF = VDD RMS Noise P-P Noise Resolution ENOB Schmitt trigger on SCLK 5 V 11.5 μV 76 μV 16 bits 16 bits 3 V 6.9 μV 45 μV 16 bits 16 bits APPLICATIONS Weigh scales Pressure measurement Industrial process control Portable instrumentation GENERAL DESCRIPTION The AD7171 is a very low power 16-bit analog-to-digital converter The output data rate of the AD7171 is 125 Hz, whereas the (ADC). It contains a precision 16-bit sigma-delta (Σ-Δ) ADC settling time is 24 ms. The AD7171 has one differential input and an on-chip oscillator. Consuming only 135 μA, the AD7171 and a gain of 1. This is useful in applications where the user is particularly suitable for portable or battery operated products needs to use an external amplifier to implement system-specific where very low power is a requirement. The AD7171 also has a filtering or gain requirements. power-down mode in which the device consumes 5 μA, thus The AD7171 operates with a power supply from 2.7 V to 5.25 V. increasing the battery life of the product. It is available in a 10-lead LFCSP package. For ease-of-use, all the features of the AD7171 are controlled by The AD7170 is a 12-bit version of the AD7171. It has the same dedicated pins. Each time a data read occurs, eight status bits feature set as the AD7171 and is pin-for-pin compatible. are appended to the 16-bit conversion. These status bits contain a pattern sequence that can be used to confirm the validity of the serial transfer. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08417-001 AD7171 TABLE OF CONTENTS Features .............................................................................................. 1  Overview ..................................................................................... 10  Interface ............................................................................................. 1  Filter, Data Rate, and Settling Time ......................................... 10  Applications ....................................................................................... 1  Gain .............................................................................................. 10  Functional Block Diagram .............................................................. 1  Power-Down/Reset(PDRST) .................................................... 10  General Description ......................................................................... 1  Analog Input Channel ............................................................... 10  Revision History ............................................................................... 2  Bipolar Configuration ................................................................ 10  Specif ica t ions ..................................................................................... 3  Data Output Coding .................................................................. 11  Timing Characteristics ..................................................................... 5  Reference ..................................................................................... 11  Timing Diagrams .......................................................................... 5  Digital Interface .......................................................................... 11  Absolute Maximum Ratings ............................................................ 6  Grounding and Layout .............................................................. 12  Thermal Resistance ...................................................................... 6  Applications Information .............................................................. 13  ESD Caution .................................................................................. 6  Temperature System ................................................................... 13 S Pin Configuration and Function Descriptions ............................. 7  Signal Conditioning Circuit ........................................................ 13  Typical Performance Characteristics ............................................. 8  Outline Dimensions ....................................................................... 14  Output Noise and Resolution Specifications ................................ 9  Ordering Guide .......................................................................... 14  ADC Circuit Information .............................................................. 10  REVISION HISTORY 10/09—Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD7171 SPECIFICATIONS VDD = 2.7 V to 5.25 V, VREF = VDD, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 AD7171B Parameter Min Typ Max Unit Test Conditions/Comments ADC CHANNEL Output Data Rate (fADC) 125 Hz Settling time = 3/fADC 2 No Missing Codes 16 Bits Resolution Peak-to-Peak (p-p) 16 Bits V = 0 V, V = V INx REF DD Effective Resolution (ENOB) 16 Bits V = 0 V, V = V INx REF DD RMS Noise See Table 6 μV V = 0 V, V = V INx REF DD Integral Nonlinearity ±0.4 LSB Offset Error ±200 μV Offset Error Drift vs. Temperature ±250 nV/°C Full-Scale Error ±0.015 % of FS Gain Drift vs. Temperature ±0.07 LSB/°C Power Supply Rejection 85 dB VINx = 1 V ANALOG INPUTS Differential Input Voltage Range ±V V V = REFIN(+) − REFIN(−) REF REF 2 Absolute AINx Voltage Limits GND − 0.03 VDD + 0.03 V 2 Average Input Current ±400 nA/V Input current varies with input voltage Average Input Current Drift ±60 pA/V/°C DC Common-Mode Rejection 90 dB V = 1 V INx REFERENCE External REFIN Voltage V V REFIN = REFIN(+) − REFIN(−) DD 2 Reference Voltage Range 0.5 V V DD 2 Absolute REFIN Voltage Limits GND − 0.03 VDD + 0.03 V Average Reference Input Current 400 nA/V Average Reference Input Current ±0.15 nA/V/°C Drift DC Common-Mode Rejection 110 dB INTERNAL CLOCK 2 Frequency 64 − 5% 64 + 5% kHz LOGIC INPUTS 2 SCLK, PDRST Input Low Voltage, V 0.4 V V = 3 V INL DD 0.8 V VDD = 5 V Input High Voltage, VINH 1.8 V VDD = 3 V 2.4 V V = 5 V DD 2 SCLK (Schmitt-Triggered Input) Hysteresis 100 mV VDD = 3 V 140 mV VDD = 5 V Input Currents ±2 μA V = V or GND IN DD Input Capacitance 5 pF All digital inputs Rev. 0 | Page 3 of 16 AD7171 1 AD7171B Parameter Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUT (DOUT/RDY) 2 Output High Voltage, V V − 0.6 V V = 3 V, I = 100 μA OH DD DD SOURCE 4 V V = 5 V, I = 200 μA DD SOURCE 2 Output Low Voltage, V 0.4 V V = 3 V, I = 100 μA OL DD SINK 0.4 V VDD = 5 V, ISINK = 1.6 mA Floating-State Leakage Current ±2 μA Floating-State Output Capacitance 5 pF Data Output Coding Offset binary 3 POWER REQUIREMENTS Power Supply Voltage V – GND 2.7 5.25 V DD Power Supply Currents IDD Current 110 130 μA VDD = 3 V 135 150 μA VDD = 5 V IDD (Power-Down/Reset Mode) 5 μA 1 Temperature range is –40°C to +105°C. 2 Specification is not production tested but is supported by characterization data at initial product release. 3 Digital inputs equal to VDD or GND. Rev. 0 | Page 4 of 16 AD7171 TIMING CHARACTERISTICS V = 2.7 V to 5.25 V,, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = V , unless otherwise noted. DD DD Table 2. 1, 2 Parameter Limit at TMIN, TMAX Unit Conditions/Comments READ t 100 ns min SCLK high pulse width 1 t2 100 ns min SCLK low pulse width 3 4 t3 0 ns min SCLK active edge to data valid delay 60 ns max VDD = 4.75 V to 5.25 V 80 ns max V = 2.7 V to 3.6 V DD t 10 ns min SCLK inactive edge to DOUT/RDY high 4 RESET t 100 ns min PDRST low pulse width 5 t 25 ms typ PDRST high to data valid delay 6 1 Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. R F DD 2 See Figure 3. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V or V limits. OL OH 4 SCLK active edge is the falling edge of SCLK. I (1.6mA WITH V = 5V, SINK DD 100µA WITH V = 3V) DD TO OUTPUT 1.6V PIN 50pF I (200µA WITH V = 5V, SOURCE DD 100µA WITH V = 3V) DD Figure 2. Load Circuit for Timing Characterization TIMING DIAGRAMS MSB LSB DOUT/RDY (O) t 4 t 3 t 1 SCLK (I) t 2 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram PDRST (I) t 5 t 6 DOUT/RDY (O) I = INPUT, O = OUTPUT Figure 4. Resetting the AD7171 Rev. 0 | Page 5 of 16 08417-002 08417-004 08417-003 AD7171 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA Table 3. soldered in a circuit board for surface-mount packages. Parameter Rating V to GND −0.3 V to +7 V DD Table 4. Analog Input Voltage to GND −0.3 V to V + 0.3 V DD Package Type θ θ Unit JA JC Reference Input Voltage to GND −0.3 V to VDD + 0.3 V LFCSP 48.7 2.96 °C/W Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V ESD CAUTION V /Digital Input Current 10 mA INx Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature, Soldering Reflow 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 16 AD7171 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 10 NC DOUT/RDY 2 AD7171 9 PDRST AIN(+) 3 TOP VIEW 8V DD (Not to Scale) AIN(–) 4 7GND REFIN(+) 5 6REFIN(–) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO GROUND. Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK has a Schmitt-triggered input. The serial clock can be continuous with all data transmitted in a constant train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted from the ADC in smaller batches of data. 2 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. In addition, it functions as a serial data output pin to access the data register of the ADC. Eight status bits accompany each data read. See Figure 13 for further details. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that new data is available. If the data is not read after the conversion, the pin goes high before the next update occurs. 3 AIN(+) Analog Input. AIN(+) is the positive terminal of the differential analog input pair AIN(+)/AIN(−). 4 AIN(−) Analog Input. AIN(−) is the negative terminal of the differential analog input pair AIN(+)/AIN(−). 5 REFIN(+) Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(–). The nominal reference voltage (REFIN(+) – REFIN(−)) is 5 V, but the part can function with a reference of 0.5 V to VDD. 6 REFIN(−) Negative Reference Input. 7 GND Ground Reference Point. 8 V Supply Voltage, 2.7 V to 5.25 V. DD 9 PDRST Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode. All the logic on the chip is reset and the DOUT/RDY pin is tristated. When PDRST is high, the ADC is taken out of power-down mode. The on-chip clock powers up and settles, and the ADC continuously converts. The internal clock requires 1 ms approximately to power up. 10 NC This pin should be connected to GND for correct operation. EPAD Connect the exposed pad to ground. Rev. 0 | Page 7 of 16 08417-005 AD7171 TYPICAL PERFORMANCE CHARACTERISTICS 10 0.025 V = V = 5V REF DD 8 0.023 V = V = 3V REF DD 6 0.021 4 0.019 2 0.017 0 0.015 –40 –10 20 50 80 110 –40 –10 20 50 80 110 TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. AD7171 RMS Noise vs. Temperature Figure 9. Gain Error vs. Temperature 140 0.266 0.200 132 V = V = 5V REF DD 0.133 124 0.066 0 116 –0.066 V = V = 3V REF DD 108 –0.133 –0.200 100 –3 –2 –1 0 1 2 3 –40 –10 20 50 80 110 V (V) TEMPERATURE (°C) IN Figure 7. Integral Nonlinearity (V = V ) Figure 10. Power Supply Current vs. Temperature REF DD 4.5 180 4.0 3.5 160 3.0 V = V = 5V REF DD 2.5 2.0 140 1.5 1.0 V = V = 3V REF DD 0.5 120 0 –40 –10 20 50 80 110 –40 –10 20 50 80 110 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Power-Down Current vs. Temperature Figure 8. Offset vs. Temperature Rev. 0 | Page 8 of 16 OFFSET (µV) RMS NOISE (µV) INL (LSB) 08417-006 08417-007 08417-015 I (µA) I (µA) GAIN ERROR (%) DD DD 08417-017 08417-016 08417-008 AD7171 OUTPUT NOISE AND RESOLUTION SPECIFICATIONS The noise-free bits, or p-p resolution, are defined as Table 6 shows the rms noise of the AD7171. The numbers given are for a 5 V and a 3 V reference. These numbers are typical and Noise-Free Bits = ln (FSR/Peak-to-Peak Noise)/ln(2) are generated with a differential input voltage of 0 V. The corres- where FSR is the full-scale range and is equal to 2 × VREF/gain. ponding p-p resolution is also listed along with the effective resolution (ENOB). It is important to note that the effective Table 6. RMS Noise and Resolution of the AD7171 resolution is calculated using the rms noise, whereas the p-p P-P resolution is based on the p-p noise. The p-p resolution V = V RMS Noise P-P Noise Resolution ENOB REF DD represents the resolution for which there is no code flicker. 5 V 11.5 μV 76 μV 16 bits 16 bits These numbers are typical. 3 V 6.9 μV 45 μV 16 bits 16 bits The effective number of bits (ENOB) is defined as ENOB = ln (FSR/RMS noise)/ln(2) Rev. 0 | Page 9 of 16 AD7171 ADC CIRCUIT INFORMATION POWER-DOWN/RESET(PDRST) OVERVIEW PDRST The pin functions as a power-down pin and a reset pin. The AD7171 is a low power ADC that incorporates a precision PDRST 16-bit Σ-Δ modulator and an on-chip digital filter intended for When is taken low, the AD7171 is powered down. The measuring wide dynamic range, low frequency signals. The entire ADC is powered down (including the on-chip clock), and device has an internal clock and one differential input. It the DOUT/RDY pin is tristated. The circuitry and serial interface operates with an output data rate of 125 Hz and has a gain of 1. are also reset. This resets the logic, the digital filter, and the analog A 2-wire interface simplifies data retrieval from the AD7171. modulator. PDRST must be held low for 100 ns minimum to initiate the reset function (see Figure 4). FILTER, DATA RATE, AND SETTLING TIME 3 PDRST When is taken high, the AD7171 is taken out of power- The AD7171 uses a sinc filter. The output data rate is set to down mode. When the on-chip clock has powered up (1 ms, 125 Hz; thus, valid conversions are available every 1/125 = 8 ms. typically), the modulator then begins sampling the analog input. If a reset occurs, then the user must allow the complete settling RDY The DOUT/ pin becomes active, going high until a valid time for the first conversion after the reset. The settling time is equal to 24 ms. Subsequent conversions are available at 125 Hz. conversion is available. A reset is automatically performed on power-up. When a step change occurs on the analog input, the AD7171 requires several conversion cycles to generate a valid conversion. ANALOG INPUT CHANNEL If the step change occurs synchronous to the conversion period, The AD7171 has one differential analog input channel that is then the settling time of the AD7171 must be allowed to generate connected to the modulator; that is, the input is unbuffered. a valid conversion. If the step change occurs asynchronous to Note that this unbuffered input path provides a dynamic load to the end of a conversion, then an extra conversion must be allowed the driving source. Therefore, resistor/capacitor combinations on to generate a valid conversion. The data register is updated with the input pins can cause dc gain errors, depending on the output all the conversions but, for an accurate result, the user must impedance of the source that is driving the ADC input. Table 7 allow the required time. shows the allowable external resistance/capacitance values such Figure 12 shows the filter response of the filter. The only external that no gain error at the 16-bit level is introduced. filtering required on the analog inputs is a simple R-C filter to Table 7. External R-C Combination for No Gain Error provide rejection at multiples of the master clock. A 1 KΩ C (pF) R (Ω) resistor in series with each analog input, a 0.01 μF capacitor 50 9 k from each input to GND, and a 0.1 μF capacitor from AIN(+) to 100 6 k AIN(−) are recommended. 500 1.5 k 0 1000 900 –10 5000 200 –20 The absolute input voltage range is restricted to a range between –30 + 30 mV. Care must be taken in setting GND − 30 mV and VDD –40 up the common-mode voltage to avoid exceeding these limits. –50 Otherwise, there is degradation in linearity and noise performance. –60 BIPOLAR CONFIGURATION –70 The AD7171 accepts a bipolar input range. A bipolar input –80 range does not imply that the part can tolerate negative voltages –90 with respect to system GND. Signals on the AIN(+) input are –100 0 125 250 375 500 625750 referenced to the voltage on the AIN(−) input. For example, if INPUT SIGNAL FREQUENCY (Hz) AIN(−) is 2.5 V, the analog input range on the AIN(+) input is Figure 12. Filter Response 0 V to 5 V when a 2.5 V reference is used. GAIN The AD7171 has a gain of 1. The acceptable analog input range is +V . Therefore, with V = 5 V, the input range is +5 V. REF REF Rev. 0 | Page 10 of 16 FILTER GAIN (dB) 08417-011 AD7171 RDY DATA OUTPUT CODING DOUT/ pin is dual purpose: it functions as a data ready RDY pin and as a data out pin. DOUT/ goes low when a new The AD7171 uses offset binary coding. Therefore, a negative data-word is available in the output register. A 24-bit word is full-scale voltage results in a code of 000...000, a zero differential placed on the DOUT/RDY pin when sufficient SCLK pulses are input voltage results in a code of 100...000, and a positive full- applied. This consists of a 16-bit conversion result followed by scale input voltage results in a code of 111...111. The output eight status bits. Table 8 shows the functions of the status bits. code for any analog input voltage can be represented as N – 1 RDY: ready bit. This bit is set low to indicate that a conversion Code = 2 × [(V /V ) + 1] INx REF is available. where: 0: This bit is set to 0. VINx is the analog input voltage. N = 16 for the AD7171. ERR: This bit is set to 1 if an error occurred during the conversion. An error occurs when the analog input is outside REFERENCE range. The AD7171 has a fully differential input capability for the ID1, ID0: ID bits. These bits indicate the ID number for the channel. The common-mode range for these differential inputs AD7171. Bit ID1 is set to 0 and bit ID0 is set to 1 for the is GND to VDD. The reference input is unbuffered; therefore, AD7171. excessive R-C source impedances introduce gain errors. The reference voltage REFIN (REFIN(+) − REFIN(−)) is V DD PAT2, PAT1, PAT0: status pattern bits. They are set to 101 by nominal, but the AD7171 is functional with reference voltages default. When the user reads the data from the AD7171, a of 0.5 V to V . In applications where the excitation (voltage or DD pattern check can be performed. If the PAT2 to PAT0 bits are current) for the transducer on the analog input also drives the different from their default values, the serial transfer from the reference voltage for the part, the effect of the low frequency ADC was not performed correctly. noise in the excitation source is removed because the application Table 8. Status Bits is ratiometric. If the AD7171 is used in a nonratiometric 0 ERR ID1 ID0 PAT2 PAT1 PAT0 application, a low noise reference should be used. RDY Recommended 2.5 V reference voltage sources for the AD7171 RDY DOUT/ is reset high when the conversion is read. If the include the ADR381 and ADR391, which are low noise, low RDY conversion is not read, DOUT/ goes high prior to the data power references. Also note that the reference inputs provide a register update to indicate when not to read from the device. high impedance, dynamic load. Because the input impedance of This ensures that a read operation is not attempted while the each reference input is dynamic, resistor/capacitor combinations register is being updated. Each conversion can be read only on these inputs can cause dc gain errors, depending on the output once. The data register is updated for every conversion. So, impedance of the source that is driving the reference inputs. when a conversion is complete, the serial interface is reset, and Reference voltage sources such as those recommended above the new conversion is placed in the data register. Therefore, the (the ADR391, for example) typically have low output impedances user must ensure that the complete word is read before the next and are, therefore, tolerant to decoupling capacitors on REFIN(+) conversion is complete. without introducing gain errors in the system. Deriving the PDRST RDY When is low, the DOUT/ pin is tristated. When reference input voltage across an external resistor means that PDRST is taken high, the internal clock requires 1 ms, approx- the reference input sees a significant external source impedance. imately, to power up. Following this, the ADC continuously External decoupling on the REFIN(±) pins is not recommended converts. The first conversion requires the complete settling in this type of circuit configuration. time (see Figure 4). DOUT/RDY goes high when PDRST is DIGITAL INTERFACE taken high and returns low only when a conversion is available. The ADC then converts continuously, subsequent conversions The serial interface of the AD7171 consists of two signals: SCLK being available at 125 Hz. Figure 3 shows the timing for a read and DOUT/RDY. SCLK is the serial clock input for the device, operation from the AD7171. and data transfers occur with respect to the SCLK signal. The Rev. 0 | Page 11 of 16 AD7171 their destinations. Avoid forcing digital currents to flow through GROUNDING AND LAYOUT the AGND sections of the layout. Because the analog input and reference input of the ADC are The ground plane of the AD7171 should be allowed to run differential, most of the voltages in the analog modulator are under the AD7171 to prevent noise coupling. The power supply common-mode voltages. The excellent common-mode reject- lines to the AD7171 should use as wide a trace as possible to ion of the part removes common-mode noise on these inputs. provide low impedance paths and reduce the effects of glitches The digital filter provides rejection of broadband noise on the on the power supply line. Fast switching signals such as clocks power supply, except at integer multiples of the modulator should be shielded with digital ground to avoid radiating noise sampling frequency. The digital filter also removes noise from to other sections of the board, and clock signals should never be the analog and reference inputs provided that these noise run near the analog inputs. Avoid crossover of digital and sources do not saturate the analog modulator. As a result, the analog signals. Traces on opposite sides of the board should run AD7171 is more immune to noise interference than conven- at right angles to each other. This reduces the effects of feedthrough tional high resolution converters. However, because the noise through the board. A microstrip technique is by far the best, but levels from the AD7171 are so low, care must be taken with it is not always possible with a double-sided board. In this regard to grounding and layout. technique, the component side of the board is dedicated to The printed circuit board that houses the AD7171 should be ground planes, while signals are placed on the solder side. designed such that the analog and digital sections are separated Good decoupling is important when using high resolution ADCs. and confined to certain areas of the board. A minimum etch V should be decoupled with 10 μF tantalum capacitors in DD technique is generally best for ground planes because it gives parallel with 0.1 μF capacitors to GND, with the system’s analog the best shielding. ground to digital ground (DGND) connection being close to It is recommended that the GND pin of the AD7171 be tied to the AD7171. To achieve the best results from these decoupling the analog ground (AGND) plane of the system. In any layout, components, they should be placed as close as possible to the it is important that the user pay attention to the flow of currents device, ideally right up against the device. All logic chips should in the system, and ensure that the return paths for all currents be decoupled with 0.1 μF ceramic capacitors to DGND. are as close as possible to the paths the currents took to reach Rev. 0 | Page 12 of 16 AD7171 SIGNAL CONDITIONING CIRCUIT APPLICATIONS INFORMATION Figure 14 shows the AD7171 used in a signal conditioning The AD7171 provides a low cost, high resolution analog-to- circuit for a single-ended analog input. In a low side shunt digital function. Because the analog-to-digital function is current monitor, a low resistance shunt resistor converts the provided by a Σ-Δ architecture, the part is more immune to current to voltage. The resulting voltage is amplified and noisy environments, making it ideal for use in sensor measure- applied to the AD7171. ment and industrial and process-control applications. 32kΩ TEMPERATURE SYSTEM 1kΩ GND V DD AIN(+) DOUT/RDY Figure 13 shows the AD7171 used in a temperature measure- 16-BIT AIN(–) Σ-Δ ADC SCLK AD8628 ment system. The thermistor is connected in series with a ANALOG INPUT precision resistor, R , the precision resistor being used to INTERNAL REF CLOCK AD5041 REFIN(+) generate the reference voltage. The value of R is equal to the REF REFIN(–) 1µF AD7171 maximum resistance produced by the thermistor. The complete dynamic range of the ADC is then used, resulting in optimum Figure 14. Signal Conditioning Circuit performance. V DD GND V DD AIN(+) DOUT/RDY 16-BIT Σ-Δ ADC AIN(–) SCLK AD7171 PDRST REFIN(+) INTERNAL R CLOCK REF REFIN(–) Figure 13. Temperature System Using the AD7171 Rev. 0 | Page 13 of 16 08417-013 08417-018 AD7171 OUTLINE DIMENSIONS 0.30 3.00 0.23 0.50 BSC BSC SQ 0.18 6 10 PIN 1 INDEX 1.74 * EXPOSED AREA PAD 1.64 (BOTTOM VIEW) 1.49 0.50 0.40 5 1 0.30 TOP VIEW 2.48 2.38 0.80 MAX 2.23 0.80 0.55 NOM 0.05 MAX 0.75 0.02 NOM 0.70 SEATING PLANE 0.20 REF * FOR PROPER CONNECTION OF THE EXPOSED PAD PLEASE REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 15. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Temperature Model Range Package Description Package Option Branding 1 AD7171BCPZ-REEL7 –40°C to +105°C 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9 C6G 1 AD7171BCPZ-500RL7 –40°C to +105°C 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9 C6G 1 Z = RoHS Compliant Part. Rev. 0 | Page 14 of 16 PIN 1 INDICATOR (R 0.20) 031208-B AD7171 NOTES Rev. 0 | Page 15 of 16 AD7171 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08417-0-10/09(0) Rev. 0 | Page 16 of 16