ANALOG DEVICES AD7152

12-Bit Capacitance-to-Digital Converter AD7152/AD7153 FEATURES GENERAL DESCRIPTION Capacitance-to-digital converters The AD7152/AD7153 are 12-bit sigma-delta (Σ-Δ) capacitance-to- Interfaces to floating sensors digital converters (CDCs). The capacitance to be measured Resolution down to 0.25 fF (that is, up to 12 ENOB) is connected directly to the device inputs. The architecture Linearity: 0.05% features inherent high resolution (12-bit no missing codes, Common-mode (not changing) capacitance up to 5 pF up to 12-bit effective resolution) and high linearity (±0.05%). Four capacitance ranges selectable per operation mode The AD7152/AD7153 have four capacitance input ranges per ±0.25 pF to ±2 pF in differential mode operation mode, ±0.25 pF to ±2 pF in differential mode and 0.5 pF to 4 pF in single-ended mode 0.5 pF to 4 pF in single-ended mode. Tolerant of parasitic capacitance to ground up to 50 pF The AD7152/AD7153 can accept up to 5 pF common-mode Conversion time per channel: 5 ms, 20 ms, 50 ms, and 60 ms capacitance (not changing), which can be balanced by a Internal clock oscillator programmable on-chip, digital-to-capacitance converter 2 2-wire serial interface (I C-compatible) (CAPDAC). Power The AD7153 has one capacitance input channel, while the 2.7 V to 3.6 V single-supply operation AD7152 has two channels. Each channel can be configured 100 μA current consumption as single-ended or differential. The AD7152/AD7153 are Operating temperature: −40°C to +85°C designed for floating capacitive sensors. 10-lead MSOP package 2 The AD7152/AD7153 have a 2-wire, I C®-compatible serial APPLICATIONS interface. Both parts can operate with a single power supply Automotive, industrial, and medical systems for from 2.7 V to 3.6 V. They are specified over the temperature Pressure measurement range of −40°C to +85°C and are available in a 10-lead MSOP Position sensing package. Level sensing Flowmeters Humidity sensing FUNCTIONAL BLOCK DIAGRAMS VDD VDD AD7152 AD7153 CAP+ CAP+ CAP– CLOCK VOLTAGE CAP– CLOCK VOLTAGE GENERATOR REFERENCE GENERATOR REFERENCE CIN1(+) CIN1(–) CIN1(+) SDA SDA 2 2 I C I C EXC1 12-BIT Σ-Δ 12-BIT Σ-Δ MUX SERIAL CIN1(–) MUX SERIAL MODULATOR MODULATOR CIN2(+) INTERFACE INTERFACE SCL SCL EXC1 CIN2(–) EXC2 EXCITATION DIGITAL CONTROL LOGIC EXCITATION DIGITAL CONTROL LOGIC FILTER CALIBRATION FILTER CALIBRATION GND GND Figure 1. Figure 2. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07450-001 07450-002 AD7152/AD7153 TABLE OF CONTENTS Features .............................................................................................. 1 Configuration Register .............................................................. 16 Applications ....................................................................................... 1 CAPDAC POS Register ............................................................. 17 General Description ......................................................................... 1 CAPDAC NEG Register ............................................................ 17 Functional Block Diagrams ............................................................. 1 Configuration2 Register ............................................................ 17 Revision History ............................................................................... 2 Circuit Description......................................................................... 18 Specif ica t ions ..................................................................................... 3 Capacitance-to-Digital Converter (CDC) .............................. 18 Timing Specifications .................................................................. 5 Excitation Source ........................................................................ 18 Absolute Maximum Ratings ............................................................ 6 CAPDAC ..................................................................................... 19 ESD Caution .................................................................................. 6 Single-Ended Capacitive Input ................................................. 19 Pin Configurations and Function Descriptions ........................... 7 Differential Capacitive Input .................................................... 20 Typical Performance Characteristics ............................................. 8 Parasitic Capacitance to Ground .............................................. 20 Serial Interface ................................................................................ 11 Parasitic Resistance to Ground ................................................. 20 Write Operation .......................................................................... 11 Parasitic Parallel Resistance ...................................................... 21 Read Operation ........................................................................... 11 Parasitic Serial Resistance ......................................................... 21 AD7152/AD7153 Reset ............................................................. 12 Input EMC Protection ............................................................... 21 General Call................................................................................. 12 Power Supply Decoupling and Filtering .................................. 21 Register Map .................................................................................... 13 Capacitive Gain Calibration ..................................................... 21 Status Register ............................................................................. 14 Capacitive System Offset Calibration ...................................... 21 Data Registers ............................................................................. 15 Typical Application Diagram .................................................... 22 Offset Calibration Registers ...................................................... 15 Outline Dimensions ....................................................................... 23 Gain Calibration Registers ........................................................ 15 Ordering Guide .......................................................................... 23 CAP Setup Registers .................................................................. 16 REVISION HISTORY 5/08—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD7152/AD7153 SPECIFICATIONS VDD = 2.7 V to 3.6 V; GND = 0 V; −40°C to +85°C, unless otherwise noted. Table 1. 1 Parameter Min Typ Max Unit Test Conditions/Comments CAPACITIVE INPUT Capacitive Input Ranges ±2 pF Differential mode ±1 pF ±0.5 pF ±0.25 pF 4 pF Single-ended mode 2 pF 1 pF 0.5 pF Gain Matching Between Ranges ±3 % of FS 2 Integral Nonlinearity (INL) ±0.05 % of FS 2 No Missing Codes 12 Bits 2, 3 Resolution, p-p 10 Bits 25°C, V = 3.3 V, 4 pF range DD 2, 3 Resolution Effective 12 Bits 25°C, VDD = 3.3 V, 4 pF range 4 Absolute Error ±20 fF 25°C, VDD = 3.3 V, after system offset calibration, ±2 pF range 5, 6 System Offset Calibration Range 40 % of FSR 2 Offset Deviation over Temperature 1 5 fF Single-ended mode, CIN and EXC pins disconnected, see Figure 8 0.3 1 fF Differential mode, CIN and EXC pins disconnected 7 Gain Error 0.5 % of FSR 25°C, VDD = 3.3 V 2 Gain Deviation over Temperature 0.3 0.4 % of FSR See Figure 7 2 Allowed Capacitance, CIN to GND 50 pF See Figure 9 and Figure 10 2 Allowed Resistance, CIN to GND 10 MΩ See Figure 13 2 Allowed Serial Resistance 20 kΩ See Figure 16 Power Supply Rejection DC 2 fF/V See Figure 17 2 Normal-Mode Rejection −70 dB 50 Hz ± 1 Hz, conversion time = 60 ms −70 dB 60 Hz ± 1 Hz, conversion time = 50 ms 2 Channel-to-Channel Isolation −70 dB AD7152 only CAPDAC Full Range 5 6.25 pF 8 Resolution 200 fF 5-bit CAPDAC 2 Differential Nonlinearity (DNL) 0.25 LSB See Figure 18 and Figure 19 2 Offset Deviation over Temperature 0.3 % of CAPDAC FSR Single-ended mode EXCITATION Frequency 30.9 32 32.8 kHz Voltage ±VDD/2 V 2 Allowed Capacitance, EXC to GND 300 pF See Figure 11 and Figure 12 SERIAL INTERFACE LOGIC INPUTS (SCL, SDA) Input High Voltage, VIH 1.5 V Input Low Voltage, V 0.8 V IL Input Leakage Current (SCL) ±0.1 ±5 μA OPEN-DRAIN OUTPUT (SDA) Output Low Voltage, V 0.4 V OL ISINK = −6.0 mA Output High Leakage Current, I 0.1 5 μA V = V OH OUT DD POWER SUPPLY MONITOR Threshold Voltage, V 2.45 2.65 V DD Rev. 0 | Page 3 of 24 AD7152/AD7153 1 Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS VDD-to-GND Voltage 2.7 3.6 V VDD = 3.3 V, nominal 9 Current, IDD 100 120 μA 9 Current Power-Down Mode, I 1 5 μA Temperature ≤ 25°C DD 3 10 μA Temperature = 85°C 1 −12 −15 −18 Capacitance units: 1 pF = 10 F; 1 fF = 10 F; 1 aF = 10 F. 2 Specification is not production tested but is supported by characterization data at initial product release. 3 2 Except Channel 2 in differential mode. To achieve the specified performance in differential mode, the I C interface must be idle during the capacitance conversion to prevent signal coupling from the SCL pin to the adjacent CIN2(−) pin. 4 Factory calibrated. The absolute error includes factory gain calibration error and integral nonlinearity error all at 25°C. At different temperatures, compensation for gain drift over temperature is required. 5 Specification is not production tested but guaranteed by design. 6 A system offset calibration is effectively a conversion; therefore, the offset error is of the order of the conversion noise. This applies after calibration at the temperature, capacitive input range, and applied V of interest. The capacitive input offset can be reduced using a system offset calibration. Large offsets should be removed using DD CAPDACs. 7 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required. 8 The CAPDAC resolution is five bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can further reduce the CIN offset or the unchanging CIN component. 9 Digital inputs equal to V or GND. DD Rev. 0 | Page 4 of 24 AD7152/AD7153 TIMING SPECIFICATIONS VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; −40°C to +85°C, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments 1, 2 SERIAL INTERFACE See Figure 3. SCL Frequency 0 400 kHz SCL High Pulse Width, tHIGH 0.6 μs SCL Low Pulse Width, tLOW 1.3 μs SCL, SDA Rise Time, t 0.3 μs R SCL, SDA Fall Time, t 0.3 μs F Hold Time (Start Condition), tHD;STA 0.6 μs After this period, the first clock is generated. Set-Up Time (Start Condition), tSU;STA 0.6 μs Relevant for repeated start condition. Data Set-Up Time, tSU;DAT 0.1 μs Setup Time (Stop Condition), t 0.6 μs SU;STO Data Hold Time, t (Master) 0.01 μs HD;DAT Bus-Free Time (Between Stop and Start Conditions, t ) 1.3 μs BUF 1 Sample tested during initial release to ensure compliance. 2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs; output load = 10 pF. t t R F t t LOW HD;STA SCL t t t HIGH SU;STA SU;STO t HD;STA t t HD;DAT SU;DAT SDA t BUF S PS P Figure 3. Serial Interface Timing Diagram Rev. 0 | Page 5 of 24 07450-003 AD7152/AD7153 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 3. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational Positive Supply Voltage, V to GND −0.3 V to +3.9 V DD section of this specification is not implied. Exposure to absolute Voltage on Any Input or Output Pin to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect ESD Rating (ESD Association Human 4 kV device reliability. Body Model, S5.1) ESD Rating (Field-Induced Charged 750 V ESD CAUTION Device Model) Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C MSOP θJA Thermal Impedance-to-Air 206°C/W θJC Thermal Impedance-to-Case 44°C/W Reflow Soldering (Pb-Free) Peak Temperature 260 (+0/−5)°C Time at Peak Temperature 10 sec to 40 sec Rev. 0 | Page 6 of 24 AD7152/AD7153 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS GND 1 10 SDA GND 1 10 SDA VDD 2 9 SCL AD7153 VDD 2 9 SCL CIN1(–) 3 8 NC TOP VIEW AD7152 CIN1(–) 3 8 CIN2(–) (Not to Scale) TOP VIEW CIN1(+) 4 7 NC (Not to Scale) CIN1(+) 4 7 CIN2(+) NC 5 6 EXC1 EXC2 5 6 EXC1 NC = NO CONNECT Figure 4. AD7152 Pin Configuration Figure 5. AD7153 Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 GND Ground Pin. 2 VDD Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example, in combination with a 10 μF tantalum and a 0.1 μF multilayer ceramic capacitor. 3 CIN1(–) CDC Negative Capacitive Input of Channel 1. If not used, this pin can be left as an open circuit or connected to GND. This pin is internally disconnected in single-ended CDC configuration. 4 CIN1(+) CDC Positive Capacitive Input of Channel 1. If not used, this pin can be left as an open circuit or connected to GND. 5 EXC2/NC AD7152: CDC Excitation Output for Channel 2. The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, these pins should be left as an open circuit. AD7153: No Connect. This pin must be left as an open circuit. 6 EXC1 CDC Excitation Output for Channel 1. The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, these pins should be left as an open circuit. 7 CIN2(+)/NC AD7152: CDC Positive Capacitive Input of Channel 2. If not used, this pin can be left as an open circuit or connected to GND. AD7153: No Connect. This pin must be left as an open circuit. 8 CIN2(–)/NC AD7152: CDC Negative Capacitive Input of Channel 2. If not used, this pin can be left as an open circuit or connected to GND. This pin is internally disconnected in single-ended CDC configuration. AD7153: No Connect. This pin must be left as an open circuit. 9 SCL Serial Interface Clock Input. Connects to the master clock line. Requires a pull-up resistor if one is not already provided in the system. 10 SDA Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if one is not provided elsewhere in the system. Rev. 0 | Page 7 of 24 07450-004 07450-005 AD7152/AD7153 TYPICAL PERFORMANCE CHARACTERISTICS 0.05 2 0.04 0 0.03 –2 0.02 3pF 9pF 0.01 –4 0 –6 0.01 0.02 –8 0.03 –10 0.04 0.05 –12 –2 –1 0 1 2 0 50 100 150 200 250 300 350 CAPACITANCE (pF) CAP LOAD TO GND (pF) Figure 6. Capacitance Input Integral Nonlinearity, Figure 9. Capacitance Input Error vs. Capacitance Between CIN and GND; V = 3.3 V, See Figure 34 Single-Ended Mode, CIN(+) to EXC = 3 pF and 9 pF, V = 3.3 V DD DD 0.20 2 TC ≈ 28ppm/°C 2pF 0.15 0 0.10 8pF –2 0.05 –4 0.00 –0.05 –6 –0.10 –8 –0.15 –10 –0.20 –12 –0.25 50 25 0 25 50 75 100 0 50 100 150 200 250 300 350 TEMPERATURE (°C) CAP LOAD TO GND (pF) Figure 7. Capacitance Input Gain Drift vs. Temperature, Figure 10. Capacitance Input Error vs. Capacitance Between CIN and GND, VDD = 3.3 V, Range = ±2 pF Differential Mode, CIN(+) to EXC = 2 pF and 8 pF, CIN(−) to EXC = 0 pF and 6 pF, VDD = 3.3 V 0.4 0.3 0.2 0.2 0.1 0 0 –0.1 –0.2 –0.2 –0.4 –0.3 –50 –25 0 25 50 75 100 0 50 100 150 200 250 300 350 TEMPERATURE (°C) CAP LOAD TO GND (pF) Figure 8. Capacitance Input Offset Drift vs. Temperature, Figure 11. Capacitance Input Error vs. Capacitance Between EXC and GND, V = 3.3 V, CIN and EXC Pins Open Circuit DD Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V Rev. 0 | Page 8 of 24 GAIN ERROR (%FSR) OFFSET CAPACITANCE (fF) INL (% of FSR) 07450-106 07450-108 07450-107 GAIN ERROR (%FSR) GAIN ERROR (%FSR) GAIN ERROR (%FSR) 07450-109 07450-111 07450-110 AD7152/AD7153 10 0.3 0 0.2 –10 0.1 –20 0 –30 –0.1 –0.2 –40 –0.3 –50 0 50 100 150 200 250 300 350 1 10 100 1000 CAP LOAD TO GND (pF) PARALLEL RESISTANCE (MΩ) Figure 12. Capacitance Input Error vs. Capacitance Between EXC and GND, Figure 15. Capacitance Input Error vs. Parasitic Parallel Resistance Differential Mode, CIN(+) to EXC = 8 pF, Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V CIN(−) to EXC = 6 pF, VDD = 3.3 V 2 0 3pF –5 0 –10 –2 9pF –4 –15 –6 –20 –8 –25 –30 –10 1 10 100 1000 0 2040 6080 100 RESISTANCE CIN TO GROUND (MΩ) SERIAL RESISTANCE (kΩ) Figure 13. Capacitance Input Error vs. Parasitic Resistance CIN to GND, Figure 16. Capacitance Input Error vs. Serial Resistance, Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V Single-Ended Mode, CIN(+) to EXC = 3 pF and 9 pF, VDD = 3.3 V 0.6 0.2 0.4 0.0 0.2 –0.2 0 –0.4 –0.2 –0.6 –0.4 –0.8 –0.6 –1.0 1 10 100 1000 2.6 2.8 3.0 3.2 3.4 3.6 3.8 RESISTANCE EXC TO GROUND (MΩ) VDD (V) Figure 14. Capacitance Input Error vs. Parasitic Resistance EXC to GND, Figure 17. Capacitance Input Power Supply Rejection (PSR), Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V Differential Mode; CIN(+) to EXC = 1.9 pF Rev. 0 | Page 9 of 24 GAIN ERROR (%FSR) GAIN ERROR (%FSR) GAIN ERROR (%FSR) 07450-113 07450-114 07450-112 GAIN ERROR (fF) GAIN ERROR (%FSR) GAIN ERROR (%FSR) 07450-116 07450-115 07450-117 AD7152/AD7153 30 0 20 –20 10 0 –40 –10 –60 –20 –80 –30 0 5 10 15 20 25 30 0 50 100 150 CAPDAC CODE INPUT SIGNAL FREQUENCY (Hz) Figure 18. CAPDAC(+) Differential Nonlinearity (DNL) Figure 20. Capacitance Channel Frequency Response, Conversion Time = 60 ms 30 0 20 –20 10 0 –40 –10 –60 –20 –30 –80 0 5 10 15 20 25 30 0 50 100 150 CAPDAC CODE INPUT SIGNAL FREQUENCY (Hz) Figure 21. Capacitance Channel Frequency Response, Figure 19. CAPDAC(−) Differential Nonlinearity (DNL) Conversion Time = 50 ms Rev. 0 | Page 10 of 24 DNL (fF) DNL (fF) 07450-119 07450-118 FILTER GAIN (dB) FILTER GAIN (dB) 07450-221 07450-120 AD7152/AD7153 SERIAL INTERFACE 2 A stop condition is defined by a low-to-high transition on SDA The AD7152/AD7153 support an I C-compatible, 2-wire serial 2 while SCL remains high. If a stop condition is ever encountered interface. The two wires on the I C bus are called SCL (clock) by the AD7152/AD7153, it returns to its idle condition and the and SDA (data). These two wires carry all addressing, control, address pointer is reset to Address 0x00. and data information one bit at a time over the bus to all connected peripheral devices. The SDA wire carries the data, while the If a data byte is transmitted after the register address pointer SCL wire synchronizes the sender and receiver during the byte, the AD7152/AD7153 load this byte into the register that 2 data transfer. I C devices are classified as either master or slave is currently addressed by the address pointer register. The parts devices. A device that initiates a data transfer message is called a send an acknowledge and the address pointer autoincrementer master; a device that responds to this message is called a slave. automatically increments the address pointer register to the next internal register address. Thus, subsequent transmitted To control the AD7152/AD7153 via the bus, the following data bytes are loaded into sequentially incremented addresses. protocol must be followed. The master initiates a data transfer by establishing a start condition, defined by a high-to-low If a repeated start condition is encountered after the address transition on SDA while SCL remains high. This indicates that pointer byte, all peripherals connected to the bus respond the start byte follows. This 8-bit start byte is made up of a 7-bit exactly as previously outlined for a start condition, that is, a address plus an R/W bit indicator. repeated start condition is treated the same as a start condition. When a master device issues a stop condition, it relinquishes All peripherals connected to the bus respond to the start control of the bus, allowing another master device to take condition and shift in the next 8 bits (7-bit address and an control. Hence, a master wanting to retain control of the bus R/W bit). The bits arrive MSB first. The peripheral that issues successive start conditions known as repeated start recognizes the transmitted address responds by pulling the conditions. data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices withdraw from the bus at READ OPERATION this point and maintain an idle condition. An exception to this When a read is selected in the start byte, the register that is is the general call address, which is described in the General currently addressed by the address pointer is transmitted onto Call section. The idle condition is where the device monitors the SDA line by the AD7152/AD7153. The regulator is then the SDA and SCL lines waiting for the start condition and the clocked out by the master device, and the AD7152/AD7153 correct address byte. The R/W bit determines the direction of await an acknowledge from the master. the data transfer. A Logic 0 LSB in the start byte means that the If an acknowledge is received from the master, the address master writes information to the addressed peripheral. In this autoincrementer automatically increments the address pointer case, the device becomes a slave receiver. A Logic 1 LSB in the register and outputs the next addressed register content onto start byte means that the master reads information from the the SDA line for transmission to the master. If no acknowledge addressed peripheral. In this case, the device becomes a slave is received, the AD7152/AD7153 return to the idle state and the transmitter. In all instances, the AD7152/AD7153 act as a 2 address pointer is not incremented. standard slave device on the I C bus. The autoincrementer of the address pointers allows block data The start byte address is Address 0x90 for a write and Address to be written or read from the starting address and subsequent 0x91 for a read. incremental addresses. WRITE OPERATION In continuous conversion mode, autoincrementer of the address When a write is selected, the byte following the start byte is pointers should be used for reading a conversion result; that is, always the register address pointer (subaddress) byte, which the three data bytes should be read using one multibyte read points to one of the internal registers on the AD7152/AD7153. transaction rather than three separate single-byte transactions. The address pointer byte is automatically loaded into the The single-byte data read transaction may result in the data address pointer register and acknowledged by the AD7152/ bytes from two different results being mixed. AD7153. After the address pointer byte acknowledge, a stop condition, a repeated start condition, or another data byte can follow from the master. Rev. 0 | Page 11 of 24 AD7152/AD7153 The user can also access any unique register (address) on a AD7152/AD7153 RESET one-to-one basis without having to update all the registers. To reset the AD7152/AD7153 without having to reset the entire However, the address pointer register contents cannot be read. 2 I C bus, an explicit reset command is provided. This command If an incorrect address pointer location is accessed, or if the user uses a particular address pointer word as a command word to allows the autoincrementer to exceed the required register reset the part and upload all default settings. The AD7152/ 2 address, apply the following requirements: AD7153 do not respond to the I C bus commands (no acknowl- edge) during the default values upload for approximately 150 μs • In read mode, the AD7152/AD7153 continue to output (maximum 200 μs). various internal register contents until the master device issues a no acknowledge, start, or stop condition. The The reset command address word is 0xBF. contents of the address pointers autoincrementer are reset GENERAL CALL to point to the status register at Address 0x00 when a stop When a master issues a slave address consisting of seven 0s with condition is received at the end of a read operation. This the eighth bit (R/W bit) set to 0, this is called the general call allows the status register to be read (polled) continually address. The general call address is for addressing every device without having to constantly write to the address pointer. 2 connected to the I C bus. The AD7152/AD7153 acknowledge • In write mode, the data for the invalid address is not this address and read the following data byte. loaded into the registers of the AD7152/AD7153, but If the second byte is 0x06, the AD7152/AD7153 are reset, an acknowledge is issued by the AD7152/AD7153. completely uploading all default values. The AD7152/AD7153 2 do not respond to the I C bus commands (no acknowledge) during the default values upload for approximately 150 μs (maximum 200 μs). The AD7152/AD7153 do not acknowledge any other general call commands. SDA SCL S 1 to 7 89 1 to 7 8 9 1 to 7 8 9 P START ADDR ACK SUBADDRESS ACK DATA ACK STOP R/W Figure 22. Bus Data Transfer WRITE S SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P SEQUENCE LSB = 1 LSB = 0 READ A(M) A(M) S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA DATA P SEQUENCE Figure 23. Write and Read Sequences 2 Table 5. I C Abbreviation Abbreviation Definition S Start bit P Stop bit A(S) Acknowledge by slave A(M) Acknowledge by master No acknowledge by slave A(S) A(M) No acknowledge by master ACK Acknowledge R/W Read/write Rev. 0 | Page 12 of 24 07450-006 07450-007 AD7152/AD7153 REGISTER MAP The master can write to or read from all of the registers except read/write operation is selected, the address pointer register is the address pointer register, which is a write-only register. The set up. The address pointer register determines from or to which address pointer register determines which register the next read register the operation takes place. A read/write operation is or write operation accesses. All communications with the part performed from/to the target address, which then increments to through the bus start with an access to the address pointer the next address until a stop command on the bus is performed. register. After the part has been accessed over the bus and a Table 6. Register Summary Subaddress Default Register Name Dec Hex Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value Status 0 0x00 R PWDN Unused Unused Unused Unused C1C2 RDY2 RDY1 0x03 Channel 1 Data MSB 1 0x01 R Channel 1 data, high byte 0x00 Channel 1 Data LSB 2 0x02 R Channel 1 data, low byte 0x00 1 Channel 2 Data MSB 3 0x03 R Channel 2 data, high byte 0x00 Channel 2 Data LSB 4 0x04 R Channel 2 data, low byte 0x00 Channel 1 Offset MSB 5 0x05 R/W Channel 1 offset calibration coefficient, high byte 0x80 Channel 1 Offset LSB 6 0x06 R/W Channel 1 offset calibration coefficient, low byte 0x00 1 Channel 2 Offset MSB 7 0x07 R/W Channel 2 offset calibration coefficient, high byte 0x80 1 Channel 2 Offset LSB 8 0x08 R/W Channel 2 offset calibration coefficient, low byte 0x00 Channel 1 Gain MSB 9 0x09 R/W Channel 1 gain coefficient, high byte, factory calibrated 0xXX Channel 1 Gain LSB 10 0x0A R/W Channel 1 gain coefficient, low byte, factory calibrated 0xXX Channel 1 Setup 11 0x0B R/W Range 1 Range 0 CAPDIFF Unused Unused 0x00 1 12 0x0C R/W Channel 2 gain coefficient, high byte, factory calibrated 0xXX Channel 2 Gain MSB 1 Channel 2 Gain LSB 13 0x0D R/W Channel 2 gain coefficient, low byte, factory calibrated 0xXX 1 Channel 2 Setup 14 0x0E R/W Range 1 Range 0 CAPDIFF Unused Unused 0x00 Configuration 15 0x0F R/W Unused Unused Unused Ch1en Ch2en MD2 MD1 MD0 0x00 Reserved 16 0x10 R/W Unused 0x00 CAPDAC POS 17 0x11 R/W DACPen Unused Unused DACP Bits[4:0] value 0x00 CAPDAC NEG 18 0x12 R/W DACNen Unused Unused DACN Bits[4:0] value 0x00 Configuration2 26 0x1A R/W Unused Unused OSR1 OSR0 Unused Unused Unused Unused 0x00 1 AD7152 only. Rev. 0 | Page 13 of 24 AD7152/AD7153 STATUS REGISTER Address 0x00 Read Only Default Value 0x03 This register indicates the status of the converter. The status register can be read via the 2-wire serial interface to query a finished conversion. Table 7. Status Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic PWDN Unused Unused Unused Unused C1C2 RDY2 RDY1 Default 0 0 0 0 0 0 1 1 Table 8. Status Register Bit Descriptions Bit Mnemonic Description 7 PWDN PWDN = 1 indicates that the V voltage level is below 2.45 V typically or part is in power-down mode DD 6 to 3 N/A Not used, always read 0 2 C1C2 C1C2 = 0 indicates that the last conversion performed was from Channel 1, C1C2 = 1 indicates that the last conversion performed was from Channel 2 1 RDY2 RDY2 = 0 indicates that a conversion on the Channel 2 has been finished and new unread data is available (AD7152 only) 0 RDY1 RDY1 = 0 indicates that a conversion on the Channel 1 has been finished and new unread data is available Rev. 0 | Page 14 of 24 AD7152/AD7153 Therefore, to prevent incorrect data reading through the DATA REGISTERS serial interface, the two bytes of a data register should be Address 0x01, Address 0x02 for Channel 1 read sequentially using the register address pointer auto- Address 0x03, Address 0x04 (AD7152 Only) Channel 2 increment feature of the serial interface. 16 Bits, Read-Only, Default Value 0x0000 Data from the last complete capacitance-to-digital conversion OFFSET CALIBRATION REGISTERS reflects the capacitance on the input. Only the 12 MSBs of the Address 0x05, Address 0x06 for Channel 1, data registers are used for the CDC result. The 4 LSBs are Address 0x07, Address 0x08 for Channel 2 (AD7152 Only) always 0, as shown in Figure 24. 16 Bits Read/Write, Default Value 0x8000 MSB DATA HIGH DATA LOW LSB The offset calibration registers hold the zero-scale calibration BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 coefficients. 12-BIT CDC RESULT 0 The zero-scale calibration coefficient digitally maps the zero Figure 24. CDC Data Register capacitance on the CDC input to the zero-scale data code. The coefficient can be used for compensation of the AD7152/ The AD7152/AD7153 are factory gain calibrated and map the AD7153 internal offset as well as the system level offset within CDC full-scale raw data range of 0x3000 to 0xCFF0F to a CDC specified offset calibration limits. full-scale data register range of 0x0000 to 0xFFF0 (see Table 9). Users can set the coefficient by executing the offset calibration Table 9. AD7152/AD7153 Capacitance-to-Data Mapping after connecting the zero-scale capacitance to the system input. Input Capacitance (4 pF range) Alternatively, the coefficient value can be written to the offset Data Reg Differential Mode Single-Ended Mode calibration register(s) by the host software, for example, values 0x0000 Negative full scale (–2 pF) Zero scale (0 pF) stored in a host nonvolatile memory. 0x8000 Zero scale (0 pF) Midscale (2 pF) Note that there is a difference between code mapping in differ- 0xFFF0 Positive full scale (+2 pF) Full scale (4 pF) ential and single-ended input mode. In differential mode, the The data register output in differential mode is internally nominal zero-scale calibration coefficient value is a power-on calculated using the following equation: default, 0x8000. In single–ended mode, the nominal zero-scale calibration coefficient value is 0x3000. Data Reg = (Code – (Offset Reg – 0x8000)) × Gain + 0x8000 (1) The difference means that before using the single-ended mode The input capacitance can be calculated from the output data (or any time when changing between modes afterwards), the using the following equation: user should either perform offset calibration with capacitance Data Reg− 0x8000 close to 0 pF connected to the input or write the offset calibra- C(pF)= × Input Range (2) 0 xFFF0 tion register(s) value(s) close to 0x8000 for differential mode or The data register output in single-ended mode is internally value close to 0x3000 for single-ended mode. calculated using the following equation: On the AD7152, the two capacitive channels have individual Data Reg = (Code − (Offset Reg − 0x3000)) × Gain (3) offset registers and each channel can be calibrated individually. The input capacitance can be calculated from the output data GAIN CALIBRATION REGISTERS using the following equation: Address 0x09, Address 0x0A for Channel1 Address 0x0C, Address 0x0D for Channel 2 (AD7152 only) Data Reg C(pF)= × Input Range (4) 16 Bits Read/Write, Default Value 0xXXXX 0 xFFF0 The capacitive gain calibration registers hold the capacitive where Input Range = 4 pF, 2 pF, 1 pF, or 0.5 pF. channel full-scale factory calibration coefficient. The gain A data register is updated after a finished conversion on the calibration factor can be calculated using the following capacitive channel, with one exception: when the serial interface equation: read operation from the data register is in progress, the data 16 2 + Gain Reg register is not updated and the new capacitance conversion Gain= (5) 16 result is lost. 2 The stop condition on the serial interface is considered to be the On the AD7152, the two capacitive channels each have a gain register, which allows the part to gain calibrate each channel end of the read operation. individually. Rev. 0 | Page 15 of 24 07450-044 AD7152/AD7153 CAP SETUP REGISTERS Address 0x0B for Channel 1 Address 0x0E Channel 2 (AD7152 Only) Default Value 0x00 Table 10. CAP Setup Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic Range 1 Range 0 CAPDIFF Unused Unused Unused Unused Unused Default 0 0 0 0 0 0 0 0 Table 11. CAP Setup Register Bit Descriptions Bit Mnemonic Description 7 Range 1 Capacitive input range and mode setup 6 Range 0 Capacitive Input Range 5 CAPDIFF Range 1 Range 0 CAPDIFF = 1 (Differential Mode) CAPDIFF = 0 (Single-Ended Mode) 0 0 ±1 pF 2 pF 0 1 ±0.25 pF 0.5 pF 1 0 ±0.5 pF 0.25 pF 1 1 ±2 pF 4 pF 4 to 0 N/A These bits must be 0 for proper operation CONFIGURATION REGISTER Address Pointer 0x0F Default Value 0x00 Table 12. Configuration Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic Unused Unused Unused Ch1en Ch2en MD2 MD1 MD0 Default 0 0 0 0 0 0 0 0 Table 13. Configuration Register Bit Descriptions Bit Mnemonic Description 7 to 5 N/A These bits must be 0 for proper operation 4 Ch1en Ch2en = 1 enables Channel 1 for single conversion, continuous conversion, or calibration 3 Ch2en Ch2en = 1 enables Channel 2 for single conversion, continuous conversion, or calibration 2 MD2 Converter mode of operation setup 1 MD1 MD2 MD1 MD0 Mode 0 MD0 0 0 0 Idle 0 0 1 Continuous conversion 0 1 0 Single conversion 0 1 1 Power-down 1 0 0 N/A 1 0 1 Capacitance system offset calibration 1 1 0 Capacitance system gain calibration 1 1 1 N/A Rev. 0 | Page 16 of 24 AD7152/AD7153 CAPDAC POS REGISTER Address 0x11 Default Value 0x00 Table 14. Status Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic DACPen Unused Unused DACP – Bits[4:0] Value Default 0 0 0 0x00 Table 15. Status Register Bit Descriptions Bit Mnemonic Description 7 DACPen DACPen = 1 connects the capacitive DAC POS to the positive capacitive input 6 to 5 N/A These bits must be 0 for proper operation 4 to 0 DACP DACP value, Code 0x00 = 0 pF, Code 0x1F = full range CAPDAC NEG REGISTER Address 0x12 Default Value 0x00 Table 16. Status Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic DACNen Unused Unused DACN – Bit[4:0] Value Default 0 0 0 0x00 Table 17. Status Register Bit Descriptions Bit Mnemonic Description 7 DACNen DACNen = 1 connects the capacitive DAC NEG to the positive capacitive input 6 to 5 N/A These bits must be 0 for proper operation 4 to 0 DACN DACN value, Code 0x00 = 0 pF, Code 0x1F = full range CONFIGURATION2 REGISTER Address 0x1A, Default Value 0x00 Table 18. Configuration2 Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic Unused Unused OSR1 OSR0 Default 0 0 0 0 0 0 0 0 Table 19. Configuration2 Register Bit Descriptions Bit Mnemonic Description 7 to 6 N/A These bits must be 0 for proper operation 5 OSR1 Capacitive channel digital filter setup; conversion time/update rate setup per channel 4 OSR0 OSR1 OSR0 Conversion Time (ms) Update Rate (Hz) 0 0 5 200 0 1 20 50 1 0 50 20 1 1 60 16.7 3 to 0 N/A These bits must be 0 for proper operation Rev. 0 | Page 17 of 24 AD7152/AD7153 CIRCUIT DESCRIPTION VDD CAPACITANCE-TO-DIGITAL CONVERTER (CDC) AD7152 CAP+ Figure 27 shows the CDC simplified functional diagram. The CLOCK VOLTAGE CAP– measured capacitance C is connected between the excitation X GENERATOR REFERENCE source and the Σ-Δ modulator input. A square-wave excitation CIN1(+) CIN1(–) signal is applied on the CX during the conversion and the mod- SDA 2 I C EXC1 12-BIT Σ-Δ ulator continuously samples the charge going through the CX. MUX SERIAL MODULATOR CIN2(+) INTERFACE The digital filter processes the modulator output, which is a SCL CIN2(–) stream of 0s and 1s containing the information in 0 and 1 EXC2 density. The data from the digital filter is scaled, applying the DIGITAL CONTROL LOGIC EXCITATION FILTER CALIBRATION calibration coefficients, and the final result can be read through the serial interface. The AD7152/AD7153 are designed for GND plates have to floating capacitive sensors. Therefore, both CX Figure 25. AD7152 Block Diagram be isolated from ground. VDD CAPACITANCE-TO-DIGITAL CONVERTER AD7153 (CDC) CAP+ CLOCK VOLTAGE CLOCK CAP– GENERATOR REFERENCE GENERATOR DATA CIN1(+) SDA CIN 2 12-BIT Σ-Δ DIGITAL I C 12-BIT Σ-Δ MODULATOR FILTER CIN1(–) MUX SERIAL MODULATOR INTERFACE SCL C X EXC1 EXC EXCITATION EXCITATION DIGITAL CONTROL LOGIC FILTER CALIBRATION Figure 27. CDC Simplified Block Diagram GND EXCITATION SOURCE Figure 26. AD7153 Block Diagram The AD7152/AD7153 have one excitation source. For the The core of the AD7152/AD7153 is a precision converter AD7152, the excitation source is switched between the consisting of a second-order modulator (Σ-Δ or charge- excitation pins, EXC1 and EXC2, depending on which balancing) and a third-order digital filter. channel performs a conversion. In addition to the converter, the AD7152/AD7153 integrate a multiplexer, an excitation source, and CAPDACs for the capaci- tive inputs, a voltage reference, a complete clock generator, a 2 control and calibration logic, and an I C-compatible serial interface. The AD7153 has one capacitive input, while the AD7152 has two capacitive inputs. For the AD7152, the modulator input and the excitation source are multiplexed between the converting channel. All other features and specifications are identical for both parts. Rev. 0 | Page 18 of 24 07450-026 07450-025 07450-027 AD7152/AD7153 CAPDAC SINGLE-ENDED CAPACITIVE INPUT The CDC full-scale input range of the AD7152/AD7153 can When configured for a single-ended mode (the CAPDIFF bit in be set to ±0.25 pF, ±0.5 pF, ± 1 pF, and ±2 pF in differential the Channel 1 Setup or Channel 2 Setup registers is set to 0), the mode or 0.5 pF, 1 pF, 2 pF, and 4 pF in single-ended mode. AD7152/AD7153 CIN(−) pin is disconnected internally. The For simplicity, the following text and figures use the maximum CDC (without using the CAPDACs) can measure positive input full scale of ±2 pF and +4 pF. capacitance in the range of 0 pF to 4 pF (see Figure 29). The parts can accept a higher capacitance on the input and the common-mode or offset capacitance (unchanging component) CAPDAC(+) OFF can be balanced by programmable on-chip CAPDACs. 0x0000 ... 0xFFF0 CIN(+) DATA 0pF TO 4pF CAPDIFF = 0 CDC CAPDAC(+) CIN(–) CIN(+) CAPDAC(–) C DATA CDC X OFF CIN(–) 0pF TO 4pF EXC CAPDAC(–) C C X Y Figure 29. CDC Single-Ended Input Mode EXC The CAPDAC can be used for programmable shifting of the input range. Figure 28. Using a CAPDAC Figure 30 shows how to shift the input range up to 9 pF absolute The CAPDAC can be understood as a negative capacitance value of capacitance connected to the CIN(+) using connected internally to the CIN pin. There are two independent the CAPDAC(+) only. CAPDACs, one connected to the CIN(+) and the second connected to the CIN(–). CAPDAC(+) 5pF In differential mode, the relationship between the capacitance 0x0000 ... 0xFFF0 CIN(+) input and output data can be expressed as DATA 0pF TO 4pF CAPDIFF = 0 CDC DATA ≈ (CX − CAPDAC(+)) − (CY − CAPDAC(−)) CIN(–) In single-ended mode, the relationship between the capacitance CAPDAC(–) input and output data can be expressed as C X OFF 5pF TO 9pF DATA ≈ C −(CAPDAC(+) + CAPDAC(−)) X EXC The CAPDACs have a 5-bit resolution each, monotonic transfer function, are well matched to each other, and have a defined Figure 30. Using CAPDAC in Single-Ended Mode temperature coefficient. The CAPDAC full range (absolute value) is not factory calibrated and can vary up to ±20% with Figure 31 shows how to shift the input range up to 14 pF the manufacturing process (see the Specifications section, absolute value of capacitance connected to the CIN(+) using Figure 18, and Figure 19). both CAPDAC(+) and CAPDAC(−). The CAPDACs are shared by the two capacitive channels on the CAPDAC(+) AD7152. If the CAPDACs need to be set individually, the host 5pF controller software should reload the CAPDAC values to the CIN(+) 0x0000 ... 0xFFF0 DATA AD7152 before executing a conversion on a different channel. 0pF TO 4pF CAPDIFF = 0 CDC CIN(–) CAPDAC(–) C X 5pF 10pF TO 14pF EXC Figure 31. Using CAPDAC in Single-Ended Mode Rev. 0 | Page 19 of 24 07450-010 07450-224 07450-124 07450-024 AD7152/AD7153 DIFFERENTIAL CAPACITIVE INPUT PARASITIC CAPACITANCE TO GROUND When configured for differential mode (the CAPDIFF bit in the Channel 1 Setup or Channel 2 Setup registers is set to 1), the CDC measures the difference between positive and negative C GND1 DATA CIN capacitance input. CDC Each of the two input capacitances, C and C , between the X Y EXC and CIN pins must be less than 2 pF (without using the C X CAPDACs) or must be less than 9 pF and balanced by the CAPDACs. Balancing by the CAPDACs means that both C GND2 EXC CX − CAPDAC(+) and CY − CAPDAC(−) are less than 2 pF. If the unbalanced capacitance between the EXC and CIN pins is higher than 2 pF, the CDC introduces a gain error, an offset Figure 35. Parasitic Capacitance to Ground error, and nonlinearity error (see Figure 32, Figure 33, and The CDC architecture used in the AD7152/AD7153 measures Figure 34). CX connected between the EXC pin and the CIN pin. In theory, any capacitance, CGND, to ground should not affect the CDC CAPDAC(+) result (see Figure 35). OFF 0x0000 ... 0xFFF0 CIN(+) The practical implementation of the circuitry in the chip DATA ±2pF implies certain limits and the result is gradually affected by CAPDIFF = 1 CDC CIN(–) capacitance to ground. See the allowed capacitance to GND in the Specifications table and, Figure 9 through Figure 12. CAPDAC(–) OFF PARASITIC RESISTANCE TO GROUND C C X Y 0pF TO 4pF 0pF TO 4pF EXC Figure 32. CDC Differential Input Mode R GND1 CIN DATA CDC CAPDAC(+) C X 5pF CIN(+) 0x0000 ... 0xFFF0 DATA R GND2 ±2pF EXC CAPDIFF = 1 CDC CIN(–) Figure 36. Parasitic Resistance to Ground CAPDAC(–) 5pF C C The CDC result can be affected by a leakage current from X Y 4pF TO 6pF 4pF TO 6pF the C to ground; therefore, the C should be isolated from X X (5 ± 1pF) (5 ± 1pF) EXC the ground. The influence of the leakage current varies with the power supply voltage (see Figure 36). Figure 33. Using CAPDAC in Differential Mode A higher leakage current to ground results in a gain error, an offset error, and a nonlinearity error (see Figure 13 and Figure 14). CAPDAC(+) 5pF 0x0000 ... 0xFFF0 CIN(+) DATA ±2pF CAPDIFF = 1 CDC CIN(–) CAPDAC(–) C C 5pF X Y 3pF TO 7pF 5pF (5 ± 2pF) EXC Figure 34. Using CAPDAC in Differential Mode Rev. 0 | Page 20 of 24 07450-121 07450-021 07450-020 07450-013 07450-012 AD7152/AD7153 Some applications may require an additional input filter for PARASITIC PARALLEL RESISTANCE improving electromagnetic compatibility (EMC). Any input filter must be carefully designed, considering the balance between the system capacitance performance and system electromagnetic DATA CIN immunity. CDC Figure 39 shows one of the possible input circuit configurations significantly improving the system immunity against high fre- C R X P quency noise and slightly affecting the AD7152 performance in terms of additional gain and offset error. EXC POWER SUPPLY DECOUPLING AND FILTERING 1kΩ V DD Figure 37. Parasitic Parallel Resistance 0.1µF 10µF 1kΩ 1kΩ The CDC measures the charge transfer between the EXC pin SDA and CIN pin. Any resistance connected in parallel to the meas- SCL ured capacitance C (see Figure 37), such as the parasitic CDC X resistance of the sensor, also transfers charge. Therefore, the parallel resistor is seen as an additional capacitance in the GND output data causing a capacitive input error (see Figure 15). Figure 40. AD7152/AD7153 VDD Decoupling and Filtering PARASITIC SERIAL RESISTANCE The AD7152 has good dc and low frequency power supply rejection but may be sensitive to higher frequency ripple and noise, specifically around the excitation frequency and its R S1 CIN DATA harmonics. Figure 40 shows a possible circuit configuration CDC for improving the system immunity against ripple and noise coupled to the AD7152 via the power supply. C X Because the serial interface is connected to the other circuits in the system, it is better to connect the pull-up resistors on the R other side of the V filter than to connect to the AD7152. S2 EXC DD CAPACITIVE GAIN CALIBRATION Figure 38. Parasitic Serial Resistance The gain of the AD7152/AD7153 is factory calibrated for the The CDC result is affected by a resistance in series with the full scale of 4 pF in the production for each part individually. measured capacitance. The total serial resistance, which refers The factory gain coefficient is stored in a one-time program- to RS1 and RS2 in Figure 38, should be less than 20 kΩ for the mable (OTP) memory and is copied to the capacitive gain specified performance (see Figure 16). registers at power-up or after reset. INPUT EMC PROTECTION The gain can be changed by executing a capacitance gain R1 R2 CIN calibration mode, for which an external full-scale capacitance C1 C2 needs to be connected to the capacitance input, or by writing a user value to the capacitive gain register. This change is tempo- C CDC X rary and the factory gain coefficient can be reloaded after R3 EXC power-up or reset. The part is tested and specified only for GND use with the default factory calibration coefficient. C3 CAPACITIVE SYSTEM OFFSET CALIBRATION Figure 39. AD7152/AD7153 EMC Protection The capacitive offset is dominated by the parasitic offset in the application, such as the initial capacitance of the sensor, any parasitic capacitance of tracks on the board, and the capacitance of any other connections between the sensor and the CDC. Therefore, the AD7152/AD7153 are not factory calibrated for capacitive offset. The user should calibrate the system capacitance offset in the application. Rev. 0 | Page 21 of 24 07450-039 07450-022 07450-023 07450-058 AD7152/AD7153 The offset register of the AD7152/AD7153 allows for offset calibration coefficient value should be stored by the host calibration over the full capacitive input range. However, the controller and reloaded as part of the AD7152/AD7153 setup. user must ensure that the offset to be removed is within 40% of Note that the AD7152/AD7153 zero scale for differential mode the full scale range; this can be achieved by using the CAPCAC is around 0x8000; therefore, the offset register also needs a to perform a coarse offset calibration and use the system offset value of around 0x8000, where the zero scale in single-ended calibration then to compensate for an offset within the 40% of mode is 0x0000, with a required offset register value of 0x3000. full-scale range pF of the CAPDAC. For more detailed information, see the Data Registers section. The offset calibration register is reloaded by the default value 0x8000 at power-on or after reset. Therefore, if the offset calibration is not repeated after each system power-up, the TYPICAL APPLICATION DIAGRAM 1kΩ 3.3V V SUPPLY ADP1720-3.3 0.1µF 10µF 1µF 1µF VDD R1 R2 CIN1(+) 1kΩ 1kΩ AD7153 C1 C2 SDA HOST SYSTEM SCL R3 R4 CIN1(–) C3 C4 GND C C SENS1 SENS2 10kΩ EXC1 47pF GND Figure 41. Basic Application Diagram for a Differential Capacitive Sensor Rev. 0 | Page 22 of 24 07450-061 AD7152/AD7153 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.33 0.60 SEATING 0.23 0° 0.05 0.17 PLANE 0.40 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 42. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding 1 AD7152BRMZ −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 C5P 1 AD7152BRMZ-REEL −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 C5P 1 AD7153BRMZ −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 C5Q 1 AD7153BRMZ-REEL −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 C5Q 1 EVAL-AD7152EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. 0 | Page 23 of 24 AD7152/AD7153 NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07450-0-5/08(0) Rev. 0 | Page 24 of 24