ANALOG DEVICES AD7151

Ultra-Low Power, 1-Channel, Capacitance Converter for Proximity Sensing AD7151 FEATURES GENERAL DESCRIPTION Ultra-low power The AD7151 delivers a complete signal processing solution for 2.7 V to 3.6 V, 70 μA capacitive proximity sensors, featuring an ultra-low power Response time: 10 ms converter with fast response time. The AD7150 is a 2-channel Adaptive environmental compensation alternative to the AD7151. 1 capacitance input channel The AD7151 uses Analog Devices, Inc., capacitance-to-digital Sensor capacitance (C ) 0 pF up to 13 pF SENS converter (CDC) technology, which combines features Sensitivity to 1 fF important for interfacing to real sensors, such as high input EMC tested sensitivity and high tolerance of both input parasitic ground 2 modes of operation capacitance and leakage current. Standalone with fixed settings The integrated adaptive threshold algorithm compensates for Interfaced to a microcontroller for user-defined settings any variations in the sensor capacitance due to environmental Proximity detection output flag 2 factors like humidity and temperature or due to changes in the 2-wire serial interface (I C compatible) dielectric material over time. Operating temperature −40°C to +85°C By default, the AD7151 operates in standalone mode using the 10-lead MSOP package fixed power-up settings and indicates detection on a digital output. Alternatively, the AD7151 can be interfaced to a APPLICATIONS microcontroller via the serial interface, the internal registers can Proximity sensing be programmed with user-defined settings, and the data and Contactless switching status can be read from the part. Position detection The AD7151 operates with a 2.7 V to 3.6 V power supply. It is Level detection specified over the temperature range of −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM VDD AD7151 CIN SCL DIGITAL SERIAL Σ-Δ CDC FILTER INTERFACE C SENS SDA EXCITATION EXC THRESHOLD OUT GND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07086-001 AD7151 TABLE OF CONTENTS Features .............................................................................................. 1 Fixed Threshold Register........................................................... 16 Applications....................................................................................... 1 Sensitivity Register ..................................................................... 16 General Description ......................................................................... 1 Timeout Register ........................................................................ 17 Functional Block Diagram .............................................................. 1 Setup Register ............................................................................. 18 Revision History ............................................................................... 2 Configuration Register .............................................................. 19 Specifications..................................................................................... 3 Power-Down Timer Register .................................................... 20 Timing Specifications .................................................................. 4 CAPDAC Register...................................................................... 20 Absolute Maximum Ratings............................................................ 5 Serial Number Register.............................................................. 20 ESD Caution.................................................................................. 5 Chip ID Register......................................................................... 20 Pin Configuration and Function Descriptions............................. 6 Serial Interface ................................................................................ 21 Typical Performance Characteristics ............................................. 7 Read Operation........................................................................... 21 Architecture and Main Features ................................................... 10 Write Operation.......................................................................... 21 Capacitance-to-Digital Converter............................................ 10 AD7151 Reset ............................................................................. 22 CAPDAC ..................................................................................... 10 General Call ................................................................................ 22 Comparator and Threshold Modes.......................................... 11 Hardware Design Considerations ................................................ 23 Adaptive Threshold.................................................................... 11 Overview ..................................................................................... 23 Data Average ............................................................................... 11 Parasitic Capacitance to Ground.............................................. 23 Sensitivity..................................................................................... 12 Parasitic Resistance to Ground................................................. 23 Hysteresis..................................................................................... 12 Parasitic Parallel Resistance ...................................................... 23 Timeout........................................................................................ 12 Parasitic Serial Resistance ......................................................... 24 AutoCAPDAC Adjustment....................................................... 13 Input Overvoltage Protection ................................................... 24 Power-Down Timer ................................................................... 13 Input EMC Protection ............................................................... 24 Power Supply Monitor ............................................................... 13 Power Supply Decoupling and Filtering.................................. 24 Register Descriptions ..................................................................... 14 Application Examples ................................................................ 25 Status Register............................................................................. 15 Outline Dimensions....................................................................... 26 Data Register ............................................................................... 16 Ordering Guide .......................................................................... 26 Average Register ......................................................................... 16 REVISION HISTORY 11/07—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7151 SPECIFICATIONS VDD = 2.7 V to 3.6 V; GND = 0 V; –40°C to +85°C, single-ended capacitance mode, unless otherwise noted. Table 1. 1 Parameter Min Typ Max Unit Test Conditions/Comments CAPACITIVE INPUT 2 Conversion Input Range CIN to EXC 3.2 4 pF 4 pF input range 1.6 2 pF 2 pF input range 0.8 1 pF 1 pF input range 0.4 0.5 pF 0.5 pF input range 3 Resolution 2.0 fF 4 pF input range 1.6 fF 2 pF input range 1.4 fF 1 pF input range 1.0 fF 0.5 pF input range 3 Allowed Capacitance CIN to GND 150 pF 3 Allowed Resistance CIN to GND 15 MΩ 3 Allowed Serial Resistance 200 kΩ Gain Error −20 +20 % 3 Gain Deviation over Temperature 0.5 % 3 Gain Matching Between Ranges −2 +2 % 3 Offset Error 50 fF CIN and EXC pins disconnected 3 Offset Deviation over Temperature 5 fF CIN and EXC pins disconnected 3 Integral Nonlinearity (INL) 0.1 % 3 Power Supply Rejection 4 fF/V 2 CAPDAC Full Range 10 12.5 pF 3 Resolution (LSB) 200 fF 3 Differential Nonlinearity (DNL) 0.25 LSB 3 AutoDAC Increment/Decrement 25 75 % of CIN Range EXCITATION Voltage ±VDD/2 V Frequency 15.4 16 16.3 kHz 3 Allowed Capacitance EXC to GND 300 pF 3 Allowed Resistance EXC to GND 1 MΩ LOGIC OUTPUT (OUT) Output Low Voltage (V) 0.4 V I = −4 mA OL SINK Output High Voltage (V) V – 0.6 V I = 4 mA OH DD SOURCE SERIAL INTERFACE INPUTS (SCL, SDA) Input High Voltage (V) 1.5 V IH Input Low Voltage (V) 0.8 V IL Input Leakage Current ±0.1 ±5 μA Input Pin Capacitance 6 pF OPEN-DRAIN OUTPUT (SDA) Output Low Voltage (VOL) 0.4 V I = −6.0 mA SINK Output High Leakage Current (IOH) 0.1 5 μA VOUT = VDD POWER SUPPLY MONITOR VDD Threshold Voltage 2.45 2.65 V Rev. 0 | Page 3 of 28 AD7151 1 Parameter Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS VDD-to-GND Voltage 2.7 3.6 V VDD = 3.3 V, nominal 4 IDD Current 70 80 μA 4 I Current Power-Down Mode 1 5 μA Temperature ≤ 25°C DD 3 10 μA Temperature = 85°C 1 −12 −15 Capacitance units: one picofarad (1 pF) = 1 × 10 farad (F); one femtofarad (1 fF) = 10 farad (F). 2 The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can, therefore, be up to the sum of the CAPDAC value and the conversion input range. With the autoCAPDAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC nominal input range. 3 Specification is not production tested but is supported by characterization data at initial product release. 4 Digital inputs equal to VDD or GND. TIMING SPECIFICATIONS VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +85°C, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments CONVERTER Conversion Time 10 ms 1, 2 Wake-Up Time from Power-Down Mode 0.3 ms 1, 3 Power-Up Time 2 ms 1, 4 Reset Time 2 ms 5, 6 SERIAL INTERFACE See Figure 2. SCL Frequency 0 400 kHz SCL High Pulse Width, t 0.6 μs HIGH SCL Low Pulse Width, t 1.3 μs LOW SCL, SDA Rise Time, tR 0.3 μs SCL, SDA Fall Time, tF 0.3 μs Hold Time (Start Condition), t 0.6 μs After this period, the first clock is generated. HD;STA Setup Time (Start Condition), t 0.6 μs Relevant for repeated start condition. SU;STA Data Setup Time, t 0.1 μs SU;DAT Setup Time (Stop Condition), tSU;STO 0.6 μs Data Hold Time (Master), tHD;DAT 10 ns Bus-Free Time (Between Stop and Start Condition), tBUF 1.3 μs 1 Specification is not production tested but is supported by characterization data at initial product release. 2 Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion. 3 Power-up time is the maximum delay between the VDD crossing the minimum level (2.7 V) and either the start of conversion or when ready to receive a serial interface command. 4 Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial interface command. 5 Sample tested during initial release to ensure compliance. 6 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF. t t R F t t LOW HD;STA SCL t t t HIGH SU;STA SU;STO t HD;STA t t HD;DAT SU;DAT SDA t BUF S PS P Figure 2. Serial Interface Timing Diagram Rev. 0 | Page 4 of 28 07086-002 AD7151 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 3. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational Positive Supply Voltage V to GND DD −0.3 V to +3.9 V section of this specification is not implied. Exposure to absolute Voltage on Any Input or Output to GND –0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect ESD Rating HBM 4 kV device reliability. (ESD Association Human Body Model, S5.1) ESD CAUTION ESD Rating FICDM 1 kV (Field-Inducted Charged Device Model) Operating Temperature Range –40°C to +85°C Storage Temperature Range –65°C to +150°C Maximum Junction Temperature 150°C MSOP Package θ , Thermal Impedance-to-Air 206°C/W JA θ , Thermal Impedance-to-Case 44°C/W JC Reflow Soldering (Pb-Free) Peak Temperature 260(+0/−5)°C Time at Peak Temperature 10 sec to 40 sec Rev. 0 | Page 5 of 28 AD7151 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 10 SDA VDD 2 9 SCL AD7151 NC 3 8 NC TOP VIEW (Not to Scale) CIN 4 7 OUT NC 5 6 EXC NC = NO CONNECT Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 GND Ground Pin. 2 VDD Power Supply Voltage. This pin should be decoupled to GND using a low impedance capacitor, for example, 0.1 μF X7R multilayer ceramic. 3 NC This pin should be left as an open circuit or connected to GND. 4 CIN CDC Capacitive Input. The measured capacitance (sensor) is connected between the EXC pin and the CIN pin. 5 NC This pin should be left as an open circuit. 6 EXC CDC Excitation Output. The measured capacitance is connected between the EXC pin and the CIN pin. 7 OUT Logic Output. High level on this output indicates proximity detected on the capacitive input. 8 NC This pin should be left as an open circuit. 9 SCL Serial Interface Clock Input. Connects to the master clock line. Requires a pull-up resistor if not provided elsewhere in the system. 10 SDA Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided elsewhere in the system. Rev. 0 | Page 6 of 28 07086-003 AD7151 TYPICAL PERFORMANCE CHARACTERISTICS 300 0.10 200 0.05 100 0 0 –0.05 –100 –0.10 03 50 100 150 200 25000 03 50 100 150 200 25000 CAPACITANCE CIN TO GND (pF) CAPACITANCE EXC TO GND (pF) Figure 4. Capacitance Input Offset Error vs. Capacitance CIN to GND, Figure 7. Capacitance Input Gain Error vs. Capacitance EXC to GND, V = 3.3 V, EXC Pin Open Circuit V = 3.3 V, CIN to EXC = 2 pF DD DD 2 200 0 100 –2 0 –4 –100 –6 –8 –200 03 50 100 150 200 25000 11 10 100000 CAPACITANCE CIN TO GND (pF) RESISTANCE CIN TO GND (MΩ) Figure 5. Capacitance Input Gain Error vs. Capacitance CIN to GND, Figure 8. Capacitance Input Offset Error vs. Resistance CIN to GND, VDD = 3.3 V, CIN to EXC = 2 pF VDD = 3.3 V, EXC Pin Open Circuit 2 10 5 1 0 0 –1 –5 –2 –10 11 10 100000 03 50 100 150 200 25000 CAPACITANCE EXC TO GND (pF) RESISTANCE CIN TO GND (MΩ) Figure 6. Capacitance Input Offset Error vs. Capacitance EXC to GND, Figure 9. Capacitance Input Gain Error vs. Resistance CIN to GND, V = 3.3 V, CIN Pin Open Circuit VDD = 3.3 V, CIN to EXC = 2 pF DD Rev. 0 | Page 7 of 28 OFFSET ERROR (fF) GAIN ERROR (%FS) OFFSET ERROR (fF) 07086-106 07086-105 07086-104 GAIN ERROR (%FS) OFFSET ERROR (fF) GAIN ERROR (%FS) 07086-107 07086-109 07086-108 AD7151 10 10 5 5 0 0 –5 –5 –10 –10 01 2 4 6 80 11 10 100000 RESISTANCE EXC TO GND (MΩ) PARALLEL RESISTANCE (MΩ) Figure 10. Capacitance Input Offset Error vs. Resistance EXC to GND, Figure 13. Capacitance Input Gain Error vs. Parallel Resistance, VDD = 3.3 V, CIN Pin Open Circuit V = 3.3 V, CIN to EXC = 2 pF DD 0.50 4 0.25 2 0 0 –0.25 –2 –0.50 –4 01 2 4 6 80 –50 –25 0 25 50 75 100 RESISTANCE EXC TO GND (MΩ) TEMPERATURE (°C) Figure 11. Capacitance Input Gain Error vs. Resistance EXC to GND, Figure 14. Capacitance Input Offset Error vs. Temperature, V = 3.3 V, CIN to EXC = 2 pF DD VDD = 3.3 V, CIN and EXC Pins Open Circuit 2 0.2 0.1 1 0 0 –0.1 –1 –0.2 –2 –0.2 02 50 100 150 20050 –50 –25 0 25 50 75 100 SERIAL RESISTANCE (kΩ) TEMPERATURE (°C) Figure 12. Capacitance Input Gain Error vs. Serial Resistance Figure 15. Capacitance Input Gain Error vs. Temperature, VDD = 3.3 V, CIN to EXC = 2 pF V = 3.3 V, CIN to EXC = 2 pF DD Rev. 0 | Page 8 of 28 GAIN ERROR (%FS) GAIN ERROR (%FS) OFFSET ERROR (fF) 07086-112 07086-111 07086-110 GAIN ERROR (%FS) GAIN ERROR (%FS) OFFSET ERROR (fF) 07086-115 07086-114 07086-113 AD7151 2 0 1 –20 0 –40 –1 –60 –2 –80 –50 –25 0 25 50 75 100 02 0.5 1.0 1.5 2.0.5 TEMPERATURE (°C) INPUT SIGNAL FREQUENCY (kHz) Figure 16. EXC Frequency Error vs. Temperature, Figure 18. Capacitance to Digital Converter Frequency Response VDD = 3.3 V 2 0.50 1 0.25 0 0 –1 –0.25 –2 –0.50 2.7 3.0 3.3 3.6 06 16 32 484 V (V) CAPDAC CODE DD Figure 17. EXC Frequency Error vs. VDD Figure 19. CAPDAC Differential Nonlinearity (DNL), VDD = 3.3 V Rev. 0 | Page 9 of 28 EXC FREQUENCY ERROR (%) EXC FREQUENCY ERROR (%) 07086-117 07086-116 GAIN (dB) CAPDAC DNL (LSB) 07086-119 07086-118 AD7151 ARCHITECTURE AND MAIN FEATURES 3.3V VDD CLOCK POWER-DOWN POWER SUPPLY GENERATOR TIMER MONITOR SCL CIN DIGITAL SERIAL PROGRAMMING Σ-Δ CDC SDA FILTER INTERFACE INTERFACE OUT THRESHOLD DIGITAL CAPDAC C X OUTPUT EXCITATION EXC AD7151 GND Figure 20. AD7151 Block Diagram The AD7151 core is a high performance capacitance-to-digital CAPACITANCE TO DIGITAL CONVERTER (CDC) converter (CDC) that allows the part to be interfaced directly to a capacitive sensor. CLOCK GENERATOR The comparator compares the CDC result with thresholds, either 0x000 TO 0xFFF DATA fixed or dynamically adjusted by the on-chip adaptive threshold CIN Σ-Δ DIGITAL MODULATOR FILTER algorithm engine. Thus, the output indicates a defined change in C X the input sensor capacitance. 0pF TO 4pF EXCITATION EXC The AD7151 also integrates an excitation source and CAPDAC for the capacitive inputs, an input multiplexer, a complete clock generator, a power-down timer, a power supply monitor, control Figure 21. CDC Simplified Block Diagram 2 logic, and an I C®-compatible serial interface for configuring the part and accessing the internal CDC data and status, if required CAPDAC in the system (see Figure 20). The AD7151 CDC core maximum full-scale input range is 4 pF. However, the part can accept a higher capacitance on the input, CAPACITANCE-TO-DIGITAL CONVERTER and the offset (nonchanging component) capacitance of up to 10 Figure 21 shows the CDC simplified functional diagram. The pF can be balanced by a programmable on-chip CAPDAC. converter consists of a second-order sigma delta (Σ-Δ), charge balancing modulator and a third-order digital filter. The measured capacitance CX is connected between an excitation CAPDAC 0x000 TO 0xFFF 10pF DATA source and the Σ-Δ modulator input. The excitation signal is CIN 0pF TO 4pF applied on the CX during the conversion, and the modulator CDC C SENS continuously samples the charge going through the C . The X 10pF TO 14pF digital filter processes the modulator output, which is a stream EXC of 0s and 1s containing the information in 0 and 1 density. The data is processed by the adaptive threshold engine and output Figure 22. Using CAPDAC comparators; the data can be also read through the serial interface. The CAPDAC can be understood as a negative capacitance The AD7151 is designed for floating capacitive sensors. connected internally to the CIN pin. The CAPDAC has a 6-bit Therefore, both CX plates have to be isolated from ground or resolution and a monotonic transfer function. Figure 22 shows any other fixed potential node in the system. how to use the CAPDAC to shift the CDC 4 pF input range to The AD7151 features slew rate limiting on the excitation voltage measure capacitance between 10 pF and 14 pF. output, which decreases the energy of higher harmonics on the excitation signal and dramatically improves the system electromagnetic compatibility (EMC). Rev. 0 | Page 10 of 28 07086-010 07086-012 07086-011 AD7151 INPUT OUTSIDE THRESHOLD WINDOW COMPARATOR AND THRESHOLD MODES POSITIVE The AD7151 comparator and its threshold can be programmed THRESHOLD to operate in several different modes. In an adaptive mode, the INPUT CAPACITANCE NEGATIVE threshold is dynamically adjusted and the comparator output THRESHOLD indicates fast changes and ignores slow changes in the input OUTPUT ACTIVE (sensor) capacitance. Alternatively, the threshold can be programmed as a constant (fixed) value, and the output then OUTPUT indicates any change in the input capacitance that crosses the TIME defined fixed threshold. Figure 26. Out-Window (Adaptive) Threshold Mode The AD7151 logic output (active high) indicates either a positive or ADAPTIVE THRESHOLD a negative change in the input capacitance, in both adaptive and In an adaptive mode, the thresholds are dynamically adjusted, fixed threshold modes (see Figure 23 and Figure 24). ensuring indication of fast changes (for example an object POSITIVE CHANGE moving close to a capacitive proximity sensor) and eliminating POSITIVE THRESHOLD slow changes in the input (sensor) capacitance, usually caused INPUT by environment changes such as humidity or temperature or CAPACITANCE changes in the sensor dielectric material over time (see Figure 27). OUTPUT ACTIVE FAST CHANGE SLOW CHANGE OUTPUT INPUT CAPACITANCE TIME THRESHOLD Figure 23. Positive Threshold Mode Indicates Positive Change in Input Capacitance OUTPUT ACTIVE OUTPUT NEGATIVE CHANGE TIME INPUT CAPACITANCE Figure 27. Adaptive Threshold NEGATIVE Indicates Fast Changes and Eliminates Slow Changes in Input Capacitance THRESHOLD DATA AVERAGE OUTPUT ACTIVE The adaptive threshold algorithm is based on an average calculated from previous CDC output data. The response of the average to an OUTPUT input capacitance step change (more exactly, response to the change TIME in the CDC output data) is an exponential settling curve, which can Figure 24. Negative Threshold Mode be characterized by the following equation: Indicates Negative Change in Input Capacitance N /TimeConst Average(N )= Average(0)+Change(1−e ) Additionally, for the adaptive mode only, the comparator can work as window comparator, indicating input either inside or where: outside a selected sensitivity band (see Figure 25 and Figure 26). Average(N) is the value of average N complete CDC conversion POSITIVE INPUT INSIDE THRESHOLD WINDOW cycles after a step change on the input. THRESHOLD Average(0) is the value before the step change. INPUT CAPACITANCE TimeConst can be selected in the range between 2 and 65,536, in NEGATIVE THRESHOLD steps of power of 2, by programming the ThrSettling bits in the OUTPUT ACTIVE setup register. OUTPUT See Figure 28 and the Register Descriptions section. INPUT CAPACITANCE TIME (CDC DATA) CHANGE Figure 25. In-Window (Adaptive) Threshold Mode DATA AVERAGE RESPONSE TIME Figure 28. Data Average Response to Data Step Change Rev. 0 | Page 11 of 28 07086-014 07086-013 07086-015 07086-018 07086-017 07086-016 AD7151 The timeout can be set independently for approaching (for change SENSITIVITY in data toward the threshold) and for receding (for change in data In adaptive threshold mode, the output comparator threshold is away from the threshold). See Figure 32, Figure 33, and the set as a defined distance (sensitivity) above the data average, Register Descriptions section. below the data average, or both, depending on the selected threshold mode of operation (see Figure 29). The sensitivity DATA AVERAGE LARGE CHANGE IN DATA value is programmable in the range 0 to 255 LSBs of the 12-bit + SENSITIVITY CDC converter (see the Register Descriptions section). DATA AVERAGE DATA AVERAGE DATA – SENSITIVITY POSITIVE THRESHOLD SENSITIVITY DATA AVERAGE TIME SENSITIVITY TIMEOUT NEGATIVE THRESHOLD Figure 31. Threshold Timeout After a Large Change in CDC Data OUTPUT ACTIVE TIMEOUT APPROACHING TIME INPUT CAPACITANCE Figure 29. Threshold Sensitivity THRESHOLD HYSTERESIS DATA AVERAGE In adaptive threshold mode, the comparator features hysteresis. The hysteresis is fixed to one-fourth of the threshold sensitivity OUTPUT ACTIVE and can be programmed on or off. The comparator does not OUTPUT have hysteresis in the fixed threshold mode. TIME DATA Figure 32. Approaching Timeout in Negative Threshold Mode Shortens False Output Trigger POSITIVE THRESHOLD HYSTERSIS TIMEOUT RECEDING DATA AVERAGE LARGE CHANGE OUTPUT ACTIVE OUTPUT TIME INPUT CAPACITANCE Figure 30. Threshold Hysteresis THRESHOLD OUTPUT ACTIVE TIMEOUT OUTPUT In the case of a large, long change in the capacitive input, when TIME the data average adapting to a new condition may take too long, a timeout can be set. Figure 33. Positive Timeout in Negative Threshold Mode Shortens Period of Missing Output Trigger The timeout becomes active (counting) when the CDC data goes outside the band of data average ± sensitivity. When the timeout elapses (a defined number of CDC conversions is counted), the data average (and thus the threshold) is forced to follow the new CDC data value immediately (see Figure 31). Rev. 0 | Page 12 of 28 07086-020 07086-019 07086-021 07086-023 07086-022 AD7151 AUTOCAPDAC ADJUSTMENT POWER SUPPLY MONITOR In adaptive threshold mode, the part can dynamically adjust the When the AD7151 VDD power supply voltage drops below a CAPDAC to keep the CDC in an optimal operating capacitive defined level needed for correct CDC operation, the on-chip range. When the AutoDAC function is enabled, the CAPDAC power supply monitor stops the adaptive threshold logic and value is automatically incremented when the data average holds it in reset. After the V reaches the required level, the DD exceeds three-fourths of the CDC full range, and the CAPDAC threshold logic is released, and the data average is reset to the value is decremented when the data average goes below one- value of the first conversion finished at the correct power supply voltage. fourth of the CDC full range. The AutoDAC increment or decrement step depends on the selected CDC capacitive input This feature prevents the adaptive threshold from being set range. See the Setup Register section. incorrectly after a very slow rise of the VDD voltage or from being corrupted by accidental drops in the VDD voltage. POWER-DOWN TIMER In power sensitive applications, the AD7151 can be set to The other AD7151 functions continue working below the power supply monitor threshold, down to approximately automatically enter power-down mode after a programmed 1.0V..1.8V, the exact level depending on the manufacturing period of time in which the output has not been activated. The process variation. In the region of the low V voltage, the part AD7151 can be then returned to a normal operational mode DD either via the serial interface or by the power supply off/on is still accessible via the serial interface and continues conversion. sequence. However, the conversion results may be incorrect and, therefore, the data should not be considered valid if the part operates below the power supply monitor threshold. The status of the power supply monitor can be determined by reading the PwrDown bit in the AD7151 status register. Rev. 0 | Page 13 of 28 AD7151 REGISTER DESCRIPTIONS Table 5. Register Summary Pointer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register (Dec) (Hex) R/W Default Value PwrDown – – DacStep OUT – – RDY Status 0 0x00 R 0 1 0 1 0 0 1 1 Data High 1 0x01 R 0x00 Data Low 2 0x02 R 0x00 – 3 0x03 R 0x00 – 4 0x04 R 0x00 Average High 5 0x05 R 0x00 Average Low 6 0x06 R 0x00 – 7 0x07 R 0x00 – 8 0x08 R 0x00 Sensitivity (in adaptive threshold mode)/Threshold High Byte (in fixed threshold mode) Sensitivity 9 0x09 R/W Threshold High 0x08 Timeout Timeout (in adaptive threshold mode)/Threshold Low Byte (in fixed threshold mode) 10 0x0A R/W Threshold Low 0x86 RngH RngL – ThrSettling (4-bit value) Hyst Setup 11 0x0B R/W 0 0 0 0 0x0B – 12 0x0C R/W 0x00 – 13 0x0D R/W 0x00 – 14 0x0E R/W 0x00 ThrFixed ThrMD1 ThrMD0 EnConv – MD2 MD1 MD0 Configuration 15 0x0F R/W 0 0 0 1 0 0 0 1 – – Power-Down Timeout (6-bit value) Power-Down Timer 16 0x10 R/W 0 0 0x00 DacEn DacAuto DacValue (6-bit value) CAPDAC 17 0x11 R/W 1 1 0x00 – 18 0x12 R/W 0x00 Serial Number 3 19 0x13 R Serial Number – Byte 3 (MSB) Serial Number 2 20 0x14 R Serial Number – Byte 2 Serial Number 1 21 0x15 R Serial Number – Byte 1 Serial Number 0 22 0x16 R Serial Number – Byte 0 (LSB) Chip ID 23 0x17 R Chip Identification Code Rev. 0 | Page 14 of 28 AD7151 STATUS REGISTER Address Pointer 0x00 8 Bits, Read-Only, Default Value 0x53 Before Conversion, 0x52 After Conversion The status register indicates the status of the part. The register can be read via the 2-wire serial interface to query the status of the outputs, check the CDC finished conversion, and check whether the CAPDAC has been changed by the autoCAPDAC function. Table 6. Status Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic PwrDown – – DacStep OUT – – RDY Default 0 1 0 1 0 0 1 1 Table 7. Status Register Bit Descriptions Bit Mnemonic Description 7 PwrDown PwrDown = 1 indicates that the part is in a power-down mode or that the part VDD is below the power supply monitor threshold voltage. 6 – Bit not used, always reads 1. 5 – Bit not used, always reads 0. 4 DacStep DacStep = 0 indicates that the CAPDAC value was changed during the last conversion as part of the AutoDac function. The bit value is updated after each finished CDC conversion. 3 OUT OUT = 1 indicates that the data (CIN capacitance) crossed the threshold, according to the selected comparator mode of operation. The bit value is updated after each finished CDC conversion. 2 – Bit not used, always reads 0. 1 – Bit not used, always reads 1. 0 RDY RDY = 0 indicates a finished CDC conversion. The bit is reset back to 1 when the data register is read via the serial interface or after the part reset or power-up. Rev. 0 | Page 15 of 28 AD7151 DATA REGISTER AVERAGE REGISTER Address Pointer 0x01, 0x02 Address Pointer 0x05, 0x06 16 Bits, Read-Only, Default Value 0x0000 16 Bits, Read-Only, Default Value 0x0000 Data from the last complete capacitance-to-digital conversion This register shows the average calculated from the previous reflects the capacitance on the input. Only the 12 MSBs (most CDC data. The 12-bit CDC result corresponds to the 12 MSBs significant bits) of the data register are used for the CDC result. of the average register. The 4 LSBs (least significant bits) are always 0, as shown in The settling time of the average can be set by programming the Figure 34. ThrSettling bits in the setup register. The average register is MSB DATA HIGH DATA LOW LSB overwritten directly with the CDC output data, that is, the BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 history is forgotten if the timeout is enabled and elapses. 12-BIT CDC RESULT 0 FIXED THRESHOLD REGISTER Figure 34. CDC Data Register Address Pointer 0x09, 0x0A The nominal AD7151 CDC transfer function (an ideal transfer 16 Bits, Read/Write, Factory Preset 0x0886 function excluding offset and/or gain error) maps the input A constant threshold for the output comparator in the fixed capacitance between zero scale and full scale to output data threshold mode can be set using this register. The 12-bit CDC codes between 0x3000 and 0xCFF0 only (see Table 8). result corresponds to the 12 MSBs of the threshold register. The fixed threshold register shares the address pointer and location Table 8. AD7151 Capacitance-to-Data Mapping on-chip with the sensitivity and timeout registers. The fixed Data Input Capacitance threshold register is not accessible in the adaptive threshold 0x0000 Not valid, underrange mode. 0x3000 Zero-scale (0 pF) 0x8000 Mid-scale (+1 pF) SENSITIVITY REGISTER 0xCFF0 Full-scale (+2 pF) Address Pointer 0x09 0xFFF0 Not valid, overrange 8 Bits, Read/Write, Factory Preset 0x08 The input capacitance can be calculated from the output data The sensitivity register sets the distance of the positive using the following equation: threshold above the data average, and the distance of the negative threshold below the data average, in the adaptive Data−12288 C(pF)= ×Input _Range threshold mode. 40944 DATA where Input_Range = 4 pF, 2 pF, 1 pF, or 0.5 pF. POSITIVE The following is the same equation written with hexadecimal THRESHOLD SENSITIVITY numbers: DATA AVERAGE SENSITIVITY Data− 0x3000 NEGATIVE C(pF)= ×Input_Range THRESHOLD 0x9FF0 OUTPUT ACTIVE The data register is updated after a finished conversion, with one exception: when the serial interface read operation from the TIME data register is in progress, the data register is not updated and Figure 35. Threshold Sensitivity the new capacitance conversion result is lost. The sensitivity is an 8-bit value and is mapped to the lower eight The stop condition on the serial interface is considered to be the bits of the 12-bit CDC data, that is, it corresponds to the 16-bit end of the read operation. Therefore, to prevent incorrect data data register as shown in Figure 36. reading through the serial interface, the two bytes of the data SENSITIVITY register should be read sequentially using the register address BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 pointer auto-increment feature of the serial interface. DATA HIGH DATA LOW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 12-BIT CDC RESULT Figure 36. Relation Between Sensitivity Register and CDC Data Register Rev. 0 | Page 16 of 28 07086-044 07086-024 07086-025 AD7151 When either the approaching or receding timeout elapses (that TIMEOUT REGISTER is, after the defined number of CDC conversions is counted), Address Pointer 0x0A the data average (and thus the thresholds) is forced to follow the 8 Bits, Read/Write, Factory Preset 0x86 new CDC data value immediately. Table 9. Timeout Register Bit Map When the timeout register equals 0, timeouts are disabled. Bit Bits [7:4] Bits [3:0] Mnemonic TimeOutApr TimeOutRec LARGE CHANGE IN DATA TOWARDS THRESHOLD DATA AVERAGE Default 0x08 0x06 + SENSITIVITY DATA AVERAGE The register sets timeouts for the adaptive threshold mode. THRESHOLD The approaching timeout starts when the CDC data crosses the data average ± sensitivity band toward the threshold, according to the selected positive, negative, or window threshold mode. The TIME approaching timeout elapses after the number of conversion cycles TIMEOUT APPROACHING TimeOutApr equals 2 , where TimeOutApr is the value of the four most Figure 37. Threshold Timeout Approaching significant bits of the timeout register. After a Large Change in CDC Data Toward Threshold The receding timeout starts when the CDC data crosses the TIMEOUT RECEDING data average ± sensitivity band away from the threshold, according to the selected positive or negative threshold mode. The receding timeout is not used in the window threshold mode. The receding timeout elapses after the number of DATA AVERAGE TimeOutRec conversion cycles equals 2 , where TimeOutRec is the + SENSITIVITY DATA AVERAGE value of the four least significant bits of the timeout register. TIME THRESHOLD LARGE CHANGE IN DATA AWAY FROM THE THRESHOLD Figure 38. Threshold Timeout Receding After a Large Change in CDC Data Away from Threshold Rev. 0 | Page 17 of 28 07086-026 07086-027 AD7151 SETUP REGISTER Address Pointer 0x0B 8 Bits, Read/Write, Factory Preset 0x0B Table 10. Setup Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic RngH RngL – Hyst ThrSettling (4-Bit Value) Default 0 0 0 0 0x0B Table 11. Setup Register Bit Descriptions Bit Mnemonic Description 7 RngH Range bits set the CDC input range and determine the step for the AutoDAC function. 6 RngL RngH RngL Capacitive Input Range (pF) AutoDAC Step (CAPDAC LSB) 0 0 2 4 0 1 0.5 1 1 0 1 2 1 1 4 8 5 – This bit should be 0 for the specified operation. 4 Hyst Hyst = 1 disables hysteresis in adaptive threshold mode. This bit has no effect in fixed threshold mode; hysteresis is always disabled in the fixed threshold mode. 3 ThrSettling Determines the settling time constant of the data average and thus the settling time of the adaptive 2 thresholds. 1 The response of the average to an input capacitance step change (that is, response to the change in the CDC 0 output data) is an exponential settling curve characterized by the following equation: N /TimeConst Average (N )= Average (0)+Change(1−e ) where: Average(N) is the value of average N complete CDC conversion cycles after a step change on the input Average(0) is the value before the step change TimeConst can be selected in the range between 2 and 65,536 conversion cycle multiples, in steps of power of 2, by programming the ThrSettling bits. (ThrSettling+ 1) TimeConst = 2 See Figure 39. INPUT CAPACITANCE (CDC DATA) CHANGE DATA AVERAGE RESPONSE TIME Figure 39. Data Average Response to Data Step Change Rev. 0 | Page 18 of 28 07086-028 AD7151 CONFIGURATION REGISTER Address Pointer 0x0F 8 Bits, Read/Write, Factory Preset 0x19 Table 12. Configuration Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic ThrFixed ThrMD1 ThrMD0 EnConv – MD2 MD1 MD0 Default 0 0 0 1 0 0 0 1 Table 13.Configuration Register Bit Descriptions Bit Mnemonic Description 7 ThrFixed ThrFixed = 1 sets the fixed threshold mode. The output reflects comparison of data and a fixed (constant) value of the threshold register. ThrFixed = 0 sets the adaptive threshold mode. The output reflects comparison of data to the adaptive threshold. The adaptive threshold is set dynamically, based on the history of the previous data. 6 ThrMD1 These bits set the output comparator mode. 5 ThrMD0 Output Active When ThrMD1 ThrMD0 Threshold Mode Adaptive Threshold Mode Fixed Threshold Mode 0 0 Negative data < average – sensitivity Data < Threshold 0 1 Positive data > average + sensitivity Data > Threshold 1 0 In-Window data > average – sensitivity - AND data < average + sensitivity 1 1 Out-Window data < average – sensitivity - OR data > average + sensitivity 4 EnConv Enables conversion. This bit must be 1 for proper operation. 3 – This bit must be 0 for proper operation. 2 MD2 Converter mode of operation setup. 1 MD1 MD2 MD1 MD0 Mode Description 0 MD0 0 0 0 Idle Part is fully powered up but performing no conversion. 0 0 1 Continuous Part is repeatedly performing conversions, provided the Conversion EnConv bit is set. 0 1 0 Single Conversion Part performs a single conversion, provided the EnConv bit is set. After finishing the conversion(s), the part goes to the idle mode. 0 1 1 Power-Down Powers down the on-chip circuits, except the digital interface. 1 X X Reserved Do not use these modes. Rev. 0 | Page 19 of 28 AD7151 POWER-DOWN TIMER REGISTER Address Pointer 0x10 8 Bits, Read/Write, Factory Preset 0x00 Table 14. Power-Down Timer Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic – – Power-Down Timeout (6-Bit Value) Default 0 0 0x00 Table 15. Power-Down Timer Register Bit Descriptions Bit Mnemonic Description [7:6] - These bits must be 0 for proper operation [5:0] Power-Down Defines the period duration of the power-down timeout. Timeout If the output comparator output has not been activated during the programmed period, the part enters power- down mode automatically. The part can be then returned to a normal operational mode either via the serial interface or by the power supply off/on sequence. The period is programmable in steps of four hours. For example, setting the value to 0x06 sets the duration to 24 hours. The maximum value of 0x3F corresponds to approximately 10.5 days. The value of 0x00 disables the power-down timeout, and the part does not enter power-down mode automatically. CAPDAC REGISTER Address Pointer 0x11 8 Bits, Read/Write, Factory Preset 0x00 Table 16. CAPDAC Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic DacEn DacAuto DacValue (6-Bit Value) Default 1 1 0x00 Table 17. CAPDAC Register Bit Descriptions Bit Mnemonic Description 7 DacEn DacEn = 1 enables capacitive DAC. 6 DacAuto DacAuto = 1 enables the AutoDAC function in the adaptive threshold mode. When the AutoDAC function is enabled, the part dynamically adjusts the CAPDAC to keep the CDC in an optimal operating capacitive range. The CAPDAC value is automatically incremented when the data average exceeds ¾ of the CDC full range, and the CAPDAC value is decremented when the data average goes below ¼ of the CDC full range. The AutoDAC increment or decrement step depends on the selected CDC capacitive input range. Bit has no effect in fixed threshold mode; the AutoDAC function is always disabled in the fixed threshold mode. [5:0] DacValue CAPDAC value, Code 0x00 ≈ 0 pF, Code 0x3F ≈ CAPDAC full range. SERIAL NUMBER REGISTER CHIP ID REGISTER Address Pointer 0x13, 0x14, 0x15, 0x16 Address Pointer 0x17 32 Bits, Read Only, 0xXXXX 8 Bits, Read Only, 0xXX This register holds a serial number, unique for each individual part. This register holds the chip identification code, used in factory manufacturing and testing. Rev. 0 | Page 20 of 28 AD7151 SERIAL INTERFACE 2 The AD7151 supports an I C-compatible 2-wire serial interface. In continuous conversion mode, the address pointers’ auto- The two wires on the serial bus (interface) are called SCL (clock) incrementer should be used for reading a conversion result. and SDA (data). These two wires carry all addressing, control, This means that the two data bytes should be read using one and data information one bit at a time over the bus to all multibyte read transaction rather than two separate single-byte connected peripheral devices. The SDA wire carries the data, transactions. The single-byte data read transaction may result in while the SCL wire synchronizes the sender and receiver during the data bytes from two different results being mixed. the data transfer. The devices on the bus are classified as either The user can also access any unique register (address) on a one- master or slave devices. A device that initiates a data transfer to-one basis without having to update all the registers. The message is called a master, while a device that responds to this address pointer register contents cannot be read. message is called a slave. If an incorrect address pointer location is accessed or if the user To control the AD7151 device on the bus, the following allows the auto-incrementer to exceed the required register protocol must be followed. First, the master initiates a data address, the following applies: transfer by establishing a start condition, defined by a high-to- • In read mode, the AD7151 continues to output various low transition on SDA while SCL remains high. This indicates internal register contents until the master device issues a that the start byte follows. This 8-bit start byte is made up of a no acknowledge, start, or stop condition. The address 7-bit address plus an R/W bit indicator. pointers’ auto-incrementer contents are reset to point to All peripherals connected to the bus respond to the start the status register at the 0x00 address when a stop condition and shift in the next eight bits (7-bit address + R/W condition is received at the end of a read operation. This bit). The bits arrive MSB first. The peripheral that recognizes allows the status register to be read (polled) continually the transmitted address responds by pulling the data line low without having to constantly write to the address pointer. during the ninth clock pulse. This is known as the acknowledge • In write mode, the data for the invalid address is not bit. All other devices withdraw from the bus at this point and loaded into the AD7151 registers, but an acknowledge is maintain an idle condition. An exception to this is the general issued by the AD7151. call address, which is described in the General Call section. In the idle condition, the device monitors the SDA and SCL lines WRITE OPERATION waiting for the start condition and the correct address byte. When a write is selected, the byte following the start byte is The R/W bit determines the direction of the data transfer. A always the register address pointer (subaddress) byte, which Logic 0 LSB in the start byte means that the master writes points to one of the internal registers on the AD7151. The information to the addressed peripheral. In this case, the address pointer byte is automatically loaded into the address AD7151 becomes a slave receiver. A Logic 1 LSB in the start pointer register and acknowledged by the AD7151. After the byte means that the master reads information from the address pointer byte acknowledge, a stop condition, a repeated addressed peripheral. In this case, the AD7151 becomes a slave start condition, or another data byte can follow from the master. transmitter. In all instances, the AD7151 acts as a standard slave A stop condition is defined by a low-to-high transition on SDA device on the serial bus. while SCL remains high. If a stop condition is encountered by the AD7151, it returns to its idle condition and the address The start byte address for the AD7151 is 0x90 for a write and pointer is reset to 0x00. 0x91 for a read. If a data byte is transmitted after the register address pointer READ OPERATION byte, the AD7151 loads this byte into the register that is When a read is selected in the start byte, the register that is currently addressed by the address pointer register and sends an currently addressed by the address pointer is transmitted to the acknowledge, and the address pointer auto-incrementer auto- SDA line by the AD7151. This is then clocked out by the master matically increments the address pointer register to the next device, and the AD7151 awaits an acknowledge from the internal register address. Thus, subsequent transmitted data master. bytes are loaded into sequentially incremented addresses. If an acknowledge is received from the master, the address auto- incrementer automatically increments the address pointer register and outputs the next addressed register content to the SDA line for transmission to the master. If no acknowledge is received, the AD7151 returns to the idle state and the address pointer is not incremented. The address pointers’ auto-incrementer allows block data to be written to or read from the starting address and subsequent incremental addresses. Rev. 0 | Page 21 of 28 AD7151 If a repeated start condition is encountered after the address GENERAL CALL pointer byte, all peripherals connected to the bus respond When a master issues a slave address consisting of seven 0s with exactly as outlined previously for a start condition; that is, a the eighth bit (R/W bit) set to 0, this is known as the general call repeated start condition is treated the same as a start condition. address. The general call address is for addressing every device When a master device issues a stop condition, it relinquishes connected to the serial bus. The AD7151 acknowledges this control of the bus, allowing another master device to take address and reads in the following data byte. control of the bus. Therefore, a master wanting to retain control If the second byte is 0x06, the AD7151 is reset, completely of the bus issues successive start conditions known as repeated uploading all default values. The AD7151 does not respond to start conditions. the serial bus commands (do not acknowledge) during the AD7151 RESET default values upload for approximately 2 ms. To reset the AD7151 without having to reset the entire serial bus, The AD7151 does not acknowledge any other general call an explicit reset command is provided. This uses a particular commands. address pointer word as a command word to reset the part and upload all default settings. The AD7151 does not respond to the serial bus commands (do not acknowledge) during the default values upload for approximately 2 ms. The reset command address word is 0xBF. SDATA SCLOCK S 1–7 8 9 1–7 8 9 1–7 8 9 P START ADDR ACK SUBADDRESS ACK DATA ACK STOP R/W Figure 40. Bus Data Transfer WRITE S SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S) A(S) DATA P SEQUENCE LSB = 1 LSB = 0 READ S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA A(M) A(M) DATA P SEQUENCE S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) = NO ACKNOWLEDGE BY SLAVE P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER A(M) = NO ACKNOWLEDGE BY MASTER Figure 41. Write and Read Sequences Rev. 0 | Page 22 of 28 07086-029 07086-030 AD7151 HARDWARE DESIGN CONSIDERATIONS OVERVIEW PARASITIC RESISTANCE TO GROUND The AD7151 is an interface to capacitive sensors. On the input side, the sensor (C ) can be connected directly X between the AD7151 EXC and CIN pins. The way it is R GND1 DATA CIN CDC connected and the electrical parameters of the sensor connection, such as parasitic resistance or capacitance, can affect the system performance. Therefore, any circuit with C X additional components in the capacitive front end, such as overvoltage protection, has to be carefully designed considering R GND2 EXC the AD7151 specified limits and information provided in this section. On the output side, the AD7151 can work as a standalone Figure 43. Parasitic Resistance to Ground device, using the power-up default register settings and flagging The AD7151 CDC result is affected by a leakage current from the result on digital outputs. Alternatively, the AD7151 can be C to ground; therefore, C should be isolated from the ground. X X interfaced to a microcontroller via the 2-wire serial interface, The equivalent resistance between C and ground should be X offering flexibility by overwriting the AD7151 register values maximized (see Figure 43). from the host with a user-specific setup. See Figure 8, Figure 9, Figure 10, and Figure 11. PARASITIC CAPACITANCE TO GROUND PARASITIC PARALLEL RESISTANCE C GND1 DATA CIN CDC DATA CIN CDC C X C R X P C GND2 EXC EXC Figure 42. Parasitic Capacitance to Ground Figure 44. Parasitic Parallel Resistance The CDC architecture used in the AD7151 measures the The AD7151 CDC measures the charge transfer between the capacitance CX connected between the EXC pin and the CIN EXC and CIN pins. Any resistance connected in parallel to the pin. In theory, any capacitance CGND to ground should not affect measured capacitance CX (see Figure 44), such as the parasitic the CDC result (see Figure 42). resistance of the sensor, also transfers charge. Therefore, the parallel resistor is seen as an additional capacitance in the The practical implementation of the circuitry in the chip output data. The equivalent parallel capacitance (or error implies certain limits, and the result is gradually affected by caused by the parallel resistance) can be approximately capacitance to ground (see Table 1 for information about the calculated as allowed capacitance to GND for CIN and information about excitation). 1 C = P See Figure 4, Figure 5, Figure 6, and Figure 7. R × f × 4 P EXC where R is the parallel resistance and f is the excitation P EXC frequency. See Figure 13. Rev. 0 | Page 23 of 28 07086-031 07086-033 07086-032 AD7151 PARASITIC SERIAL RESISTANCE INPUT EMC PROTECTION 39kΩ 82kΩ CIN C X 68pF 22pF CDC R S1 DATA CIN CDC 10kΩ EXC 47pF GND C X Figure 47. AD7151 CIN EMC Protection R S2 EXC Some applications may require an additional input filter for improving electromagnetic compatibility (EMC). Any input Figure 45. Parasitic Serial Resistance filter must be carefully designed, considering the balance between the system capacitance performance and system electromagnetic The AD7151 CDC result is affected by a resistance in series immunity. with the measured capacitance. The total serial resistance (R + S1 R in Figure 45) should be on the order of hundreds of Ω. S2 Figure 47 shows one of the possible input circuit configurations significantly improving the system immunity against high See Figure 12. frequency noise and slightly affecting the AD7151 performance INPUT OVERVOLTAGE PROTECTION in terms of additional gain and offset error. CDC POWER SUPPLY DECOUPLING AND FILTERING R S1 1kΩ VDD CIN 0.1µF 10µF C X VDD 1kΩ 1kΩ R S2 SDA EXC SCL CDC GND GND Figure 46. AD7151 CIN Overvoltage Protection Figure 48. AD7151 VDD Decoupling and Filtering The AD7151 capacitive input has an internal ESD protection. However, some applications may require an additional The AD7151 has good dc and low frequency power supply rejection but may be sensitive to higher frequency ripple and overvoltage protection, depending on the application-specific noise, specifically around the excitation frequency and its requirements. Any additional circuit in the capacitive front end harmonics. Figure 48 shows a possible circuit configuration for must be carefully designed, especially with respect to the limits improving the system immunity against ripple and noise recommended for maximum capacitance to ground, maximum coupled to the AD7151 via the power supply. serial resistance, maximum leakage, and so on. If the serial interface is connected to the other circuits in the system, it is better to connect the pull-up resistors on the other side of the VDD filter than connect to the AD7151. If the AD7151 is used in standalone mode and the serial interface is not used, it is better to connect the pull-up resistors directly to the AD7151 VDD. Rev. 0 | Page 24 of 28 07086-035 07086-034 07086-036 07086-058 AD7151 APPLICATION EXAMPLES 0.1µF 10kΩ 10kΩ VDD AD7151 CIN SDA SCL 3V C SENS EXC BATTERY OUT 1kΩ LED GND Figure 49. AD7151 Standalone Operation Application Diagram 3.3V 0.1µF 1kΩ 1kΩ VDD HOST AD7151 MICROCONTROLLER CIN SDA SDA C SENS SCL SCL EXC OUT IRQ GND Figure 50. AD7151 Interfaced to a Host Microcontroller 1kΩ 3.3V V SUPPLY ADP1720-3.3 0.1µF 10µF 1µF 1µF VDD 39kΩ 82kΩ CIN R1 1kΩ 1kΩ AD7151 68pF 22pF SDA C SENS 10kΩ EXC OUT SCL 47pF OUT Q1 GND Figure 51. AD7151 Standalone Operation with EMC Protection and Optional Serial Interface Rev. 0 | Page 25 of 28 07086-037 07086-038 07086-061 AD7151 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.60 0.33 SEATING 0.23 0° 0.05 PLANE 0.40 0.17 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 52. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding 1 AD7151BRMZ −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 C5M 1 AD7151BRMZ-REEL −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 C5M 1 Z = RoHS Compliant Part. Rev. 0 | Page 26 of 28 AD7151 NOTES Rev. 0 | Page 27 of 28 AD7151 NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07086-0-11/07(0) Rev. 0 | Page 28 of 28