ANALOG DEVICES AD7147A

CapTouch Programmable Controller for Single-Electrode Capacitance Sensors AD7147A FEATURES FUNCTIONAL BLOCK DIAGRAM AC V GND BIAS SHIELD CC Programmable capacitance-to-digital converter (CDC) E4 D2 E2 E3 Femtofarad (fF) resolution 13 capacitance sensor inputs POWER-ON CIN0 D3 RESET LOGIC 9 ms update rate, all 13 sensor inputs A3 CIN1 No external RC components required B3 CIN2 EXCITATION Automatic conversion sequencer SOURCE CIN3 A4 On-chip automatic calibration logic C3 CIN4 Automatic compensation for environmental changes CIN5 A5 CALIBRATION AD7147A Automatic adaptive threshold and sensitivity levels RAM CIN6 B4 Register map is compatible with the AD714x B5 CIN7 On-chip RAM to store calibration data CIN8 C4 16-BIT CALIBRATION Serial peripheral interface (SPI) (AD7147A) Σ-Δ ENGINE CIN9 C5 CDC 2 I C-compatible serial interface (AD7147A-1) D4 CIN10 Separate V level for serial interface DRIVE CIN11 D5 CONTROL Interrupt output and general-purpose input/output (GPIO) AND DATA E5 REGISTERS CIN12 25-ball, 2.3 mm × 2.1 mm WLCSP 2.6 V to 3.6 V supply voltage B2 TP Low operating current Full power mode: 1 mA INTERRUPT SERIAL INTERFACE V C2 AND GPIO A2 GPIO DRIVE AND CONTROL LOGIC LOGIC Low power mode: 28.96 μA APPLICATIONS E1 D1 C1 B1 A1 SDO SDI SCLK CS INT Cell phones (SDA) (ADD0) (ADD1) NOTES Personal music and multimedia players 1. PIN NAMES IN PARENTHESES ARE FOR THE AD7147A-1. Smart handheld devices Figure 1. Television, A/V, and remote controls Gaming consoles Digital still cameras The AD7147A is designed for single electrode capacitance sensors (grounded sensors). There is an active shield output to GENERAL DESCRIPTION minimize noise pickup in the sensor. The AD7147A CapTouch™ controller is designed for use with The AD7147A has on-chip calibration logic to compensate for capacitance sensors implementing functions such as buttons, changes in the ambient environment. The calibration sequence scroll bars, and wheels. The sensors need only one PCB layer, is performed automatically and at continuous intervals as long enabling ultrathin applications. as the sensors are not touched. This ensures that there are no The AD7147A is an integrated CDC with on-chip environmen- false or nonregistering touches on the external sensors due to a tal calibration. The CDC has 13 inputs channeled through a changing environment. switch matrix to a 16-bit, 250 kHz sigma-delta (Σ-Δ) converter. The AD7147A has an SPI-compatible serial interface, and the The CDC is capable of sensing changes in the capacitance of the 2 AD7147A-1 has an I C®-compatible serial interface. Both parts external sensors and uses this information to register a sensor have an interrupt output, as well as a GPIO. There is a VDRIVE pin activation. By programming the registers, the user has full control to set the voltage level for the serial interface independent of VCC. over the CDC setup. The AD7147A is available in a 25-ball, 2.3 mm × 2.1 mm High resolution sensors require minor software to run on the WLCSP and operates from a 2.6 V to 3.6 V supply. The operating host processor and may require two PCB layers. current consumption in low power mode is typically 28.96 μA for 13 sensors. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. SWITCH MATRIX 06663-001 AD7147A TABLE OF CONTENTS Features .............................................................................................. 1 Capacitance Sensor Behavior Without Calibration ............... 23 Applications ....................................................................................... 1 Threshold Equations .................................................................. 23 General Description ......................................................................... 1 Capacitance Sensor Behavior with Calibration ...................... 24 Functional Block Diagram .............................................................. 1 Slow FIFO .................................................................................... 24 Revision History ............................................................................... 2 SLOW_FILTER_UPDATE_LVL .............................................. 24 Specif ica t ions ..................................................................................... 3 Adaptive Threshold and Sensitivity ............................................. 25 Average Current Specifications .................................................. 4 Interrupt Output ............................................................................. 27 SPI Timing Specifications (AD7147A) ...................................... 5 CDC Conversion-Complete Interrupt .................................... 27 2 I C Timing Specifications (AD7147A-1) .................................. 6 Sensor-Touch Interrupt ............................................................. 27 Absolute Maximum Ratings ............................................................ 7 GPIO INT Output Control ....................................................... 29 ESD Caution .................................................................................. 7 Outputs ............................................................................................ 31 Pin Configurations and Function Descriptions ........................... 8 ACSHIELD Output .......................................................................... 31 Typical Performance Characteristics ............................................. 9 General-Purpose Input/Output (GPIO) ................................. 31 Theory of Operation ...................................................................... 11 Using the GPIO to Turn On/Off an LED ................................ 31 Capacitance Sensing Theory ..................................................... 11 Serial Interfaces ............................................................................... 32 BIAS Pin ....................................................................................... 12 SPI Interface ................................................................................ 32 2 Operating Modes ........................................................................ 12 I C-Compatible Interface .......................................................... 34 Capacitance-to-Digital Converter ................................................ 14 VDRIVE Input ................................................................................. 36 Oversampling the CDC Output ............................................... 14 PCB Design Guidelines ................................................................. 37 Capacitance Sensor Offset Control .......................................... 14 Capacitive Sensor Board Mechanical Specifications ............. 37 Conversion Sequencer ............................................................... 14 WLCSP Package ......................................................................... 37 CDC Conversion Sequence Time ............................................ 16 Power-Up Sequence ....................................................................... 38 CDC Conversion Results ........................................................... 16 Typical Application Circuits ......................................................... 39 Capacitance Sensor Input Configuration .................................... 17 Register Map ................................................................................... 40 CINx Input Multiplexer Setup .................................................. 17 Detailed Register Descriptions ..................................................... 41 Single-Ended Connections to the CDC .................................. 17 Bank 1 Registers ......................................................................... 41 Noncontact Proximity Detection ................................................. 18 Bank 2 Registers ......................................................................... 51 Recalibration ............................................................................... 18 Bank 3 Registers ......................................................................... 56 Proximity Sensitivity .................................................................. 18 Outline Dimensions ....................................................................... 68 FF_SKIP_CNT ............................................................................ 21 Ordering Guide .......................................................................... 68 Environmental Calibration ........................................................... 23 3/09—Rev. 0 to Rev. A REVISION HISTORY 12/09—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 68 1/09—Revision 0: Initial Version Changes to Figure 1 .......................................................................... 1 Changes to Figure 5, Figure 6, and Pin Description for B2 ........ 8 Changes to Figure 59 and Figure 60 ............................................. 39 Changes to Ordering Guide .......................................................... 68 Rev. B | Page 2 of 68 AD7147A SPECIFICATIONS o VCC = 2.6 V to 3.6 V, TA = −40 C to +85°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments CAPACITANCE-TO-DIGITAL CONVERTER Update Rate 8.73 9 9.27 ms 12 conversion stages, decimation = 64 17.46 18 18.54 ms 12 conversion stages, decimation = 128 34.9 36 37.1 ms 12 conversion stages, decimation = 256 Resolution 16 Bits CINx Input Range ±8 pF No Missing Codes 16 Bits Guaranteed by design, but not production tested CINx Input Leakage 25 nA Maximum Output Load 20 pF Capacitance load on CINx to ground Total Unadjusted Error ±20 % Output Noise (Peak-to-Peak) 12 Codes Decimation rate = 64 7 Codes Decimation rate = 128 3 Codes Decimation rate = 256 Output Noise (RMS) 1.1 Codes Decimation rate = 64 0.8 Codes Decimation rate = 128 0.5 Codes Decimation rate = 256 C Offset Range 20 pF STRAY CSTRAY Offset Resolution 0.32 pF Low Power Mode Delay Accuracy 4 % Percentage of 200 ms, 400 ms, 600 ms, or 800 ms AC SHIELD Frequency 250 kHz Output Voltage 0 VCC V Oscillating Short-Circuit Source Current 10 mA Short-Circuit Sink Current 10 mA Maximum Output Load 150 pF Capacitance load on ACSHIELD to ground LOGIC INPUTS (SDI, SCLK, CS, SDA, GPIO) Input High Voltage, V 0.7 × V V IH DRIVE Input Low Voltage, VIL 0.4 V Input High Current, IIH −1 μA VIN = VDRIVE Input Low Current, I 1 μA V = GND IL IN Hysteresis 150 mV OPEN-DRAIN OUTPUTS (SCLK, SDA, INT) Output Low Voltage, V 0.4 V I = −1 mA OL SINK Output High Leakage Current, I ±0.1 ±1 μA V = V OH OUT DRIVE LOGIC OUTPUTS (SDO, GPIO) Output Low Voltage, VOL 0.4 V ISINK = 1 mA, VDRIVE = 1.65 V to 3.6 V Output High Voltage, V V − 0.6 V I = 1 mA, V = 1.65 V to 3.6 V OH DRIVE SOURCE DRIVE GPO, SDO Floating State Leakage ±1 μA Pin three-state, leakage measured to GND and VCC Current POWER V 2.6 3.3 3.6 V CC VDRIVE 1.65 3.6 V Serial interface operating voltage ICC 0.8 1 mA In full power mode, VCC + VDRIVE, Register 0x00, Bits[15:14] = 00 1.1 1.3 mA In full power mode, V + V , Register 0x00, Bits[15:14] = 01 CC DRIVE 1.2 1.5 mA In full power mode, VCC + VDRIVE, Register 0x00, Bits[15:14] = 10 1.6 1.8 mA In full power mode, V + V , Register 0x00, Bits[15:14] = 11 CC DRIVE 15.5 24 μA Low power mode, converter idle, V + V , decimation = 256; CC DRIVE Register 0x00, Bits[15:14] = 01 2.3 10 μA Full shutdown, V + V , Register 0x00, Bits[15:14] = 01 CC DRIVE Rev. B | Page 3 of 68 AD7147A AVERAGE CURRENT SPECIFICATIONS 1 Table 2. Typical Average Current in Low Power Mode Current Values of Conversion Stages (μA) Low Power Decimation Mode Delay Rate 1 2 3 4 5 6 7 8 9 10 11 12 200 ms 64 22.27 26.53 30.77 34.98 39.15 43.29 47.40 51.48 55.53 59.55 63.54 67.51 128 27.95 36.37 44.66 52.84 60.89 68.82 76.64 84.34 91.94 99.42 106.80 114.08 256 39.15 55.53 71.44 86.89 101.9 116.48 130.67 144.47 157.90 170.98 183.71 196.11 400 ms 64 18.89 21.04 23.19 25.32 27.45 29.57 31.68 33.78. 35.88 37.96 40.04 42.11 128 21.76 26.03 30.27 34.48 38.66 42.80 46.92 51.00 55.05 59.08 63.07 67.04 256 27.45 35.88 44.18 52.36 60.41 68.35 76.18 83.89 91.49 98.98 106.37 113.65 600 ms 64 17.76 19.20 20.63 22.06 23.49 24.91 26.33 27.75 29.16 30.57 31.98 33.38 128 19.68 22.54 25.39 28.22 31.04 33.85 36.64 39.42 42.18 44.93 47.67 50.39 256 23.49 29.16 34.78 40.34 45.84 51.29 56.69 62.03 67.32 72.56 77.75 82.89 800 ms 64 17.20 18.28 19.35 20.43 21.50 22.57 23.64 24.71 25.78 26.84 27.90 28.96 128 18.63 20.79 22.93 25.07 27.20 29.32 31.43 33.53 35.63 37.72 39.80 41.87 256 21.50 25.78 30.02 34.23 38.41 42.56 46.67 50.76 54.82 58.84 62.84 66.80 1 VCC = 3.3 V, TA = 25°C, load = 50 pF. 1 Table 3. Maximum Average Current in Low Power Mode Current Values of Conversion Stages (μA) Low Power Decimation Mode Delay Rate 1 2 3 4 5 6 7 8 9 10 11 12 200 ms 64 32.62 38.12 43.58 48.99 54.35 59.67 64.95 70.18 75.37 80.52 85.63 90.69 128 39.95 50.78 61.44 71.92 82.23 92.37 102.36 112.18 121.85 131.27 140.74 149.97 256 54.35 75.37 95.72 115.42 134.51 153.02 170.96 188.38 205.28 221.70 237.65 253.15 400 ms 64 28.32 31.10 33.86 36.61 39.35 42.08 44.80 47.50 50.19 52.88 55.55 58.21 128 32.02 37.53 42.99 48.40 53.77 59.09 64.38 69.61 74.81 79.96 85.07 90.14 256 39.35 50.19 60.86 71.35 81.67 91.82 101.82 111.65 121.33 130.86 140.24 149.47 600 ms 64 26.88 28.74 30.59 32.43 34.27 36.11 37.94 39.76 41.58 43.39 45.20 47.00 128 29.36 33.05 36.72 40.37 44.00 47.60 51.19 54.76 58.31 61.84 65.35 68.84 256 34.27 41.58 48.80 55.95 63.01 70.00 76.92 83.76 90.52 97.21 103.83 110.39 800 ms 64 26.16 27.56 28.95 30.33 31.72 33.10 34.48 35.85 37.23 38.60 39.96 41.33 128 28.02 30.80 33.56 36.31 39.05 41.78 44.50 47.21 49.90 52.59 55.26 57.92 256 31.72 37.23 42.69 48.11 53.48 58.80 64.09 69.33 74.53 79.68 84.80 89.87 1 V = 3.6 V, T = −40°C to +85°C, load = 50 pF. CC A Rev. B | Page 4 of 68 AD7147A SPI TIMING SPECIFICATIONS (AD7147A) TA = −40°C to +85°C, sample tested at 25°C to ensure compliance. VDRIVE = 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise noted. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. Table 4. SPI Timing Specifications Parameter Limit Unit Description fSCLK 5 MHz max SCLK frequency t1 5 ns min CS falling edge to first SCLK falling edge t2 20 ns min SCLK high pulse width t 20 ns min SCLK low pulse width 3 t 15 ns min SDI setup time 4 t 15 ns min SDI hold time 5 t6 20 ns max SDO access time after SCLK falling edge t7 16 ns max CS rising edge to SDO high impedance t 15 ns min SCLK rising edge to CS high 8 SPI Timing Diagram CS t 1 t 2 t 8 t 3 11 23 156 12 15 16 SCLK t 4 t 5 MSB LSB SDI t 6 t 7 SDO MSB LSB Figure 2. SPI Detailed Timing Diagram Rev. B | Page 5 of 68 07727-002 AD7147A 2 I C TIMING SPECIFICATIONS (AD7147A-1) TA = −40°C to +85°C, sample tested at 25°C to ensure compliance. VDRIVE = 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise noted. All input signals timed from a voltage level of 1.6 V. 2 1 Table 5. I C Timing Specifications Parameter Limit Unit Description fSCLK 400 kHz max t 0.6 μs min Start condition hold time, t 1 HD; STA t 1.3 μs min Clock low period, t 2 LOW t 0.6 μs min Clock high period, t 3 HIGH t4 100 ns min Data setup time, tSU; DAT t5 300 ns min Data hold time, tHD; DAT t6 0.6 μs min Stop condition setup time, tSU; STO t 0.6 μs min Start condition setup time, t 7 SU; STA t 1.3 μs min Bus-free time between stop and start conditions, t 8 BUF t 300 ns max Clock/data rise time R tF 300 ns max Clock/data fall time 1 Guaranteed by design, not production tested. 2 I C Timing Diagram t t R F t t 1 2 SCLK t 3 t t 1 7 t 6 t 5 t 4 SDA t 8 STOP START START STOP 2 Figure 3. I C Detailed Timing Diagram 200µA I OL TO OUTPUT 1.6V PIN C L 50pF 200µA I OH Figure 4. Load Circuit for Digital Output Timing Specifications Rev. B | Page 6 of 68 07727-004 07727-003 AD7147A ABSOLUTE MAXIMUM RATINGS Table 6. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to +3.6 V CC rating only; functional operation of the device at these or any Analog Input Voltage to GND −0.3 V to V + 0.3 V CC other conditions above those indicated in the operational Digital Input Voltage to GND −0.3 V to V + 0.3 V DRIVE section of this specification is not implied. Exposure to absolute Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V maximum rating conditions for extended periods may affect 1 Input Current to Any Pin Except Supplies 10 mA device reliability. ESD Rating BIAS and AC Pins (HBM Contact 8 kV ESD CAUTION SHIELD and Air Discharge) All Other Pins (HBM Contact) 2 kV Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C WLCSP Power Dissipation 1 W θJA Thermal Impedance 65°C/W IR Reflow Peak Temperature 260°C (± 0.5°C) Lead Temperature (Soldering, 10 sec) 300°C 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. B | Page 7 of 68 AD7147A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BALL A1 BALL A1 INDICATOR INDICATOR 1 2 3 4 5 1 2 3 4 5 INT GPIO CIN1 CIN3 CIN5 INT GPIO CIN1 CIN3 CIN5 A A TP ADD1 TP CS CIN2 CIN6 CIN7 CIN2 CIN6 CIN7 B B SCLK V CIN4 CIN8 CIN9 SCLK V CIN4 CIN8 CIN9 DRIVE DRIVE C C SDI V CIN0 CIN10 CIN11 ADD0 V CIN0 CIN10 CIN11 CC CC D D SDO GND BIAS AC CIN12 SDA GND BIAS AC CIN12 SHIELD SHIELD E E TOP VIEW TOP VIEW (BALL SIDE DOWN) (BALL SIDE DOWN) Not to Scale Not to Scale NOTES NOTES 1. TP DENOTES FACTORY TEST POINT. 1. TP DENOTES FACTORY TEST POINT. Figure 6. AD7147A-1 Pin Configuration Figure 5. AD7147A Pin Configuration Table 7. Pin Function Descriptions Pin No. AD7147A AD7147A-1 Mnemonic Description B4 B4 CIN6 Capacitance Sensor Input. B5 B5 CIN7 Capacitance Sensor Input. C4 C4 CIN8 Capacitance Sensor Input. C5 C5 CIN9 Capacitance Sensor Input. D4 D4 CIN10 Capacitance Sensor Input. D5 D5 CIN11 Capacitance Sensor Input. E5 E5 CIN12 Capacitance Sensor Input. E4 E4 ACSHIELD CDC Active Shield Output. Connect to external shield or plane. E3 E3 BIAS Bias Node for Internal Circuitry. Requires 100 nF capacitor to ground. E2 E2 GND Ground Reference Point for All Circuitry. D2 D2 V Supply Voltage. CC C2 C2 VDRIVE Serial Interface Operating Voltage Supply. E1 N/A SDO SPI Serial Data Output. 2 N/A E1 SDA I C Serial Data Input/Output. SDA requires pull-up resistor. D1 N/A SDI SPI Serial Data Input. 2 N/A D1 ADD0 I C Address Bit 0. C1 C1 SCLK Clock Input for Serial Interface. B1 N/A CS SPI Chip Select Signal. 2 N/A B1 ADD1 I C Address Bit 1. A1 A1 INT General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor. A2 A2 GPIO Programmable General-Purpose Input/Output. D3 D3 CIN0 Capacitance Sensor Input. A3 A3 CIN1 Capacitance Sensor Input. B3 B3 CIN2 Capacitance Sensor Input. A4 A4 CIN3 Capacitance Sensor Input. C3 C3 CIN4 Capacitance Sensor Input. A5 A5 CIN5 Capacitance Sensor Input. B2 B2 Factory Test Point Only. Tie to ground. Rev. B | Page 8 of 68 07727-005 07727-006 AD7147A TYPICAL PERFORMANCE CHARACTERISTICS 935 70 915 60 200ms 895 50 DECIMATION = 64 875 40 400ms DECIMATION = 128 600ms DECIMATION = 256 855 30 800ms 835 20 815 10 795 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 2.5 2.7 2.9 3.1 3.3 3.5 3.7 V (V) V (V) CC CC Figure 7. Supply Current vs. Supply Voltage Figure 10. Low Power Supply Current vs. Supply Voltage, Decimation Rate = 64 180 2.5 200ms 160 2.0 140 120 1.5 100 400ms 80 600ms 1.0 60 800ms 40 0.5 20 0 0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V (V) V (V) CC CC Figure 8. Low Power Supply Current vs. Supply Voltage, Figure 11. Shutdown Supply Current vs. Supply Voltage Decimation Rate = 256 0.12 1150 0.10 200ms 1100 0.08 1050 0.06 400ms 600ms 1000 0.04 800ms 950 0.02 0 900 2.5 2.72.93.13.33.5 3.7 0 100 200 300 400 500 V (V) CC AC CAPACITIVE LOAD (pF) SHIELD Figure 9. Low Power Supply Current vs. Supply Voltage, Figure 12. Supply Current vs. Capacitive Load on ACSHIELD Decimation Rate = 128 Rev. B | Page 9 of 68 I (mA) CC I (μA) I (µA) CC CC 07727-008 07727-007 07727-009 I (µA) I (μA) CC I (µA) CC CC 07727-011 07727-012 07727-010 AD7147A 58,000 160 25mV 75mV 125mV 175mV 50mV 100mV 150mV 200mV 56,000 140 54,000 120 52,000 100 50,000 80 48,000 60 46,000 40 44,000 20 42,000 40,000 0 0 100 200 300 400 500 AC CAPACITIVE LOAD (pF) SHIELD SINE WAVE FREQUENCY (Hz) Figure 16. Power Supply Sine Wave Rejection, V = 3.6 V Figure 13. CDC Code vs. Capacitive Load on ACSHIELD CC 120 25mV 75mV 125mV 175mV 50mV 100mV 150mV 200mV 960 100 940 3.6V 920 80 900 3.3V 60 880 860 40 840 20 820 2.6V 800 0 780 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) SQUARE WAVE FREQUENCY (Hz) Figure 14. Supply Current vs. Temperature Figure 17. Power Supply Square Wave Rejection, V = 3.6 V CC 12 35 30 10 25 8 20 6 15 3.6V 4 3.3V 10 2.6V 2 5 0 0 –45 –25 –5 15 35 55 75 95 115 135 0 10,000 20,000 30,000 40,000 50,000 60,000 TEMPERATURE (°C) CDC OUTPUT CODE Figure 15. Shutdown Supply Current vs. Temperature Figure 18. CDC Linearity, VCC = 3.3 V Rev. B | Page 10 of 68 CDC CODE (d) I (µA) CC I (µA) CC 07727-014 07727-015 07727-013 INPUT CAPACITANCE (pF) CDC NOISE p-p (LSB) CDC NOISE p-p (LSB) 25 25 50 50 100 100 200 200 400 400 800 800 1600 1600 3200 3200 6400 6400 12,800 12,800 25,600 25,600 51,200 51,200 102,400 102,400 204,800 204,800 409,600 409,600 819,200 819,200 1,640,000 1,640,000 07727-018 07727-017 07727-016 AD7147A THEORY OF OPERATION The AD7147A and AD7147A-1 are CDCs with on-chip environ- The AD7147A can be programmed to operate in either full mental compensation. They are intended for use in portable power mode or low power automatic wake-up mode. The systems requiring high resolution user input. The internal automatic wake-up mode is particularly suited for portable circuitry consists of a 16-bit, Σ-Δ converter that can change a devices that require low power operation to provide the user capacitive input signal into a digital value. There are 13 input with significant power savings and full functionality. pins, CIN0 to CIN12. A switch matrix routes the input signals INT The AD7147A has an interrupt output, , to indicate when new to the CDC. The result of each capacitance-to-digital conversion INT data has been placed into the registers. is used to interrupt the is stored in on-chip registers. The host subsequently reads the host on sensor activation. The AD7147A operates from a 2.6 V to results over the serial interface. The AD7147A has an SPI interface, 3.6 V supply and is available in a 2.3 mm × 2.1 mm WLCSP. 2 and the AD7147A-1 has an I C interface, ensuring that the parts CAPACITANCE SENSING THEORY are compatible with a wide range of host processors. AD7147A refers to both the AD7147A and AD7147A-1, unless otherwise The AD7147A measures capacitance changes from single electrode noted, from this point forward in this data sheet. sensors. The sensor electrode on the PCB comprises one plate of a virtual capacitor. The other plate of the capacitor is the user’s The AD7147A interfaces with up to 13 external capacitance finger, which is grounded with respect to the sensor input. sensors. These sensors can be arranged as buttons, scroll bars, or wheels, or as a combination of sensor types. The external The AD7147A first outputs an excitation signal to charge the sensors consist of an electrode on a single- or multiple-layer plate of the capacitor. When the user comes close to the sensor, PCB that interfaces directly to the AD7147A. the virtual capacitor is formed, with the user acting as the second capacitor plate. The AD7147A can be set up to implement any set of input sensors by programming the on-chip registers. The registers can also be programmed to control features such as averaging, offsets, and gains for each of the external sensors. There is an on-chip sequencer that controls how each of the capacitance inputs is polled. PLASTIC COVER The AD7147A has on-chip digital logic and 528 words of RAM that are used for environmental compensation. The effects of humidity, temperature, and other environmental factors can SENSOR PCB affect the operation of capacitance sensors. Transparent to the user, the AD7147A performs continuous calibration to compen- Σ-Δ 16-BIT sate for these effects, allowing the AD7147A to consistently ADC DATA provide error-free results. The AD7147A requires a companion algorithm that runs on the EXCITATION host or another microcontroller to implement high resolution SIGNAL 250kHz sensor functions, such as scroll bars or wheels. However, no AD7147A companion algorithm is required to implement buttons. Button Figure 19. Capacitance-Sensing Method sensors are implemented on chip, entirely in digital logic. A square wave excitation signal is applied to CINx during the conversion, and the modulator continuously samples the charge going through CINx. The output of the modulator is processed via a digital filter, and the resulting digital data is stored in the CDC_RESULT_Sx registers for each conversion stage, at Address 0x00B to Address 0x016. Rev. B | Page 11 of 68 MUX 07727-019 AD7147A Registering a Sensor Activation Complete Solution for Capacitance Sensing When a user approaches a sensor, the total capacitance associated Analog Devices, Inc., provides a complete solution for capacitance with that sensor changes and is measured by the AD7147A. If sensing. The two main elements to the solution are the sensor the change causes a set threshold to be exceeded, the AD7147A PCB and the AD7147A. interprets this as a sensor activation. If the application requires high resolution sensors such as scroll On-chip threshold limits are used to determine when a sensor bars or wheels, software that runs on the host processor is required. activation occurs. Figure 20 shows the change in CDC_RESULT_Sx The memory requirements for the host depend on the sensor when a user activates a sensor. The sensor is deemed to be active and are typically 10 kB of code and 600 bytes of data memory, only when the value of CDC_RESULT_Sx is either greater than the depending on the sensor type. value of STAGEx_HIGH_THRESHOLD or less than the value SENSOR PCB of STAGEx_LOW_THRESHOLD. SENSOR ACTIVE A HOST PROCESSOR 2 SPI OR I C 1 MIPS AD7147A 10kB ROM STAGEx_HIGH_THRESHOLD 600 BYTES RAM CDC_RESULT_Sx AMBIENT OR Figure 21. Three-Part Capacitance Sensing Solution NO-TOUCH VALUE Analog Devices supplies the sensor PCB footprint design STAGEx_LOW_THRESHOLD libraries to the customer and supplies any necessary software on an open-source basis. SENSOR ACTIVE B BIAS PIN Figure 20. Sensor Activation Thresholds This pin is connected internally to a bias node of the AD7147A. In Figure 20, two sensor activations are shown. Sensor Active A To ensure correct operation of the AD7147A, connect a 100 nF occurs when a sensor is connected to the positive input of the capacitor between the BIAS pin and ground. The voltage seen at converter. In this case, when a user activates the sensor, there is an the BIAS pin is V /2. CC increase in CDC code, and the value of CDC_RESULT_Sx exceeds that of STAGEx_HIGH_THRESHOLD. Sensor Active B occurs OPERATING MODES when the sensor is connected to the negative input of the converter. The AD7147A has three operating modes. Full power mode, where In this case, when a user activates the sensor, there is a decrease the device is always fully powered, is suited for applications where in CDC code, and the value of CDC_RESULT_Sx becomes less power is not a concern (for example, game consoles that have an than the value of STAGEx_LOW_THRESHOLD. ac power supply). Low power mode, where the part automatically For each conversion stage, the STAGEx_HIGH_THRESHOLD powers down when no sensor is active, is tailored to provide and STAGEx_LOW_THRESHOLD registers are in Bank 3. significant power savings compared with full power mode and The values in these registers are updated automatically by the is suited for mobile applications, where power must be conserved. AD7147A due to its environmental calibration and adaptive In shutdown mode, the part shuts down completely. threshold logic. The POWER_MODE Bits[1:0] of the power control register At power-up, the values in the STAGEx_HIGH_THRESHOLD (PWR_CONTROL, Address 0x000) set the operating mode on and STAGEx_LOW_THRESHOLD registers are the same as those the AD7147A. Table 8 shows the POWER_MODE settings for in the STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW each operating mode. To put the AD7147A into shutdown registers in Bank 2. The user must program the STAGEx_OFFSET mode, set the POWER_MODE bits to either 01 or 11. _HIGH and STAGEx_OFFSET_LOW registers on device power- Table 8. POWER_MODE Settings up. See the Environmental Calibration section of the data sheet POWER_MODE Bits Operating Mode for more information. 00 Full power mode 01 Shutdown mode 10 Low power mode 11 Shutdown mode The power-on default setting of the POWER_MODE bits is 00, full power mode. Rev. B | Page 12 of 68 CDC OUTPUT CODES 07727-020 07727-021 AD7147A Full Power Mode is 400 ms, the AD7147A typically uses 0.85 mA of current for 36 ms and 14 μA of current for 400 ms during the conversion In full power mode, all sections of the AD7147A remain fully interval. (Note that these conversion timings can be altered powered and converting at all times. While a sensor is being through the register settings. See the CDC Conversion Sequence touched, the AD7147A processes the sensor data. If no sensor is Time section for more information.) touched, the AD7147A measures the ambient capacitance level and uses this data for the on-chip compensation routines. In full The time for the AD7147A to transition from a full power state power mode, the AD7147A converts at a constant rate. See the to a reduced power state after the user stops touching the external CDC Conversion Sequence Time section for more information. sensors is configurable. The PWR_DOWN_TIMEOUT bits in the Ambient Compensation Control 0 register (AMB_COMP_ Low Power Mode CTRL0, Address 0x002) control the time delay before the When AD7147A is in low power mode, the POWER_MODE AD7147A transitions to the reduced power state after the user bits are set to 10 upon device initialization. If the external stops touching the sensors. sensors are not touched, the AD7147A reduces its conversion Low Latency from Touch to Response frequency, thereby greatly reducing its power consumption. The part remains in a reduced power state while the sensors are In low power mode, the AD7147A remains in a low power state not touched. The AD7147A performs a conversion after a delay until proximity is detected on any one of the external sensors. defined by the LP_CONV_DELAY bits, and it uses this data to When proximity is detected, the AD7147A begins a conversion update the compensation logic and check if the sensors are active. sequence every 36 ms, or 18 ms, or 9 ms to read back data from The LP_CONV_DELAY bits set the delay between conversions the sensors. The latency between first touch and AD7147A to 200 ms, 400 ms, 600 ms, or 800 ms. response is greatly reduced compared to the AD7147 because the part is already in a full power state by the time the user In low power mode, the total current consumption of the touches the sensor. AD7147A is an average of the current used during a conversion and the current used while the AD7147A is waiting for the next conversion to begin. For example, when LP_CONV_DELAY AD7147A SETUP AND INITIALIZATION POWER_MODE = 10 USER IN NO YES PROXIMITY TO SENSOR? CONVERSION SEQUENCE CONVERSION SEQUENCE EVERY 9ms, 18ms, OR EVERY LP_CONV_DELAY 36ms FOR SENSOR READBACK UPDATE COMPENSATION LOGIC DATA PATH USER IN YES PROXIMITY TO SENSOR? NO TIMEOUT PROXIMITY TIMER COUNTDOWN Figure 22. Low Power Mode Operation, AD7147A Rev. B | Page 13 of 68 07727-022 AD7147A CAPACITANCE-TO-DIGITAL CONVERTER The capacitance-to-digital converter on the AD7147A has a from midscale, decrease the POS_AFE_OFFSET or Σ-Δ architecture with 16-bit resolution. There are 13 possible NEG_AFE_OFFSET value by 1. inputs to the CDC that are connected to the input of the converter The goal is to ensure that the CDC_RESULT_Sx is as close through a switch matrix. The sampling frequency of the CDC is to midscale as possible. This process is required only once 250 kHz. during the initial capacitance sensor characterization. OVERSAMPLING THE CDC OUTPUT 6 +DAC POS_AFE_OFFSET (20pF RANGE) The decimation rate, or oversampling ratio, is determined by Bits[9:8] of the power control register (PWR_CONTROL, Address 0x000), as listed in Table 9. POS_AFE_OFFSET_SWAP BIT Table 9. CDC Decimation Rate CDC Output Rate CINx + 16 16-BIT Decimation Bits Decimation Rate Per Stage (ms) CDC _ 00 256 3.072 NEG_AFE_OFFSET_SWAP BIT 01 128 1.536 10 64 0.768 11 64 0.768 6 –DAC NEG_AFE_OFFSET The decimation process on the AD7147A is an averaging (20pF RANGE) process, where a number of samples are taken and the averaged CINx_CONNECTION_SETUP result is output. Due to the architecture of the digital filter employed, the number of samples taken (per stage) is equal to 3× Figure 23. Analog Front-End Offset Control the decimation rate. So 3 × 256 or 3 × 128 samples are averaged to obtain each stage result. CONVERSION SEQUENCER The decimation process reduces the amount of noise present in The AD7147A has an on-chip sequencer to implement conversion the final CDC result. However, the higher the decimation rate, control for the input channels. Up to 12 conversion stages can be the lower the output rate per stage; therefore, there is a trade-off performed in one sequence. Each of the 12 conversions stages can possible between the amount of noise in the signal and the measure the input from a different sensor. By using the Bank 2 speed of sampling. registers, each stage can be uniquely configured to support multiple capacitance sensor interface requirements. For example, a slider CAPACITANCE SENSOR OFFSET CONTROL sensor can be assigned to STAGE1 through STAGE8, with a There are two programmable DACs on board the AD7147A to null button sensor assigned to STAGE0. For each conversion stage, the effect of any stray capacitances on the CDC measurement. the input mux that connects the CINx inputs to the converter These offsets are due to stray capacitance to ground. can have a unique setting. A simplified block diagram in Figure 23 shows how to apply The AD7147A on-chip sequence controller provides conversion the STAGEx_AFE_OFFSET registers to null the offsets. The control, beginning with STAGE0. Figure 24 shows a block diagram POS_AFE_OFFSET and NEG_AFE_OFFSET bits (Bits[13:8] and of the CDC conversion stages and CINx inputs. A conversion Bits[5:0], respectively) program the offset DACs to provide 0.32 sequence is defined as a sequence of CDC conversions starting pF resolution offset adjustment over a range of 20 pF. at STAGE0 and ending at the stage determined by the value The best practice is to ensure that the CDC output for any stage programmed in the SEQUENCE_STAGE_NUM bits (Bits[7:4], is approximately equal to midscale (~32,700) when all sensors Address 0x00). Depending on the number and type of capacitance are inactive. To correctly offset the stray capacitance to ground for sensors that are used, not all conversion stages are required. Use each stage, use the following procedure: the SEQUENCE_STAGE_NUM bits to set the number of conver- sions in one sequence. This number depends on the sensor 1. Read back the CDC value from the CDC_RESULT_Sx interface requirements. For example, the register should be set register. to 5 if the CINx inputs are mapped to only six conversion stages. 2. If this value is not close to midscale, increase the value of In addition, the STAGE_CAL_EN register (Address 0x001) POS_AFE_OFFSET or NEG_AFE_OFFSET (depending should be set according to the number of stages that are used. on if the CINx input is connected to the positive or negative input of the converter) by 1. The CINx connections are The number of required conversion stages depends solely on determined by the STAGEx_CONNECTION registers. the number of sensors attached to the AD7147A. Figure 25 3. If the CDC value in CDC_RESULT_Sx is now closer shows how many conversion stages are required for each sensor to midscale, repeat Step 2. If the CDC value is further and how many inputs to the AD7147A each sensor requires. Rev. B | Page 14 of 68 07727-023 AD7147A A button sensor generally requires one sequencer stage; this is A wheel sensor requires eight stages, whereas a slider requires shown in Figure 25 as B1. However, it is possible to configure two stages. The result from each stage is used by the host soft- two button sensors to operate differentially for one conversion ware to determine the user’s position on the slider or wheel. The algorithms that perform this process are available from Analog stage. Only one button can be activated at a time; pressing both buttons simultaneously results in neither button being activated. Devices and are free of charge but require signing a software The configuration with two button sensors operating differen- license. tially requires one conversion stage and is shown in Figure 25, with B2 and B3 representing the differentially configured button sensors. STAGE11 STAGE10 STAGE9 STAGE8 STAGE7 STAGE6 STAGE5 STAGE4 STAGE3 STAGE2 STAGE1 STAGE0 CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 Σ-Δ CIN6 16-BIT ADC CIN7 CIN8 CIN9 CIN10 CIN11 CIN12 Figure 24. CDC Conversion Stages AD7147A AD7147A SEQUENCER SEQUENCER BUTTONS STAGE0 STAGE8 + B1 + CDC CDC – – STAGE1 STAGE9 + B2 + CDC CDC – – STAGE2 B3 + CDC – STAGE3 + CDC – SCROLL WHEEL STAGE4 + AD7147A CDC – SEQUENCER STAGE5 STAGE10 + + CDC CDC – – SLIDER STAGE6 STAGE11 + + CDC CDC – – STAGE7 + CDC – Figure 25. Sequencer Setup for Sensors Rev. B | Page 15 of 68 CONVERSION SEQUENCE SWITCH MATRIX 07727-024 07727-025 AD7147A CDC CONVERSION SEQUENCE TIME Table 10. CDC Conversion Times for Full Power Mode Conversion Time (ms) SEQUENCE_STAGE_NUM Decimation = 64 Decimation = 128 Decimation = 256 0 0.768 1.536 3.072 1 1.536 3.072 6.144 2 2.304 4.608 9.216 3 3.072 6.144 12.288 4 3.84 7.68 15.36 5 4.608 9.216 18.432 6 5.376 10.752 21.504 7 6.144 12.288 24.576 8 6.912 13.824 27.648 9 7.68 15.36 30.72 10 8.448 16.896 33.792 11 9.216 18.432 36.864 The time required for the CDC to complete the measurement of For example, maximum power savings is achieved when the all 12 stages is defined as the CDC conversion sequence time. The LP_CONV_DELAY bits are set to 11. With a setting of 11, SEQUENCE_STAGE_NUM and DECIMATION bits determine the AD7147A automatically wakes up, performing a conversion the conversion time, as listed in Table 10. every 800 ms. For example, if the device is operated with a decimation rate Table 11. LP_CONV_DELAY Settings of 128 and the SEQUENCE_STAGE_NUM bit is set to 5 for the LP_CONV_DELAY Bits Delay Between Conversions (ms) conversion of six stages in a sequence, the conversion sequence 00 200 time is 9.216 ms. 01 400 Full Power Mode CDC Conversion Sequence Time 10 600 11 800 The full power mode CDC conversion sequence time for all 12 stages is set by configuring the SEQUENCE_STAGE_NUM Figure 27 shows a simplified timing example of the low power and DECIMATION bits as outlined in Table 10. mode CDC conversion time. As shown, the low power mode CDC conversion time is set by tCONV_FP and the LP_CONV_DELAY bits. Figure 26 shows a simplified timing diagram of the full power mode CDC conversion time. The full power mode CDC con- t CONV_LP version time (t ) is set using the values shown in Table 10. CONV_FP t CONV_FP t CONV_FP CDC CONVERSION CONVERSION LP_CONV_DELAY CONVERSION SEQUENCE N SEQUENCE N + 1 CDC CONVERSION CONVERSION CONVERSION CONVERSION SEQUENCE N SEQUENCE N + 1 SEQUENCE N + 2 Figure 27. Low Power Mode CDC Conversion Sequence Time Figure 26. Full Power Mode CDC Conversion Sequence Time CDC CONVERSION RESULTS Low Power Mode CDC Conversion Sequence Time Certain high resolution sensors require the host to read back the with Delay CDC conversion results for processing. The registers required The frequency of each CDC conversion while operating in the for host processing are located in Bank 3. The host processes the low power automatic wake-up mode is controlled by using the data read back from these registers using a software algorithm to LP_CONV_DELAY Bits[3:2] located at Address 0x000 in addi- determine position information. tion to the registers listed in Table 10. This feature provides some In addition to the results registers in Bank 3, the AD7147A flexibility for optimizing the trade-off between the conversion time provides the 16-bit CDC output data directly, starting at needed to meet system requirements and the power consumption Address 0x00B of Bank 1. Reading back the CDC 16-bit of the AD7147A. conversion data register allows for customer-specific application data processing. Rev. B | Page 16 of 68 07727-026 07727-027 AD7147A CAPACITANCE SENSOR INPUT CONFIGURATION Each input connection from the external capacitance sensors to To connect CIN0 to the positive CDC input and CIN12 to the the converter of the AD7147A can be uniquely configured by negative CIN input on STAGE5, use the following settings: using the stage configuration registers in Bank 2 (see Table 39). STAGE5_CONNECTION[6:0] = 0xFFFE These registers are used to configure the input pin connection STAGE5_CONNECTION[12:7] = 0x37FF setups, sensor offsets, sensor sensitivities, and sensor limits SINGLE-ENDED CONNECTIONS TO THE CDC for each stage. Each sensor can be individually optimized. For example, a button sensor connected to STAGE0 can have differ- A single-ended connection to the CDC is defined as one CINx ent sensitivity and offset values than a button with another input connected to either the positive or negative CDC input function that is connected to a different stage. for one conversion stage. A differential connection to the CDC is defined as one CINx input connected to the positive CDC input CINx INPUT MULTIPLEXER SETUP and a second CINx input connected to the negative input of the Table 35 and Table 36 list the available options for the CINx_ CDC for one conversion stage. CONNECTION_SETUP bits when the sensor input pins are For any stage, if a single-ended connection to the CDC is made connected to the CDC. in that stage, the SE_CONNECTION_SETUP Bits[13:12] in the The AD7147A has an on-chip multiplexer that routes the input STAGEx_CONNECTION[12:7] register should be applied as signals from each CINx pin to the input of the converter. Each described in Table 12. input pin can be tied to either the negative or positive input of the CDC, or it can be left floating. Each input can also be Table 12. SE_CONNECTION_SETUP Bits internally connected to the BIAS signal to help prevent cross- SE_CONNECTION_SETUP Description coupling. If an input is not used, always connect it to BIAS. 00 Do not use. 01 Single-ended connection. For this Connecting a CINx input pin to the positive CDC input results stage, there is one CINx connected in an increase in CDC output code when the corresponding to the positive CDC input. sensor is activated. Connecting a CINx input pin to the negative 10 Single-ended connection. For this CDC input results in a decrease in CDC output code when the stage, there is one CINx connected corresponding sensor is activated. to the negative CDC input. 11 Differential connection. For this The AD7147A performs a sequence of 12 conversions. The multi- stage, there is one CINx connected plexer can have different settings for each of the 12 conversions. to the negative CDC input and one For example, CIN0 is connected to the negative CDC input for CINx connected to the positive conversion STAGE1, left floating for conversion STAGE1, and CDC input. so on, for all 12 conversion stages. The SE_CONNECTION_SETUP Bits[13:12] ensure that during a For each CINx input for each conversion stage, two bits control single-ended connection to the CDC, the input paths to both how the input is connected to the converter, as shown in Figure 28. CDC terminals are matched, which, in turn, improves the power-supply rejection of the converter measurement. Examples To connect CIN3 to the positive CDC input on Stage 0, use the These bits should be applied in addition to setting the other bits in the STAGEx_CONNECTION registers, as outlined in the following setting: CINX Input Multiplexer Setup section. STAGE0_CONNECTION[6:0] = 0xFFBF If more than one CINx input is connected to either the positive STAGE0_CONNECTION[12:7] = 0x2FFF or negative input of the converter for the same conversion, set SE_CONNECTION_SETUP to 11. For example, if CIN0 and CIN3 are connected to the positive input of the CDC, set SE_CONNECTION_SETUP to 11. CIN CONNECTION SETUP BITS CIN SETTING CIN0 CIN1 00 CINx FLOATING CIN2 CIN3 CIN4 CINx CONNECTED TO 01 + CIN5 NEGATIVE CDC INPUT CIN6 CDC CIN7 CINx CONNECTED TO – 10 CIN8 POSITIVE CDC INPUT CIN9 CIN10 CINx CONNECTED TO CIN11 11 BIAS CIN12 Figure 28. Input Mux Configuration Options Rev. B | Page 17 of 68 07727-028 AD7147A NONCONTACT PROXIMITY DETECTION The AD7147A internal signal processing continuously monitors The AD7147A recalibrates automatically when the measured CDC all capacitance sensors for noncontact proximity detection. This value exceeds the stored ambient value by an amount determined feature provides the ability to detect when a user is approaching by the PROXIMITY_RECAL_LVL bits for a set period of time a sensor, at which time all internal calibration is immediately known as the recalibration timeout. In full power mode, the recali- disabled while the AD7147 is automatically configured to detect bration timeout is controlled by FP_PROXIMITY_RECAL; in a valid contact. low power mode, by LP_PROXMTY_RECAL. The proximity control register bits are described in Table 13. The The recalibration timeout in full power mode is the value of FP_PROXIMITY_CNT and LP_PROXIMITY_CNT register FP_PROXIMITY_RECAL multiplied by the time for one bits control the length of the calibration disable period after the conversion sequence in full power mode. The recalibration time- user stops touching the sensor and is not in close proximity to out in low power mode is the value of LP_PROXIMITY_RECAL the sensor during full or low power mode. The calibration is multiplied by the time for one conversion sequence in low disabled during this period and then enabled again. Figure 29 power mode. and Figure 30 show examples of how these register bits are Figure 31 and Figure 32 show examples of how the FP_ used to set the calibration disable periods for the full and low PROXIMITY_RECAL and LP_PROXIMITY_RECAL register power modes. bits control the timeout period before a recalibration while The calibration disable period in full power mode is the value operating in the full and low power modes. In these examples, of the FP_PROXIMITY_CNT multiplied by 16 multiplied by a user approaches a sensor and then leaves, but the proximity the time for one conversion sequence in full power mode. The detection remains active. The measured CDC value exceeds the calibration disable period in low power mode is the value of the stored ambient value by the amount set in the PROXIMITY_ LP_PROXIMITY_CNT multiplied by 4 multiplied by the time RECAL_LVL bits for the entire timeout period. The sensor is for one conversion sequence in low power mode. automatically recalibrated at the end of the timeout period. RECALIBRATION PROXIMITY SENSITIVITY In certain situations, for example, when a user hovers over a The fast filter in Figure 33 is used to detect when someone is sensor for a long time, the proximity flag can be set for a long close to the sensor (proximity). Two conditions, detected by period. The environmental calibration on the AD7147A is sus- Comparator 1 and Comparator 2, set the internal proximity pended while proximity is detected, but changes may occur detection signal: Comparator 1 detects when a user is approach- to the ambient capacitance level during the proximity event. ing or leaving a sensor, and Comparator 2 detects when a user This means that the ambient value stored on the AD7147A no hovers over a sensor or approaches a sensor very slowly. longer represents the actual ambient value. In this case, even The sensitivity of Comparator 1 is controlled by the PROXIMITY_ when the user is not in close proximity to the sensor, the prox- DETECTION_RATE bits (Address 0x003). For example, if imity flag may still be set. This situation can occur if the user PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1 interaction creates some moisture on the sensor, causing the signal is set when the absolute difference between WORD1 and new sensor ambient value to be different from the expected WORD3 exceeds (4 × 16) LSB codes. value. In this situation, the AD7147A automatically forces a The PROXIMITY_RECAL_LVL bits (Address 0x003) control recalibration internally. This ensures that the ambient values the sensitivity of Comparator 2. For example, if PROXIMITY_ are recalibrated, regardless of how long the user hovers over RECAL_LVL is set to 75, the Proximity 2 signal is set when the the sensor. A recalibration ensures maximum AD7147A sensor absolute difference between the fast filter average value and the performance. ambient value exceeds (75 × 16) LSB codes. Rev. B | Page 18 of 68 AD7147A Table 13. Proximity Control Registers (See Figure 33) Length Bit Name (Bits) Register Address Description FP_PROXIMITY_CNT 4 0x002[7:4] Calibration disable time in full power mode. LP_PROXIMITY_CNT 4 0x002[11:8] Calibration disable time in low power mode. FP_PROXIMITY_RECAL 10 0x004[9:0] Full power mode proximity recalibration time control. LP_PROXIMITY_RECAL 6 0x004[15:10] Low power mode proximity recalibration time control. PROXIMITY_RECAL_LVL 8 0x003[7:0] Proximity recalibration level. This value, multiplied by 16, controls the sensitivity of Comparator 2 (see Figure 33). PROXIMITY_DETECTION_RATE 6 0x003[13:8] Proximity detection rate. This value, multiplied by 16, controls the sensitivity of Comparator 1 (see Figure 33). USER APPROACHES USER LEAVES SENSOR SENSOR AREA t CONV_FP CDC CONVERSION 12 3456789 10111213141516 17 18 19 20 21 22 23 24 SEQUENCE (INTERNAL) t CALDIS PROXIMITY DETECTION (INTERNAL) CALIBRATION CALIBRATION DISABLED CALIBRATION ENABLED (INTERNAL) Figure 29. Example of Full Power Mode Proximity Detection (FP_PROXIMITY_CNT = 1) USER APPROACHES USER LEAVES SENSOR SENSOR AREA t CONV_LP 123456 789 10111213141516 17 18 19 20 21 22 23 24 CDC CONVERSION SEQUENCE (INTERNAL) t CALDIS PROXIMITY DETECTION (INTERNAL) CALIBRATION CALIBRATION DISABLED CALIBRATION ENABLED (INTERNAL) NOTES 1. SEQUENCE CONVERSION TIME t = t + LP_CONV_DELAY. CONV_LP CONV_FP 2. PROXIMITY IS SET WHEN THE USER APPROACHES THE SENSOR, AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED. 3. t = (t × LP_PROXIMITY_CNT × 4). CALDIS CONV_LP Figure 30. Example of Low Power Mode Proximity Detection (LP_PROXIMITY_CNT = 4) Rev. B | Page 19 of 68 07727-029 07727-030 AD7147A USER APPROACHES SENSOR t RECAL MEASURED CDC VALUE > STORED AMBIENT USER LEAVES BY PROXIMITY_RECAL _LVL SENSOR AREA t CONV_FP 16 30 70 CDC CONVERSION SEQUENCE (INTERNAL) t CALDIS PROXIMITY DETECTION (INTERNAL) CALIBRATION CALIBRATION DISABLED RECALIBRATION TIMEOUT CALIBRATION ENABLED (INTERNAL) t RECAL_TIMEOUT RECALIBRATION COUNTER (INTERNAL) NOTES 1. SEQUENCE CONVERSION TIME t (SEE TABLE 10). CONV_FP 2. t = t × FP_PROXIMITY_CNT × 16. CALDIS CONV_FP 3. t = t × FP_PROXIMITY_RECAL. RECAL_TIMEOUT CONV_FP 4. t = 2 × t . RECAL CONV_FP Figure 31. Example of Full Power Mode Proximity Detection with Forced Recalibration (FP_PROXIMITY_CNT = 1 and FP_PROXIMITY_RECAL = 40) USER APPROACHES SENSOR t RECAL MEASURED CDC VALUE > STORED AMBIENT USER LEAVES BY PROXIMITY_RECAL _LVL SENSOR AREA t CONV_LP 16 30 70 CDC CONVERSION SEQUENCE (INTERNAL) PROXIMITY DETECTION t CALDIS (INTERNAL) CALIBRATION CALIBRATION DISABLED RECALIBRATION TIMEOUT CALIBRATION ENABLED (INTERNAL) t RECAL_TIMEOUT RECALIBRATION (INTERNAL) NOTES 1. SEQUENCE CONVERSION TIME t = t + LP_CONV_DELAY. CONV_LP CONV_FP 2. t = t × LP_PROXIMITY_CNT × 4. CALDIS CONV_LP 3. t = t × LP_PROXIMITY_RECAL. RECAL_TIMEOUT CONV_LP 4. t = 2 × t . RECAL CONV_LP Figure 32. Example of Low Power Mode Proximity Detection with Forced Recalibration (LP_PROXIMITY_CNT = 4 and LP_PROXIMITY_RECAL = 40) Rev. B | Page 20 of 68 07727-032 07727-031 AD7147A Determining the FF_SKIP_CNT value is required only once FF_SKIP_CNT during the initial setup of the capacitance sensor interface. The proximity detection fast FIFO is used by the on-chip logic Table 13 shows how FF_SKIP_CNT controls the update rate of to determine if proximity is detected. The fast FIFO expects to the fast FIFO. The recommended value for the setting when receive samples from the converter at a set rate. The fast filter using all 12 conversion stages on the AD7147A is 0000, or no skip control, FF_SKIP_CNT (Bits[3:0], Address 0x002), is used samples skipped. to normalize the frequency of the samples going into the FIFO, regardless of how many conversion stages are in a sequence. This value determines which CDC samples are not used (skipped) by the proximity detection fast FIFO. Table 14. FF_SKIP_CNT Settings FAST FIFO Update Rate FF_SKIP _CNT Decimation = 64 Decimation = 128 Decimation = 256 0 0.768 × (SEQUENCE_STAGE_NUM + 1) ms 1.536 × (SEQUENCE_STAGE_NUM + 1) ms 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 1 1.536 × (SEQUENCE_STAGE_NUM + 1) ms 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 2 2.304 × (SEQUENCE_STAGE_NUM + 1) ms 4.608 × (SEQUENCE_STAGE_NUM + 1) ms 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 3 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 4 3.84 × (SEQUENCE_STAGE_NUM + 1) ms 7.68 × (SEQUENCE_STAGE_NUM + 1) ms 15.36 × (SEQUENCE_STAGE_NUM + 1) ms 5 4.608 × (SEQUENCE_STAGE_NUM + 1) ms 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 18.432 × (SEQUENCE_STAGE_NUM + 1) ms 6 5.376 × (SEQUENCE_STAGE_NUM + 1) ms 10.752 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms 7 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms 8 6.912 × (SEQUENCE_STAGE_NUM + 1) ms 13.824 × (SEQUENCE_STAGE_NUM + 1) ms 27.648 × (SEQUENCE_STAGE_NUM + 1) ms 9 7.68 × (SEQUENCE_STAGE_NUM + 1) ms 15.36 × (SEQUENCE_STAGE_NUM + 1) ms 30.72 × (SEQUENCE_STAGE_NUM + 1) ms 10 8.448 × (SEQUENCE_STAGE_NUM + 1) ms 16.896 × (SEQUENCE_STAGE_NUM + 1) ms 33.792 × (SEQUENCE_STAGE_NUM + 1) ms 11 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 18.432 × (SEQUENCE_STAGE_NUM + 1) ms 36.864 × (SEQUENCE_STAGE_NUM + 1) ms 12 9.984 × (SEQUENCE_STAGE_NUM + 1) ms 19.968 × (SEQUENCE_STAGE_NUM + 1) ms 39.936 × (SEQUENCE_STAGE_NUM + 1) ms 13 10.752 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms 43.008 × (SEQUENCE_STAGE_NUM + 1) ms 14 11.52 × (SEQUENCE_STAGE_NUM + 1) ms 23.04 × (SEQUENCE_STAGE_NUM + 1) ms 46.08 × (SEQUENCE_STAGE_NUM + 1) ms 15 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms 49.152 × (SEQUENCE_STAGE_NUM + 1) ms Rev. B | Page 21 of 68 AD7147A FP_PROXIMITY_CNT LP_PROXIMITY_CNT 16 REGISTER 0x002 REGISTER 0x002 CDC STAGEx_FF_WORD0 STAGEx_FF_WORD1 PROXIMITY 1 PROXIMITY COMPARATOR 1 PROXIMITY TIMING |WORD0 – WORD3| STAGEx_FF_WORD2 CONTROL LOGIC STAGEx_FF_WORD3 STAGEx_FF_WORD4 STAGEx_FF_WORD5 PROXIMITY_DETECTION_RATE REGISTER 0x003 FP_PROXIMITY_RECAL LP_PROXIMITY_RECAL STAGEx_FF_WORD6 REGISTER 0x004 REGISTER 0x004 STAGEx_FF_WORD7 BANK 3 REGISTERS 7 WORD(N) STAGEx_FF_AVG Σ BANK 3 REGISTERS N = 0 8 COMPARATOR 2 |AVERAGE – AMBIENT| STAGEx_FF_WORDx PROXIMITY SW1 SLOW_FILTER_EN PROXIMITY_RECAL_LVL REGISTER 0x003 COMPARATOR 3 STAGEx_SF_WORD0 |WORD0 – CDC VALUE| STAGEx_SF_WORD1 AMBIENT STAGEx_SF_AMBIENT STAGEx_SF_WORD2 VALUE BANK 3 REGISTERS STAGEx_SF_WORDx STAGEx_SF_WORD3 SLOW_FILTER_UPDATE_LVL SENSOR STAGEx_SF_WORD4 REGISTER 0x003 CONTACT STAGEx_SF_WORD5 STAGEx_SF_WORD6 t STAGEx_SF_WORD7 BANK 3 REGISTERS NOTES 1. SLOW_FILTER_EN, WHICH IS THE NAME OF THE OUTPUT OF COMPARATOR 3, IS SET AND SW1 IS CLOSED WHEN |STAGEx_SF_WORD0 – CDC VALUE| EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE_LVL REGISTER PROVIDING PROXIMITY IS NOT SET. |STAGEx_FF_ | 2. PROXIMITY 1 IS SET WHEN WORD0 – STAGEx_FF_WORD3 EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_DETECTION_RATE REGISTER. 3. PROXIMITY 2 IS SET WHEN |AVERAGE – AMBIENT| EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER. 4. DESCRIPTION OF COMPARATOR FUNCTIONS: COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR. COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR OR APPROACHING A SENSOR VERY SLOWLY. ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION. FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR. COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW_FILTER_EN IS SET AND PROXIMITY IS NOT SET. Figure 33. Proximity-Detection Logic Rev. B | Page 22 of 68 PROXIMITY 2 CDC OUTPUT CODE 07727-033 AD7147A ENVIRONMENTAL CALIBRATION SENSOR 1 INT The AD7147A provides on-chip capacitance sensor calibration ASSERTED to automatically adjust for environmental conditions that have STAGEx_HIGH_THRESHOLD an effect on the ambient levels of the capacitance sensor. The output levels of the capacitance sensor are sensitive to tempera- ture, humidity, and, in some cases, dirt. CDC AMBIENT VALUE The AD7147A achieves optimal and reliable sensor performance by continuously monitoring the CDC ambient levels and compen- STAGEx_LOW_THRESHOLD sating for any environmental changes by adjusting the values of SENSOR 2 INT the STAGEx_HIGH_THRESHOLD registers and the STAGEx_ ASSERTED LOW_THRESHOLD registers as described in the Threshold t Equations section. The CDC ambient level is defined as the CHANGING ENVIRONMENTAL CONDITIONS output level of the capacitance sensor during periods when the Figure 34. Ideal Sensor Behavior with a Constant Ambient Level user is not approaching or in contact with the sensor. CAPACITANCE SENSOR BEHAVIOR WITHOUT After the AD7147A is configured, the compensation logic runs CALIBRATION automatically with each conversion when the AD7147A is not Figure 35 shows the typical behavior of a capacitance sensor when being touched. This allows the AD7147A to compensate for calibration is not applied and the ambient levels drifting over time rapidly changing environmental conditions. as environmental conditions change. As a result of the initial The ambient compensation control registers provide the host threshold levels remaining constant while the ambient levels with access to general setup and controls for the compensation drift upward, Sensor 2 fails to detect a user contact in this example. algorithm. On-chip RAM stores the compensation data for each The Capacitance Sensor Behavior with Calibration section conversion stage, as well as setup information specific for each stage. describes how the AD7147A adaptive calibration algorithm Figure 34 shows an example of the ideal behavior of a capaci- prevents such errors from occurring. tance sensor, where the CDC ambient level remains constant SENSOR 1 INT regardless of the environmental conditions. The CDC output ASSERTED STAGEx_HIGH_THRESHOLD shown is for a pair of differential button sensors, where one sensor caused an increase and the other caused a decrease in measured capacitance when activated. The positive and negative CDC AMBIENT VALUE DRIFTING sensor threshold levels are calculated as a percentage of the STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW values, and are based on the threshold sensitivity settings and the STAGEx_LOW_THRESHOLD ambient value. These values are sufficient to detect a sensor SENSOR 2 INT contact and result in the AD7147A asserting the INT output NOT ASSERTED when the threshold levels are exceeded. t CHANGING ENVIRONMENTAL CONDITIONS Figure 35. Typical Sensor Behavior Without Calibration THRESHOLD EQUATIONS On-Chip Logic Stage High Threshold STAGEx _ OFFSET _ HIGH ⎛ ⎞ STAGEx _ HIGH _ THRESHOLD= STAGEx _ SF _ AMBIENT+ + ⎜ ⎟ ⎝ 4 ⎠ STAGEx _ OFFSET _ HIGH ⎛ ⎞ ⎛ ⎞ (1) STAGEx _ OFFSET _ HIGH− ⎜⎜ ⎟⎟ ⎝ 4 ⎠ ⎜ ⎟ × POS _ THRESHOLD _ SENSITIVITY ⎜ 16 ⎟ ⎜ ⎟ ⎝ ⎠ On-Chip Logic Stage Low Threshold STAGEx _ OFFSET _ LOW ⎛ ⎞ STAGEx _ LOW _ THRESHOLD= STAGEx _ SF _ AMBIENT+ + ⎜ ⎟ ⎝ 4 ⎠ STAGEx _ OFFSET _ LOW ⎛ ⎞ ⎛ ⎞ (2) STAGEx _ OFFSET _ LOW− ⎜⎜ ⎟⎟ ⎝ 4 ⎠ ⎜ ⎟ × NEG _ THRESHOLD _ SENSITIVITY ⎜ 16 ⎟ ⎜ ⎟ ⎝ ⎠ Rev. B | Page 23 of 68 CDC OUTPUT CODES CDC OUTPUT CODES 07727-035 07727-034 AD7147A AVG_FP_SKIP and AVG_LP_SKIP CAPACITANCE SENSOR BEHAVIOR WITH CALIBRATION In Register 0x001, Bits[13:12] are the slow FIFO skip control for full power mode, AVG_FP_SKIP. Bits[15:14] in the same register The AD7147A on-chip adaptive calibration algorithm prevents are the slow FIFO skip control for low power mode, AVG_LP_ sensor detection errors such as the one shown in Figure 35. SKIP, and determine which CDC samples are not used (skipped) This is achieved by monitoring the CDC ambient levels and in the slow FIFO. Changing the values of the AVG_FP_SKIP readjusting the initial STAGEx_OFFSET_HIGH and STAGEx_ and AVG_LP_SKIP bits slows down or speeds up the rate at OFFSET_LOW values according to the amount of ambient drift which the ambient capacitance value tracks the measured measured on each sensor. Based on the new stage offset values, capacitance value read by the converter. the internal STAGEx_HIGH_THRESHOLD and STAGEx_ LOW_THRESHOLD values described in Equation 1 and • Slow FIFO update rate in full power mode = AVG_FP_SKIP × Equation 2 are automatically updated. [(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM + 1) × −6 (FF_SKIP_CNT + 1) × 4 × 10 ]. This closed-loop routine ensures the reliability and repeatable operation of every sensor connected to the AD7147A when they • Slow FIFO update rate in low power mode = are subjected to dynamic environmental conditions. Figure 36 ((AVG_LP_SKIP + 1) × (3 × Decimation Rate) × −6 shows a simplified example of how the AD7147A applies the (SEQUENCE_STAGE_NUM + 1) × (4 × 10 ))+ adaptive calibration process, resulting in no interrupt errors LP_CONV_DELAY. even with changing CDC ambient levels due to dynamic The slow FIFO is used by the on-chip logic to track the ambient environmental conditions. capacitance value. The slow FIFO expects to receive samples from SENSOR 1 INT the converter at a rate between 33 ms and 40 ms. AVG_FP_SKIP ASSERTED 3 STAGEx_HIGH_THRESHOLD 2 and AVG_LP_SKIP are used to normalize the frequency of the (POSTCALIBRATED REGISTER VALUE) 1 samples going into the FIFO, regardless of how many conversion stages are in a sequence. CDC AMBIENT Determining the AVG_FP_SKIP and AVG_LP_SKIP values is VALUE DRIFTING required only once during the initial setup of the capacitance 6 sensor interface. The recommended values for these settings 5 STAGEx_LOW_THRESHOLD (POSTCALIBRATED when using all 12 conversion stages on the AD7147A are as follows: 4 REGISTER VALUE) • AVG_FP_SKIP = 00 = skip three samples SENSOR 2 INT ASSERTED • AVG_LP_SKIP = 00 = skip zero samples t CHANGING ENVIRONMENTAL CONDITIONS SLOW_FILTER_UPDATE_LVL 1 INITIAL STAGEx_OFFSET_HIGH REGISTER VALUE. SLOW_FILTER_UPDATE_LVL controls whether the most 2 POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD. 3 POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD. recent CDC measurement goes into the slow FIFO (slow filter). 4 INITIAL STAGEx_LOW_THRESHOLD. 5 POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD. The slow filter is updated when the difference between the 6 POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD. current CDC value and the last value of the slow FIFO is Figure 36. Typical Sensor Behavior with Calibration Applied on the Data Path greater than the value of SLOW_FILTER_UPDATE_LVL, SLOW FIFO which is in the Ambient Control 1 register (AMB_COMP_ CTRL1), Address 0x003. As shown in Figure 33, there are a number of FIFOs imple- mented on the AD7147A. These FIFOs are located in Bank 3 of the on-chip memory. The slow FIFOs are used by the on-chip logic to monitor the ambient capacitance level from each sensor. Rev. B | Page 24 of 68 CDC OUTPUT CODES 07727-036 AD7147A ADAPTIVE THRESHOLD AND SENSITIVITY The AD7147A provides an on-chip, self-adjusting adaptive finger results in a large average maximum or minimum value, threshold and sensitivity algorithm. This algorithm continu- whereas a small finger results in smaller values. When the ously monitors the output levels of each sensor and automatically average maximum or minimum value changes, the threshold rescales the threshold levels in proportion to the sensor area levels are rescaled to ensure that the threshold levels are covered by the user. As a result, the AD7147A maintains appropriate for the current user. Figure 38 shows how the optimal threshold and sensitivity levels for all users regardless minimum and maximum sensor responses are tracked by the of their finger sizes. on-chip logic. The threshold level is always referenced from the ambient level Reference A in Figure 37 shows a less sensitive threshold level and is defined as the CDC converter output level that must be for a user with small fingers and demonstrates the disadvantages exceeded before a valid sensor contact can occur. The sensitivity of a fixed threshold level. level is defined as how sensitive the sensor must be before a By enabling the adaptive threshold and sensitivity algorithm, the valid contact can be registered. positive and negative threshold levels are determined by the Figure 37 provides an example of how the adaptive threshold POS_THRESHOLD_SENSITIVITY and NEG_THRESHOLD_ and sensitivity algorithm works. The positive and negative SENSITIVITY bit values and by the most recent average maxi- sensor threshold levels are calculated as a percentage of the mum sensor output value. These bits can be used to select 16 STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW different positive and negative sensitivity levels ranging between values and are based on the threshold sensitivity settings and 25% and 95.32% of the most recent average maximum output the ambient value. After the AD7147A is configured, initial level referenced from the ambient value. The smaller the sensi- estimates are supplied for both STAGEx_OFFSET_HIGH tivity percentage setting, the easier it is to trigger a sensor and STAGEx_OFFSET_LOW, and then the calibration engine activation. Reference B shows that the positive adaptive threshold automatically adjusts the STAGEx_HIGH_THRESHOLD and level is set at almost midsensitivity with a 62.51% threshold STAGEx_LOW_THRESHOLD values for sensor response. level by setting POS_THRESHOLD_ SENSITIVITY = 1000. Figure 37 also provides a similar example for the negative thre- The AD7147A tracks the average maximum and minimum shold level, with NEG_THRESHOLD_SENSITIVITY = 0011. values measured from each sensor. These values provide an indication of how the user is interacting with the sensor. A large AVERAGE MAXIMUM VALUE 95.32% STAGEx_OFFSET_HIGH IS UPDATED AVERAGE MAXIMUM VALUE 62.51% = A POS_THRESHOLD STAGEx_OFFSET_HIGH _SENSITIVITY 95.32% STAGEx_OFFSET_HIGH IS UPDATED 62.51% = 25% POS_THRESHOLD _SENSITIVITY 25% B AMBIENT LEVEL 25% NEG_THRESHOLD_SENSITIVITY = 39.08% STAGEx_OFFSET_LOW 25% IS UPDATED STAGEx_OFFSET_LOW NEG_THRESHOLD_SENSITIVITY = 39.08% 95.32% STAGEx_OFFSET_LOW IS UPDATED 95.32% SENSOR CONTACTED SENSOR CONTACTED BY LARGE FINGER BY SMALL FINGER Figure 37. Example of Threshold Sensitivity (POS_THRESHOLD_SENSITIVITY = 1000, NEG_THRESHOLD_SENSITIVITY = 0011) Rev. B | Page 25 of 68 CDC OUTPUT CODES 07727-037 AD7147A STAGEx_MAX_WORD0 STAGEx_MAX_WORD1 BANK 3 REGISTERS STAGEx_MAX_WORD2 STAGEx_MAX_WORD3 MAXIMUM STAGEx_MAX_AVG Σ-Δ 16 LEVEL 16-BIT BANK 3 REGISTERS DETECTION CDC LOGIC STAGEx_MAX_TEMP BANK 3 REGISTERS STAGEx_HIGH_THRESHOLD BANK 3 REGISTERS STAGEx_MIN_WORD0 STAGEx_MIN_WORD1 BANK 3 REGISTERS STAGEx_MIN_WORD2 STAGEx_MIN_WORD3 MINIMUM STAGEx_MIN_AVG LEVEL BANK 3 REGISTERS DETECTION LOGIC STAGEx_MIN_TEMP BANK 3 REGISTERS STAGEx_LOW_THRESHOLD BANK 3 REGISTERS Figure 38. Tracking the Minimum and Maximum Average Sensor Values Table 15. Additional Information About Environmental Calibration and Adaptive Threshold Registers Register Register/Bit Location Description NEG_THRESHOLD_SENSITIVITY Bank 2 Used in Equation 2. This value is programmed once at startup. NEG_PEAK_DETECT Bank 2 Used by internal adaptive threshold logic only. The NEG_PEAK_DETECT is set to a percentage of the difference between the ambient CDC value and the minimum average CDC value. If the output of the CDC approaches the NEG_PEAK_DETECT percentage of the minimum average, the minimum average value is updated. POS_THRESHOLD_SENSITIVITY Bank 2 Used in Equation 1. This value is programmed once at startup. POS_PEAK_DETECT Bank 2 Used by internal adaptive threshold logic only. The POS_PEAK_DETECT is set to a percentage of the difference between the ambient CDC value and the maximum average CDC value. If the output of the CDC approaches the POS_PEAK_DETECT percentage of the maximum average, the maximum average value is updated. STAGEx_OFFSET_LOW Bank 2 Used in Equation 2. An initial value (based on sensor characterization) is programmed into this register at startup. The AD7147A on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set this register to 80% of the STAGEx_OFFSET_LOW_CLAMP value. STAGEx_OFFSET_HIGH Bank 2 Used in Equation 1. An initial value (based on sensor characterization) is programmed into this register at startup. The AD7147A on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set this register to 80% of the STAGEx_OFFSET_HIGH_CLAMP value. STAGEx_OFFSET_HIGH_CLAMP Bank 2 Used by internal environmental calibration and adaptive threshold algorithms only. An initial value (based on sensor characterization) is programmed into this register at startup. The value in this register prevents a user from causing the output value of a sensor to exceed the expected nominal value. Set this register to the maximum expected sensor response or the maximum change in CDC output code. STAGEx_OFFSET_LOW_CLAMP Bank 2 Used by internal environmental calibration and adaptive threshold algorithms only. An initial value (based on sensor characterization) is programmed into this register at startup. The value in this register prevents a user from causing the output value of a sensor to exceed the expected nominal value. Set this register to the minimum expected sensor response or the minimum change in CDC output code. STAGEx_SF_AMBIENT Bank 3 Used in Equation 1 and Equation 2. This is the ambient sensor output when the sensor is not touched, as calculated using the slow FIFO. STAGEx_HIGH_THRESHOLD Bank 3 Equation 1 value. STAGEx_LOW_THRESHOLD Bank 3 Equation 2 value. Rev. B | Page 26 of 68 07727-038 AD7147A INTERRUPT OUTPUT The AD7147A has an interrupt output that triggers an interrupt SENSOR-TOUCH INTERRUPT service routine on the host processor. The INT signal is on Pin A1 The sensor-touch interrupt mode is implemented when the host and is an open-drain output. There are three types of interrupt processor requires an interrupt only when a sensor is contacted. events on the AD7147A: a CDC conversion-complete interrupt, Configuring the AD7147A into this mode results in the interrupt a sensor-touch interrupt, and a GPIO interrupt. Each interrupt being asserted when the user makes contact with the sensor and has enable and status registers. The conversion-complete and again when the user stops touching the sensor. The second sensor-touch (sensor-activation) interrupts can be enabled on interrupt is required to alert the host processor that the user is a per-conversion-stage basis. The status registers indicate what no longer contacting the sensor. type of interrupt triggered the INT pin. Status registers are cleared, The registers located at Address 0x005 and Address 0x006 are and the INT signal is reset high during a read operation. The used to enable the interrupt output for each stage. The registers signal returns high as soon as the read address has been set up. located at Address 0x008 and Address 0x009 are used to read CDC CONVERSION-COMPLETE INTERRUPT back the interrupt status for each stage. The AD7147A interrupt signal asserts low to indicate the comple- Figure 39 shows the interrupt output timing during contact with tion of a conversion stage and that new conversion result data is one of the sensors connected to STAGE0 while operating in the available in the registers. sensor-touch interrupt mode. For a low limit configuration, the The interrupt can be independently enabled for each conversion interrupt output is asserted as soon as the sensor is contacted and stage. Each conversion-stage-complete interrupt can be enabled via again after the user has stopped touching the sensor. (Note that the STAGE_COMPLETE_INT_ENABLE register (Address 0x007). the interrupt output remains low until the host processor reads This register has a bit that corresponds to each conversion stage. back the interrupt status registers located at Address 0x008 and Setting this bit to 1 enables the interrupt for that stage. Clearing this Address 0x009.) bit to 0 disables the conversion-complete interrupt for that stage. The interrupt output is asserted when there is a change in the The AD7147A interrupt should be enabled only for the last interrupt status bits. This can indicate that a user is touching the stage in a conversion sequence. For example, if there are five sensor(s) for the first time, the number of sensors being touched conversion stages, only the conversion-complete interrupt for has changed, or the user is no longer touching the sensor(s). INT STAGE4 is enabled. Therefore, asserts only when all five Reading the status bits in the interrupt status register shows the conversion stages are complete and the host can read new data current sensor activations. from all five result registers. The interrupt is cleared by reading FINGER ON SENSOR the STAGE_COMPLETE_INT_STATUS register located at 1 3 FINGER OFF SENSOR Address 0x00A. Register 0x00A is the conversion-complete interrupt status CONVERSION STAGE0 STAGE1 STAGE register. Each bit in this register corresponds to a conversion stage. If a bit is set, it means that the conversion-complete 2 4 interrupt for the corresponding stage was triggered. This SERIAL register is cleared upon a read if the underlying condition READBACK that triggered the interrupt is not present. INT OUTPUT 1 USER TOUCHING SENSOR. 2 ADDRESS 0x008 IS READ BACK TO CLEAR INTERRUPT. 3 USER STOPS TOUCHING SENSOR. 4 ADDRESS 0x008 IS READ BACK TO CLEAR INTERRUPT. Figure 39. Example of Sensor-Touch Interrupt Rev. B | Page 27 of 68 07727-039 AD7147A STAGE0 STAGE1 STAGE2 STAGE3 STAGE4 STAGE5 STAGE6 STAGE7 STAGE8 STAGE9 STAGE10 STAGE11 CONVERSIONS INT 1 23 SERIAL READS NOTES THIS IS AN EXAMPLE OF A CDC CONVERSION-COMPLETE INTERRUPT. THIS TIMING EXAMPLE SHOWS THAT THE INTERRUPT OUTPUT HAS BEEN ENABLED TO BE ASSERTED AT THE END OF A CONVERSION CYCLE FOR STAGE0, STAGE5, AND STAGE9. THE INTERRUPTS FOR ALL OTHER STAGES HAVE BEEN DISABLED. STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE5, AND STAGE9 (x = 0, 5, 9): STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0 STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0 STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 1 STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 6, 7, 8, 10, 11): STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0 STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0 STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0 SERIAL READBACK REQUIREMENTS FOR STAGE0, STAGE5, AND STAGE9 (THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT.): 1 READ THE STAGE0_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT 2 READ THE STAGE5_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT 3 READ THE STAGE9_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT Figure 40. Example of Configuring the Registers for Conversion-Complete Interrupt Setup CONVERSIONS STAGE0 STAGE1 STAGE2 STAGE3 STAGE4 STAGE5 STAGE6 STAGE7 STAGE8 STAGE9 STAGE10 STAGE11 INT 1 42 SERIAL READS NOTES THIS IS AN EXAMPLE OF A SENSOR-TOUCH INTERRUPT FOR A CASE WHERE THE LOW THRESHOLD LEVELS WERE EXCEEDED. FOR EXAMPLE, THE SENSOR CONNECTED TO STAGE0 AND STAGE9 WERE CONTACTED, AND THE LOW THRESHOLD LEVELS WERE EXCEEDED, RESULTING IN THE INTERRUPT BEING ASSERTED. THE STAGE6 INTERRUPT WAS NOT ASSERTED BECAUSE THE USER DID NOT CONTACT THE SENSOR CONNECTED TO STAGE6. STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE6, AND STAGE9 (x = 0, 6, 9): STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 1 STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0 STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0 STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE7, STAGE8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 5, 7, 8, 10, 11): STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0 STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0 STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0 SERIAL READBACK REQUIREMENTS FOR STAGE0 AND STAGE9 (THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT.): 1 READ THE STAGE0_LOW_INT_STATUS (ADDRESS 0x008) BIT 2 READ THE STAGE5_LOW_INT_STATUS (ADDRESS 0x008) BIT Figure 41. Example of Configuring the Registers for Sensor-Touch Interrupt Setup Rev. B | Page 28 of 68 07727-041 07727-040 AD7147A INT GPIO INT OUTPUT CONTROL interrupt. This bit is set to 1 when the GPIO has triggered . The bit is cleared upon reading the GPIO_INT_STATUS bit if the The INT output signal can be controlled by the GPIO pin when condition that caused the interrupt is no longer present. the GPIO is configured as an input. The GPIO is configured as The GPIO interrupt can be set to trigger on a rising edge, falling an input by setting the GPIO_SETUP bits in the interrupt enable edge, high level, or low level at the GPIO input pin. Table 16 shows register to 01. See the General-Purpose Input/Output (GPIO) how the settings of the GPIO_INPUT_CONFIG bits in the inter- section for more information on how to configure the GPIO. rupt enable (STAGE_LOW_INT_ENABLE) register affect the Enable the GPIO interrupt by setting the GPIO_INT_ENABLE INT behavior of . bit in Register 0x007 to 1, or disable the GPIO interrupt by Figure 42 to Figure 45 show how the interrupt output is cleared clearing this bit to 0. The GPIO status bit in the conversion- upon a read from the GPIO_INT_STATUS bit. complete interrupt status register reflects the status of the GPIO Table 16. GPIO Interrupt Behavior INT INT Behavior GPIO_INPUT_CONFIG GPIO Pin GPIO_INT_STATUS 00 = Negative Level Triggered 1 0 1 Not triggered 00 = Negative Level Triggered 0 1 0 Asserted while signal on GPIO pin is low 01 = Positive Edge Triggered 1 1 0 Pulses low at low-to-high GPIO transition 01 = Positive Edge Triggered 0 0 1 Not triggered 10 = Negative Edge Triggered 1 0 1 Pulses low at high-to-low GPIO transition 10 = Negative Edge Triggered 0 1 0 Not triggered 11 = Positive Level Triggered 1 1 0 Asserted while signal on GPIO pin is high 11 = Positive Level Triggered 0 0 1 Not triggered Rev. B | Page 29 of 68 AD7147A 1 1 SERIAL SERIAL READBACK READBACK GPIO INPUT HIGH WHEN REGISTER IS READ BACK GPIO INPUT LOW WHEN REGISTER IS READ BACK GPIO GPIO INPUT INPUT INT INT OUTPUT OUTPUT GPIO INPUT LOW WHEN REGISTER IS READ BACK GPIO INPUT HIGH WHEN REGISTER IS READ BACK GPIO GPIO INPUT INPUT INT INT OUTPUT OUTPUT 1 1 READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT. READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT. Figure 42. Example of INT Output Controlled by the GPIO Input INT Figure 44. Example of Output Controlled by the GPIO Input (GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 00) (GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 10) 1 1 SERIAL SERIAL READBACK READBACK GPIO INPUT HIGH WHEN REGISTER IS READ BACK GPIO INPUT LOW WHEN REGISTER IS READ BACK GPIO GPIO INPUT INPUT INT INT OUTPUT OUTPUT GPIO INPUT LOW WHEN REGISTER IS READ BACK GPIO INPUT HIGH WHEN REGISTER IS READ BACK GPIO GPIO INPUT INPUT INT INT OUTPUT OUTPUT NOTES 1 READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT. 1 READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT. Figure 43. Example of INT Output Controlled by the GPIO Input Figure 45. Example of INT Output Controlled by the GPIO Input (GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01) (GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 11) Rev. B | Page 30 of 68 07727-043 07727-042 07727-045 07727-044 AD7147A OUTPUTS AC OUTPUT When the GPIO is configured as an output, the voltage level on SHIELD the pin is set to either a low level or a high level, as defined by The AD7147A measures the capacitance between CINx and the GPIO_SETUP bits (see Table 17). ground. Any capacitance to ground on the signal path between the CINx pins and the sensor is included in the AD7147A The GPIO_INPUT_CONFIG bits in the STAGE_LOW_INT_ conversion result. ENABLE register determine the response of the AD7147A to a signal on the GPIO pin when the GPIO is configured as an To eliminate stray capacitance to ground, the ACSHIELD signal should input. The GPIO can be configured as either active high or be used to shield the connection between the sensor and CINx, active low, as well as either edge triggered or level triggered (see as shown in Figure 46. The plane around the sensors should also Table 18). be connected to AC . SHIELD Table 18. GPIO_INPUT_CONFIG Bits CIN0 AD7147A GPIO_INPUT_CONFIG GPIO Configuration CIN1 00 Triggered on negative level (active low) CIN2 CIN3 01 Triggered on positive edge (active high) AC GND SHIELD 10 Triggered on negative edge (active low) 11 Triggered on positive level (active high) When GPIO is configured as an input, it triggers the interrupt output on the AD7147A. Figure 46. AC SHIELD Table 16 lists the interrupt output behavior for each of the GPIO configuration setups. The AC output is the same signal waveform as the excitation SHIELD signal on CINx. Therefore, there is no ac current between CINx USING THE GPIO TO TURN ON/OFF AN LED and AC , and any capacitance between these pins does not SHIELD The GPIO on the AD7147A can be used to turn an LED on and affect the CINx charge transfer. off by setting the GPIO as either output high or low. Setting the Using ACSHIELD eliminates capacitance-to-ground pickup, which GPIO output high turns on the LED; setting the GPIO output means that the AD7147A can be placed up to 10 cm away from low turns off the LED. The GPIO pin connects to a transistor the sensors. This allows the AD7147A to be placed on a separate that provides the drive current for the LED. Suitable transistors PCB from that of the sensors if the connections between the include the KTC3875 from Korea Electronics Co., Ltd. (KEC). sensors and the CINx inputs are correctly shielded using V CC KTC3875 OR SIMILAR AC . SHIELD AD7147A GENERAL-PURPOSE INPUT/OUTPUT (GPIO) GPIO The AD7147A has one GPIO pin. It can be configured as an input or an output. The GPIO_SETUP Bits[13:12] in the STAGE_LOW_ INT_ENABLE register determine how the GPIO pin is configured. Figure 47. Controlling an LED Using the GPIO Table 17. GPIO_SETUP Bits GPIO_SETUP GPIO Configuration 00 GPIO disabled 01 Input 10 Output low 11 Output high Rev. B | Page 31 of 68 SENSOR PCB 07727-046 07727-047 AD7147A SERIAL INTERFACES The AD7147A is available with an SPI interface. The AD7147A-1 Bits[15:11] of the command word must be set to 11100 to 2 is available with an I C-compatible interface. Both parts are the successfully begin a bus transaction. same, with the exception of the serial interface. Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a write. SPI INTERFACE The AD7147A has a 4-wire serial peripheral interface (SPI). Bits[9:0] contain the target register address. When reading or writing to more than one register, this address indicates the The SPI has a data input pin (SDI) for inputting data to the address of the first register to be written to or read from. device, a data output pin (SDO) for reading data back from the device, and a data clock pin (SCLK) for clocking data into and Writing Data CS out of the device. A chip select pin ( ) enables or disables the Data is written to the AD7147A in 16-bit words. The first word CS serial interface. is required for correct operation of the SPI. written to the device is the command word, with the read/write Data is clocked out of the AD7147A on the negative edge of bit set to 0. The master then supplies the 16-bit input data-word SCLK and data is clocked into the device on the positive edge on the SDI line. The AD7147A clocks the data into the register of SCLK. addressed in the command word. If there is more than one word of SPI Command Word data to be clocked in, the AD7147A automatically increments the address pointer and clocks the subsequent data-word into All data transactions on the SPI bus begin with the master the next register. CS taking from high to low and sending out the command word. This indicates to the AD7147A whether the transaction is The AD7147A continues to clock in data on the SDI line until a read or a write and provides the address of the register from CS either the master finishes the write transition by pulling high which to begin the data transfer. The following bit map shows or the address pointer reaches its maximum value. The AD7147A the SPI command word. address pointer does not wrap around. When it reaches its maximum value, any data provided by the master on the SDI MSB LSB line is ignored by the AD7147A. 15 14 13 12 11 10 9:0 1 1 1 0 0 R/W Register address 16-BIT COMMAND WORD ENABLE WORD R/W REGISTER ADDRESS 16-BIT DATA CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW SDI D15 D14 D13 D2 D1 D0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t t t 2 4 5 SCLK 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 t t t 1 8 3 CS NOTES 1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR THE CONTROL WORD AND 16 BITS FOR THE DATA. 3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS) Figure 48. Single Register Write SPI Timing Rev. B | Page 32 of 68 07727-048 AD7147A 16-BIT COMMAND WORD DATA FOR STARTING DATA FOR NEXT ENABLE WORD R/W STARTING REGISTER ADDRESS REGISTER ADDRESS REGISTER ADDRESS CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW SDI D15 D14 D1 D0 D15 D14 D1 D0 D15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLK 1 23 4 56 7 8 910 11 12 13 14 15 16 17 18 31 32 33 34 47 48 49 CS NOTES 1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN). 4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB-JUSTIFIED REGISTER ADDRESS) Figure 49. Sequential Register Write SPI Timing 16-BIT COMMAND WORD ENABLE WORD R/W REGISTER ADDRESS CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW SDI XX X XX X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t t t 2 4 5 SCLK 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 t t t 1 3 8 CS t t 6 7 SDO XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 D13 D2 D1 D0 XXX 16-BIT READBACK DATA NOTES 1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE REGISTER DATA IS READ BACK ON THE SDO PIN. 4. X DENOTES DON’T CARE. 5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS) Figure 50. Single Register Readback SPI Timing The AD7147A continues to clock out data on the SDO line if Reading Data the master continues to supply the clock signal on SCLK. The A read transaction begins when the master writes the command CS read transaction finishes when the master takes high. If the word to the AD7147A with the read/write bit set to 1. The AD7147A address pointer reaches its maximum value, the master then supplies 16 clock pulses per data-word to be read, AD7147A repeatedly clocks out data from the addressed register. and the AD7147A clocks out data from the addressed register The address pointer does not wrap around. on the SDO line. The first data-word is clocked out on the first falling edge of SCLK following the command word, as shown in Figure 50. Rev. B | Page 33 of 68 07727-050 07727-049 AD7147A 16-BIT COMMAND WORD ENABLE WORD R/W REGISTER ADDRESS CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW SDI XX XX X X XX X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLK 1 23 4 56 7 8 910 11 12 13 14 15 16 17 18 31 32 33 34 47 48 49 CS SDO XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 D1 D0 D15 D14 D1 D0 D15 READBACK DATA FOR READBACK DATA FOR STARTING REGISTER ADDRESS NEXT REGISTER ADDRESS NOTES 1. MULTIPLE REGISTERS CAN BE READ BACK CONTINUOUSLY. 2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDO PIN. 4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 5. X DENOTES DON’T CARE. 6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB-JUSTIFIED REGISTER ADDRESS) Figure 51. Sequential Register Readback SPI Timing All slave peripherals connected to the serial bus respond to the 2 I C-COMPATIBLE INTERFACE start condition and shift in the next eight bits, consisting of a 2 The AD7147A-1 supports the industry standard, 2-wire I C 7-bit address (MSB first) plus an R/W bit that determines the serial interface protocol. The two wires associated with the direction of the data transfer. The peripheral whose address 2 I C timing are the SCLK and SDA inputs. The SDA is an I/O pin corresponds to the transmitted address responds by pulling the that allows both register write and register readback operations. The data line low during the ninth clock pulse. This is known as the 2 AD7147A-1 is always a slave device on the I C serial interface bus. acknowledge bit. All other devices on the bus then remain idle The AD7147A-1 has a 7-bit device address, Address 0101 1XX. while the selected device waits for data to be read from or written The lower two bits are set by tying the ADD0 and ADD1 pins to it. If the R/W bit is 0, the master writes to the slave device. If high or low. The AD7147A-1 responds when the master device the R/W bit is 1, the master reads from the slave device. sends its device address over the bus. The AD7147A-1 cannot Data is sent over the serial bus in a sequence of nine clock initiate data transfers on the bus. pulses—eight bits of data followed by an acknowledge bit from 2 Table 19. AD7147A-1 I C Device Address the slave device. Transitions on the data line must occur during 2 the low period of the clock signal and remain stable during the ADD1 ADD0 I C Address high period, because a low-to-high transition when the clock is 0 0 0101 100 high can be interpreted as a stop signal. The number of data 0 1 0101 101 bytes transmitted over the serial bus in a single read or write 1 0 0101 110 operation is limited only by what the master and slave devices 1 1 0101 111 can handle. Data Transfer When all data bytes are read or written, a stop condition is 2 established. A stop condition is defined by a low-to-high Data is transferred over the I C serial interface in 8-bit bytes. transition on SDA while SCLK remains high. If the AD7147A The master initiates a data transfer by establishing a start con- encounters a stop condition, it returns to its idle condition, and dition, defined as a high-to-low transition on the serial data the address pointer register resets to Address 0x00. line, SDA, while the serial clock line, SCLK, remains high. This indicates that an address/data stream follows. Rev. B | Page 34 of 68 07727-051 AD7147A START AD7147A-1 DEVICE ADDRESS REGISTER ADDRESS [A15:A8] REGISTER ADDRESS [A7:A0] SDA DEV DEV DEV DEV DEV DEV DEV R/W ACK A15 A14 A9 A8 ACK A7 A6 A1 A0 A6 A5 A4 A3 A2 A1 A0 t t 1 3 SCLK 1 23 4 5 678 910 11 16 17 18 19 20 25 26 t 2 STOP START REGISTER DATA [D15:D8] REGISTER DATA [D7:D0] AD7147A-1 DEVICE ADDRESS t 8 DEV DEV DEV ACK D15 D14 D9 D8 ACK D7 D6 D1 D0 ACK A6 A5 A4 t t t t 6 7 4 5 12 3 27 28 29 34 35 36 37 38 43 44 45 46 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X IS A DON’T CARE BIT. 4. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X IS A DON’T CARE BIT. 5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 2 Figure 52. Example of I C Timing for Single Register Write Operation 2 wrap around after the last address. Therefore, any data written Writing Data over the I C Bus to the AD7147A-1 after the address pointer has reached its 2 The process for writing to the AD7147A-1 over the I C bus is maximum value is discarded. shown in Figure 52 and Figure 54. The device address is sent All registers on the AD7147A-1 are 16 bits. Two consecutive over the bus, followed by the R/W bit being set to 0 and then 8-bit data bytes are combined and written to the 16-bit registers. two bytes of data that contain the 10-bit address of the internal To avoid errors, all writes to the device must contain an even data register to be written. The following bit map shows the number of data bytes. upper register address bytes. Note that Bit 7 to Bit 2 in the upper address byte are don’t care bits. The address is contained in the To finish the transaction, the master generates a stop condition 10 LSBs of the register address bytes. on SDO, or generates a repeat start condition if the master is to maintain control of the bus. MSB LSB 2 Reading Data over the I C Bus 7 6 5 4 3 2 1 0 X X X X X X Register Register To read from the AD7147A-1, the address pointer register must Address Address first be set to the address of the required internal register. The Bit 9 Bit 8 master performs a write transaction and then writes to the The following bit map shows the lower register address bytes: AD7147A-1 to set the address pointer. Next, the master outputs a repeat start condition to keep control of the bus, or if this is MSB LSB not possible, ends the write transaction with a stop condition. 7 6 5 4 3 2 1 0 W A read transaction is initiated, with the R/ bit set to 1. Reg Reg Reg Reg Reg Reg Reg Reg Add Add Add Add Add Add Add Add The AD7147A-1 supplies the upper eight bits of data from the Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 addressed register in the first readback byte, followed by the lower eight bits in the next byte. This is shown in Figure 53 and The third data byte contains the eight MSBs of the data to be Figure 54. written to the internal register. The fourth data byte contains Because the address pointer automatically increments after each the eight LSBs of data to be written to the internal register. read, the AD7147A-1 continues to output readback data until The AD7147A-1 address pointer register automatically incre- the master sends a no acknowledge and stop condition to the ments after each write. This allows the master to sequentially bus. If the address pointer reaches its maximum value and the write to all registers on the AD7147A-1 in the same write master continues to read from the part, the AD7147A-1 repeatedly transaction. However, the address pointer register does not sends data from the last register that was addressed. Rev. B | Page 35 of 68 07727-052 AD7147A START AD7147A-1 DEVICE ADDRESS REGISTER ADDRESS [A15:A8] REGISTER ADDRESS [A7:A0] SDA DEV DEV DEV DEV DEV DEV DEV R/W ACK A15 A14 A9 A8 ACK A7 A6 A1 A0 ACK A6 A5 A4 A3 A2 A1 A0 t t 1 3 SCLK 1 23 4 567 8 910 11 16 17 18 19 20 25 26 27 t 2 P AD7147A-1 DEVICE ADDRESS REGISTER DATA [D7:D0] SR t AD7147A-1 DEVICE ADDRESS 8 DEV DEV DEV DEV DEV DEV DEV ACK D7 D6 D1 D0 ACK R/W A6 A5 A1 A0 A6 A5 A4 USING t t t t 4 6 7 5 REPEATED START 34 35 36 37 38 44 45 46 12 3 28 29 30 39 AD7147A-1 DEVICE ADDRESS REGISTER DATA [D7:D0] P P S DEV DEV DEV DEV D7 D6 D1 D0 ACK ACK R/W A6 A5 A1 A0 t SEPARATE READ AND t 4 5 WRITE TRANSACTIONS 34 35 36 37 38 44 45 46 28 29 30 39 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA. 4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB Xs ARE DON'T CARE BITS. 5. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB Xs ARE DON’T CARE BITS. 6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY LOW ACK BITS. 7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION. 2 Figure 53. Example of I C Timing for Single Register Readback Operation WRITE 6-BIT DEVICE REGISTER ADDR REGISTER ADDR WRITE DATA WRITE DATA WRITE DATA WRITE DATA S P W ADDRESS [15:8] [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] READ (USING REPEATED START) 6-BIT DEVICE REGISTER ADDR REGISTER ADDR 6-BIT DEVICE READ DATA READ DATA READ DATA READ DATA P S ACK W ADDRESS HIGH BYTE LOW BYTE ADDRESS HIGH BYTE [15:8] LOW BYTE [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS) 6-BIT DEVICE REGISTER ADDR REGISTER ADDR 6-BIT DEVICE READ DATA READ DATA READ DATA READ DATA S P S ACK P W ADDRESS HIGH BYTE LOW BYTE ADDRESS HIGH BYTE [15:8] LOW BYTE [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] OUTPUT FROM MASTER S = START BIT ACK = ACKNOWLEDGE BIT P = STOP BIT ACK = NO ACKNOWLEDGE BIT OUTPUT FROM AD7147-1 SR = REPEATED START BIT 2 Figure 54. Example of Sequential I C Write and Readback Operations This allows the AD7147A to be connected directly to processors V INPUT DRIVE whose supply voltage is less than the minimum operating voltage The supply voltage for the pins (SDO, SDI, SCLK, SDA, CS, of the AD7147A without the need for external level-shifters. 2 INT, and GPIO) associated with both the I C and SPI serial The V pin can be connected to voltage supplies as low as DRIVE interfaces is supplied from the VDRIVE pin and is separate from the 1.65 V and as high as V . CC main VCC supply. Rev. B | Page 36 of 68 ACK ACK ACK ACK ACK ACK ACK ACK ACK SR R ACK ACK R ACK ACK ACK ACK ACK ACK ACK 07727-054 07727-053 AD7147A PCB DESIGN GUIDELINES CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS Table 20. Parameter Symbol Min Typ Max Unit Distance from Edge of Any Sensor to Edge of Grounded Metal Object D1 0.1 mm 1 Distance Between Sensor Edges D2 = D3 = D4 0 mm Distance Between Bottom of Sensor Board and Controller Board or Grounded D 1.0 mm 5 2 Metal Casing 1 The distance is dependent on the application and the position of the switches relative to each other and with respect to the user’s finger position and handling. Adjacent sensors with no space between them are implemented differentially. 2 The 1.0 mm specification is intended to prevent direct sensor board contact with any conductive material. This specification, however, does not guarantee an absence of EMI coupling from the controller board to the sensors. To avoid potential EMI-coupling issues, place a grounded metal shield between the capacitive sensor board and the main controller board, as shown in Figure 57. CAPACITIVE SENSOR BOARD METAL OBJECT D 5 CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING CAPACITIVE SENSOR PRINTED CIRCUIT 8-WAY Figure 56. Capacitive Sensor Board, Side View SWITCH D CAPACITIVE SENSOR BOARD 4 SLIDER D 5 GROUNDED METAL SHIELD CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING BUTTONS D 3 Figure 57. Capacitive Sensor Board with Grounded Shield D 2 WLCSP PACKAGE Nonsolder mask definer PCB fabrication is recommended to D 1 increase the reliability of the solder joint. The copper pad on the user’s PCB should be 80% of the diameter of the WLCSP ball. The solder mask opening should be 50 μm Figure 55. Capacitive Sensor Board, Top View on either side of the copper pad. See the AN-617 Application Note, MicroCSP™ Wafer Level Chip Scale Package, for more information and layout guidelines for the WLCSP package. Rev. B | Page 37 of 68 07727-055 07727-057 07727-056 AD7147A POWER-UP SEQUENCE To power up the AD7147A, use the following sequence when Address 0x004 = 832 initially developing the AD7147A and microprocessor serial Address 0x005 = interrupt enable register (depends on interface: required interrupt behavior) Address 0x006 = interrupt enable register (depends on 1. Turn on the power supplies to the AD7147A. required interrupt behavior) 2. Write to the Bank 2 registers at Address 0x080 through Address 0x007 = interrupt enable register (depends on Address 0x0DF. These registers are contiguous; therefore, a required interrupt behavior) sequential register write sequence can be applied. 4. Write to the Bank 1 register, Address 0x001 = 0x0FFF Note that the Bank 2 register values are unique for each (depends on number of conversion stages used). application. Register values come from characterization of 5. Read back the corresponding interrupt status register at the sensor in the application. The characterization process Address 0x008, Address 0x009, or Address 0x00A. This is is outlined in the AN-929 Application Note, available from determined by the interrupt output configuration, as Analog Devices. explained in the Interrupt Output section. 3. Write to the Bank 1 registers at Address 0x000 through Note that the specific registers required to be read back Address 0x007, outlined as follows. These registers are depend on each application. For buttons, the interrupt contiguous; therefore, a sequential register write sequence status registers are read back while other sensors read data can be applied (see Figure 49 and Figure 54). back from the AD7147A according to the slider or wheel Caution: At this time, Address 0x001 must remain set algorithm requirements. Analog Devices can provide this to a default value of 0x0000 during this contiguous write information after the user develops the sensor board. operation. 6. Repeat Step 5 every time INT is asserted. Register values: Address 0x000 = 0x82B2 Address 0x001 = 0x000 Address 0x002 = 0x3230 (depends on number of conversion stages used) Address 0x003 = 0x419 POWER HOST SERIAL INTERFACE CONVERSION 1 2 3 4 5 678 9 10 11 0 1 2 9 10 11 012 910 11 0 1 CONVERSION STAGES DISABLED 0 STAGE AD7147A INT SECOND CONVERSION THIRD CONVERSION FIRST CONVERSION SEQUENCE SEQUENCE SEQUENCE Figure 58. Recommended Start-Up Sequence Rev. B | Page 38 of 68 07727-058 AD7147A TYPICAL APPLICATION CIRCUITS V DRIVE 2.2kΩ HOST WITH SPI INTERFACE INT GPIO CIN1 CIN3 CIN5 INT A1 A2 A3 A4 A5 TP SS CS CIN2 CIN6 CIN7 B1 B2 B3 B4 B5 BUTTON BUTTON SCK SCLK V CIN4 CIN8 CIN9 DRIVE MOSI SCROLL C1 C2 C3 C4 C5 WHEEL MISO SDI V CIN0 CIN10 CIN11 CC V BUTTON HOST D1 D2 D3 D4 D5 SDO GND BIAS AC CIN12 SHIELD 1.8V E1 E2 E3 E4 E5 BUTTON AD7147A SENSOR PCB V 2.7V TO 3.6V CC 1μFTO 10μF 100nF PLANE AROUND SENSORS (OPTIONAL) CONNECTED TO AC SHIELD Figure 59. Typical Application Circuit with SPI Interface V DRIVE V DRIVE V DRIVE 2.2kΩ 2.2kΩ 2 HOST WITH I C INTERFACE 2.2kΩ INT GPIO CIN1 CIN3 CIN5 BUTTON INT A1 A2 A3 A4 A5 TP ADD1 CIN2 CIN6 CIN7 BUTTON B1 B2 B3 B4 B5 SCK SCLK V CIN4 CIN8 CIN9 DRIVE C1 C2 C3 C4 C5 BUTTON SDO ADD0 V CIN0 CIN10 CIN11 CC D1 D2 D3 D4 D5 2-WAY SWITCH SDA GND BIAS AC CIN12 SHIELD E1 E2 E3 E4 E5 AD7147A-1 V 2.7V TO 3.6V CC 1μFTO10μF PLANE AROUND SENSORS 100nF (OPTIONAL) CONNECTED TO AC SHIELD 2 Figure 60. Typical Application Circuit with I C Interface Rev. B | Page 39 of 68 SLIDER 07727-059 07727-060 AD7147A REGISTER MAP The AD7147A address space is divided into three register Bank 3 registers contain the results of each conversion stage. banks, referred to as Bank 1, Bank 2, and Bank 3. Figure 61 These registers automatically update at the end of each conversion illustrates the division of these banks. sequence. Although these registers are primarily used by the AD7147A internal data processing, they are accessible by the Bank 1 registers contain control registers, CDC conversion host processor for additional external data processing, if control registers, interrupt enable registers, interrupt status desired. registers, CDC 16-bit conversion data registers, device ID registers, and proximity status registers. Default values are undefined for Bank 2 registers and Bank 3 registers until after power-up and configuration of the Bank 2 Bank 2 registers contain the configuration registers used to registers. configure the individual CINx inputs for each conversion stage. Initialize the Bank 2 configuration registers immediately after power-up to obtain valid CDC conversion result data. BANK 1 REGISTERS BANK 2 REGISTERS BANK 3 REGISTERS ADDR 0x000 ADDR 0x080 ADDR 0x0E0 STAGE0 CONFIGURATION STAGE0 RESULTS SETUP CONTROL (8 REGISTERS) (36 REGISTERS) (1 REGISTER) ADDR 0x088 ADDR 0x104 ADDR 0x001 STAGE1 CONFIGURATION STAGE1 RESULTS (8 REGISTERS) (36 REGISTERS) CALIBRATION AND SETUP ADDR 0x090 ADDR 0x128 (4 REGISTERS) STAGE2 CONFIGURATION STAGE2 RESULTS (8 REGISTERS) (36 REGISTERS) ADDR 0x005 ADDR 0x098 ADDR 0x14C STAGE3 CONFIGURATION STAGE3 RESULTS INTERRUPT ENABLE (8 REGISTERS) (36 REGISTERS) (3 REGISTERS) ADDR 0x0A0 ADDR 0x170 STAGE4 CONFIGURATION STAGE4 RESULTS ADDR 0x008 (8 REGISTERS) (36 REGISTERS) INTERRUPT STATUS ADDR 0x194 ADDR 0x0A8 (3 REGISTERS) STAGE5 CONFIGURATION STAGE5 RESULTS (8 REGISTERS) (36 REGISTERS) ADDR 0x00B ADDR 0x0B0 ADDR 0x1B8 CDC 16-BIT CONVERSION DATA STAGE6 RESULTS STAGE6 CONFIGURATION (12 REGISTERS) (8 REGISTERS) (36 REGISTERS) ADDR 0x017 ADDR 0x0B8 ADDR 0x1DC STAGE7 CONFIGURATION STAGE7 RESULTS DEVICE ID REGISTER (8 REGISTERS) (36 REGISTERS) (1 REGISTER) ADDR 0x0C0 ADDR 0x200 ADDR 0x018 STAGE8 CONFIGURATION STAGE8 RESULTS INVALID DO NOT ACCESS (8 REGISTERS) (36 REGISTERS) ADDR 0x042 ADDR 0x0C8 ADDR 0x224 PROXIMITY STATUS REGISTER STAGE9 CONFIGURATION STAGE9 RESULTS (1 REGISTER) (8 REGISTERS) (36 REGISTERS) ADDR 0x0D0 ADDR 0x248 ADDR 0x043 STAGE10 CONFIGURATION STAGE10 RESULTS (8 REGISTERS) (36 REGISTERS) ADDR 0x0D8 ADDR 0x26C INVALID DO NOT ACCESS STAGE11 CONFIGURATION STAGE11 RESULTS (8 REGISTERS) (36 REGISTERS) ADDR 0x7F0 Figure 61. Layout of Bank 1, Bank 2, and Bank 3 Registers Rev. B | Page 40 of 68 26 REGISTERS 96 REGISTERS 432 REGISTERS 07727-061 AD7147A DETAILED REGISTER DESCRIPTIONS BANK 1 REGISTERS All addresses and default values are expressed in hexadecimal. Table 21. PWR_CONTROL Register Default Address Data Bit Value Type Name Description 0x000 [1:0] 0 R/W POWER_MODE Operating modes 00 = full power mode (normal operation, CDC conversions approximately every 36 ms) 01 = full shutdown mode (no CDC conversions) 10 = low power mode (automatic wake-up operation) 11 = full shutdown mode (no CDC conversions) [3:2] 0 R/W LP_CONV_DELAY Low power mode conversion delay 00 = 200 ms 01 = 400 ms 10 = 600 ms 11 = 800 ms [7:4] 0 R/W SEQUENCE_STAGE_NUM Number of stages in sequence (N + 1) 0000 = 1 conversion stage in sequence 0001 = 2 conversion stages in sequence … Maximum value = 1011 = 12 conversion stages per sequence [9:8] 0 R/W DECIMATION ADC decimation factor 00 = decimate by 256 01 = decimate by 128 10 = decimate by 64 11 = decimate by 64 [10] 0 R/W SW_RESET Software reset control (self-clearing) 1 = resets all registers to default values [11] 0 R/W INT_POL Interrupt polarity control 0 = active low 1 = active high [12] 0 R/W EXT_SOURCE Excitation source control 0 = enable excitation source to CINx pins 1 = disable excitation source to CINx pins [13] 0 Unused Set to 0 [15:14] 0 R/W CDC_BIAS CDC bias current control 00 = normal operation 01 = normal operation + 20% 10 = normal operation + 35% 11 = normal operation + 50% Rev. B | Page 41 of 68 AD7147A Table 22. STAGE_CAL_EN Register Default Address Data Bit Value Type Name Description 0x001 [0] 0 R/W STAGE0_CAL_EN STAGE0 calibration enable 0 = disable 1 = enable [1] 0 R/W STAGE1_CAL_EN STAGE1 calibration enable 0 = disable 1 = enable [2] 0 R/W STAGE2_CAL_EN STAGE2 calibration enable 0 = disable 1 = enable [3] 0 R/W STAGE3_CAL_EN STAGE3 calibration enable 0 = disable 1 = enable [4] 0 R/W STAGE4_CAL_EN STAGE4 calibration enable 0 = disable 1 = enable [5] 0 R/W STAGE5_CAL_EN STAGE5 calibration enable 0 = disable 1 = enable [6] 0 R/W STAGE6_CAL_EN STAGE6 calibration enable 0 = disable 1 = enable [7] 0 R/W STAGE7_CAL_EN STAGE7 calibration enable 0 = disable 1 = enable [8] 0 R/W STAGE8_CAL_EN STAGE8 calibration enable 0 = disable 1 = enable [9] 0 R/W STAGE9_CAL_EN STAGE9 calibration enable 0 = disable 1 = enable [10] 0 R/W STAGE10_CAL_EN STAGE10 calibration enable 0 = disable 1 = enable [11] 0 R/W STAGE11_CAL_EN STAGE11 calibration enable 0 = disable 1 = enable [13:12] 0 R/W AVG_FP_SKIP Full power mode skip control 00 = skip three samples 01 = skip seven samples 10 = skip 15 samples 11 = skip 31 samples [15:14] 0 R/W AVG_LP_SKIP Low power mode skip control 00 = use all samples 01 = skip one sample 10 = skip two samples 11 = skip three samples Rev. B | Page 42 of 68 AD7147A Table 23. AMB_COMP_CTRL0 Register Default Address Data Bit Value Type Name Description 0x002 [3:0] 0 R/W FF_SKIP_CNT Fast filter skip control (N + 1) 0000 = no sequence of results is skipped 0001 = one sequence of results is skipped for every one allowed into fast FIFO 0010 = two sequences of results are skipped for every one allowed into fast FIFO 1011 = maximum value = 12 sequences of results are skipped for every one allowed into fast FIFO [7:4] F R/W FP_PROXIMITY_CNT Calibration disable period in full power mode = FP_PROXIMITY_CNT × 16 × time for one conversion sequence in full power mode [11:8] F R/W LP_PROXIMITY_CNT Calibration disable period in low power mode = LP_PROXIMITY_CNT × 4 × time for one conversion sequence in low power mode [13:12] 0 R/W PWR_DOWN_TIMEOUT Full power to low power mode timeout control 00 = 1.25 × (FP_PROXIMITY_CNT) 01 = 1.50 × (FP_PROXIMITY_CNT) 10 = 1.75 × (FP_PROXIMITY_CNT) 11 = 2.00 × (FP_PROXIMITY_CNT) [14] 0 R/W FORCED_CAL Forced calibration control 0 = normal operation 1 = forces all conversion stages to recalibrate [15] 0 R/W CONV_RESET Conversion reset control (self-clearing) 0 = normal operation 1 = resets the conversion sequence to STAGE0 Table 24. AMB_COMP_CTRL1 Register Default Address Data Bit Value Type Name Description 0x003 [7:0] 64 R/W PROXIMITY_RECAL_LVL Proximity recalibration level. Value is multiplied by 16 to determine actual recalibration level. [13:8] 1 R/W PROXIMITY_DETECTION_RATE Proximity detection rate. Value is multiplied by 16 to determine actual detection rate. [15:14] 0 R/W SLOW_FILTER_UPDATE_LVL Slow filter update level. Table 25. AMB_COMP_CTRL2 Register Default Address Data Bit Value Type Name Description 0x004 [9:0] 3FF R/W FP_PROXIMITY_RECAL Full power mode proximity recalibration time control [15:10] 3F R/W LP_PROXIMITY_RECAL Low power mode proximity recalibration time control Rev. B | Page 43 of 68 AD7147A Table 26. STAGE_LOW_INT_ENABLE Register Default Address Data Bit Value Type Name Description 0x005 [0] 0 R/W STAGE0_LOW_INT_ENABLE STAGE0 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded [1] 0 R/W STAGE1_LOW_INT_ENABLE STAGE1 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE1 low threshold is exceeded [2] 0 R/W STAGE2_LOW_INT_ENABLE STAGE2 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE2 low threshold is exceeded [3] 0 R/W STAGE3_LOW_INT_ENABLE STAGE3 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE3 low threshold is exceeded [4] 0 R/W STAGE4_LOW_INT_ENABLE STAGE4 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE4 low threshold is exceeded [5] 0 R/W STAGE5_LOW_INT_ENABLE STAGE5 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE5 low threshold is exceeded [6] 0 R/W STAGE6_LOW_INT_ENABLE STAGE6 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE6 low threshold is exceeded [7] 0 R/W STAGE7_LOW_INT_ENABLE STAGE7 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE7 low threshold is exceeded [8] 0 R/W STAGE8_LOW_INT_ENABLE STAGE8 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE8 low threshold is exceeded [9] 0 R/W STAGE9_LOW_INT_ENABLE STAGE9 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE9 low threshold is exceeded [10] 0 R/W STAGE10_LOW_INT_ENABLE STAGE10 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE10 low threshold is exceeded [11] 0 R/W STAGE11_LOW_INT_ENABLE STAGE11 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE11 low threshold is exceeded [13:12] 0 R/W GPIO_SETUP GPIO setup 00 = disable GPIO pin 01 = configure GPIO as an input 10 = configure GPIO as an active low output 11 = configure GPIO as an active high output [15:14] 0 R/W GPIO_INPUT_CONFIG GPIO input configuration 00 = triggered on negative level 01 = triggered on positive edge 10 = triggered on negative edge 11 = triggered on positive level Rev. B | Page 44 of 68 AD7147A Table 27. STAGE_HIGH_INT_ENABLE Register Default Address Data Bit Value Type Name Description 0x006 [0] 0 R/W STAGE0_HIGH_INT_ENABLE STAGE0 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded [1] 0 R/W STAGE1_HIGH_INT_ENABLE STAGE1 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE1 high threshold is exceeded [2] 0 R/W STAGE2_HIGH_INT_ENABLE STAGE2 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE2 high threshold is exceeded [3] 0 R/W STAGE3_HIGH_INT_ENABLE STAGE3 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE3 high threshold is exceeded [4] 0 R/W STAGE4_HIGH_INT_ENABLE STAGE4 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE4 high threshold is exceeded [5] 0 R/W STAGE5_HIGH_INT_ENABLE STAGE5 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE5 high threshold is exceeded [6] 0 R/W STAGE6_HIGH_INT_ENABLE STAGE6 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE6 high threshold is exceeded [7] 0 R/W STAGE7_HIGH_INT_ENABLE STAGE7 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE7 high threshold is exceeded [8] 0 R/W STAGE8_HIGH_INT_ENABLE STAGE8 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE8 high threshold is exceeded [9] 0 R/W STAGE9_HIGH_INT_ENABLE STAGE9 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE9 high threshold is exceeded [10] 0 R/W STAGE10_HIGH_INT_ENABLE STAGE10 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE10 high threshold is exceeded [11] 0 R/W STAGE11_HIGH_INT_ENABLE STAGE11 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE11 high threshold is exceeded [15:12] Unused Set to 0 Rev. B | Page 45 of 68 AD7147A Table 28. STAGE_COMPLETE_INT_ENABLE Register Default Address Data Bit Value Type Name Description 0x007 [0] 0 R/W STAGE0_COMPLETE_INT_ENABLE STAGE0 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE0 conversion [1] 0 R/W STAGE1_COMPLETE_INT_ENABLE STAGE1 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE1 conversion [2] 0 R/W STAGE2_COMPLETE_INT_ENABLE STAGE2 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE2 conversion [3] 0 R/W STAGE3_COMPLETE_INT_ENABLE STAGE3 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE3 conversion [4] 0 R/W STAGE4_COMPLETE_INT_ENABLE STAGE4 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE4 conversion [5] 0 R/W STAGE5_COMPLETE_INT_ENABLE STAGE5 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE5 conversion [6] 0 R/W STAGE6_COMPLETE_INT_ENABLE STAGE6 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE6 conversion [7] 0 R/W STAGE7_COMPLETE_INT_ENABLE STAGE7 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE7 conversion [8] 0 R/W STAGE8_COMPLETE_INT_ENABLE STAGE8 conversion complete interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE8 conversion [9] 0 R/W STAGE9_COMPLETE_INT_ENABLE STAGE9 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE9 conversion [10] 0 R/W STAGE10_COMPLETE_INT_ENABLE STAGE10 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE10 conversion [11] 0 R/W STAGE11_COMPLETE_INT_ENABLE STAGE11 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE11 conversion [12] 0 R/W GPIO_INT_ENABLE Interrupt control when GPIO input pin changes level 0 = disabled 1 = enabled [15:13] Unused Set to 0 Rev. B | Page 46 of 68 AD7147A 1 Table 29. STAGE_LOW_INT_STATUS Register Default Address Data Bit Value Type Name Description 0x008 [0] 0 R STAGE0_LOW_INT_STATUS STAGE0 CDC conversion low limit interrupt result 1 = indicates STAGE0_LOW_THRESHOLD value was exceeded [1] 0 R STAGE1_LOW_INT_STATUS STAGE1 CDC conversion low limit interrupt result 1 = indicates STAGE1_LOW_THRESHOLD value was exceeded [2] 0 R STAGE2_LOW_INT_STATUS STAGE2 CDC conversion low limit interrupt result 1 = indicates STAGE2_LOW_THRESHOLD value was exceeded [3] 0 R STAGE3_LOW_INT_STATUS STAGE3 CDC conversion low limit interrupt result 1 = indicates STAGE3_LOW_THRESHOLD value was exceeded [4] 0 R STAGE4_LOW_INT_STATUS STAGE4 CDC conversion low limit interrupt result 1 = indicates STAGE4_LOW_THRESHOLD value was exceeded [5] 0 R STAGE5_LOW_INT_STATUS STAGE5 CDC conversion low limit interrupt result 1 = indicates STAGE5_LOW_THRESHOLD value was exceeded [6] 0 R STAGE6_LOW_INT_STATUS STAGE6 CDC conversion low limit interrupt result 1 = indicates STAGE6_LOW_THRESHOLD value was exceeded [7] 0 R STAGE7_LOW_INT_STATUS STAGE7 CDC conversion low limit interrupt result 1 = indicates STAGE7_LOW_THRESHOLD value was exceeded [8] 0 R STAGE8_LOW_INT_STATUS STAGE8 CDC conversion low limit interrupt result 1 = indicates STAGE8_LOW_THRESHOLD value was exceeded [9] 0 R STAGE9_LOW_INT_STATUS STAGE9 CDC conversion low limit interrupt result 1 = indicates STAGE9_LOW_THRESHOLD value was exceeded [10] 0 R STAGE10_LOW_INT_STATUS STAGE10 CDC conversion low limit interrupt result 1 = indicates STAGE10_LOW_THRESHOLD value was exceeded [11] 0 R STAGE11_LOW_INT_STATUS STAGE11 CDC conversion low limit interrupt result 1 = indicates STAGE11_LOW_THRESHOLD value was exceeded [15:12] Unused Set to 0 1 Registers self-clear to 0 after readback if the limits are not exceeded. Rev. B | Page 47 of 68 AD7147A 1 Table 30. STAGE_HIGH_INT_STATUS Register Default Address Data Bit Value Type Name Description 0x009 [0] 0 R STAGE0_HIGH_INT_STATUS STAGE0 CDC conversion high limit interrupt result 1 = indicates STAGE0_HIGH_THRESHOLD value was exceeded [1] 0 R STAGE1_HIGH_INT_STATUS STAGE1 CDC conversion high limit interrupt result 1 = indicates STAGE1_HIGH_THRESHOLD value was exceeded [2] 0 R STAGE2_HIGH_INT_STATUS STAGE2 CDC conversion high limit interrupt result 1 = indicates STAGE2_HIGH_THRESHOLD value was exceeded [3] 0 R STAGE3_HIGH_INT_STATUS STAGE3 CDC conversion high limit interrupt result 1 = indicates STAGE3_HIGH_THRESHOLD value was exceeded [4] 0 R STAGE4_HIGH_INT_STATUS STAGE4 CDC conversion high limit interrupt result 1 = indicates STAGE4_HIGH_THRESHOLD value was exceeded [5] 0 R STAGE5_HIGH_INT_STATUS STAGE5 CDC conversion high limit interrupt result 1 = indicates STAGE5_HIGH_THRESHOLD value was exceeded [6] 0 R STAGE6_HIGH_INT_STATUS STAGE6 CDC conversion high limit interrupt result 1 = indicates STAGE6_HIGH_THRESHOLD value was exceeded [7] 0 R STAGE7_HIGH_INT_STATUS STAGE7 CDC conversion high limit interrupt result 1 = indicates STAGE7_HIGH_THRESHOLD value was exceeded [8] 0 R STAGE8_HIGH_INT_STATUS STAGE8 CDC conversion high limit interrupt result 1 = indicates STAGE8_HIGH_THRESHOLD value was exceeded [9] 0 R STAGE9_HIGH_INT_STATUS STAGE9 CDC conversion high limit interrupt result 1 = indicates STAGE9_HIGH_THRESHOLD value was exceeded [10] 0 R STAGE10_HIGH_INT_STATUS STAGE10 CDC conversion high limit interrupt result 1 = indicates STAGE10_HIGH_THRESHOLD value was exceeded [11] 0 R STAGE11_HIGH_INT_STATUS STAGE11 CDC conversion high limit interrupt result 1 = indicates STAGE11_HIGH_THRESHOLD value was exceeded [15:12] Unused Set to 0 1 Registers self-clear to 0 after readback if the limits are not exceeded. Rev. B | Page 48 of 68 AD7147A 1 Table 31. STAGE_COMPLETE_INT_STATUS Register Default Address Data Bit Value Type Name Description 0x00A [0] 0 R STAGE0_COMPLETE_INT_STATUS STAGE0 conversion-complete register interrupt status 1 = indicates STAGE0 conversion completed [1] 0 R STAGE1_COMPLETE_INT_STATUS STAGE1 conversion-complete register interrupt status 1 = indicates STAGE1 conversion completed [2] 0 R STAGE2_COMPLETE_INT_STATUS STAGE2 conversion-complete register interrupt status 1 = indicates STAGE2 conversion completed [3] 0 R STAGE3_COMPLETE_INT_STATUS STAGE3 conversion-complete register interrupt status 1 = indicates STAGE3 conversion completed [4] 0 R STAGE4_COMPLETE_INT_STATUS STAGE4 conversion-complete register interrupt status 1 = indicates STAGE4 conversion completed [5] 0 R STAGE5_COMPLETE_INT_STATUS STAGE5 conversion-complete register interrupt status 1 = indicates STAGE5 conversion completed [6] 0 R STAGE6_COMPLETE_INT_STATUS STAGE6 conversion-complete register interrupt status 1 = indicates STAGE6 conversion completed [7] 0 R STAGE7_COMPLETE_INT_STATUS STAGE7 conversion-complete register interrupt status 1 = indicates STAGE7 conversion completed [8] 0 R STAGE8_COMPLETE_INT_STATUS STAGE8 conversion-complete register interrupt status 1 = indicates STAGE8 conversion completed [9] 0 R STAGE9_COMPLETE_INT_STATUS STAGE9 conversion-complete register interrupt status 1 = indicates STAGE9 conversion completed [10] 0 R STAGE10_COMPLETE_INT_STATUS STAGE10 conversion-complete register interrupt status 1 = indicates STAGE10 conversion completed [11] 0 R STAGE11_COMPLETE_INT_STATUS STAGE11 conversion-complete register interrupt status 1 = indicates STAGE11 conversion completed [12] 0 R GPIO_INT_STATUS GPIO input pin status 1 = indicates level on GPIO pin has changed [15:13] Unused Set to 0 1 Registers self-clear to 0 after readback if the limits are not exceeded. Table 32. CDC 16-Bit Conversion Data Registers Default Address Data Bit Value Type Name Description 0x00B [15:0] 0 R CDC_RESULT_S0 STAGE0 CDC 16-bit conversion data 0x00C [15:0] 0 R CDC_RESULT_S1 STAGE1 CDC 16-bit conversion data 0x00D [15:0] 0 R CDC_RESULT_S2 STAGE2 CDC 16-bit conversion data 0x00E [15:0] 0 R CDC_RESULT_S3 STAGE3 CDC 16-bit conversion data 0x00F [15:0] 0 R CDC_RESULT_S4 STAGE4 CDC 16-bit conversion data 0x010 [15:0] 0 R CDC_RESULT_S5 STAGE5 CDC 16-bit conversion data 0x011 [15:0] 0 R CDC_RESULT_S6 STAGE6 CDC 16-bit conversion data 0x012 [15:0] 0 R CDC_RESULT_S7 STAGE7 CDC 16-bit conversion data 0x013 [15:0] 0 R CDC_RESULT_S8 STAGE8 CDC 16-bit conversion data 0x014 [15:0] 0 R CDC_RESULT_S9 STAGE9 CDC 16-bit conversion data 0x015 [15:0] 0 R CDC_RESULT_S10 STAGE10 CDC 16-bit conversion data 0x016 [15:0] 0 R CDC_RESULT_S11 STAGE11 CDC 16-bit conversion data Rev. B | Page 49 of 68 AD7147A Table 33. Device ID Register Default Address Data Bit Value Type Name Description 0x017 [3:0] 0 R REVISION_CODE Revision code [15:4] 147 R DEVID Device ID = 0001 0100 0111 Table 34. Proximity Status Register Default Address Data Bit Value Type Name Description 0x042 [0] 0 R STAGE0_PROXIMITY_STATUS STAGE0 proximity status register 1 = indicates proximity has been detected on STAGE0 [1] 0 R STAGE1_PROXIMITY_STATUS STAGE1 proximity status register 1 = indicates proximity has been detected on STAGE1 [2] 0 R STAGE2_PROXIMITY_STATUS STAGE2 proximity status register 1 = indicates proximity has been detected on STAGE2 [3] 0 R STAGE3_PROXIMITY_STATUS STAGE3 proximity status register 1 = indicates proximity has been detected on STAGE3 [4] 0 R STAGE4_PROXIMITY_STATUS STAGE4 proximity status register 1 = indicates proximity has been detected on STAGE4 [5] 0 R STAGE5_PROXIMITY_STATUS STAGE5 proximity status register 1 = indicates proximity has been detected on STAGE5 [6] 0 R STAGE6_PROXIMITY_STATUS STAGE6 proximity status register 1 = indicates proximity has been detected on STAGE6 [7] 0 R STAGE7_PROXIMITY_STATUS STAGE7 proximity status register 1 = indicates proximity has been detected on STAGE7 [8] 0 R STAGE8_PROXIMITY_STATUS STAGE8 proximity status register 1 = indicates proximity has been detected on STAGE8 [9] 0 R STAGE9_PROXIMITY_STATUS STAGE9 proximity status register 1 = indicates proximity has been detected on STAGE9 [10] 0 R STAGE10_PROXIMITY_STATUS STAGE10 proximity status register 1 = indicates proximity has been detected on STAGE10 [11] 0 R STAGE11_PROXIMITY_STATUS STAGE11 proximity status register 1 = indicates proximity has been detected on STAGE11 [15:12] Unused Set to 0 Rev. B | Page 50 of 68 AD7147A BANK 2 REGISTERS All address values are expressed in hexadecimal. Table 35. STAGEx_CONNECTION[6:0] Register Description (x = 0 to 11) Default 1 Data Bit Value Type Name Description [1:0] X R/W CIN0_CONNECTION_SETUP CIN0 connection setup 00 = CIN0 not connected to CDC inputs 01 = CIN0 connected to CDC negative input 10 = CIN0 connected to CDC positive input 11 = CIN0 connected to BIAS (connect unused CINx inputs) [3:2] X R/W CIN1_CONNECTION_SETUP CIN1 connection setup 00 = CIN1 not connected to CDC inputs 01 = CIN1 connected to CDC negative input 10 = CIN1 connected to CDC positive input 11 = CIN1 connected to BIAS (connect unused CINx inputs) [5:4] X R/W CIN2_CONNECTION_SETUP CIN2 connection setup 00 = CIN2 not connected to CDC inputs 01 = CIN2 connected to CDC negative input 10 = CIN2 connected to CDC positive input 11 = CIN2 connected to BIAS (connect unused CINx inputs) [7:6] X R/W CIN3_CONNECTION_SETUP CIN3 connection setup 00 = CIN3 not connected to CDC inputs 01 = CIN3 connected to CDC negative input 10 = CIN3 connected to CDC positive input 11 = CIN3 connected to BIAS (connect unused CINx inputs) [9:8] X R/W CIN4_CONNECTION_SETUP CIN4 connection setup 00 = CIN4 not connected to CDC inputs 01 = CIN4 connected to CDC negative input 10 = CIN4 connected to CDC positive input 11 = CIN4 connected to BIAS (connect unused CINx inputs) [11:10] X R/W CIN5_CONNECTION_SETUP CIN5 connection setup 00 = CIN5 not connected to CDC inputs 01 = CIN5 connected to CDC negative input 10 = CIN5 connected to CDC positive input 11 = CIN5 connected to BIAS (connect unused CINx inputs) [13:12] X R/W CIN6_CONNECTION_SETUP CIN6 connection setup 00 = CIN6 not connected to CDC inputs 01 = CIN6 connected to CDC negative input 10 = CIN6 connected to CDC positive input 11 = CIN6 connected to BIAS (connect unused CINx inputs) [15:14] X Unused Set to 0 1 X = don’t care. Rev. B | Page 51 of 68 AD7147A Table 36. STAGEx_CONNECTION[12:7] Register Description (x = 0 to 11) Default 1 Data Bit Value Type Name Description [1:0] X R/W CIN7_CONNECTION_SETUP CIN7 connection setup 00 = CIN7 not connected to CDC inputs 01 = CIN7 connected to CDC negative input 10 = CIN7 connected to CDC positive input 11 = CIN7 connected to BIAS (connect unused CINx inputs) [3:2] X R/W CIN8_CONNECTION_SETUP CIN8 connection setup 00 = CIN8 not connected to CDC inputs 01 = CIN8 connected to CDC negative input 10 = CIN8 connected to CDC positive input 11 = CIN8 connected to BIAS (connect unused CINx inputs) [5:4] X R/W CIN9_CONNECTION_SETUP CIN9 connection setup 00 = CIN9 not connected to CDC inputs 01 = CIN9 connected to CDC negative input 10 = CIN9 connected to CDC positive input 11 = CIN9 connected to BIAS (connect unused CINx inputs) [7:6] X R/W CIN10_CONNECTION_SETUP CIN10 connection setup 00 = CIN10 not connected to CDC inputs 01 = CIN10 connected to CDC negative input 10 = CIN10 connected to CDC positive input 11 = CIN10 connected to BIAS (connect unused CINx inputs) [9:8] X R/W CIN11_CONNECTION_SETUP CIN11 connection setup 00 = CIN11 not connected to CDC inputs 01 = CIN11 connected to CDC negative input 10 = CIN11 connected to CDC positive input 11 = CIN11 connected to BIAS (connect unused CINx inputs) [11:10] X R/W CIN12_CONNECTION_SETUP CIN12 connection setup 00 = CIN12 not connected to CDC inputs 01 = CIN12 connected to CDC negative input 10 = CIN12 connected to CDC positive input 11 = CIN12 connected to BIAS (connect unused CINx inputs) [13:12] X R/W SE_CONNECTION_SETUP Single-ended measurement connection setup 00 = Do not use 01 = Use when one CINx is connected to CDC positive input, single-ended measurements only 10 = Use when one CINx is connected to CDC negative input, single-ended measurements only 11 = Differential connection to CDC [14] X R/W NEG_AFE_OFFSET_DISABLE Negative AFE offset enable control 0 = enable 1 = disable [15] X R/W POS_AFE_OFFSET_DISABLE Positive AFE offset enable control 0 = enable 1 = disable 1 X = don’t care. Rev. B | Page 52 of 68 AD7147A Table 37. STAGEx_AFE_OFFSET Register Description (x = 0 to 11) Default 1 Data Bit Value Type Name Description [5:0] X R/W NEG_AFE_OFFSET Negative AFE offset setting (20 pF range) 1 LSB value = 0.32 pF of offset [6] X Unused Set to 0 [7] X R/W NEG_AFE_OFFSET_SWAP Negative AFE offset swap control 0 = NEG_AFE_OFFSET applied to CDC negative input 1 = NEG_AFE_OFFSET applied to CDC positive input [13:8] X R/W POS_AFE_OFFSET Positive AFE offset setting (20 pF range) 1 LSB value = 0.32 pF of offset [14] X Unused Set to 0 [15] X R/W POS_AFE_OFFSET_SWAP Positive AFE offset swap control 0 = POS_AFE_OFFSET applied to CDC positive input 1 = POS_AFE_OFFSET applied to CDC negative input 1 X = don’t care. Table 38. STAGEx_SENSITIVITY Register Description (x = 0 to 11) Default 1 Data Bit Value Type Name Description [3:0] X R/W NEG_THRESHOLD_SENSITIVITY Negative threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [6:4] X R/W NEG_PEAK_DETECT Negative peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [7] X R/W Unused Set to 0 [11:8] X R/W POS_THRESHOLD_SENSITIVITY Positive threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [14:12] X R/W POS_PEAK_DETECT Positive peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [15] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 53 of 68 AD7147A Table 39. STAGE0 to STAGE12 Configuration Registers 1 Address Data Bit Default Type Name Description 0x080 [15:0] X R/W STAGE0_CONNECTION[6:0] STAGE0 CIN[6:0] connection setup (see Table 35) 0x081 [15:0] X R/W STAGE0_CONNECTION[12:7] STAGE0 CIN[12:7] connection setup (see Table 36) 0x082 [15:0] X R/W STAGE0_AFE_OFFSET STAGE0 AFE offset control (see Table 37) 0x083 [15:0] X R/W STAGE0_SENSITIVITY STAGE0 sensitivity control (see Table 38) 0x084 [15:0] X R/W STAGE0_OFFSET_LOW STAGE0 initial offset low value 0x085 [15:0] X R/W STAGE0_OFFSET_HIGH STAGE0 initial offset high value 0x086 [15:0] X R/W STAGE0_OFFSET_HIGH_CLAMP STAGE0 offset high clamp value 0x087 [15:0] X R/W STAGE0_ OFFSET_LOW_CLAMP STAGE0 offset low clamp value 0x088 [15:0] X R/W STAGE1_CONNECTION[6:0] STAGE1 CIN[6:0] connection setup (see Table 35) 0x089 [15:0] X R/W STAGE1_CONNECTION[12:7] STAGE1 CIN[12:7] connection setup (see Table 36) 0x08A [15:0] X R/W STAGE1_AFE_OFFSET STAGE1 AFE offset control (see Table 37) 0x08B [15:0] X R/W STAGE1_SENSITIVITY STAGE1 sensitivity control (see Table 38) 0x08C [15:0] X R/W STAGE1_OFFSET_LOW STAGE1 initial offset low value 0x08D [15:0] X R/W STAGE1_OFFSET_HIGH STAGE1 initial offset high value 0x08E [15:0] X R/W STAGE1_OFFSET_HIGH_CLAMP STAGE1 offset high clamp value 0x08F [15:0] X R/W STAGE1_OFFSET_LOW_CLAMP STAGE1 offset low clamp value 0x090 [15:0] X R/W STAGE2_CONNECTION[6:0] STAGE2 CIN[6:0] connection setup (see Table 35) 0x091 [15:0] X R/W STAGE2_CONNECTION[12:7] STAGE2 CIN[12:7] connection setup (see Table 36) 0x092 [15:0] X R/W STAGE2_AFE_OFFSET STAGE2 AFE offset control (see Table 37) 0x093 [15:0] X R/W STAGE2_SENSITIVITY STAGE2 sensitivity control (see Table 38) 0x094 [15:0] X R/W STAGE2_OFFSET_LOW STAGE2 initial offset low value 0x095 [15:0] X R/W STAGE2_OFFSET_HIGH STAGE2 initial offset high value 0x096 [15:0] X R/W STAGE2_OFFSET_HIGH_CLAMP STAGE2 offset high clamp value 0x097 [15:0] X R/W STAGE2_OFFSET_LOW_CLAMP STAGE2 offset low clamp value 0x098 [15:0] X R/W STAGE3_CONNECTION[6:0] STAGE3 CIN[6:0] connection setup (see Table 35) 0x099 [15:0] X R/W STAGE3_CONNECTION[12:7] STAGE3 CIN[12:7] connection setup (see Table 36) 0x09A [15:0] X R/W STAGE3_AFE_OFFSET STAGE3 AFE offset control (see Table 37) 0x09B [15:0] X R/W STAGE3_SENSITIVITY STAGE3 sensitivity control (see Table 38) 0x09C [15:0] X R/W STAGE3_OFFSET_LOW STAGE3 initial offset low value 0x09D [15:0] X R/W STAGE3_OFFSET_HIGH STAGE3 initial offset high value 0x09E [15:0] X R/W STAGE3_OFFSET_HIGH_CLAMP STAGE3 offset high clamp value 0x09F [15:0] X R/W STAGE3_OFFSET_LOW_CLAMP STAGE3 offset low clamp value 0x0A0 [15:0] X R/W STAGE4_CONNECTION[6:0] STAGE4 CIN[6:0] connection setup (see Table 35) 0x0A1 [15:0] X R/W STAGE4_CONNECTION[12:7] STAGE4 CIN[12:7] connection setup (see Table 36) 0x0A2 [15:0] X R/W STAGE4_AFE_OFFSET STAGE4 AFE offset control (see Table 37) 0x0A3 [15:0] X R/W STAGE4_SENSITIVITY STAGE4 sensitivity control (see Table 38) 0x0A4 [15:0] X R/W STAGE4_OFFSET_LOW STAGE4 initial offset low value 0x0A5 [15:0] X R/W STAGE4_OFFSET_HIGH STAGE4 initial offset high value 0x0A6 [15:0] X R/W STAGE4_OFFSET_HIGH_CLAMP STAGE4 offset high clamp value 0x0A7 [15:0] X R/W STAGE4_OFFSET_LOW_CLAMP STAGE4 offset low clamp value 0x0A8 [15:0] X R/W STAGE5_CONNECTION[6:0] STAGE5 CIN[6:0] connection setup (see Table 35) 0x0A9 [15:0] X R/W STAGE5_CONNECTION[12:7] STAGE5 CIN[12:7] connection setup (see Table 36) 0x0AA [15:0] X R/W STAGE5_AFE_OFFSET STAGE5 AFE offset control (see Table 37) 0x0AB [15:0] X R/W STAGE5_SENSITIVITY STAGE5 sensitivity control (see Table 38) 0x0AC [15:0] X R/W STAGE5_OFFSET_LOW STAGE5 initial offset low value 0x0AD [15:0] X R/W STAGE5_OFFSET_HIGH STAGE5 initial offset high value 0x0AE [15:0] X R/W STAGE5_OFFSET_HIGH_CLAMP STAGE5 offset high clamp value 0x0AF [15:0] X R/W STAGE5_OFFSET_LOW_CLAMP STAGE5 offset low clamp value Rev. B | Page 54 of 68 AD7147A 1 Address Data Bit Default Type Name Description 0x0B0 [15:0] X R/W STAGE6_CONNECTION[6:0] STAGE6 CIN[6:0] connection setup (see Table 35) 0x0B1 [15:0] X R/W STAGE6_CONNECTION[12:7] STAGE6 CIN[12:7] connection setup (see Table 36) 0x0B2 [15:0] X R/W STAGE6_AFE_OFFSET STAGE6 AFE offset control (see Table 37) 0x0B3 [15:0] X R/W STAGE6_SENSITIVITY STAGE6 sensitivity control (see Table 38) 0x0B4 [15:0] X R/W STAGE6_OFFSET_LOW STAGE6 initial offset low value 0x0B5 [15:0] X R/W STAGE6_OFFSET_HIGH STAGE6 initial offset high value 0x0B6 [15:0] X R/W STAGE6_OFFSET_HIGH_CLAMP STAGE6 offset high clamp value 0x0B7 [15:0] X R/W STAGE6_OFFSET_LOW_CLAMP STAGE6 offset low clamp value 0x0B8 [15:0] X R/W STAGE7_CONNECTION[6:0] STAGE7 CIN[6:0] connection setup (see Table 35) 0x0B9 [15:0] X R/W STAGE7_CONNECTION[12:7] STAGE7 CIN[12:7] connection setup (see Table 36) 0x0BA [15:0] X R/W STAGE7_AFE_OFFSET STAGE7 AFE offset control (see Table 37) 0x0BB [15:0] X R/W STAGE7_SENSITIVITY STAGE7 sensitivity control (see Table 38) 0x0BC [15:0] X R/W STAGE7_OFFSET_LOW STAGE7 initial offset low value 0x0BD [15:0] X R/W STAGE7_OFFSET_HIGH STAGE7 initial offset high value 0x0BE [15:0] X R/W STAGE7_OFFSET_HIGH_CLAMP STAGE7 offset high clamp value 0x0BF [15:0] X R/W STAGE7_OFFSET_LOW_CLAMP STAGE7 offset low clamp value 0x0C0 [15:0] X R/W STAGE8_CONNECTION[6:0] STAGE8 CIN[6:0] connection setup (see Table 35) 0x0C1 [15:0] X R/W STAGE8_CONNECTION[12:7] STAGE8 CIN[12:7] connection setup (see Table 36) 0x0C2 [15:0] X R/W STAGE8_AFE_OFFSET STAGE8 AFE offset control (see Table 37) 0x0C3 [15:0] X R/W STAGE8_SENSITIVITY STAGE8 sensitivity control (see Table 38) 0x0C4 [15:0] X R/W STAGE8_OFFSET_LOW STAGE8 initial offset low value 0x0C5 [15:0] X R/W STAGE8_OFFSET_HIGH STAGE8 initial offset high value 0x0C6 [15:0] X R/W STAGE8_OFFSET_HIGH_CLAMP STAGE8 offset high clamp value 0x0C7 [15:0] X R/W STAGE8_OFFSET_LOW_CLAMP STAGE8 offset low clamp value 0x0C8 [15:0] X R/W STAGE9_CONNECTION[6:0] STAGE9 CIN[6:0] connection setup (see Table 35) 0x0C9 [15:0] X R/W STAGE9_CONNECTION[12:7] STAGE9 CIN[12:7] connection setup (see Table 36) 0x0CA [15:0] X R/W STAGE9_AFE_OFFSET STAGE9 AFE offset control (see Table 37) 0x0CB [15:0] X R/W STAGE9_SENSITIVITY STAGE9 sensitivity control (see Table 38) 0x0CC [15:0] X R/W STAGE9_OFFSET_LOW STAGE9 initial offset low value 0x0CD [15:0] X R/W STAGE9_OFFSET_HIGH STAGE9 initial offset high value 0x0CE [15:0] X R/W STAGE9_OFFSET_HIGH_CLAMP STAGE9 offset high clamp value 0x0CF [15:0] X R/W STAGE9_OFFSET_LOW_CLAMP STAGE9 offset low clamp value 0x0D0 [15:0] X R/W STAGE10_CONNECTION[6:0] STAGE10 CIN[6:0] connection setup (see Table 35) 0x0D1 [15:0] X R/W STAGE10_CONNECTION[12:7] STAGE10 CIN[12:7] connection setup (see Table 36) 0x0D2 [15:0] X R/W STAGE10_AFE_OFFSET STAGE10 AFE offset control (see Table 37) 0x0D3 [15:0] X R/W STAGE10_SENSITIVITY STAGE10 sensitivity control (see Table 38) 0x0D4 [15:0] X R/W STAGE10_OFFSET_LOW STAGE10 initial offset low value 0x0D5 [15:0] X R/W STAGE10_OFFSET_HIGH STAGE10 initial offset high value 0x0D6 [15:0] X R/W STAGE10_OFFSET_HIGH_CLAMP STAGE10 offset high clamp value 0x0D7 [15:0] X R/W STAGE10_OFFSET_LOW_CLAMP STAGE10 offset low clamp value 0x0D8 [15:0] X R/W STAGE11_CONNECTION[6:0] STAGE11 CIN[6:0] connection setup (see Table 35) 0x0D9 [15:0] X R/W STAGE11_CONNECTION[12:7] STAGE11 CIN[12:7] connection setup (see Table 36) 0x0DA [15:0] X R/W STAGE11_AFE_OFFSET STAGE11 AFE offset control (see Table 37) 0x0DB [15:0] X R/W STAGE11_SENSITIVITY STAGE11 sensitivity control (see Table 38) 0x0DC [15:0] X R/W STAGE11_OFFSET_LOW STAGE11 initial offset low value 0x0DD [15:0] X R/W STAGE11_OFFSET_HIGH STAGE11 initial offset high value 0x0DE [15:0] X R/W STAGE11_OFFSET_HIGH_CLAMP STAGE11 offset high clamp value 0x0DF [15:0] X R/W STAGE11_OFFSET_LOW_CLAMP STAGE11 offset low clamp value 1 X = don’t care. Rev. B | Page 55 of 68 AD7147A BANK 3 REGISTERS All address values are expressed in hexadecimal. Table 40. STAGE0 Results Registers Default 1 Address Data Bit Value Type Name Description 0x0E0 [15:0] X R/W STAGE0_CONV_DATA STAGE0 CDC 16-bit conversion data (copy of CDC_RESULT_S0 register) 0x0E1 [15:0] X R/W STAGE0_FF_WORD0 STAGE0 fast FIFO WORD0 0x0E2 [15:0] X R/W STAGE0_FF_WORD1 STAGE0 fast FIFO WORD1 0x0E3 [15:0] X R/W STAGE0_FF_WORD2 STAGE0 fast FIFO WORD2 0x0E4 [15:0] X R/W STAGE0_FF_WORD3 STAGE0 fast FIFO WORD3 0x0E5 [15:0] X R/W STAGE0_FF_WORD4 STAGE0 fast FIFO WORD4 0x0E6 [15:0] X R/W STAGE0_FF_WORD5 STAGE0 fast FIFO WORD5 0x0E7 [15:0] X R/W STAGE0_FF_WORD6 STAGE0 fast FIFO WORD6 0x0E8 [15:0] X R/W STAGE0_FF_WORD7 STAGE0 fast FIFO WORD7 0x0E9 [15:0] X R/W STAGE0_SF_WORD0 STAGE0 slow FIFO WORD0 0x0EA [15:0] X R/W STAGE0_SF_WORD1 STAGE0 slow FIFO WORD1 0x0EB [15:0] X R/W STAGE0_SF_WORD2 STAGE0 slow FIFO WORD2 0x0EC [15:0] X R/W STAGE0_SF_WORD3 STAGE0 slow FIFO WORD3 0x0ED [15:0] X R/W STAGE0_SF_WORD4 STAGE0 slow FIFO WORD4 0x0EE [15:0] X R/W STAGE0_SF_WORD5 STAGE0 slow FIFO WORD5 0x0EF [15:0] X R/W STAGE0_SF_WORD6 STAGE0 slow FIFO WORD6 0x0F0 [15:0] X R/W STAGE0_SF_WORD7 STAGE0 slow FIFO WORD7 0x0F1 [15:0] X R/W STAGE0_SF_AMBIENT STAGE0 slow FIFO ambient value 0x0F2 [15:0] X R/W STAGE0_FF_AVG STAGE0 fast FIFO average value 0x0F3 [15:0] X R/W STAGE0_PEAK_DETECT_WORD0 STAGE0 peak FIFO WORD0 value 0x0F4 [15:0] X R/W STAGE0_PEAK_DETECT_WORD1 STAGE0 peak FIFO WORD1 value 0x0F5 [15:0] X R/W STAGE0_MAX_WORD0 STAGE0 maximum value FIFO WORD0 0x0F6 [15:0] X R/W STAGE0_MAX_WORD1 STAGE0 maximum value FIFO WORD1 0x0F7 [15:0] X R/W STAGE0_MAX_WORD2 STAGE0 maximum value FIFO WORD2 0x0F8 [15:0] X R/W STAGE0_MAX_WORD3 STAGE0 maximum value FIFO WORD3 0x0F9 [15:0] X R/W STAGE0_MAX_AVG STAGE0 average maximum FIFO value 0x0FA [15:0] X R/W STAGE0_HIGH_THRESHOLD STAGE0 high threshold value 0x0FB [15:0] X R/W STAGE0_MAX_TEMP STAGE0 temporary maximum value 0x0FC [15:0] X R/W STAGE0_MIN_WORD0 STAGE0 minimum value FIFO WORD0 0x0FD [15:0] X R/W STAGE0_MIN_WORD1 STAGE0 minimum value FIFO WORD1 0x0FE [15:0] X R/W STAGE0_MIN_WORD2 STAGE0 minimum value FIFO WORD2 0x0FF [15:0] X R/W STAGE0_MIN_WORD3 STAGE0 minimum value FIFO WORD3 0x100 [15:0] X R/W STAGE0_MIN_AVG STAGE0 average minimum FIFO value 0x101 [15:0] X R/W STAGE0_LOW_THRESHOLD STAGE0 low threshold value 0x102 [15:0] X R/W STAGE0_MIN_TEMP STAGE0 temporary minimum value 0x103 [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 56 of 68 AD7147A Table 41. STAGE1 Results Registers Default 1 Address Data Bit Value Type Name Description 0x104 [15:0] X R/W STAGE1_CONV_DATA STAGE1 CDC 16-bit conversion data (copy of CDC_RESULT_S1 register 0x105 [15:0] X R/W STAGE1_FF_WORD0 STAGE1 fast FIFO WORD0 0x106 [15:0] X R/W STAGE1_FF_WORD1 STAGE1 fast FIFO WORD1 0x107 [15:0] X R/W STAGE1_FF_WORD2 STAGE1 fast FIFO WORD2 0x108 [15:0] X R/W STAGE1_FF_WORD3 STAGE1 fast FIFO WORD3 0x109 [15:0] X R/W STAGE1_FF_WORD4 STAGE1 fast FIFO WORD4 0x10A [15:0] X R/W STAGE1_FF_WORD5 STAGE1 fast FIFO WORD5 0x10B [15:0] X R/W STAGE1_FF_WORD6 STAGE1 fast FIFO WORD6 0x10C [15:0] X R/W STAGE1_FF_WORD7 STAGE1 fast FIFO WORD7 0x10D [15:0] X R/W STAGE1_SF_WORD0 STAGE1 slow FIFO WORD0 0x10E [15:0] X R/W STAGE1_SF_WORD1 STAGE1 slow FIFO WORD1 0x10F [15:0] X R/W STAGE1_SF_WORD2 STAGE1 slow FIFO WORD2 0x110 [15:0] X R/W STAGE1_SF_WORD3 STAGE1 slow FIFO WORD3 0x111 [15:0] X R/W STAGE1_SF_WORD4 STAGE1 slow FIFO WORD4 0x112 [15:0] X R/W STAGE1_SF_WORD5 STAGE1 slow FIFO WORD5 0x113 [15:0] X R/W STAGE1_SF_WORD6 STAGE1 slow FIFO WORD6 0x114 [15:0] X R/W STAGE1_SF_WORD7 STAGE1 slow FIFO WORD7 0x115 [15:0] X R/W STAGE1_SF_AMBIENT STAGE1 slow FIFO ambient value 0x116 [15:0] X R/W STAGE1_FF_AVG STAGE1 fast FIFO average value 0x117 [15:0] X R/W STAGE1_PEAK_DETECT_WORD0 STAGE1 peak FIFO WORD0 value 0x118 [15:0] X R/W STAGE1_PEAK_DETECT_WORD1 STAGE1 peak FIFO WORD1 value 0x119 [15:0] X R/W STAGE1_MAX_WORD0 STAGE1 maximum value FIFO WORD0 0x11A [15:0] X R/W STAGE1_MAX_WORD1 STAGE1 maximum value FIFO WORD1 0x11B [15:0] X R/W STAGE1_MAX_WORD2 STAGE1 maximum value FIFO WORD2 0x11C [15:0] X R/W STAGE1_MAX_WORD3 STAGE1 maximum value FIFO WORD3 0x11D [15:0] X R/W STAGE1_MAX_AVG STAGE1 average maximum FIFO value 0x11E [15:0] X R/W STAGE1_HIGH_THRESHOLD STAGE1 high threshold value 0x11F [15:0] X R/W STAGE1_MAX_TEMP STAGE1 temporary maximum value 0x120 [15:0] X R/W STAGE1_MIN_WORD0 STAGE1 minimum value FIFO WORD0 0x121 [15:0] X R/W STAGE1_MIN_WORD1 STAGE1 minimum value FIFO WORD1 0x122 [15:0] X R/W STAGE1_MIN_WORD2 STAGE1 minimum value FIFO WORD2 0x123 [15:0] X R/W STAGE1_MIN_WORD3 STAGE1 minimum value FIFO WORD3 0x124 [15:0] X R/W STAGE1_MIN_AVG STAGE1 average minimum FIFO value 0x125 [15:0] X R/W STAGE1_LOW_THRESHOLD STAGE1 low threshold value 0x126 [15:0] X R/W STAGE1_MIN_TEMP STAGE1 temporary minimum value 0x127 [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 57 of 68 AD7147A Table 42. STAGE2 Results Registers Default 1 Address Data Bit Value Type Name Description 0x128 [15:0] X R/W STAGE2_CONV_DATA STAGE2 CDC 16-bit conversion data (copy of CDC_RESULT_S2 register) 0x129 [15:0] X R/W STAGE2_FF_WORD0 STAGE2 fast FIFO WORD0 0x12A [15:0] X R/W STAGE2_FF_WORD1 STAGE2 fast FIFO WORD1 0x12B [15:0] X R/W STAGE2_FF_WORD2 STAGE2 fast FIFO WORD2 0x12C [15:0] X R/W STAGE2_FF_WORD3 STAGE2 fast FIFO WORD3 0x12D [15:0] X R/W STAGE2_FF_WORD4 STAGE2 fast FIFO WORD4 0x12E [15:0] X R/W STAGE2_FF_WORD5 STAGE2 fast FIFO WORD5 0x12F [15:0] X R/W STAGE2_FF_WORD6 STAGE2 fast FIFO WORD6 0x130 [15:0] X R/W STAGE2_FF_WORD7 STAGE2 fast FIFO WORD7 0x131 [15:0] X R/W STAGE2_SF_WORD0 STAGE2 slow FIFO WORD0 0x132 [15:0] X R/W STAGE2_SF_WORD1 STAGE2 slow FIFO WORD1 0x133 [15:0] X R/W STAGE2_SF_WORD2 STAGE2 slow FIFO WORD2 0x134 [15:0] X R/W STAGE2_SF_WORD3 STAGE2 slow FIFO WORD3 0x135 [15:0] X R/W STAGE2_SF_WORD4 STAGE2 slow FIFO WORD4 0x136 [15:0] X R/W STAGE2_SF_WORD5 STAGE2 slow FIFO WORD5 0x137 [15:0] X R/W STAGE2_SF_WORD6 STAGE2 slow FIFO WORD6 0x138 [15:0] X R/W STAGE2_SF_WORD7 STAGE2 slow FIFO WORD7 0x139 [15:0] X R/W STAGE2_SF_AMBIENT STAGE2 slow FIFO ambient value 0x13A [15:0] X R/W STAGE2_FF_AVG STAGE2 fast FIFO average value 0x13B [15:0] X R/W STAGE2_PEAK_DETECT_WORD0 STAGE2 peak FIFO WORD0 value 0x13C [15:0] X R/W STAGE2_PEAK_DETECT_WORD1 STAGE2 peak FIFO WORD1 value 0x13D [15:0] X R/W STAGE2_MAX_WORD0 STAGE2 maximum value FIFO WORD0 0x13E [15:0] X R/W STAGE2_MAX_WORD1 STAGE2 maximum value FIFO WORD1 0x13F [15:0] X R/W STAGE2_MAX_WORD2 STAGE2 maximum value FIFO WORD2 0x140 [15:0] X R/W STAGE2_MAX_WORD3 STAGE2 maximum value FIFO WORD3 0x141 [15:0] X R/W STAGE2_MAX_AVG STAGE2 average maximum FIFO value 0x142 [15:0] X R/W STAGE2_HIGH_THRESHOLD STAGE2 high threshold value 0x143 [15:0] X R/W STAGE2_MAX_TEMP STAGE2 temporary maximum value 0x144 [15:0] X R/W STAGE2_MIN_WORD0 STAGE2 minimum value FIFO WORD0 0x145 [15:0] X R/W STAGE2_MIN_WORD1 STAGE2 minimum value FIFO WORD1 0x146 [15:0] X R/W STAGE2_MIN_WORD2 STAGE2 minimum value FIFO WORD2 0x147 [15:0] X R/W STAGE2_MIN_WORD3 STAGE2 minimum value FIFO WORD3 0x148 [15:0] X R/W STAGE2_MIN_AVG STAGE2 average minimum FIFO value 0x149 [15:0] X R/W STAGE2_LOW_THRESHOLD STAGE2 low threshold value 0x14A [15:0] X R/W STAGE2_MIN_TEMP STAGE2 temporary minimum value 0x14B [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 58 of 68 AD7147A Table 43. STAGE3 Results Registers Default 1 Address Data Bit Value Type Name Description 0x14C [15:0] X R/W STAGE3_CONV_DATA STAGE3 CDC 16-bit conversion data (copy of CDC_RESULT_S3 register) 0x14D [15:0] X R/W STAGE3_FF_WORD0 STAGE3 fast FIFO WORD0 0x14E [15:0] X R/W STAGE3_FF_WORD1 STAGE3 fast FIFO WORD1 0x14F [15:0] X R/W STAGE3_FF_WORD2 STAGE3 fast FIFO WORD2 0x150 [15:0] X R/W STAGE3_FF_WORD3 STAGE3 fast FIFO WORD3 0x151 [15:0] X R/W STAGE3_FF_WORD4 STAGE3 fast FIFO WORD4 0x152 [15:0] X R/W STAGE3_FF_WORD5 STAGE3 fast FIFO WORD5 0x153 [15:0] X R/W STAGE3_FF_WORD6 STAGE3 fast FIFO WORD6 0x154 [15:0] X R/W STAGE3_FF_WORD7 STAGE3 fast FIFO WORD7 0x155 [15:0] X R/W STAGE3_SF_WORD0 STAGE3 slow FIFO WORD0 0x156 [15:0] X R/W STAGE3_SF_WORD1 STAGE3 slow FIFO WORD1 0x157 [15:0] X R/W STAGE3_SF_WORD2 STAGE3 slow FIFO WORD2 0x158 [15:0] X R/W STAGE3_SF_WORD3 STAGE3 slow FIFO WORD3 0x159 [15:0] X R/W STAGE3_SF_WORD4 STAGE3 slow FIFO WORD4 0x15A [15:0] X R/W STAGE3_SF_WORD5 STAGE3 slow FIFO WORD5 0x15B [15:0] X R/W STAGE3_SF_WORD6 STAGE3 slow FIFO WORD6 0x15C [15:0] X R/W STAGE3_SF_WORD7 STAGE3 slow FIFO WORD7 0x15D [15:0] X R/W STAGE3_SF_AMBIENT STAGE3 slow FIFO ambient value 0x15E [15:0] X R/W STAGE3_FF_AVG STAGE3 fast FIFO average value 0x15F [15:0] X R/W STAGE3_PEAK_DETECT_WORD0 STAGE3 peak FIFO WORD0 value 0x160 [15:0] X R/W STAGE3_PEAK_DETECT_WORD1 STAGE3 peak FIFO WORD1 value 0x161 [15:0] X R/W STAGE3_MAX_WORD0 STAGE3 maximum value FIFO WORD0 0x162 [15:0] X R/W STAGE3_MAX_WORD1 STAGE3 maximum value FIFO WORD1 0x163 [15:0] X R/W STAGE3_MAX_WORD2 STAGE3 maximum value FIFO WORD2 0x164 [15:0] X R/W STAGE3_MAX_WORD3 STAGE3 maximum value FIFO WORD3 0x165 [15:0] X R/W STAGE3_MAX_AVG STAGE3 average maximum FIFO value 0x166 [15:0] X R/W STAGE3_HIGH_THRESHOLD STAGE3 high threshold value 0x167 [15:0] X R/W STAGE3_MAX_TEMP STAGE3 temporary maximum value 0x168 [15:0] X R/W STAGE3_MIN_WORD0 STAGE3 minimum value FIFO WORD0 0x169 [15:0] X R/W STAGE3_MIN_WORD1 STAGE3 minimum value FIFO WORD1 0x16A [15:0] X R/W STAGE3_MIN_WORD2 STAGE3 minimum value FIFO WORD2 0x16B [15:0] X R/W STAGE3_MIN_WORD3 STAGE3 minimum value FIFO WORD3 0x16C [15:0] X R/W STAGE3_MIN_AVG STAGE3 average minimum FIFO value 0x16D [15:0] X R/W STAGE3_LOW_THRESHOLD STAGE3 low threshold value 0x16E [15:0] X R/W STAGE3_MIN_TEMP STAGE3 temporary minimum value 0x16F [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 59 of 68 AD7147A Table 44. STAGE4 Results Registers Default 1 Address Data Bit Value Type Name Description 0x170 [15:0] X R/W STAGE4_CONV_DATA STAGE4 CDC 16-bit conversion data (copy of CDC_RESULT_S4 register) 0x171 [15:0] X R/W STAGE4_FF_WORD0 STAGE4 fast FIFO WORD0 0x172 [15:0] X R/W STAGE4_FF_WORD1 STAGE4 fast FIFO WORD1 0x173 [15:0] X R/W STAGE4_FF_WORD2 STAGE4 fast FIFO WORD2 0x174 [15:0] X R/W STAGE4_FF_WORD3 STAGE4 fast FIFO WORD3 0x175 [15:0] X R/W STAGE4_FF_WORD4 STAGE4 fast FIFO WORD4 0x176 [15:0] X R/W STAGE4_FF_WORD5 STAGE4 fast FIFO WORD5 0x177 [15:0] X R/W STAGE4_FF_WORD6 STAGE4 fast FIFO WORD6 0x178 [15:0] X R/W STAGE4_FF_WORD7 STAGE4 fast FIFO WORD7 0x179 [15:0] X R/W STAGE4_SF_WORD0 STAGE4 slow FIFO WORD0 0x17A [15:0] X R/W STAGE4_SF_WORD1 STAGE4 slow FIFO WORD1 0x17B [15:0] X R/W STAGE4_SF_WORD2 STAGE4 slow FIFO WORD2 0x17C [15:0] X R/W STAGE4_SF_WORD3 STAGE4 slow FIFO WORD3 0x17D [15:0] X R/W STAGE4_SF_WORD4 STAGE4 slow FIFO WORD4 0x17E [15:0] X R/W STAGE4_SF_WORD5 STAGE4 slow FIFO WORD5 0x17F [15:0] X R/W STAGE4_SF_WORD6 STAGE4 slow FIFO WORD6 0x180 [15:0] X R/W STAGE4_SF_WORD7 STAGE4 slow FIFO WORD7 0x181 [15:0] X R/W STAGE4_SF_AMBIENT STAGE4 slow FIFO ambient value 0x182 [15:0] X R/W STAGE4_FF_AVG STAGE4 fast FIFO average value 0x183 [15:0] X R/W STAGE4_PEAK_DETECT_WORD0 STAGE4 peak FIFO WORD0 value 0x184 [15:0] X R/W STAGE4_PEAK_DETECT_WORD1 STAGE4 peak FIFO WORD1 value 0x185 [15:0] X R/W STAGE4_MAX_WORD0 STAGE4 maximum value FIFO WORD0 0x186 [15:0] X R/W STAGE4_MAX_WORD1 STAGE4 maximum value FIFO WORD1 0x187 [15:0] X R/W STAGE4_MAX_WORD2 STAGE4 maximum value FIFO WORD2 0x188 [15:0] X R/W STAGE4_MAX_WORD3 STAGE4 maximum value FIFO WORD3 0x189 [15:0] X R/W STAGE4_MAX_AVG STAGE4 average maximum FIFO value 0x18A [15:0] X R/W STAGE4_HIGH_THRESHOLD STAGE4 high threshold value 0x18B [15:0] X R/W STAGE4_MAX_TEMP STAGE4 temporary maximum value 0x18C [15:0] X R/W STAGE4_MIN_WORD0 STAGE4 minimum value FIFO WORD0 0x18D [15:0] X R/W STAGE4_MIN_WORD1 STAGE4 minimum value FIFO WORD1 0x18E [15:0] X R/W STAGE4_MIN_WORD2 STAGE4 minimum value FIFO WORD2 0x18F [15:0] X R/W STAGE4_MIN_WORD3 STAGE4 minimum value FIFO WORD3 0x190 [15:0] X R/W STAGE4_MIN_AVG STAGE4 average minimum FIFO value 0x191 [15:0] X R/W STAGE4_LOW_THRESHOLD STAGE4 low threshold value 0x192 [15:0] X R/W STAGE4_MIN_TEMP STAGE4 temporary minimum value 0x193 [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 60 of 68 AD7147A Table 45. STAGE5 Results Registers Default 1 Address Data Bit Value Type Name Description 0x194 [15:0] X R/W STAGE5_CONV_DATA STAGE5 CDC 16-bit conversion data (copy of CDC_RESULT_S5 register) 0x195 [15:0] X R/W STAGE5_FF_WORD0 STAGE5 fast FIFO WORD0 0x196 [15:0] X R/W STAGE5_FF_WORD1 STAGE5 fast FIFO WORD1 0x197 [15:0] X R/W STAGE5_FF_WORD2 STAGE5 fast FIFO WORD2 0x198 [15:0] X R/W STAGE5_FF_WORD3 STAGE5 fast FIFO WORD3 0x199 [15:0] X R/W STAGE5_FF_WORD4 STAGE5 fast FIFO WORD4 0x19A [15:0] X R/W STAGE5_FF_WORD5 STAGE5 fast FIFO WORD5 0x19B [15:0] X R/W STAGE5_FF_WORD6 STAGE5 fast FIFO WORD6 0x19C [15:0] X R/W STAGE5_FF_WORD7 STAGE5 fast FIFO WORD7 0x19D [15:0] X R/W STAGE5_SF_WORD0 STAGE5 slow FIFO WORD0 0x19E [15:0] X R/W STAGE5_SF_WORD1 STAGE5 slow FIFO WORD1 0x19F [15:0] X R/W STAGE5_SF_WORD2 STAGE5 slow FIFO WORD2 0x1A0 [15:0] X R/W STAGE5_SF_WORD3 STAGE5 slow FIFO WORD3 0x1A1 [15:0] X R/W STAGE5_SF_WORD4 STAGE5 slow FIFO WORD4 0x1A2 [15:0] X R/W STAGE5_SF_WORD5 STAGE5 slow FIFO WORD5 0x1A3 [15:0] X R/W STAGE5_SF_WORD6 STAGE5 slow FIFO WORD6 0x1A4 [15:0] X R/W STAGE5_SF_WORD7 STAGE5 slow FIFO WORD7 0x1A5 [15:0] X R/W STAGE5_SF_AMBIENT STAGE5 slow FIFO ambient value 0x1A6 [15:0] X R/W STAGE5_FF_AVG STAGE5 fast FIFO average value 0x1A7 [15:0] X R/W STAGE5_PEAK_DETECT_WORD0 STAGE5 peak FIFO WORD0 value 0x1A8 [15:0] X R/W STAGE5_PEAK_DETECT_WORD1 STAGE5 peak FIFO WORD1 value 0x1A9 [15:0] X R/W STAGE5_MAX_WORD0 STAGE5 maximum value FIFO WORD0 0x1AA [15:0] X R/W STAGE5_MAX_WORD1 STAGE5 maximum value FIFO WORD1 0x1AB [15:0] X R/W STAGE5_MAX_WORD2 STAGE5 maximum value FIFO WORD2 0x1AC [15:0] X R/W STAGE5_MAX_WORD3 STAGE5 maximum value FIFO WORD3 0x1AD [15:0] X R/W STAGE5_MAX_AVG STAGE5 average maximum FIFO value 0x1AE [15:0] X R/W STAGE5_HIGH_THRESHOLD STAGE5 high threshold value 0x1AF [15:0] X R/W STAGE5_MAX_TEMP STAGE5 temporary maximum value 0x1B0 [15:0] X R/W STAGE5_MIN_WORD0 STAGE5 minimum value FIFO WORD0 0x1B1 [15:0] X R/W STAGE5_MIN_WORD1 STAGE5 minimum value FIFO WORD1 0x1B2 [15:0] X R/W STAGE5_MIN_WORD2 STAGE5 minimum value FIFO WORD2 0x1B3 [15:0] X R/W STAGE5_MIN_WORD3 STAGE5 minimum value FIFO WORD3 0x1B4 [15:0] X R/W STAGE5_MIN_AVG STAGE5 average minimum FIFO value 0x1B5 [15:0] X R/W STAGE5_LOW_THRESHOLD STAGE5 low threshold value 0x1B6 [15:0] X R/W STAGE5_MIN_TEMP STAGE5 temporary minimum value 0x1B7 [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 61 of 68 AD7147A Table 46. STAGE6 Results Registers Default 1 Address Data Bit Value Type Name Description 0x1B8 [15:0] X R/W STAGE6_CONV_DATA STAGE6 CDC 16-bit conversion data (copy of CDC_RESULT_S6 register) 0x1B9 [15:0] X R/W STAGE6_FF_WORD0 STAGE6 fast FIFO WORD0 0x1BA [15:0] X R/W STAGE6_FF_WORD1 STAGE6 fast FIFO WORD1 0x1BB [15:0] X R/W STAGE6_FF_WORD2 STAGE6 fast FIFO WORD2 0x1BC [15:0] X R/W STAGE6_FF_WORD3 STAGE6 fast FIFO WORD3 0x1BD [15:0] X R/W STAGE6_FF_WORD4 STAGE6 fast FIFO WORD4 0x1BE [15:0] X R/W STAGE6_FF_WORD5 STAGE6 fast FIFO WORD5 0x1BF [15:0] X R/W STAGE6_FF_WORD6 STAGE6 fast FIFO WORD6 0x1C0 [15:0] X R/W STAGE6_FF_WORD7 STAGE6 fast FIFO WORD7 0x1C1 [15:0] X R/W STAGE6_SF_WORD0 STAGE6 slow FIFO WORD0 0x1C2 [15:0] X R/W STAGE6_SF_WORD1 STAGE6 slow FIFO WORD1 0x1C3 [15:0] X R/W STAGE6_SF_WORD2 STAGE6 slow FIFO WORD2 0x1C4 [15:0] X R/W STAGE6_SF_WORD3 STAGE6 slow FIFO WORD3 0x1C5 [15:0] X R/W STAGE6_SF_WORD4 STAGE6 slow FIFO WORD4 0x1C6 [15:0] X R/W STAGE6_SF_WORD5 STAGE6 slow FIFO WORD5 0x1C7 [15:0] X R/W STAGE6_SF_WORD6 STAGE6 slow FIFO WORD6 0x1C8 [15:0] X R/W STAGE6_SF_WORD7 STAGE6 slow FIFO WORD7 0x1C9 [15:0] X R/W STAGE6_SF_AMBIENT STAGE6 slow FIFO ambient value 0x1CA [15:0] X R/W STAGE6_FF_AVG STAGE6 fast FIFO average value 0x1CB [15:0] X R/W STAGE6_PEAK_DETECT_WORD0 STAGE6 peak FIFO WORD0 value 0x1CC [15:0] X R/W STAGE6_PEAK_DETECT_WORD1 STAGE6 peak FIFO WORD1 value 0x1CD [15:0] X R/W STAGE6_MAX_WORD0 STAGE6 maximum value FIFO WORD0 0x1CE [15:0] X R/W STAGE6_MAX_WORD1 STAGE6 maximum value FIFO WORD1 0x1CF [15:0] X R/W STAGE6_MAX_WORD2 STAGE6 maximum value FIFO WORD2 0x1D0 [15:0] X R/W STAGE6_MAX_WORD3 STAGE6 maximum value FIFO WORD3 0x1D1 [15:0] X R/W STAGE6_MAX_AVG STAGE6 average maximum FIFO value 0x1D2 [15:0] X R/W STAGE6_HIGH_THRESHOLD STAGE6 high threshold value 0x1D3 [15:0] X R/W STAGE6_MAX_TEMP STAGE6 temporary maximum value 0x1D4 [15:0] X R/W STAGE6_MIN_WORD0 STAGE6 minimum value FIFO WORD0 0x1D5 [15:0] X R/W STAGE6_MIN_WORD1 STAGE6 minimum value FIFO WORD1 0x1D6 [15:0] X R/W STAGE6_MIN_WORD2 STAGE6 minimum value FIFO WORD2 0x1D7 [15:0] X R/W STAGE6_MIN_WORD3 STAGE6 minimum value FIFO WORD3 0x1D8 [15:0] X R/W STAGE6_MIN_AVG STAGE6 average minimum FIFO value 0x1D9 [15:0] X R/W STAGE6_LOW_THRESHOLD STAGE6 low threshold value 0x1DA [15:0] X R/W STAGE6_MIN_TEMP STAGE6 temporary minimum value 0x1DB [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 62 of 68 AD7147A Table 47. STAGE7 Results Registers Default 1 Address Data Bit Value Type Name Description 0x1DC [15:0] X R/W STAGE7_CONV_DATA STAGE7 CDC 16-bit conversion data (copy of CDC_RESULT_S7 register) 0x1DD [15:0] X R/W STAGE7_FF_WORD0 STAGE7 fast FIFO WORD0 0x1DE [15:0] X R/W STAGE7_FF_WORD1 STAGE7 fast FIFO WORD1 0x1DF [15:0] X R/W STAGE7_FF_WORD2 STAGE7 fast FIFO WORD2 0x1E0 [15:0] X R/W STAGE7_FF_WORD3 STAGE7 fast FIFO WORD3 0x1E1 [15:0] X R/W STAGE7_FF_WORD4 STAGE7 fast FIFO WORD4 0x1E2 [15:0] X R/W STAGE7_FF_WORD5 STAGE7 fast FIFO WORD5 0x1E3 [15:0] X R/W STAGE7_FF_WORD6 STAGE7 fast FIFO WORD6 0x1E4 [15:0] X R/W STAGE7_FF_WORD7 STAGE7 fast FIFO WORD7 0x1E5 [15:0] X R/W STAGE7_SF_WORD0 STAGE7 slow FIFO WORD0 0x1E6 [15:0] X R/W STAGE7_SF_WORD1 STAGE7 slow FIFO WORD1 0x1E7 [15:0] X R/W STAGE7_SF_WORD2 STAGE7 slow FIFO WORD2 0x1E8 [15:0] X R/W STAGE7_SF_WORD3 STAGE7 slow FIFO WORD3 0x1E9 [15:0] X R/W STAGE7_SF_WORD4 STAGE7 slow FIFO WORD4 0x1EA [15:0] X R/W STAGE7_SF_WORD5 STAGE7 slow FIFO WORD5 0x1EB [15:0] X R/W STAGE7_SF_WORD6 STAGE7 slow FIFO WORD6 0x1EC [15:0] X R/W STAGE7_SF_WORD7 STAGE7 slow FIFO WORD7 0x1ED [15:0] X R/W STAGE7_SF_AMBIENT STAGE7 slow FIFO ambient value 0x1EE [15:0] X R/W STAGE7_FF_AVG STAGE7 fast FIFO average value 0x1EF [15:0] X R/W STAGE7_PEAK_DETECT_WORD0 STAGE7 peak FIFO WORD0 value 0x1F0 [15:0] X R/W STAGE7_PEAK_DETECT_WORD1 STAGE7 peak FIFO WORD1 value 0x1F1 [15:0] X R/W STAGE7_MAX_WORD0 STAGE7 maximum value FIFO WORD0 0x1F2 [15:0] X R/W STAGE7_MAX_WORD1 STAGE7 maximum value FIFO WORD1 0x1F3 [15:0] X R/W STAGE7_MAX_WORD2 STAGE7 maximum value FIFO WORD2 0x1F4 [15:0] X R/W STAGE7_MAX_WORD3 STAGE7 maximum value FIFO WORD3 0x1F5 [15:0] X R/W STAGE7_MAX_AVG STAGE7 average maximum FIFO value 0x1F6 [15:0] X R/W STAGE7_HIGH_THRESHOLD STAGE7 high threshold value 0x1F7 [15:0] X R/W STAGE7_MAX_TEMP STAGE7 temporary maximum value 0x1F8 [15:0] X R/W STAGE7_MIN_WORD0 STAGE7 minimum value FIFO WORD0 0x1F9 [15:0] X R/W STAGE7_MIN_WORD1 STAGE7 minimum value FIFO WORD1 0x1FA [15:0] X R/W STAGE7_MIN_WORD2 STAGE7 minimum value FIFO WORD2 0x1FB [15:0] X R/W STAGE7_MIN_WORD3 STAGE7 minimum value FIFO WORD3 0x1FC [15:0] X R/W STAGE7_MIN_AVG STAGE7 average minimum FIFO value 0x1FD [15:0] X R/W STAGE7_LOW_THRESHOLD STAGE7 low threshold value 0x1FE [15:0] X R/W STAGE7_MIN_TEMP STAGE7 temporary minimum value 0x1FF [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 63 of 68 AD7147A Table 48. STAGE8 Results Registers Default 1 Address Data Bit Value Type Name Description 0x200 [15:0] X R/W STAGE8_CONV_DATA STAGE8 CDC 16-bit conversion data (copy of CDC_RESULT_S8 register) 0x201 [15:0] X R/W STAGE8_FF_WORD0 STAGE8 fast FIFO WORD0 0x202 [15:0] X R/W STAGE8_FF_WORD1 STAGE8 fast FIFO WORD1 0x203 [15:0] X R/W STAGE8_FF_WORD2 STAGE8 fast FIFO WORD2 0x204 [15:0] X R/W STAGE8_FF_WORD3 STAGE8 fast FIFO WORD3 0x205 [15:0] X R/W STAGE8_FF_WORD4 STAGE8 fast FIFO WORD4 0x206 [15:0] X R/W STAGE8_FF_WORD5 STAGE8 fast FIFO WORD5 0x207 [15:0] X R/W STAGE8_FF_WORD6 STAGE8 fast FIFO WORD6 0x208 [15:0] X R/W STAGE8_FF_WORD7 STAGE8 fast FIFO WORD7 0x209 [15:0] X R/W STAGE8_SF_WORD0 STAGE8 slow FIFO WORD0 0x20A [15:0] X R/W STAGE8_SF_WORD1 STAGE8 slow FIFO WORD1 0x20B [15:0] X R/W STAGE8_SF_WORD2 STAGE8 slow FIFO WORD2 0x20C [15:0] X R/W STAGE8_SF_WORD3 STAGE8 slow FIFO WORD3 0x20D [15:0] X R/W STAGE8_SF_WORD4 STAGE8 slow FIFO WORD4 0x20E [15:0] X R/W STAGE8_SF_WORD5 STAGE8 slow FIFO WORD5 0x20F [15:0] X R/W STAGE8_SF_WORD6 STAGE8 slow FIFO WORD6 0x210 [15:0] X R/W STAGE8_SF_WORD7 STAGE8 slow FIFO WORD7 0x211 [15:0] X R/W STAGE8_SF_AMBIENT STAGE8 slow FIFO ambient value 0x212 [15:0] X R/W STAGE8_FF_AVG STAGE8 fast FIFO average value 0x213 [15:0] X R/W STAGE8_PEAK_DETECT_WORD0 STAGE8 peak FIFO WORD0 value 0x214 [15:0] X R/W STAGE8_PEAK_DETECT_WORD1 STAGE8 peak FIFO WORD1 value 0x215 [15:0] X R/W STAGE8_MAX_WORD0 STAGE8 maximum value FIFO WORD0 0x216 [15:0] X R/W STAGE8_MAX_WORD1 STAGE8 maximum value FIFO WORD1 0x217 [15:0] X R/W STAGE8_MAX_WORD2 STAGE8 maximum value FIFO WORD2 0x218 [15:0] X R/W STAGE8_MAX_WORD3 STAGE8 maximum value FIFO WORD3 0x219 [15:0] X R/W STAGE8_MAX_AVG STAGE8 average maximum FIFO value 0x21A [15:0] X R/W STAGE8_HIGH_THRESHOLD STAGE8 high threshold value 0x21B [15:0] X R/W STAGE8_MAX_TEMP STAGE8 temporary maximum value 0x21C [15:0] X R/W STAGE8_MIN_WORD0 STAGE8 minimum value FIFO WORD0 0x21D [15:0] X R/W STAGE8_MIN_WORD1 STAGE8 minimum value FIFO WORD1 0x21E [15:0] X R/W STAGE8_MIN_WORD2 STAGE8 minimum value FIFO WORD2 0x21F [15:0] X R/W STAGE8_MIN_WORD3 STAGE8 minimum value FIFO WORD3 0x220 [15:0] X R/W STAGE8_MIN_AVG STAGE8 average minimum FIFO value 0x221 [15:0] X R/W STAGE8_LOW_THRESHOLD STAGE8 low threshold value 0x222 [15:0] X R/W STAGE8_MIN_TEMP STAGE7 temporary minimum value 0x223 [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 64 of 68 AD7147A Table 49. STAGE9 Results Registers Default 1 Address Data Bit Value Type Name Description 0x224 [15:0] X R/W STAGE9_CONV_DATA STAGE9 CDC 16-bit conversion data (copy of CDC_RESULT_S9 register) 0x225 [15:0] X R/W STAGE9_FF_WORD0 STAGE9 fast FIFO WORD0 0x226 [15:0] X R/W STAGE9_FF_WORD1 STAGE9 fast FIFO WORD1 0x227 [15:0] X R/W STAGE9_FF_WORD2 STAGE9 fast FIFO WORD2 0x228 [15:0] X R/W STAGE9_FF_WORD3 STAGE9 fast FIFO WORD3 0x229 [15:0] X R/W STAGE9_FF_WORD4 STAGE9 fast FIFO WORD4 0x22A [15:0] X R/W STAGE9_FF_WORD5 STAGE9 fast FIFO WORD5 0x22B [15:0] X R/W STAGE9_FF_WORD6 STAGE9 fast FIFO WORD6 0x22C [15:0] X R/W STAGE9_FF_WORD7 STAGE9 fast FIFO WORD7 0x22D [15:0] X R/W STAGE9_SF_WORD0 STAGE9 slow FIFO WORD0 0x22E [15:0] X R/W STAGE9_SF_WORD1 STAGE9 slow FIFO WORD1 0x22F [15:0] X R/W STAGE9_SF_WORD2 STAGE9 slow FIFO WORD2 0x230 [15:0] X R/W STAGE9_SF_WORD3 STAGE9 slow FIFO WORD3 0x231 [15:0] X R/W STAGE9_SF_WORD4 STAGE9 slow FIFO WORD4 0x232 [15:0] X R/W STAGE9_SF_WORD5 STAGE9 slow FIFO WORD5 0x233 [15:0] X R/W STAGE9_SF_WORD6 STAGE9 slow FIFO WORD6 0x234 [15:0] X R/W STAGE9_SF_WORD7 STAGE9 slow FIFO WORD7 0x235 [15:0] X R/W STAGE9_SF_AMBIENT STAGE9 slow FIFO ambient value 0x236 [15:0] X R/W STAGE9_FF_AVG STAGE9 fast FIFO average value 0x237 [15:0] X R/W STAGE9_PEAK_DETECT_WORD0 STAGE9 peak FIFO WORD0 value 0x238 [15:0] X R/W STAGE9_PEAK_DETECT_WORD1 STAGE9 peak FIFO WORD1 value 0x239 [15:0] X R/W STAGE9_MAX_WORD0 STAGE9 maximum value FIFO WORD0 0x23A [15:0] X R/W STAGE9_MAX_WORD1 STAGE9 maximum value FIFO WORD1 0x23B [15:0] X R/W STAGE9_MAX_WORD2 STAGE9 maximum value FIFO WORD2 0x23C [15:0] X R/W STAGE9_MAX_WORD3 STAGE9 maximum value FIFO WORD3 0x23D [15:0] X R/W STAGE9_MAX_AVG STAGE9 average maximum FIFO value 0x23E [15:0] X R/W STAGE9_HIGH_THRESHOLD STAGE9 high threshold value 0x23F [15:0] X R/W STAGE9_MAX_TEMP STAGE9 temporary maximum value 0x240 [15:0] X R/W STAGE9_MIN_WORD0 STAGE9 minimum value FIFO WORD0 0x241 [15:0] X R/W STAGE9_MIN_WORD1 STAGE9 minimum value FIFO WORD1 0x242 [15:0] X R/W STAGE9_MIN_WORD2 STAGE9 minimum value FIFO WORD2 0x243 [15:0] X R/W STAGE9_MIN_WORD3 STAGE9 minimum value FIFO WORD3 0x244 [15:0] X R/W STAGE9_MIN_AVG STAGE9 average minimum FIFO value 0x245 [15:0] X R/W STAGE9_LOW_THRESHOLD STAGE9 low threshold value 0x246 [15:0] X R/W STAGE9_MIN_TEMP STAGE9 temporary minimum value 0x247 [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 65 of 68 AD7147A Table 50. STAGE10 Results Registers Default 1 Address Data Bit Value Type Name Description 0x248 [15:0] X R/W STAGE10_CONV_DATA STAGE10 CDC 16-bit conversion data (copy of CDC_RESULT_S10 register) 0x249 [15:0] X R/W STAGE10_FF_WORD0 STAGE10 fast FIFO WORD0 0x24A [15:0] X R/W STAGE10_FF_WORD1 STAGE10 fast FIFO WORD1 0x24B [15:0] X R/W STAGE10_FF_WORD2 STAGE10 fast FIFO WORD2 0x24C [15:0] X R/W STAGE10_FF_WORD3 STAGE10 fast FIFO WORD3 0x24D [15:0] X R/W STAGE10_FF_WORD4 STAGE10 fast FIFO WORD4 0x24E [15:0] X R/W STAGE10_FF_WORD5 STAGE10 fast FIFO WORD5 0x24F [15:0] X R/W STAGE10_FF_WORD6 STAGE10 fast FIFO WORD6 0x250 [15:0] X R/W STAGE10_FF_WORD7 STAGE10 fast FIFO WORD7 0x251 [15:0] X R/W STAGE10_SF_WORD0 STAGE10 slow FIFO WORD0 0x252 [15:0] X R/W STAGE10_SF_WORD1 STAGE10 slow FIFO WORD1 0x253 [15:0] X R/W STAGE10_SF_WORD2 STAGE10 slow FIFO WORD2 0x254 [15:0] X R/W STAGE10_SF_WORD3 STAGE10 slow FIFO WORD3 0x255 [15:0] X R/W STAGE10_SF_WORD4 STAGE10 slow FIFO WORD4 0x256 [15:0] X R/W STAGE10_SF_WORD5 STAGE10 slow FIFO WORD5 0x257 [15:0] X R/W STAGE10_SF_WORD6 STAGE10 slow FIFO WORD6 0x258 [15:0] X R/W STAGE10_SF_WORD7 STAGE10 slow FIFO WORD7 0x259 [15:0] X R/W STAGE10_SF_AMBIENT STAGE10 slow FIFO ambient value 0x25A [15:0] X R/W STAGE10_FF_AVG STAGE10 fast FIFO average value 0x25B [15:0] X R/W STAGE10_PEAK_DETECT_WORD0 STAGE10 peak FIFO WORD0 value 0x25C [15:0] X R/W STAGE10_PEAK_DETECT_WORD1 STAGE10 peak FIFO WORD1 value 0x25D [15:0] X R/W STAGE10_MAX_WORD0 STAGE10 maximum value FIFO WORD0 0x25E [15:0] X R/W STAGE10_MAX_WORD1 STAGE10 maximum value FIFO WORD1 0x25F [15:0] X R/W STAGE10_MAX_WORD2 STAGE10 maximum value FIFO WORD2 0x260 [15:0] X R/W STAGE10_MAX_WORD3 STAGE10 maximum value FIFO WORD3 0x261 [15:0] X R/W STAGE10_MAX_AVG STAGE10 average maximum FIFO value 0x262 [15:0] X R/W STAGE10_HIGH_THRESHOLD STAGE10 high threshold value 0x263 [15:0] X R/W STAGE10_MAX_TEMP STAGE10 temporary maximum value 0x264 [15:0] X R/W STAGE10_MIN_WORD0 STAGE10 minimum value FIFO WORD0 0x265 [15:0] X R/W STAGE10_MIN_WORD1 STAGE10 minimum value FIFO WORD1 0x266 [15:0] X R/W STAGE10_MIN_WORD2 STAGE10 minimum value FIFO WORD2 0x267 [15:0] X R/W STAGE10_MIN_WORD3 STAGE10 minimum value FIFO WORD3 0x268 [15:0] X R/W STAGE10_MIN_AVG STAGE10 average minimum FIFO value 0x269 [15:0] X R/W STAGE10_LOW_THRESHOLD STAGE10 low threshold value 0x26A [15:0] X R/W STAGE10_MIN_TEMP STAGE10 temporary minimum value 0x26B [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 66 of 68 AD7147A Table 51. STAGE11 Results Registers Default 1 Address Data Bit Value Type Name Description 0x26C [15:0] X R/W STAGE11_CONV_DATA STAGE11 CDC 16-bit conversion data (copy of CDC_RESULT_S11 register) 0x26D [15:0] X R/W STAGE11_FF_WORD0 STAGE11 fast FIFO WORD0 0x26E [15:0] X R/W STAGE11_FF_WORD1 STAGE11 fast FIFO WORD1 0x26F [15:0] X R/W STAGE11_FF_WORD2 STAGE11 fast FIFO WORD2 0x270 [15:0] X R/W STAGE11_FF_WORD3 STAGE11 fast FIFO WORD3 0x271 [15:0] X R/W STAGE11_FF_WORD4 STAGE11 fast FIFO WORD4 0x272 [15:0] X R/W STAGE11_FF_WORD5 STAGE11 fast FIFO WORD5 0x273 [15:0] X R/W STAGE11_FF_WORD6 STAGE11 fast FIFO WORD6 0x274 [15:0] X R/W STAGE11_FF_WORD7 STAGE11 fast FIFO WORD7 0x275 [15:0] X R/W STAGE11_SF_WORD0 STAGE11 slow FIFO WORD0 0x276 [15:0] X R/W STAGE11_SF_WORD1 STAGE11 slow FIFO WORD1 0x277 [15:0] X R/W STAGE11_SF_WORD2 STAGE11 slow FIFO WORD2 0x278 [15:0] X R/W STAGE11_SF_WORD3 STAGE11 slow FIFO WORD3 0x279 [15:0] X R/W STAGE11_SF_WORD4 STAGE11 slow FIFO WORD4 0x27A [15:0] X R/W STAGE11_SF_WORD5 STAGE11 slow FIFO WORD5 0x27B [15:0] X R/W STAGE11_SF_WORD6 STAGE11 slow FIFO WORD6 0x27C [15:0] X R/W STAGE11_SF_WORD7 STAGE11 slow FIFO WORD7 0x27D [15:0] X R/W STAGE11_SF_AMBIENT STAGE11 slow FIFO ambient value 0x27E [15:0] X R/W STAGE11_FF_AVG STAGE11 fast FIFO average value 0x27F [15:0] X R/W STAGE11_PEAK_DETECT_WORD0 STAGE11 peak FIFO WORD0 value 0x280 [15:0] X R/W STAGE11_PEAK_DETECT_WORD1 STAGE11 peak FIFO WORD1 value 0x281 [15:0] X R/W STAGE11_MAX_WORD0 STAGE11 maximum value FIFO WORD0 0x282 [15:0] X R/W STAGE11_MAX_WORD1 STAGE11 maximum value FIFO WORD1 0x283 [15:0] X R/W STAGE11_MAX_WORD2 STAGE11 maximum value FIFO WORD2 0x284 [15:0] X R/W STAGE11_MAX_WORD3 STAGE11 maximum value FIFO WORD3 0x285 [15:0] X R/W STAGE11_MAX_AVG STAGE11 average maximum FIFO value 0x286 [15:0] X R/W STAGE11_HIGH_THRESHOLD STAGE11 high threshold value 0x287 [15:0] X R/W STAGE11_MAX_TEMP STAGE11 temporary maximum value 0x288 [15:0] X R/W STAGE11_MIN_WORD0 STAGE11 minimum value FIFO WORD0 0x289 [15:0] X R/W STAGE11_MIN_WORD1 STAGE11 minimum value FIFO WORD1 0x28A [15:0] X R/W STAGE11_MIN_WORD2 STAGE11 minimum value FIFO WORD2 0x28B [15:0] X R/W STAGE11_MIN_WORD3 STAGE11 minimum value FIFO WORD3 0x28C [15:0] X R/W STAGE11_MIN_AVG STAGE11 average minimum FIFO value 0x28D [15:0] X R/W STAGE11_LOW_THRESHOLD STAGE11 low threshold value 0x28E [15:0] X R/W STAGE11_MIN_TEMP STAGE11 temporary minimum value 0x28F [15:0] X R/W Unused Set to 0 1 X = don’t care. Rev. B | Page 67 of 68 AD7147A OUTLINE DIMENSIONS 0.600 0.555 2.295 0.510 2.245 2.195 SEATING 5 4 3 2 1 PLANE A BALL 1 IDENTIFIER B 2.100 2.050 1.60 C 2.000 0.287 REF 0.267 0.247 D E 0.40 REF TOP VIEW BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.23 1.60 REF 0.20 0.17 Figure 62. 25-Ball Wafer Level Chip Scale Package [WLCSP] (CB-25-3) Dimensions shown in millimeters ORDERING GUIDE Temperature Serial Interface Package Package Model Range Description Description Description Option Branding 1, 2 AD7147AACBZ-RL −40°C to +85°C Wake-up on proximity SPI Interface 25-Ball WLCSP CB-25-3 T3K 1, 2 AD7147AACBZ500RL7 −40°C to +85°C Wake-up on proximity SPI Interface 25-Ball WLCSP CB-25-3 T3K 1, 2 2 AD7147A-1ACBZ-RL −40°C to +85°C Wake-up on proximity I C Interface 25-Ball WLCSP CB-25-3 T3J 1, 2 2 AD7147A-1ACBZ500RL7 −40°C to +85°C Wake-up on proximity I C Interface 25-Ball WLCSP CB-25-3 T3J 1 EVAL-AD7147EBZ SPI Interface Evaluation Board 1 2 EVAL-AD7147-1EBZ I C Interface Evaluation Board 1 Z = RoHS Compliant Part. 2 This package is halide free. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07727-0-12/09(B) Rev. B | Page 68 of 68 081908-A