ANALOG DEVICES AD7143

Programmable Controller for Capacitance Touch Sensors AD7143 FEATURES FUNCTIONAL BLOCK DIAGRAM Programmable capacitance-to-digital converter POWER-ON 25 ms update rate (@ maximum sequence length) RESET AD7143 15 CIN0 LOGIC Better than 1 fF resolution CIN1 16 8 capacitance sensor input channels CIN2 1 16-BIT CALIBRA- CIN3 2 No external RC tuning components required Σ-Δ TION CIN4 3 CDC ENGINE Automatic conversion sequencer CIN5 4 On-chip automatic calibration logic CIN6 5 CALIBRA- 9 VCC Automatic compensation for environmental changes TION CIN7 6 CONTROL RAM 10 GND AND Automatic adaptive threshold and sensitivity levels DATA REGISTERS On-chip RAM to store calibration data 2 I C®-compatible serial interface 7 250kHz CSHIELD Separate VDRIVE level for serial interface EXCITATION SRC 8 SOURCE Interrupt output for host controller 16-lead, 4 mm x 4 mm LFCSP-VQ INTERRUPT 2 I C SERIAL INTERFACE LOGIC AND CONTROL LOGIC 2.6 V to 3.6 V supply voltage Low operating current 11 12 13 14 Full power mode: less than 1 mA VDRIVE SDA SCLK INT Low power mode: 50 μA Figure 1. APPLICATIONS Personal music and multimedia players Cell phones Digital still cameras Smart hand-held devices Television, A/V, and remote controls Gaming consoles The AD7143 has on-chip calibration logic to account for GENERAL DESCRIPTION changes in the ambient environment. The calibration sequence is The AD7143 is an integrated capacitance-to-digital converter performed automatically and at continuous intervals, while the (CDC) with on-chip environmental calibration for use in sensors are not touched. This ensures that there are no false or systems requiring a novel user input method. The AD7143 nonregistering touches on the external sensors due to a interfaces to external capacitance sensors implementing changing environment. functions, such as capacitive buttons, scroll bars, and 2 The AD7143 has an I C-compatible serial interface and a scroll wheels. 2 separate VDRIVE pin for I C serial interface operating voltages The CDC has eight inputs channeled through a switch matrix to between 1.65 V and 3.6 V. a 16-bit, 250 kHz sigma-delta (∑-Δ) capacitance-to-digital The AD7143 is available in a 16-lead, 4 mm × 4 mm LFCSP-VQ converter. The CDC is capable of sensing changes in the and operates from a 2.6 V to 3.6 V supply. The operating capacitance of the external sensors and uses this information to current consumption is less than 1 mA, falling to 50 μA in low register a sensor activation. The external sensors can be power mode (conversion interval of 400 ms). arranged as a series of buttons, as a scroll bar or wheel, or as a combination of sensor types. By programming the registers, the user has full control over the CDC setup. High resolution sensors require software to run on the host processor. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. SWITCH MATRIX 06472-001 AD7143 TABLE OF CONTENTS Features .............................................................................................. 1 Proximity Sensitivity.................................................................. 17 Applications....................................................................................... 1 Slow FIFO.................................................................................... 19 Functional Block Diagram .............................................................. 1 SLOW_FILTER_UPDATE_LVL .............................................. 19 General Description ......................................................................... 1 Environmental Calibration ........................................................... 22 Revision History ............................................................................... 2 Capacitance Sensor Behavior without Calibration................ 22 Specifications..................................................................................... 3 Capacitance Sensor Behavior with Calibration...................... 23 2 I C Timing Specifications............................................................ 5 Adaptive Threshold and Sensitivity ............................................. 25 Absolute Maximum Ratings............................................................ 6 Interrupt Output............................................................................. 26 ESD Caution.................................................................................. 6 CDC Conversion Complete Interrupt..................................... 26 Pin Configurations and Function Descriptions ........................... 7 Sensor Touch Interrupt.............................................................. 26 Typical Performance Characteristics ............................................. 8 Serial Interface ................................................................................ 28 2 Theory of Operation ...................................................................... 11 I C Compatible Interface........................................................... 28 Capacitance Sensing Theory..................................................... 11 PCB Design Guidelines ................................................................. 31 Operating Modes........................................................................ 12 Capacitive Sensor Board Mechanical Specifications ............. 31 Capacitance Sensor Input Configuration.................................... 13 Chip Scale Packages ................................................................... 31 CIN Input Multiplexer Setup .................................................... 13 Power-Up Sequence ....................................................................... 32 Capacitiance-to-Digital Converter............................................... 14 Typical Application Circuits ......................................................... 33 Oversampling the CDC Output ............................................... 14 Register Map ................................................................................... 34 Capacitance Sensor Offset Control.......................................... 14 Detailed Register Descriptions ..................................................... 35 Conversion Sequencer ............................................................... 14 Bank 1 Registers ......................................................................... 35 CDC Conversion Sequence Time ............................................ 15 Bank 2 Registers ......................................................................... 43 CDC Conversion Results........................................................... 16 Bank 3 Registers ......................................................................... 47 Noncontact Proximity Detection ................................................. 17 Outline Dimensions ....................................................................... 55 Recalibration ............................................................................... 17 Ordering Guide .......................................................................... 55 REVISION HISTORY 1/07—Revision 0: Initial Version Rev. 0 | Page 2 of 56 AD7143 SPECIFICATIONS o VCC = 2.6 V to 3.6 V, TA = −40 C to +85°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments CAPACITANCE-TO-DIGITAL CONVERTER Update Rate 23 25 26 ms Eight conversion stages in sequencer, decimation = 256 Resolution 16 Bit 1 CIN Input Range ±2 pF No Missing Codes 16 Bit Guaranteed by design, but not production tested CIN Input Leakage 25 nA Total Unadjusted Error ±20 % Output Noise (Peak-to-Peak) 7 Codes Decimation rate = 128 3 Codes Decimation rate = 256 Output Noise (RMS) 0.8 Codes Decimation rate = 128 0.5 Codes Decimation rate = 256 Parasitic Capacitance 40 pF Parasitic capacitance to ground, per CIN input guaranteed by characterization 1 CBULK Offset Range ±20 pF CBULK Offset Resolution 156.25 fF Low Power Mode Delay Accuracy 5 % % of 200 ms, 400 ms, 600 ms, or 800 ms EXCITATION SOURCE Frequency 237.5 240 262.5 kHz Output Voltage VCC V Short-Circuit Source Current 20 mA Short-Circuit Sink Current 50 mA Maximum Output Load 250 pF Capacitance load on source to ground CSHIELD Output Drive 10 μA CSHIELD Bias Level VCC/2 V LOGIC INPUTS (SCLK, SDA) VIH Input High Voltage 0.7 × VDRIVE V VIL Input Low Voltage 0.4 V I Input High Voltage −1 μA IH I Input Low Voltage 1 μA V = GND IL IN Hysteresis 150 mV OPEN-DRAIN OUTPUTS (SCLK, SDA, INT) V Output Low Voltage 0.4 V I = −1 mA OL SINK I Output High Leakage Current +0.1 ±1 μA OH POWER V 2.6 3.3 3.6 V CC V 1.65 3.6 V DRIVE ICC 0.9 1 mA In full power mode 20 μA Low power mode, converter idle, TA = 25°C 16 30 μA Low power mode, converter idle 4.5 μA Full shutdown, T = 25°C A 2.25 15 μA Full shutdown 1 C and C are defined as follows: IN BULK C IN PLASTIC OVERLAY C BULK SENSOR BOARD CAPACITIVE SENSOR Rev. 0 | Page 3 of 56 05702-054 AD7143 Table 2. Typical Average Current in Low Power Mode, V = 3.6 V, T = 25°C, Load of 50 pF on SRC Pin CC Number of Conversion Stages, Current Values Expressed in μA Low Power Mode Delay Decimation Rate 1 2 3 4 5 6 7 8 200 ms 128 26.4 33.3 40.1 46.9 53.5 60 66.5 72.8 256 35.6 49.1 62.2 74.9 87.3 99.3 111 122.3 400 ms 128 21.3 24.8 28.3 31.7 35.2 38.6 42 45.4 256 26 32.9 39.7 46.5 53.1 59.6 66.1 72.4 600 ms 128 19.6 21.9 24.3 26.6 28.9 31.2 33.5 35.8 256 22.7 27.4 32 25.6 41.1 45.6 50 54.4 800 ms 128 18.7 20.5 22.2 24 25.7 27.5 29.2 31 256 21.1 24.6 28.1 31.5 35 38.4 41.8 45.2 Table 3. Maximum Average Current in Low Power Mode, V = 3.6 V, Load of 50 pF on SRC Pin CC Number of Conversion Stages, Current Values Expressed in μA Low Power Mode Delay Decimation Rate 1 2 3 4 5 6 7 8 200 ms 128 42.2 50.5 58.7 66.7 74.6 82.3 90.0 97.5 256 53.2 69.3 84.9 100.0 114.6 128.7 142.5 155.8 400 ms 128 36.1 40.4 44.5 48.7 52.8 56.9 60.9 64.5 256 41.8 50.1 58.2 66.2 74.1 82.0 89.5 97.1 600 ms 128 34.1 37.0 39.7 42.5 45.3 48.1 50.8 53.4 256 37.9 43.5 49.0 54.5 60.0 65.2 70.5 75.7 800 ms 128 33.1 35.2 37.3 39.4 41.5 43.6 45.7 47.7 256 35.9 40.1 44.3 48.4 52.6 56.6 60.7 64.7 Rev. 0 | Page 4 of 56 AD7143 2 I C TIMING SPECIFICATIONS TA = −40°C to +85°C, VCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals timed from a voltage level of 1.6 V. 2 1 Table 4. I C Timing Specifications Parameter Limit Unit Description fSCLK 400 kHz max t 0.6 μs min Start condition hold time, t 1 HD; STA t 1.3 μs min Clock low period, t 2 LOW t 0.6 μs min Clock high period, t 3 HIGH t4 100 ns min Data setup time, tSU; DAT t5 300 ns min Data hold time, tHD; DAT t6 0.6 μs min Stop condition setup time, tSU; STO t 0.6 μs min Start condition setup time, t 7 SU; STA t 1.3 μs min Bus free time between stop and start conditions, t 8 BUF t 300 ns max Clock/data rise time R tF 300 ns max Clock/data fall time 1 Guaranteed by design, not production tested. 200µA I OL TO OUTPUT 1.6V PIN C L 50pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Specifications Rev. 0 | Page 5 of 56 06472-003 AD7143 ABSOLUTE MAXIMUM RATINGS Parameter Rating Stresses above those listed under Absolute Maximum Ratings VCC to GND −0.3 V to +3.6 V may cause permanent damage to the device. This is a stress Analog Input Voltage to GND −0.3 V to VCC + 0.3 V rating only; functional operation of the device at these or any Digital Input Voltage to GND −0.3 V to VDRIVE + 0.3 V other conditions above those indicated in the operational Digital Output Voltage to GND −0.3 V to VDRIVE + 0.3 V section of this specification is not implied. Exposure to absolute Input Current to Any Pin Except 10 mA maximum rating conditions for extended periods may affect 1 Supplies device reliability. ESD Rating (Human Body Model) 2.5 kV Operating Temperature Range −40°C to +150°C ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature 150°C LFCSP_VQ Power Dissipation 450 mW θ Thermal Impedance 135.7°C/W JA IR Reflow Peak Temperature 260°C (±0.5°C) Lead Temperature (Soldering 10 sec) 300°C 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. 0 | Page 6 of 56 AD7143 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR CIN2 1 12 SDA CIN3 2 11 VDRIVE AD7143 CIN4 3 TOP VIEW 10 GND (Not to Scale) CIN5 4 9VCC Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 CIN2 Capacitance Sensor Input. 2 CIN3 Capacitance Sensor Input. 3 CIN4 Capacitance Sensor Input. 4 CIN5 Capacitance Sensor Input. 5 CIN6 Capacitance Sensor Input. 6 CIN7 Capacitance Sensor Input. 7 CSHIELD CDC Shield Potential Output. Requires 10 nF capacitor to ground. 8 SRC CDC Excitation Source Output. 9 VCC CDC Supply Voltage. 10 GND Ground Reference Point for All CDC Circuitry. Tie to ground plane. 2 11 VDRIVE I C Serial Interface Operating Voltage 2 12 SDA I C Serial Data Input/Output. SDA requires pull-up resistor. 13 SCLK Clock Input for Serial Interface. SCLK requires pull-up resistor. 14 General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor. INT 15 CIN0 Capacitance Sensor Input. 16 CIN1 Capacitance Sensor Input. Rev. 0 | Page 7 of 56 06472-004 CIN6 5 16 CIN1 CIN7 6 15 CIN0 CSHIELD 7 14 INT SRC 8 13 SCLK AD7143 TYPICAL PERFORMANCE CHARACTERISTICS 1000 2.45 980 DEVICE 1 2.30 DEVICE 2 960 2.15 DEVICE 3 940 2.00 920 DEVICE 2 DEVICE 1 DEVICE 3 900 1.85 880 1.70 860 1.55 840 1.40 820 2.7 2.8 2.9 3.0 3.13.23.33.43.53.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V (V) CC V (V) CC Figure 4. Supply Current vs. Supply Voltage Figure 7. Shutdown Supply Current vs. Supply Voltage 180 1.10 DEVICE 1 LP_CONV_DELAY = 200ms 160 1.05 140 1.00 120 0.95 LP_CONV_DELAY = 400ms 100 DEVICE 3 DEVICE 2 0.90 80 LP_CONV_DELAY = 600ms 0.85 60 LP_CONV_DELAY = 800ms 40 0.80 2.72.82.93.03.13.2 3.3 3.4 3.5 3.6 0 50 100 150 200 250 300 350 400 450 500 V (V) CAPACITANCE LOAD ON SOURCE (pF) CC Figure 5. Low Power Supply Current vs. Supply Voltage, Figure 8. Supply Current vs. Capacitive Load on SRC Decimation Rate = 256 120 16015 DEVICE 1 16010 100 LP_CONV_DELAY = 200ms 16005 DEVICE 2 80 16000 15995 LP_CONV_DELAY = 400ms 60 DEVICE 3 15990 LP_CONV_DELAY = 600ms 40 15985 LP_CONV_DELAY = 800ms 20 15980 0 50 100 150 200 250 300 350 400 450 500 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V (V) CAPACITANCE LOAD ON SOURCE (pF) CC Figure 9. Output Code vs. Capacitive Load on SRC Figure 6. Low Power Supply Current vs. Supply Voltage Decimation Rate = 128 Rev. 0 | Page 8 of 56 I (µA) CC I (µA) I (µA) CC CC 06472-007 06472-005 06472-006 CDC OUTPUT CODE I (mA) SHUTDOWN I (µA) CC CC 06472-008 06472-010 06472-009 AD7143 0.020 960 940 0.015 3.6V 920 0.010 900 3.3V 880 0.005 860 CDC OUTPUT CODE 0 840 820 –0.005 2.7V 800 –0.010 780 0 10k 20k 30k 40k 50k 60k 70k –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) CDC OUTPUT CODE Figure 13. 3.3 V Linearity Error Figure 10. Supply Current vs. Temperature 12 2.5 100mV 300mV 200mV 400mV 500mV 10 2.0 8 1.5 6 3.6V 1.0 3.3V 4 0.5 2 2.7V 0 0 –40 –20 0 20 40 60 80 100 120 10 1k 100k 10M TEMPERATURE (°C) FREQUENCY (Hz) Figure 11. Shutdown Supply Current vs. Temperature Figure 14. Power Supply Sine Wave Rejection 180 4.8 160 4.3 140 3.8 120 CDC OUTPUT CODE 100 3.3 300mV 80 2.8 60 200mV 2.3 40 100mV 50mV 20 1.8 25mV 0 100 1k 10k 100k 1M 10M 1.3 0 10k 20k 30k 40k 50k 60k SQUARE WAVE FREQUENCY (Hz) CDC OUTPUT CODE Figure 15. Power Supply Square Wave Rejection Figure 12. 3.3 V Linearity Rev. 0 | Page 9 of 56 SUPPLY CURRENT (µA) CAPACITANCE (pF) SUPPLY CURRENT (µA) 06472-012 06472-045 06472-011 CDC PEAK-TO-PEAK NOISE (Codes) CDC PEAK-TO-PEAK NOISE (Codes) ERROR (pF) 06472-014 06472-013 06472-046 AD7143 32900 32800 32700 32600 32500 32400 32300 PARASITIC 32200 CAPACITANCE 32100 32000 31900 06 10 20 30 40 500 PCB PARASITIC CAPACITANCE (pF) Figure 16. CDC Output Codes vs. Parasitic Capacitance Rev. 0 | Page 10 of 56 CDC OUTPUT CODE (D) 06472-047 AD7143 THEORY OF OPERATION The AD7143 is a capacitance-to-digital converter (CDC) with The AD7143 operates from a 2.6 V to 3.6 V supply, and is on-chip environmental compensation, intended for use in available in a 16-lead, 4 mm × 4 mm LFCSP_VQ. portable systems requiring high resolution user input. The CAPACITANCE SENSING THEORY internal circuitry consists of a 16-bit, ∑-Δ converter that The AD7143 uses a method of sensing capacitance known as converts a capacitive input signal into a digital value. There are eight input pins, CIN0 to CIN7, on the AD7143. A switch the shunt method. Using this method, an excitation source is matrix routes the input signals to the CDC. The result of each connected to a transmitter generating an electric field to a capacitance-to-digital conversion is stored in on-chip registers. receiver. The field lines measured at the receiver are translated into the digital domain by a ∑-Δ converter. When a finger, or The host subsequently reads the results over the serial interface. 2 other grounded object, interferes with the electric field, some of The AD7143 has an I C interface, ensuring that the parts are the field lines are shunted to ground and do not reach the compatible with a wide range of host processors. receiver (see Figure 17). Therefore, the total capacitance The AD7143 interfaces with up to eight external capacitance measured at the receiver decreases when an object comes close sensors. These sensors can be arranged as buttons, scroll bars, to the induced field. wheels, or as a combination of sensor types. The external sensors consist of electrodes on a single or multiple layer PCB that interface directly to the AD7143. The AD7143 can be set up to implement any set of input sensors by programming the on-chip registers. The registers can PLASTIC COVER also be programmed to control features such as averaging, offsets, and gains for each of the external sensors. There is a sequencer on-chip to control how each of the capacitance Rx PCB LAYER Tx inputs is polled. 16-BIT The AD7143 has on-chip digital logic and 528 words of RAM EXCITATION DATA Σ-Δ SIGNAL used for environmental compensation. The effects of humidity, ADC 250kHz temperature, and other environmental factors can effect the AD7143 operation of capacitance sensors. Transparent to the user, the Figure 17. Single Layer Sensing Capacitance Method AD7143 performs continuous calibration to compensate for these effects, allowing the AD7143 to give error-free results at In practice, the excitation source and ∑-Δ ADC are implemented all times. on the AD7143, while the transmitter and receiver are constructed on a PCB that comprises the external sensor. The AD7143 requires some minor companion software that runs on the host or other microcontroller to implement high Registering a Sensor Activation resolution sensor functions, such as a scroll bar or wheel. When a sensor is approached, the total capacitance associated However, no host software is required to implement buttons, with that sensor, measured by the AD7143, changes. When the including 8-way button functionality. Button sensors are capacitance changes to such an extent that a set threshold is implemented completely in digital logic on-chip with the status exceeded, the AD7143 registers this as a sensor touch and then of each button reported in interrupt status registers. automatically updates the internal interrupt status registers. The AD7143 can be programmed to operate in either full power Preprogrammed threshold levels are used to determine if a mode, or in low power automatic wake-up mode. The change in capacitance is due to a button being activated. If the automatic wake-up mode is particularly suited for portable capacitance exceeds one of the threshold limits, the AD7143 devices that require low power operation giving the user registers this as a true button activation. The same threshold significant power savings coupled with full functionality. principle is used to determine if other types of sensors, such as INT The AD7143 has an interrupt output, , to indicate when sliders or scroll wheels, are activated. INT new data has been placed into the registers. is used to interrupt the host on sensor activation. Rev. 0 | Page 11 of 56 06472-015 AD7143 Full Power Mode Complete Solution for Capacitance Sensing In full power mode, all sections of the AD7143 remain fully Analog Devices, Inc. provides a complete solution for powered at all times. While a sensor is being touched, the capacitance sensing. The two main elements to the solution are AD7143 processes the sensor data. If no sensor is touched, the the sensor PCB and the AD7143. AD7143 measures the ambient capacitance level and uses this If the application requires high resolution sensors, such as scroll data for the on-chip compensation routines. In full power bars or wheels, software is required that runs on the host mode, the AD7143 converts at a constant rate. See the CDC processor. (No software is required for button sensors.) The Conversion Sequence Time section for more information. memory requirements for the host depend upon the sensor, and Low Power Mode are typically 9 kB of code and 600 bytes of data memory. When in low power mode, the AD7143 POWER_MODE bits SENSOR PCB are set to 10 upon device initialization. If the external sensors S1 are not touched, the AD7143 reduces its conversion frequency, S2 thereby greatly reducing its power consumption. The part S3 remains in a reduced power state when the sensors are not S4 HOST PROCESSOR 2 touched. Every LP_CONV_DELAY ms (200 ms, 400 ms, 600 8 I C 1 MIPS AD7143 S5 9kB ROM ms or 800 ms), the AD7143 performs a conversion and uses this 600 BYTES RAM S6 data to update the compensation logic. When an external SRC S7 sensor is touched, the AD7143 begins a conversion sequence S8 every 25 ms to read back data from the sensors. In low power mode, the total current consumption of the AD7143 is an average of the current used during a conversion, Figure 18. Three Part Capacitance Sensing Solution and the current used while the AD7143 is waiting for the next Analog Devices supplies the sensor PCB footprint design conversion to begin. For example, when LP_CONV_DELAY is libraries to the customer based on the customer’s specifications, 400 ms, the AD7143 typically uses 0.9 mA current for 25 ms and supplies any necessary software on an open-source basis. and 15 μA for 400 ms of the conversion interval. Note that these conversion timings can be altered through the register settings. OPERATING MODES See the CDC Conversion Sequence Time section for more The AD7143 has three operating modes. Full power mode, information. where the device is always fully powered, is suited for applications AD7143 SETUP where power is not a concern. One example is game consoles AND INITIALIZATION POWER_MODE = 10 that have an ac power supply. Low power mode, where the part automatically powers down, is tailored to give significant power ANY savings over full power mode, and is suited for mobile applications NO YES SENSOR TOUCHED? where power must be conserved. In shutdown mode, the part CONVERSION SEQUENCE shuts down completely. CONVERSION SEQUENCE EVERY LP_CONV_DELAY ms EVERY 25ms FOR UPDATE COMPENSATION SENSOR READBACK LOGIC DATA PATH The POWER_MODE bits (Bit 0 and Bit 1) of the control register set the operating mode on the AD7143. The control register is at Address 0x000. Table 6 shows the POWER_MODE YES ANY SENSOR TOUCHED? settings for each operating mode. To put the AD7143 into shutdown mode, set the POWER_MODE bits to either 01 or 11. NO Table 6. POWER_MODE Settings TIMEOUT PROXIMITY TIMER COUNT DOWN POWER_MODE Bits Operating Mode Figure 19. Low Power Mode Operation 00 Full power mode 01 Full shutdown mode The time taken for the AD7143 to go from a full power state to 10 Low power mode a reduced power state, once the user stops touching the external 11 Full shutdown mode sensors, is configurable. Once the sensors are not touched, the The power-on default setting of the POWER_MODE bits is 00, PWR_DWN_TIMEOUT bits, in the Ambient Compensation full power mode. Ctrl 0 Register at Address 0x002, control the amount of time necessary for the device to return to a reduced power state. Rev. 0 | Page 12 of 56 06472-016 06472-017 AD7143 CAPACITANCE SENSOR INPUT CONFIGURATION Each input connection from the external capacitance sensors to The AD7143 has an on-chip multiplexer to route the input the AD7143 converter can be uniquely configured by using the signals from each pin to the input of the converter. Each input registers in Table 38 and Table 39. These registers are used to pin can be tied to either the negative or the positive input of the configure input pin connection setups, sensor offsets, sensor CDC or can be left floating. Each input can also be internally sensitivities, and sensor limits for each stage. Each sensor can be connected to the C signal to help prevent cross coupling. If SHIELD individually optimized. For example, a button sensor connected an input is not used, always connect it to C . SHIELD to STAGE0 can have a different sensitivity and offset values Connecting a CINx input pin to the positive CDC input results than a button with a different function that is connected to a in a decrease in CDC output code when the corresponding different stage. sensor is activated. Connecting a CINx input pin to the negative CIN INPUT MULTIPLEXER SETUP CDC input results in an increase in CDC output code when the corresponding sensor is activated. The CIN_CONNECTION_SETUP registers in Table 38 list the available options for connecting the sensor input pin to the CDC. Two bits in each sequencer stage register control the mux setting for the input pin. CIN CONNECTION SETUP BITS CIN SETTING CIN0 00 CINx FLOATING CIN1 CIN2 CINx CONNECTED TO 01 + NEGATIVE CDC INPUT CIN3 CDC CIN4 CINx CONNECTED TO – 10 CIN5 POSITIVE CDC INPUT CIN6 CINx CONNECTED TO CIN7 11 INTERNAL BIAS Figure 20. Input Mux Configuration Options Rev. 0 | Page 13 of 56 06472-018 AD7143 CAPACITIANCE-TO-DIGITAL CONVERTER The capacitance-to-digital converter on the AD7143 has a Σ-Δ A simplified block diagram in Figure 22 shows how to apply the architecture with 16-bit resolution. Eight possible inputs to the STAGE_OFFSET registers to null the offsets. The 7-bit CDC are connected to the input of the converter through a POS_AFE_OFFSET and NEG_AFE_OFFSET registers program switch matrix. The sampling frequency of the CDC is 250 kHz. the offset DAC to provide 0.16 pF resolution offset adjustment over a range of ±20 pF. Apply the positive and negative offsets OVERSAMPLING THE CDC OUTPUT to either the positive or the negative CDC input using the The decimation rate, or oversampling ratio, is determined by NEG_AFE_OFFSET register and POS_AFE_OFFSET register. Bits[9:8] of the PWR_CONTROL register located at Address 0x000 This process is only required once during the initial capacitance and listed in Table 7. sensor characterization. 7 +DAC Table 7. CDC Decimation Rate POS_AFE_OFFSET (20pF RANGE) Decimation Bit Decimation CDC Output Rate Value Rate Per Stage 00 256 3.072 ms POS_AFE_OFFSET_SWAP BIT 01 128 1.525 ms 1 10 – – CIN + 16 16-BIT 1 11 – – _ CDC 1 Do not use this setting. NEG_AFE_OFFSET_SWAP BIT The decimation process on the AD7143 is an averaging process where a number of samples are taken and the averaged result is output. Due to the architecture of the digital filter employed, the SRC 7 –DAC NEG_AFE_OFFSET (20pF RANGE) amount of samples taken (per stage) is equal to 3× the decimation rate. Therefore, 3 × 256 or 3 × 128 samples are CIN_CONNECTION_SETUP averaged to obtain each stage result. REGISTER The decimation process reduces the amount of noise present in Figure 22. Analog Front-End Offset Control the final CDC result. However, the higher the decimation rate, CONVERSION SEQUENCER the lower the output rate per stage thus, a trade-off is possible between a noise free signal and speed of sampling. The AD7143 has an on-chip sequencer to implement conversion control for the input channels. Up to eight CAPACITANCE SENSOR OFFSET CONTROL conversion stages can be performed in sequence. Each of the There are two programmable DACs on board the AD7143 to eight conversion stages can measure an input from a different null any capacitance sensor offsets. These offsets are associated sensor. By using the Bank 2 registers, each stage can be uniquely with printed circuit board capacitance or capacitance due to any configured to support multiple capacitance sensor interface other source, such as connectors. In Figure 21, C is the IN requirements. For example, a sensor S1 can be assigned to capacitance of the input sensors, while C is the capacitance BULK STAGE1 and sensor S2 assigned to STAGE2. between layers of the sensor PCB. CBULK can be offset using the The AD7143 on-chip sequence controller provides conversion on-board DACs. control beginning with STAGE0. Figure 23 shows a block diagram of C IN the CDC conversion stages and CIN inputs. A conversion sequence is PLASTIC OVERLAY a sequence of CDC conversions starting at STAGE0 and ending at C BULK SENSOR BOARD the stage determined by the value programmed in the CAPACITIVE SENSOR SEQUENCE_STAGE_NUM register. Depending on the number and Figure 21. Capacitances Around the Sensor PCB type of capacitance sensors used, not all conversion stages are required. Use the SEQUENCE_STAGE_NUM register to set the number of conversions in one sequence, depending on the sensor interface requirements. For example, this register is set to 5 if the CIN inputs are mapped to only six stages. In addition, set the STAGE_CAL_EN registers according to the number of stages that are used. Rev. 0 | Page 14 of 56 06472-019 SENSOR 06472-020 AD7143 STAGE7 In this case, only one button from the pair is activated at a time; STAGE6 pressing both buttons together activates neither button. This STAGE5 example is shown in Figure 24 for sensor buttons S2 and S3. STAGE4 STAGE3 A scroll bar or slider requires eight stages. The result from each STAGE2 stage is used by the host software to determine the user’s STAGE1 position on the scroll bar. The algorithm that performs this STAGE0 process is available from Analog Devices free of charge, upon signing a software license. Scroll wheels also require eight stages. CIN0 CIN1 CDC CONVERSION SEQUENCE TIME CIN2 The time required for one complete measurement for all eight CIN3 Σ-Δ stages by the CDC is defined as the CDC conversion sequence 16-BIT ADC CIN4 time. The SEQUENCE_STAGE_NUM register and CIN5 DECIMATION register determine the conversion time as listed CIN6 in Table 8. CIN7 Table 8. CDC Conversion Times for Full Power Mode Conversion Time (ms) Figure 23. CDC Conversion Stages SEQUENCE_STAGE_NUM Decimation = 128 Decimation = 256 0 1.525 3.072 The number of required conversion stages depends completely 1 3.072 6.144 on the number of sensors attached to the AD7143. Figure 24 2 4.608 9.216 shows how many conversion stages are required for each sensor, 3 6.144 12.288 and how many inputs each sensor requires to the AD7143. 4 7.68 15.25 5 9.216 18.432 AD7143 6 10.752 21.504 SEQUENCER STAGE0 7 12.288 24.576 + 8-ELEMENT CDC – SLIDER For example, while operating with a decimation rate of 128, STAGE1 if the SEQUENCE_STAGE_NUM register is set to 5 for the + CDC – conversion of six stages in a sequence, the conversion sequence AD7143 STAGE2 time is 9.216 ms. SEQUENCER + BUTTONS CDC – STAGE0 S1 + Full Power Mode CDC Conversion Sequence Time STAGE3 CDC – + CDC – The full power mode CDC conversion sequence time for all STAGE1 S2 + STAGE4 CDC eight stages is set by configuring the SEQUENCE_STAGE_NUM – + CDC – register and the DECIMATION register as outlined in Table 8. S3 STAGE5 SRC + Figure 25 shows a simplified timing diagram of the full power CDC – CDC conversion time. The full power mode CDC conversion STAGE6 + is set using Table 8. CDC time tCONV_FP – STAGE7 SRC t CONV_FP + CDC – CDC CONVERSION CONVERSION CONVERSION CONVERSION SEQUENCE N SEQUENCE N + 1 SEQUENCE N + 2 Figure 24. Sequencer Setup for Sensors Figure 25. Full Power Mode CDC Conversion Sequence Time A button sensor generally requires one sequencer stage. However, it is possible to configure two button sensors to operate differentially for special applications where the user should not press both buttons simultaneously, such as a with rocker zoom switch on a digital camera. Rev. 0 | Page 15 of 56 CONVERSION SEQUENCE SWITCH MATRIX 06472-021 06472-022 06472-023 AD7143 Low Power Mode CDC Conversion Sequence Time Figure 26 shows a simplified timing example of the low power with Delay CDC conversion time. As shown, the low power CDC The frequency of each CDC conversion while operating in the conversion time is set by t and the LP_CONV_DELAY CONV_FP low power automatic wake-up mode is controlled by using the register. LP_CONV_DELAY register located at Address 0x000[3:2], in t CONV_LP addition to the registers listed in Table 8. t CONV_FP This feature provides some flexibility for optimizing the CDC CONVERSION CONVERSION LP_CONV_DELAY conversion time to meet system requirements vs. AD7143 CONVERSION SEQUENCE N SEQUENCE N + 1 power consumption. For example, maximum power savings is Figure 26. Low Power Mode CDC Conversion Sequence Time achieved when the LP_CONV_DELAY register is set to 3. With a setting of 3, the AD7143 automatically wakes up, performing a CDC CONVERSION RESULTS conversion every 800 ms. Certain high-resolution sensors require the host to read back the CDC conversion results for processing. The registers Table 9. LP_CONV_DELAY Settings required for host processing are located in the Bank 3 registers. LP_CONV_DELAY Bits Delay Between Conversions The host processes the data readback from these registers using 00 200 ms a software algorithm to determine position information. In 01 400 ms addition to the results registers in the Bank 3 registers, the 10 600 ms AD7143 provides the 16-bit CDC output data directly starting 11 800 ms at Address 0x00B of Bank 1. Reading back the CDC 16-bit conversion data register allows for customer-specific application data processing. Rev. 0 | Page 16 of 56 06472-024 AD7143 NONCONTACT PROXIMITY DETECTION The AD7143 internal signal processing continuously monitors timeout is controlled by FP_PROXIMITY_RECAL and in low all capacitance sensors for noncontact proximity detection. This power mode, it is controlled by LP_PROXMTY_RECAL. feature provides the ability to detect when a user is approaching Recalibration timeout in full power mode = a sensor, immediately disabling all internal calibration while the FP_PROXIMITY_RECAL × Time for one conversion AD7143 is automatically configured to detect a valid contact. sequence in full power mode The proximity control register bits are described in Table 10. Recalibration timeout in low power mode = FP_PROXIMITY_CNT register bits and LP_PROXIMITY LP_PROXIMITY_RECAL × Time taken for one conversion _CNT register bits control the length of the calibration disable sequence in low power mode period after proximity is detected in full power and low power modes. The calibration is disabled during this time and enabled Figure 29 and Figure 30 show examples of using the again at the end of this period if the user is no longer FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL approaching, or in contact with, the sensor. Figure 27 and Figure register bits to force a recalibration while operating in the full 28 show examples of how these registers are used to set the full and low power modes. These figures show the result of a user and low power mode calibration disable periods. approaching a sensor then leaving the sensor while the proximity detection remains active after the user discontinues Calibration disable period in full power mode = contact with the sensor. This situation could occur if the user (FP_PROXIMITY_CNT × 16 × Time for one conversion interaction created some moisture on the sensor causing the sequence in full power mode) new sensor value to be different from the expected value. In this Calibration disable period in low power mode = case, the internal recalibration is applied to automatically (LP_PROXIMITY_CNT × 4 × Time for one conversion recalibrate the sensor. The forced recalibration event takes two sequence in low power mode) interrupt cycles; therefore, it should not be set again during this interval. RECALIBRATION PROXIMITY SENSITIVITY In certain situations, the proximity flag can be set for a long period, such as when a user hovers over a sensor for a long The fast filter in Figure 31 is used to detect when some one is in time. The environmental calibration on the AD7143 is close proximity to the sensor. Two conditions set the internal suspended while the proximity is detected, but changes may proximity detection signal using Comparator 1 and Comparator 2. occur to the ambient capacitance level during the proximity Comparator 1 detects when a user is approaching a sensor. event. Even when the user has left the sensor untouched, the The PROXIMITY_DETECTION_RATE register controls the proximity flag may still be set. This could occur if the user sensitivity of Comparator 1. Consider, for example, if the interaction creates some moisture on the sensor causing the PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1 new sensor value to be different from the expected value. In this signal is set when the absolute difference between WORD1 and case, the AD7143 automatically forces an internal recalibration. WORD3 exceeds four LSB codes. This ensures that the ambient values are recalibrated, regardless of how long the user hovers over a sensor. Comparator 2 detects when a user hovers over a sensor or approaches a sensor very slowly. The PROXIMITY_RECAL_LVL The AD7143 recalibrates automatically when the measured CDC value register (Address 0x003) controls the sensitivity of Comparator 2. exceeds the stored ambient value by an amount determined by For example, if PROXIMITY_RECAL_LVL is set to 75, the PROXIMITY_RECAL_LVL, for a set period know as the Proximity 2 signal is set when the absolute difference between recalibration timeout. In full power mode, the recalibration the fast filter average value and the ambient value exceeds 75 LSB codes. Table 10. Proximity Control Registers (See Figure 31) Register Length Register Address Description FP_PROXIMITY_CNT 4 bits 0x002 [7:4] Calibration disable time in full power mode LP_PROXIMITY_CNT 4 bits 0x002 [11:8] Calibration disable time in low power mode FP_PROXIMITY_RECAL 8 bits 0x004 [9:0] Full power mode proximity recalibration control LP_PROXIMITY_RECAL 6 bits 0x004 [15:10] Low power mode proximity recalibration control PROXIMITY_RECAL_LVL 8 bits 0x003 [13:8] Proximity recalibration level PROXIMITY_DETECTION_RATE 6 bits 0x003 [7:0] Proximity detection rate Rev. 0 | Page 17 of 56 AD7143 USER APPROACHES USER LEAVES SENSOR SENSOR HERE AREA HERE t CONV_FP CDC CONVERSION 12 3456789 10111213141516 17 18 19 20 21 22 23 24 SEQUENCE (INTERNAL) t CALDIS PROXIMITY DETECTION (INTERNAL) CALIBRATION CALIBRATION DISABLED CALIBRATION ENABLED (INTERNAL) Figure 27. Full Power Mode Proximity Detection Example with FP_PROXIMITY_CNT = 1 USER APPROACHES USER LEAVES SENSOR SENSOR HERE AREA HERE t CONV_LP 12 3456789 10111213141516 17 18 19 20 21 22 23 24 CDC CONVERSION SEQUENCE (INTERNAL) t CALDIS PROXIMITY DETECTION (INTERNAL) CALIBRATION CALIBRATION DISABLED CALIBRATION ENABLED (INTERNAL) NOTES 1. SEQUENCE CONVERSION TIME t = t + LP_CONV_DELAY. CONV_LP CONV_FP 2. PROXIMITY IS SET WHEN USER APPROACHES THE SENSOR AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED. 3. t = (t × LP_PROXIMITY_CNT × 4). CALDIS CONV_LP Figure 28. Low Power Mode Proximity Detection with LP_PROXIMITY_CNT = 4 and LP_CONV_DELAY = 0 USER APPROACHES SENSOR HERE t RECAL MEASURED CDC VALUE > STORED AMBIENT USER LEAVES SENSOR BY PROXIMITY_RECAL _LVL AREA HERE t CONV_FP 16 30 70 CDC CONVERSION SEQUENCE (INTERNAL) t CALDIS PROXIMITY DETECTION (INTERNAL) CALIBRATION CALIBRATION DISABLED RECALIBRATION TIMEOUT CALIBRATION ENABLED (INTERNAL) t RECAL_TIMEOUT RECALIBRATION COUNTER (INTERNAL) NOTES 1. t = t × FP_PROXIMITY_CNT × 16. CALDIS CONV_FP 2. t = t × FP_PROXIMITY_RECAL. RECAL_TIMEOUT CONV_FP 3. t = 2 × t . RECAL CONV_FP Figure 29. Full Power Mode Proximity Detection with Forced Recalibration Example with FP_PROXIMIT_CNT = 1 and FP_PROXIMITY_RECAL = 40 Note that in Figure 29, the sequence conversion time, tCONV_FP, is determined from Table 8. Rev. 0 | Page 18 of 56 06472-026 06472-025 06472-027 AD7143 USER APPROACHES SENSOR HERE t RECAL MEASURED CDC VALUE > STORED AMBIENT USER LEAVES SENSOR BY PROXIMITY_RECAL _LVL AREA HERE t CONV_FP 16 30 70 CDC CONVERSION SEQUENCE (INTERNAL) PROXIMITY DETECTION t CALDIS (INTERNAL) CALIBRATION CALIBRATION DISABLED RECALIBRATION TIMEOUT CALIBRATION ENABLED (INTERNAL) t RECAL_TIMEOUT RECALIBRATION (INTERNAL) NOTES 1. SEQUENCE CONVERSION TIME t = t + LP_CONV_DELAY. CONV_LP CONV_FP 2. t = t × LP_PROXIMITY_CNT × 4. CALDIS CONV_LP 3. t = t × LP_PROXIMITY_RECAL. RECAL_TIMEOUT CONV_FP 4. t = 2 × t . RECAL CONV_LP Figure 30. Low Power Mode Proximity Detection with Forced Recalibration Example with LP_PROXIMIT_CNT = 4 and LP_PROXIMITY_RECAL = 10 FF_SKIP_CNT capacitance value tracks the measured capacitance value read by the converter. The proximity detection fast FIFO is used by the on-chip logic to determine if proximity is detected. The fast FIFO expects to Slow FIFO update rate in full power mode is equal to receive samples from the converter at a set rate. Using AVG_FP_SKIP × [(3 × Decimation Rate) × FF_SKIP_CNT normalizes the frequency of the samples going -7 (SEQUENCE_STAGE_NUM +1) × (FF_SKIP_CNT +1) × 4 × 10 ] into the FIFO, regardless of how many conversion stages are in a Slow FIFO update rate in low power mode is equal to sequence. In Register 0x02, Bits[3:0] are the fast filter skip control, FF_SKIP_CNT. This value determines which CDC samples are not (AVG_LP_SKIP +1) × [(3 × Decimation Rate) × used (skipped) in the proximity detection fast FIFO. -7 SEQUENCE_STAGE_NUM +1) × (FF_SKIP_CNT +1) × 4 × 10 ] / [(FF_SKIP_CNT +1)+ LP_CONV_DELAY] Determining the FF_SKIP_CNT value is required only once during the initial setup of the capacitance sensor interface. The slow FIFO is used by the on-chip logic to track the ambient capacitance value. The slow FIFO expects to receive samples Table 11 shows how FF_SKIP_CNT controls the update rate to from the converter at a rate of 33 ms to 40 ms. AVG_FP_SKIP the fast FIFO. The recommended value for FF_SKIP_CNT and AVG_LP_SKIP are used to normalize the frequency of the when using all 12 conversion stages on the AD7143 is samples going into the FIFO, regardless of how many conversion stages are in a sequence. FF_SKIP_CNT = 0000 = no samples skipped Determining the AVG_FP_SKIP and AVG_LP_SKIP value is SLOW FIFO only required once during the initial setup of the capacitance As shown in Figure 31, a number of FIFOs are implemented on sensor interface. Recommended values for these settings when the AD7143. These FIFOs are located in Bank 3 of the on-chip using all 12 conversion stages on the AD7143 are memory. The slow FIFOs are used by the on-chip logic to AVG_FP_SKIP = 00 = skip 3 samples monitor the ambient capacitance level from each sensor. AVG_LP_SKIP = 00 = no samples skipped AVG_FP_SKIP and AVG_LP_SKIP SLOW_FILTER_UPDATE_LVL In Register 0x001, Bits[13:12] are the slow FIFO skip control for The SLOW_FILTER_UPDATE_LVL controls whether or not full power mode, AVG_FP_SKIP. Bits[15:14] in the same the most recent CDC measurement goes into the slow FIFO register are the slow FIFO skip control for low power mode, (slow filter). The slow filter is updated when the difference AVG_LP_SKIP. These values determine which CDC samples between the current CDC value and last value pushed into the are not used (skipped) in the slow FIFO. Changing theses values slow FIFO is greater than SLOW_FILTER_UPDATE_LVL. This slows down or speeds up the rate at which the ambient variable is in Ambient Control Register 1, at Address 0x003. Rev. 0 | Page 19 of 56 06472-028 AD7143 Table 11. FF_SKIP_CNT Settings FAST FIFO Update Rate FF_SKIP_CNT Decimation = 128 Decimation = 256 0 1.525 × (SEQUENCE_STAGE_NUM + 1) ms 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 1 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 2 4.608 × (SEQUENCE_STAGE_NUM + 1) ms 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 3 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 4 7.68 × (SEQUENCE_STAGE_NUM + 1) ms 15.25 × (SEQUENCE_STAGE_NUM + 1) ms 5 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 18.432 × (SEQUENCE_STAGE_NUM + 1) ms 6 10.752 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms 7 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms 8 13.824 × (SEQUENCE_STAGE_NUM + 1) ms 27.648 × (SEQUENCE_STAGE_NUM + 1) ms 9 15.25 × (SEQUENCE_STAGE_NUM + 1) ms 30.72 × (SEQUENCE_STAGE_NUM + 1) ms 10 16.896 × (SEQUENCE_STAGE_NUM + 1) ms 33.792 × (SEQUENCE_STAGE_NUM + 1) ms 11 18.432 × (SEQUENCE_STAGE_NUM + 1) ms 25.864 × (SEQUENCE_STAGE_NUM + 1) ms 12 19.968 × (SEQUENCE_STAGE_NUM + 1) ms 39.925 × (SEQUENCE_STAGE_NUM + 1) ms 13 21.504 × (SEQUENCE_STAGE_NUM + 1) ms 43.008 × (SEQUENCE_STAGE_NUM + 1) ms 14 23.04 × (SEQUENCE_STAGE_NUM + 1) ms 46.08 × (SEQUENCE_STAGE_NUM + 1) ms 15 24.576 × (SEQUENCE_STAGE_NUM + 1) ms 49.152 × (SEQUENCE_STAGE_NUM + 1) ms Rev. 0 | Page 20 of 56 AD7143 FP_PROXIMITY_CNT LP_PROXIMITY_CNT 16 REGISTER 0x002 REGISTER 0x002 CDC STAGE_FF_WORD0 STAGE_FF_WORD1 PROXIMITY 1 PROXIMITY COMPARATOR 1 PROXIMITY TIMING |WORD0 TO WORD3| STAGE_FF_WORD2 CONTROL LOGIC STAGE_FF_WORD3 STAGE_FF_WORD4 STAGE_FF_WORD5 PROXIMITY_DETECTION_RATE REGISTER 0x003 FP_PROXIMITY_RECAL LP_PROXIMITY_RECAL STAGE_FF_WORD6 REGISTER 0x004 REGISTER 0x004 STAGE_FF_WORD7 BANK 3 REGISTERS 7 WORD(N) STAGE_FF_AVG Σ BANK 3 REGISTERS N = 0 8 COMPARATOR 2 |AVERAGE–AMBIENT| STAGE_FF_WORDx PROXIMITY SW1 SLOW_FILTER_EN PROXIMITY_RECAL_LVL STAGE_SF_WORD0 REGISTER 0x003 COMPARATOR 3 WORD0 TO WORD1 STAGE_SF_WORD1 AMBIENT STAGE_SF_AMBIENT STAGE_SF_WORD2 VALUE BANK 3 REGISTERS STAGE_SF_WORD3 STAGE_SF_WORDx SLOW_FILTER_UPDATE_LVL STAGE_SF_WORD4 SENSOR REGISTER 0x003 CONTACT STAGE_SF_WORD5 STAGE_SF_WORD6 TIME STAGE_SF_WORD7 NOTES 1. SLOW FILTER EN IS SET AND SW1 IS CLOSED WHEN |STAGE_SF_WORD 0 TO STAGE_SF_WORD 1| EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE_LVL REGISTER PROVIDING PROXIMITY IS NOT SET. |STAGE_FF_ | 2. PROXIMITY 1 IS SET WHEN WORD 0 TO STAGE_FF_WORD 3 EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_DETECTION_RATE REGISTER. 3. PROXIMITY 2 IS SET WHEN |AVERAGE–AMBIENT| EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER. 4. DESCRIPTION OF COMPARATOR FUNCTIONS: COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR. COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR, OR APPROACHING A SENSOR VERY SLOWLY. ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION. FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR. COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW FILTER EN IS SET AND PROXIMITY IS NOT SET. Figure 31. AD7143 Proximity Detection and Environmental Calibration STAGE_MAX_WORD0 STAGE_MAX_WORD1 BANK 3 REGISTERS STAGE_MAX_WORD2 STAGE_MAX_WORD3 STAGE_MAX_AVG Σ-Δ 16 MAX LEVEL 16-BIT DETECTION BANK 3 REGISTERS CDC LOGIC STAGE_MAX_TEMP BANK 3 REGISTERS STAGE_HIGH_THRESHOLD BANK 3 REGISTERS STAGE_MIN_WORD0 STAGE_MIN_WORD1 BANK 3 REGISTERS STAGE_MIN_WORD2 STAGE_MIN_WORD3 STAGE_MIN_AVG MIN LEVEL DETECTION BANK 3 REGISTERS LOGIC STAGE_MIN_AVG BANK 3 REGISTERS STAGE_LOW_THRESHOLD BANK 3 REGISTERS Figure 32. AD7143 Maximum and Minimum Level Detection Logic Rev. 0 | Page 21 of 56 PROXIMITY 2 CDC OUTPUT CODE 06472-048 06472-029 AD7143 ENVIRONMENTAL CALIBRATION SENSOR 1 INT The AD7143 provides on-chip capacitance sensor calibration to ASSERTED automatically adjust for environmental conditions that have an STAGE_HIGH_THRESHOLD effect on the capacitance sensor ambient levels. Capacitance sensor output levels are sensitive to temperature, humidity, and in some cases, dirt. The AD7143 achieves optimal and reliable CDC AMBIENT VALUE sensor performance by continuously monitoring the CDC ambient levels and correcting for any changes by adjusting the STAGE_HIGH_THRESHOLD and STAGE_LOW_THRESHOLD STAGE_LOW_THRESHOLD register values as described in Equation 1 and Equation 2. The SENSOR 2 INT ASSERTED CDC ambient level is defined as the capacitance sensor output level during periods when the user is not approaching or in t CHANGING ENVIRONMENTAL CONDITIONS contact with the sensor. Figure 33. Ideal Sensor Behavior with a Constant Ambient Level The compensation logic runs automatically on every conversion after configuration when the AD7143 is not being touched. This CAPACITANCE SENSOR BEHAVIOR WITHOUT allows the AD7143 to account for rapidly changing CALIBRATION environmental conditions. Figure 34 shows the typical behavior of a capacitance sensor with no applied calibration. This figure shows ambient levels The ambient compensation control registers located at drifting over time as environmental conditions change. The Address 0x002, Address 0x003 and Address 0x004 give the host ambient level drift has resulted in the detection of a missed user access to general setup and controls for the compensation contact on Sensor 2. algorithm. The RAM stores the compensation data for each conversion stage, as well as setup information specific to each stage. This is a result of the initial STAGE_LOW_THRESHOLD remaining constant while the ambient levels drifted upward Figure 33 shows an example of an ideal capacitance sensor beyond the detection range. The Capacitance Sensor Behavior behavior where the CDC ambient level remains constant with Calibration section describes how the AD7143 adaptive regardless of the environmental conditions. The CDC output calibration algorithm prevents errors such as this from shown is for a pair of differential button sensors, where one occurring. sensor caused an increase, and the other a decrease in measured capacitance when activated. SENSOR 1 INT ASSERTED STAGE_HIGH_THRESHOLD The positive and negative sensor threshold levels are calculated as a percentage of the STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values based on the threshold CCDC AMBIENT sensitivity settings and the ambient value. These values for this VALUE DRIFTING example are sufficient to detect a sensor contact, resulting with the AD7143 asserting the INT output when the threshold levels STAGE_LOW_THRESHOLD are exceeded. SENSOR 2 INT NOT ASSERTED t CHANGING ENVIRONMENTAL CONDITIONS Figure 34. Typical Sensor Behavior without Calibration Applied Rev. 0 | Page 22 of 56 CDC OUTPUT CODES CDC OUTPUT CODES 06472-030 06472-031 AD7143 SENSOR 1 INT CAPACITANCE SENSOR BEHAVIOR WITH ASSERTED 3 STAGE_HIGH_THRESHOLD CALIBRATION 2 (POST CALIBRATED REGISTER VALUE) 1 The AD7143 on-chip adaptive calibration algorithm prevents Figure 34. sensor detection errors, such as the one shown in This is achieved by monitoring the CDC ambient levels and CDC AMBIENT VALUE DRIFTING readjusting the initial STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values according to the amount of 6 5 STAGE_LOW_THRESHOLD ambient drift measured on each sensor. (POST CALIBRATED 4 REGISTER VALUE) The internal STAGE_HIGH_THRESHOLD and SENSOR 2 INT STAGE_LOW_THRESHOLD values, shown in Equation 1 and ASSERTED Equation 2, are automatically updated based on the new t CHANGING ENVIRONMENTAL CONDITIONS STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values. 1 This closed-loop routine ensures the reliability and repeatable INITIAL STAGE_OFFSET_HIGH REGISTER VALUE. 2 POST CALIBRATED REGISTER STAGE_HIGH_THRESHOLD. operation of every sensor connected to the AD7143 under 3 POST CALIBRATED REGISTER STAGE_HIGH_THRESHOLD. 4 INITIAL STAGE_LOW_THRESHOLD. dynamic environmental conditions. Figure 35 shows a 5 POST CALIBRATED REGISTER STAGE_LOW_THRESHOLD. 6 simplified example of how the AD7143 applies the adaptive POST CALIBRATED REGISTER STAGE_LOW_THRESHOLD. calibration process resulting in no interrupt errors under Figure 35. Typical Sensor Behavior with Calibration Applied on the Data Path changing CDC ambient levels due to environmental conditions. On-Chip Logic Stage High Threshold Calculation STAGE _ OFFSET _ HIGH ⎛ ⎞ STAGE _ HIGH _ THRESHOLD= STAGE _ SF _ AMBIENT+ + ⎜ ⎟ ⎝ 4 ⎠ STAGE _ OFFSET _ HIGH ⎛ ⎞ ⎛ ⎞ (1) STAGE _ OFFSET _ HIGH− ⎜⎜ ⎟⎟ ⎝ 4 ⎠ ⎜ ⎟ × POS _ THRESHOLD _ SENSITIVITY ⎜ 16 ⎟ ⎜ ⎟ ⎝ ⎠ On-Chip Logic Stage Low Threshold Calculation STAGE _ OFFSET _ LOW ⎛ ⎞ STAGE _ LOW _ THRESHOLD= STAGE _ SF _ AMBIENT+ + ⎜ ⎟ ⎝ 4 ⎠ STAGE _ OFFSET _ LOW ⎛⎛ ⎞⎞ (2) STAGE _ OFFSET _ LOW− ⎜⎜ ⎟⎟ ⎝ 4 ⎠ ⎜ ⎟ × NEG _ THRESHOLD _ SENSITIVITY ⎜ 16 ⎟ ⎜ ⎟ ⎝ ⎠ Rev. 0 | Page 23 of 56 CDC OUTPUT CODES 06472-032 AD7143 Table 12. Additional Information about Environmental Calibration and Adaptive Threshold Registers Register Location Description NEG_THRESHOLD_SENSITIVITY Bank 2 Used in Equation 2. This value is programmed once at start up. NEG_PEAK_DETECT Bank 2 Used by Internal Adaptive Threshold Logic Only. The NEG_PEAK_DETECT is set to a percentage of the difference between the ambient CDC value and the minimum average CDC value. If the output of the CDC gets within the NEG_PEAK_DETECT percentage of the minimum average, only then is the minimum average value updated. POS_THRESHOLD_SENSITIVITY Bank 2 Used in Equation 1. This value is programmed once at startup. POS_PEAK_DETECT Bank 2 Used by Internal Adaptive Threshold Logic Only. The POS_PEAK_DETECT is set to a percentage of the difference between the ambient CDC value, and the maximum average CDC value. If the output of the CDC gets within the POS_PEAK_DETECT percentage of the minimum average, only then is the maximum average value updated. STAGE_OFFSET_LOW Bank 2 Used in Equation 2. An initial value (based on sensor characterization) is programmed into this register at startup. The AD7143 on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set to 80% of the STAGE_OFFSET_LOW_CLAMP value. STAGE_OFFSET_HIGH Bank 2 Used in Equation 1. An initial value (based on sensor characterization) is programmed into this register at startup. The AD7143 on-chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set to 80% of the STAGE_OFFSET_HIGH_CLAMP value. STAGE_OFFSET_HIGH_CLAMP Bank 2 Used by Internal Environmental Calibration and Adaptive Threshold Algorithms Only. An initial value (based on sensor characterization) is programmed into this register at startup. The value in this register prevents a user from causing a sensor output value to exceed the expected nominal value. Set to the maximum expected sensor response, maximum change in CDC output code. STAGE_OFFSET_LOW_CLAMP Bank 2 Used by Internal Environmental Calibration and Adaptive Threshold Algorithms Only. An initial value (based on sensor characterization) is programmed into this register at startup. The value in this register prevents a user from causing a sensor output value to exceed the expected nominal value. Set to the minimum expected sensor response, minimum change in CDC output code . STAGE_SF_AMBIENT Bank 3 Used in Equation 1 and Equation 2. This is the ambient sensor output, when the sensor is not touched, as calculated using the slow FIFO. STAGE_HIGH_THRESHOLD Bank 3 Equation 1 Value. STAGE_LOW_THRESHOLD Bank 3 Equation 2 Value. Rev. 0 | Page 24 of 56 AD7143 ADAPTIVE THRESHOLD AND SENSITIVITY The AD7143 provides an on-chip self-learning adaptive On configuration, initial estimates are supplied for both threshold and sensitivity algorithm. This algorithm continu- STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW after ously monitors the output levels of each sensor and automatically which the calibration engine automatically adjusts the rescales the threshold levels proportionally to the sensor area STAGE_HIGH_THRESHOLD and STAGE_LOW_THRESHOLD covered by the user. As a result, the AD7143 maintains optimal values for sensor response. threshold and sensitivity levels for all types of users regardless Reference A in Figure 36 shows an under sensitive threshold of their finger sizes. level for a small finger user, demonstrating the disadvantages of The threshold level is always referenced from the ambient level a fixed threshold level. By enabling the adaptive threshold and and is defined as the CDC converter output level that must be sensitivity algorithm, the positive and negative threshold levels exceeded for a valid sensor contact. The sensitivity level is are determined by the POS_THRESHOLD_SENSITIVITY and defined as how sensitive the sensor is before a valid contact is NEG_THRESHOLD_SENSITIVITY register values and the registered. most recent average maximum sensor output value. These registers can be used to select 16 different positive and negative Figure 36 provides an example of how the adaptive threshold and sensitivity levels ranging between 25% and 95.32% of the most sensitivity algorithm works. The positive and negative sensor recent average maximum output level referenced from the threshold levels are calculated as a percentage of the ambient value. The smaller the sensitivity percentage setting, STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values the easier it is to trigger a sensor activation. Reference B shows based on the threshold sensitivity settings and the ambient value. that the positive adaptive threshold level is set at almost mid- sensitivity with a 62.51% threshold level by setting POS_THRESHOLD_SENSITIVITY = 1000. Figure 36 also provides a similar example for the negative threshold level with NEG_THRESHOLD_SENSITIVITY = 0001. AVERAGE MAX VALUE 95.32% STAGE_OFFSET_HIGH IS UPDATED AVERAGE MAX VALUE 62.51% = POS ADAPTIVE THRESHOLD LEVEL A STAGE_OFFSET_HIGH 95.32% STAGE_OFFSET_HIGH IS UPDATED HERE 62.51% = POS 25% ADAPTIVE THRESHOLD LEVEL 25% B AMBIENT LEVEL 25% NEG ADAPTIVE THRESHOLD LEVEL = 39.08% STAGE_OFFSET_LOW 25% IS UPDATED HERE STAGE_OFFSET_LOW NEG ADAPTIVE THRESHOLD LEVEL = 39.08% 95.32% STAGE_OFFSET_LOW IS UPDATED HERE 95.32% SENSOR CONTACTED SENSOR CONTACTED BY LARGE FINGER BY SMALL FINGER Figure 36. Threshold Sensitivity Example with POS_THRESHOLD_SENSITIVITY = 1000 and NEG_THRESHOLD_SENSITIVITY = 0011 Rev. 0 | Page 25 of 56 CDC OUTPUT CODES 06472-033 AD7143 INTERRUPT OUTPUT The AD7143 has an interrupt output that triggers an interrupt Configuring the AD7143 into this mode results in the interrupt service routine on the host processor. The INT signal is on being asserted when the user makes contact with the sensor and again when the user lifts off the sensor. The second interrupt is Pin 14, and is an open-drain output. There are two types of required to alert the host processor that the user is no longer interrupt events on the AD7143: a CDC conversion complete contacting the sensor. interrupt and a sensor touch interrupt. Each interrupt has enable and status registers described in Table 13. The The registers located at Address 0x005 and Address 0x006 are conversion complete and sensor threshold interrupts can be used to enable the interrupt output for each stage. The registers enabled on a per conversion stage basis. The status registers located at Address 0x008 and Address 0x009 are used to read indicate what type of interrupt triggered the INT pin. Status back the interrupt status for each stage. registers are cleared, and the INT signal is reset high, during a read operation of the interrupt status registers. The signal Figure 37 shows the interrupt output timing during contact with returns high as soon as the read address has been set up. one of the sensors connected to STAGE0 while operating in the sensor touch interrupt mode. For a low limit configuration, the CDC CONVERSION COMPLETE INTERRUPT interrupt output is asserted as soon as the sensor is contacted and The AD7143 interrupt signal asserts low to indicate the again after the user has stopped contacting the sensor. completion of a conversion stage, and new conversion result Note that the interrupt output remains low until the host data is available in the registers. processor reads back the interrupt status registers located at The interrupt can be independently enabled for each conversion Address 0x008 and Address 0x009. stage. Each conversion stage complete interrupt can be enabled The interrupt output is asserted when there is a change in the via the STAGE_COMPLETE_EN register (Address 0x007). This threshold status bits. This could indicate that a user is now register has a bit that corresponds to each conversion stage. touching the sensor(s) for the first time, the number of sensors Setting this bit to 1 enables the interrupt for that stage. Clearing being touched has changed, or the user is no longer touching this bit to 0 disables the conversion complete interrupt for that the sensor(s). Reading the status bits in the interrupt status stage. Figure 38 shows an end of conversion interrupt timing register shows the current sensor activations. with the STAGE0 interrupt enabled. FINGER ON SENSOR In normal operation, the AD7143’s interrupt is enabled only for FINGER OFF SENSOR 1 3 the last stage in a conversion sequence as shown in Figure 38. Register 0x00A is the conversion complete interrupt status CONVERSION STAGE0 STAGE1 STAGE register. Each bit in this register corresponds to a conversion stage. If a bit is set, it means that the conversion complete 2 4 interrupt for the corresponding stage was triggered. This register is cleared on a read, provided the underlying condition SERIAL READ BACK that triggered the interrupt has gone away. SENSOR TOUCH INTERRUPT INT OUTPUT 1 The sensor touch interrupt mode is implemented when the host USER TOUCHING DOWN ON SENSOR. 2 ADDRESS 0x008 READ BACK TO CLEAR INTERRUPT. 3 processor requires an interrupt only when a sensor is contacted. USER LIFTING OFF OF SENSOR. 4 ADDRESS 0x008 READ BACK TO CLEAR INTERRUPT. Figure 37. Example of Sensor Touch Interrupt Rev. 0 | Page 26 of 56 06472-034 AD7143 Table 13. Interrupt Mode Registers Interrupt Enable Interrupt Status Interrupt Mode Register Address Register Address Notes Sensor Touch Interrupt asserted when the user contacts a sensor. See Figure 37. Low 0x005 0x008 Enable for the CIN inputs connected to the CDC positive stage. High 0x006 0x009 Enable for the CIN inputs connected to the CDC negative stage. CDC Conversion Complete 0x007 0x00A Continuous interrupt at the end of each STAGEx that is enabled. STAGE0 STAGE1 STAGE2 STAGE3 STAGE4 STAGE5 STAGE6 STAGE7 STAGE8 STAGE9 STAGE10 STAGE11 STAGE0 STAGE1 CONVERSIONS INT 1 2 SERIAL READS NOTES 1. THIS IS AN EXAMPLE OF A CDC CONVERSION COMPLETE INTERRUPT. 2. THIS TIMING EXAMPLE SHOWS THAT THE INTERRUPT OUTPUT HAS BEEN ENABLED TO BE ASSERTED AT THE END OF A CONVERSION CYCLE FOR STAGE0 ONLY. 3. STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE5, AND STAGE9 (x = 0, 5, 9) STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0 STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0 STAGEx_COMPLETE_EN (ADDRESS 0x007) = 1 Figure 38. Example of Configuring the Registers for End of Conversion Interrupt Setup Rev. 0 | Page 27 of 56 06472-035 AD7143 SERIAL INTERFACE 2 The AD7143 is available with a fixed address I C-compatible All slave peripherals connected to the serial bus respond to the interface. start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit that determines the 2 I C COMPATIBLE INTERFACE direction of the data transfer. The peripheral whose address 2 The AD7143 supports the industry standard 2-wire I C serial corresponds to the transmitted address responds by pulling the 2 interface protocol. The two wires associated with the I C timing are data line low during the ninth clock pulse. This is known as the the SCLK and the SDA inputs. The SDA is an I/O pin that allows acknowledge bit. All other devices on the bus now remain idle both register write and register readback operations. The AD7143 is while the selected device waits for data to be read from, or 2 always a slave device on the I C serial interface bus. written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. The AD7143 has a single fixed 7-bit device address, Address 0101 110. The AD7143 responds when the master Data is sent over the serial bus in a sequence of nine clock device sends its device address over the bus. The AD7143 pulses, eight bits of data followed by an acknowledge bit from cannot initiate data transfers on the bus. the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the 2 Table 14. AD7143 I C Fixed Device Address high period, since a low-to-high transition when the clock is DEV DEV DEV DEV DEV DEV DEV high can be interpreted as a stop signal. The number of data A6 A5 A4 A3 A2 A1 A0 bytes transmitted over the serial bus in a single read or write 0 1 0 1 1 1 0 operation is limited only by what the master and slave devices can handle. Data Transfer 2 When all data bytes are read or written, a stop condition is Data is transferred over the I C serial interface in 8-bit bytes. established. A stop condition is defined by a low-to-high The master initiates a data transfer by establishing a start con- transition on SDA while SCLK remains high. If the AD7143 dition, defined as a high-to-low transition on the serial data encounters a stop condition, it returns to its idle condition, and line, SDA, while the serial clock line, SCLK, remains high. This the address pointer register resets to Address 0x00. indicates that an address/data stream follows. START AD7143 DEVICE ADDRESS REGISTER ADDRESS [A15:A8] REGISTER ADDRESS [A7:A0] SDA DEV DEV DEV DEV DEV DEV DEV R/W ACK A15 A14 A9 A8 ACK A7 A6 A1 A0 A6 A5 A4 A3 A2 A1 A0 t t 1 3 SCLK 1 23 4 5 678 910 11 16 17 18 19 20 25 26 t 2 STOP START REGISTER DATA [D15:D8] REGISTER DATA [D7:D0] AD7143 DEVICE ADDRESS t 8 DEV DEV DEV ACK D15 D14 D9 D8 ACK D7 D6 D1 D0 ACK A6 A5 A4 t t t t 6 7 4 5 12 3 27 28 29 34 35 36 37 38 43 44 45 46 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 1 0]. 4. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X ARE DON’T CARE BITS. 5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 2 Figure 39. Example of I C Timing for Single Register Write Operation Rev. 0 | Page 28 of 56 06472-036 AD7143 2 Writing Data over the I C Bus Any data written to the AD7143 after the address pointer has 2 The process for writing to the AD7143 over the I C bus is reached its maximum value is discarded. shown in Figure 39 and Figure 41. The device address is sent All registers on the AD7143 are 16-bit. Two consecutive 8-bit W over the bus followed by the R/ bit set to 0. This is followed data bytes are combined and written to the 16-bit registers. To by two bytes of data that contain the 10-bit address of the avoid errors, all writes to the device must contain an even internal data register to be written. The following bit map shows number of data bytes. the upper register address bytes. Note that Bit 7 to Bit 2 in the upper address byte are don’t care bits. The address is contained To finish the transaction, the master generates a stop condition in the 10 LSBs of the register address bytes. on SDA, or generates a repeat start condition if the master is to MSB LSB maintain control of the bus. 7 6 5 4 3 2 1 0 2 Reading Data over the I C Bus X X X X X X Register Register Address Address To read from the AD7143, the address pointer register must first Bit 9 Bit 8 be set to the address of the required internal register. The master performs a write transaction, and writes to the AD7143 to set the The following bit map shows the lower register address bytes. address pointer. The master then outputs a repeat start condition MSB LSB to keep control of the bus, or, if this is not possible, ends the write 7 6 5 4 3 2 1 0 transaction with a stop condition. A read transaction is initiated, Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. with the R/W bit set to 1. Addr. Addr. Addr. Addr. Addr. Addr. Addr. Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 The AD7143 supplies the upper eight bits of data from the addressed register in the first readback byte, followed by the The third data byte contains the 8 MSBs of the data to be lower eight bits in the next byte. This is shown in Figure 40 and written to the internal register. The fourth data byte contains Figure 41. the 8 LSBs of data to be written to the internal register. Because the address pointer automatically increases after each The AD7143 address pointer register automatically increments read, the AD7143 continues to output readback data until the after each write. This allows the master to sequentially write to all master puts a no acknowledge and stop condition on the bus. If registers on the AD7143 in the same write transaction. However, the address pointer reaches its maximum value, and the master the address pointer register does not wrap around after the last continues to read from the part, the AD7143 repeatedly sends address. data from the last register addressed. Rev. 0 | Page 29 of 56 AD7143 START AD7143 DEVICE ADDRESS REGISTER ADDRESS [A15:A8] REGISTER ADDRESS [A7:A0] SDA DEV DEV DEV DEV DEV DEV DEV R/W ACK A15 A14 A9 A8 ACK A7 A6 A1 A0 ACK A6 A5 A4 A3 A2 A1 A0 t t 1 3 SCLK 1 234 5678 910 11 16 17 18 19 20 25 26 27 t 2 P AD7143 DEVICE ADDRESS REGISTER DATA [D7:D0] SR t AD7143 DEVICE ADDRESS 8 DEV DEV DEV DEV DEV DEV DEV D7 D6 D1 D0 ACK ACK R/W A6 A5 A1 A0 A6 A5 A4 USING t t t t 4 6 7 5 REPEATED START 12 3 34 35 36 37 38 39 44 45 46 28 29 30 AD7143 DEVICE ADDRESS REGISTER DATA [D7:D0] P P S DEV DEV DEV DEV D7 D6 D1 D0 ACK ACK R/W A6 A5 A1 A0 SEPARATE READ AND t t 4 5 WRITE TRANSACTIONS 34 35 36 37 38 44 45 46 28 29 30 39 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA. 4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 1 0]. 5. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB Xs ARE DON’T CARE BITS. 6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY LOW ACK BITS. 7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT. 8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION. 2 Figure 40. Example of I C Timing for Single Register Readback Operation WRITE 7-BIT DEVICE REGISTER ADDR REGISTER ADDR WRITE DATA WRITE DATA WRITE DATA WRITE DATA S P W ADDRESS [15:8] [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] READ (USING REPEATED START) 7-BIT DEVICE REGISTER ADDR REGISTER ADDR 6-BIT DEVICE READ DATA READ DATA READ DATA READ DATA ACK P S W ADDRESS HIGH BYTE LOW BYTE ADDRESS HIGH BYTE [15:8] LOW BYTE [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS) 7-BIT DEVICE REGISTER ADDR REGISTER ADDR 6-BIT DEVICE READ DATA READ DATA READ DATA READ DATA S P S ACK P W ADDRESS HIGH BYTE LOW BYTE ADDRESS HIGH BYTE [15:8] LOW BYTE [7:0] HIGH BYTE [15:8] LOW BYTE [7:0] OUTPUT FROM MASTER S = START BIT ACK = ACKNOWLEDGE BIT P = STOP BIT ACK = NO ACKNOWLEDGE BIT OUTPUT FROM AD7143 SR = REPEATED START BIT 2 Figure 41. Example of Sequential I C Write and Readback Operation Rev. 0 | Page 30 of 56 ACK ACK ACK ACK ACK ACK ACK ACK ACK SR R ACK ACK R ACK ACK ACK ACK ACK ACK ACK 06472-038 06472-037 AD7143 PCB DESIGN GUIDELINES CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS Table 15. Parameter Symbol Min Typ Max Unit Distance from Edge of Any Sensor to Edge of Metal Object D1 1.0 mm 1 Distance Between Sensor Edges D2 = D3 = D4 0 mm 2 Distance Between Bottom of Sensor Board and Controller Board or Metal Casing (4-Layer, D 1.0 mm 5 2-Layer, and Flex Circuit) 1 The distance is dependent on the application and the positioning of the switches relative to each other and with respect to the user’s finger positioning and handling. Adjacent sensors, with 0 minimum space between them, are implemented differentially. 2 The 1.0 mm specification is meant to prevent direct sensor board contact with any conductive material. This specification does not guarantee no EMI coupling from the controller board to the sensors. Address potential EMI coupling issues by placing a grounded metal shield between the capacitive sensor board and the main controller board as shown in Figure 44. CAPACITIVE SENSOR BOARD D 5 METAL OBJECT CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING CAPACITIVE SENSOR PRINTED CIRCUIT Figure 44. Capacitive Sensor Board with Grounded Shield 8-WAY SWITCH CHIP SCALE PACKAGES The lands on the chip scale package (CP-16-13) are rectangular. D 4 SLIDER The printed circuit board pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. Center the land on the pad to maximize the solder joint size. BUTTONS D 3 The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least D 2 as large as this exposed pad. To avoid shorting, provide a clearance of at least 0.25 mm between the thermal pad and the D 1 inner edges of the land pattern on the printed circuit board. Thermal vias can be used on the printed circuit board thermal Figure 42. Capacitive Sensor Board Mechanicals Top View pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm CAPACITIVE SENSOR BOARD and 0.33 mm, and the via barrel should be plated with 1 oz. D 5 copper to plug the via. GROUNDED METAL SHIELD Connect the printed circuit board thermal pad to GND. CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING Figure 43. Capacitive Sensor Board Mechanicals Side View Rev. 0 | Page 31 of 56 06472-040 06472-039 06472-041 AD7143 POWER-UP SEQUENCE When the AD7143 is powered up, the following sequence is Register values: recommended when initially developing the AD7143 and Address 0x000 = 0x00B2 Host μC serial interface: Address 0x001 = 0x0000 1. Turn on the power supplies to the AD7143. Address 0x002 = 0x0690 2. Write to the Bank 2 registers at Address 0x080 through Address 0x0DF. These registers are contiguous, so a Address 0x003 = 0x0664 sequential register write sequence can be applied. Address 0x004 = 0x290F Note: The Bank 2 register values are unique for each Address 0x005 = 0x0000 application. Register values are provided by Analog Devices after the sensor board has been developed. Address 0x006 = 0x0000 3. Write to the Bank 1 registers at Address 0x000 through Address 0x007 = 0x0001 (The AD7143 interrupt is asserted Address 0x007 as outlined below. These registers are approximately every 25 ms.) contiguous so a sequential register write sequence can be applied 4. Write to the Bank 1 register, Address 0x001 = 0x0FFF. Caution: At this time, Address 0x001 must remain set to 5. Read back the corresponding interrupt status register at default value 0x0000 during this contiguous write Address 0x008, Address 0x009, or Address 0x00A. This is operation. determined by the interrupt output configuration as explained in the Interrupt Output section. Note: The specific registers required to be readback depend on each application. Analog Devices provides this information after the sensor board has been developed. 6. Repeat Step 5 each time INT is asserted. POWER HOST SERIAL INTERFACE CONVERSION CONVERSION STAGES DISABLED 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 910 11 0 1 2 910 11 0 1 STAGE AD7143 INT SECOND CONVERSION THIRD CONVERSION FIRST CONVERSION SEQUENCE SEQUENCE SEQUENCE Figure 45. Recommended Start-Up Sequence Rev. 0 | Page 32 of 56 06472-042 AD7143 TYPICAL APPLICATION CIRCUITS VDRIVE 2.2kΩ 2.2kΩ 2.2kΩ INT SCLK HOST WITH 2 I C INTERFACE V SDA 12 1CIN2 SDA HOST 2CIN3 VDRIVE 11 SCROLL AD7143 WHEEL OPTIONAL 3CIN4 GND 10 2 I C INTERFACE VOLTAGE VCC 4CIN5 VCC 9 (1.65V TO 3.6V) 2.7V TO 3.6V 0.1µF 1µF TO 10µF SENSOR PCB (OPTIONAL) 10nF 2 Figure 46. Typical Application Circuit with I C Interface Rev. 0 | Page 33 of 56 RECOMMENDED TO CONNECT FLOODED PLANE AROUND SENSORS TO GROUND 06472-043 5 CIN6 CIN1 16 6 CIN7 CIN0 15 7 CSHIELD INT 14 8 SRC SCLK 13 AD7143 REGISTER MAP The AD7143 address space is divided into three different Bank 3 registers contains the results of each conversion stage. register banks, referred to as Bank 1, Bank 2, and Bank 3. These registers automatically update at the end of each conversion Figure 47 illustrates the division of these three banks. sequence. Although these registers are primarily used by the AD7143 internal data processing, they are accessible by the host Bank 1 registers contain control registers, CDC conversion processor for additional external data processing, if desired. control registers, interrupt enable registers, interrupt status registers, CDC 16-bit conversion data registers, device ID Default values are undefined for Bank 2 registers and Bank 3 registers, and proximity status registers. registers until after power up and configuration of the Bank 2 registers. Bank 2 registers contain the configuration registers used for uniquely configuring the CIN inputs for each conversion stage. Initialize the Bank 2 configuration registers immediately after power-up to obtain valid CDC conversion result data. REGISTER BANK 1 REGISTER BANK 2 REGISTER BANK 3 ADDR 0x000 ADDR 0x080 ADDR 0x0E0 STAGE0 CONFIGURATION STAGE0 RESULTS SET UP CONTROL (8 REGISTERS) (36 REGISTERS) (1 REGISTER) ADDR 0x088 ADDR 0x088 ADDR 0x001 STAGE1 CONFIGURATION STAGE1 RESULTS (8 REGISTERS) (36 REGISTERS) CALIBRATION AND SET UP ADDR 0x090 ADDR 0x090 (4 REGISTERS) STAGE2 CONFIGURATION STAGE2 RESULTS (8 REGISTERS) (36 REGISTERS) ADDR 0x005 ADDR 0x098 ADDR 0x098 STAGE3 CONFIGURATION STAGE3 RESULTS INTERRUPT ENABLE (8 REGISTERS) (36 REGISTERS) (3 REGISTERS) ADDR 0x0A0 ADDR 0x0A0 STAGE4 CONFIGURATION STAGE4 RESULTS ADDR 0x008 (8 REGISTERS) (36 REGISTERS) INTERRUPT STATUS ADDR 0x0A8 ADDR 0x0A8 (3 REGISTERS) STAGE5 CONFIGURATION STAGE5 RESULTS (8 REGISTERS) (36 REGISTERS) ADDR 0x00B ADDR 0x0B0 ADDR 0x0B0 CDC 16-BIT CONVERSION DATA STAGE6 CONFIGURATION STAGE6 RESULTS (8 REGISTERS) (8 REGISTERS) (36 REGISTERS) ADDR 0x013 ADDR 0x0B8 ADDR 0x0B8 STAGE7 CONFIGURATION STAGE7 RESULTS UNUSED (4 REGISTERS) (8 REGISTERS) (36 REGISTERS) ADDR 0x017 DEVICE ID REGISTER ADDR 0x018 INVALID DO NOT ACCESS ADDR 0x042 PROXIMITY STATUS REGISTER ADDR 0x043 INVALID DO NOT ACCESS ADDR 0x7F0 Figure 47. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers Rev. 0 | Page 34 of 56 24 REGISTERS 64 REGISTERS 288 REGISTERS 06472-044 AD7143 DETAILED REGISTER DESCRIPTIONS BANK 1 REGISTERS All addresses and default values are expressed in hexadecimal format. Table 16. PWR_CONTROL Register Address Data Bit Default Type Name Description 0x000 [1:0] 0 R/W POWER_MODE Operating modes 00 = full power mode (normal operation, CDC conversions approximately every 25 ms) 01 = full shutdown mode (no CDC conversions) 10 = low power mode (automatic wake-up operation) 11 = full shutdown mode (no CDC conversions) [3:2] 0 LP_CONV_DELAY Low power mode conversion delay 00 = 200 ms 01 = 400 ms 10 = 600 ms 11 = 800 ms [7:4] 0 SEQUENCE_STAGE_NUM Number of stages in sequence (N + 1) 0000 = 1 conversion stage in sequence 0001 = 2 conversion stages in sequence …… Maximum value = 1011 = 12 conversion stages per sequence [9:8] 0 DECIMATION ADC decimation factor 00 = decimate by 256 01 = decimate by 128 10 = do not use this setting 11 = do not use this setting [10] 0 SW_RESET Software reset control (self-clearing) 1 = resets all registers to default values [11] 0 INT_POL Interrupt polarity control 0 = active low 1 = active high [12] 0 EXCITATION_SOURCE Excitation source control for Pin 15 0 = enable output 1 = disable output [13] 0 Unused Set unused register bits = 0 [15:14] 0 CDC_BIAS CDC bias current control 00 = normal operation 01 = normal operation + 20% 10 = normal operation + 35% 11 = normal operation + 50% Rev. 0 | Page 35 of 56 AD7143 Table 17. STAGE_CAL_EN Register Address Data Bit Default Type Name Description 0x001 [0] 0 R/W STAGE0_CAL_EN STAGE0 calibration enable 0 = disable 1 = enable [1] 0 STAGE1_CAL_EN STAGE1 calibration enable 0 = disable 1 = enable [2] 0 STAGE2_CAL_EN STAGE2 calibration enable 0 = disable 1 = enable [3] 0 STAGE3_CAL_EN STAGE3 calibration enable 0 = disable 1 = enable [4] 0 STAGE4_CAL_EN STAGE4 calibration enable 0 = disable 1 = enable [5] 0 STAGE5_CAL_EN STAGE5 calibration enable 0 = disable 1 = enable [6] 0 STAGE6_CAL_EN STAGE6 calibration enable 0 = disable 1 = enable [7] 0 STAGE7_CAL_EN STAGE7 calibration enable 0 = disable 1 = enable [11:8] 0 Unused Set unused register bits = 0 [13:12] 0 AVG_FP_SKIP Full power mode skip control 00 = skip 3 samples 01 = skip 7 samples 10 = skip 15 samples 11 = skip 31 samples [15:14] 0 AVG_LP_SKIP Low power mode skip control 00 = use all samples 01 = skip 1 sample 10 = skip 2 samples 11 = skip 3 samples Rev. 0 | Page 36 of 56 AD7143 Table 18. AMB_COMP_CTRL0 Register Address Data Bit Default Type Name Description 0x002 [3:0] 0 R/W FF_SKIP_CNT Fast filter skip control (N+1) 0000 = no sequence of results are skipped 0001 = one sequence of results is skipped for every one allowed into Fast FIFO 0010 = two sequences of results are skipped for every one allowed into Fast FIFO 1011 = maximum value = 12 sequences of results are skipped for every one allowed into Fast FIFO [7:4] F FP_PROXIMITY_CNT Full power mode proximity period [11:8] F LP_PROXIMITY_CNT Low power mode proximity period [13:12] 0 PWR_DOWN_TIMEOUT Full power to low power mode time out control 00 = 1.25 × (FP_PROXIMITY_CNT) 01 = 1.50 × (FP_PROXIMITY_CNT) 10 = 1.75 × (FP_PROXIMITY_CNT) 11 = 2.00 × (FP_PROXIMITY_CNT) [14] 0 FORCED_CAL Forced calibration control 0 = normal operation 1 = forces all conversion stages to recalibrate [15] 0 CONV_RESET Conversion reset control (self-clearing) 0 = normal operation 1 = resets the conversion sequence back to STAGE0 Table 19. AMB_COMP_CTRL1 Register Address Data Bit Default Type Name Description 0x003 [7:0] 64 R/W PROXIMITY_RECAL_LVL Proximity recalibration level [13:8] 1 PROXIMITY_DETECTION_RATE Proximity detection rate [15:14] 0 SLOW_FILTER_UPDATE_LVL Slow filter update level Table 20. AMB_COMP_CTRL2 Register Address Data Bit Default Type Name Description 0x004 [9:0] 3FF R/W FP_PROXIMITY_RECAL Full power mode proximity recalibration time control [15:10] 3F LP_PROXIMITY_RECAL Low power mode proximity recalibration time control Rev. 0 | Page 37 of 56 AD7143 Table 21. STAGE_LOW_INT_EN Register Address Data Bit Default Type Name Description 0x005 [0] 0 R/W STAGE0_LOW_INT_EN STAGE0 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded [1] 0 STAGE1_LOW_INT_EN STAGE1 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded [2] 0 STAGE2_LOW_INT_EN STAGE2 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded [3] 0 STAGE3_LOW_INT_EN STAGE3 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded [4] 0 STAGE4_LOW_INT_EN STAGE4 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded [5] 0 STAGE5_LOW_INT_EN STAGE5 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded [6] 0 STAGE6_LOW_INT_EN STAGE6 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded [7] 0 STAGE7_LOW_INT_EN STAGE7 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded [11:8] 0 Unused Set unused register bits = 0 [15:12] 0 TESTMODE Set test mode register bits = 0 (at all times) Rev. 0 | Page 38 of 56 AD7143 Table 22. STAGE_HIGH_INT_EN Register Address Data Bit Default Type Name Description 0x006 [0] 0 R/W STAGE0_HIGH_INT_EN STAGE0 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded [1] 0 STAGE1_HIGH_INT_EN STAGE1 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded [2] 0 STAGE2_HIGH_INT_EN STAGE2 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded [3] 0 STAGE3_HIGH_INT_EN STAGE3 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded [4] 0 STAGE4_HIGH_INT_EN STAGE4 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded [5] 0 STAGE5_HIGH_INT_EN STAGE5 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded [6] 0 STAGE6_HIGH_INT_EN STAGE6 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded [7] 0 STAGE7_HIGH_INT_EN STAGE7 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded [15:8] Unused Set unused register bits = 0 Rev. 0 | Page 39 of 56 AD7143 Table 23. STAGE_COMPLETE_INT_EN Register Address Data Bit Default Type Name Description 0x007 [0] 0 R/W STAGE0_COMPLETE_EN STAGE0 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE0 conversion [1] 0 STAGE1_COMPLETE_EN STAGE1 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE1 conversion [2] 0 STAGE2_COMPLETE_EN STAGE2 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE2 conversion [3] 0 STAGE3_COMPLETE_EN STAGE3 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE3 conversion [4] 0 STAGE4_COMPLETE_EN STAGE4 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE4 conversion [5] 0 STAGE5_COMPLETE_EN STAGE5 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE5 conversion [6] 0 STAGE6_COMPLETE_EN STAGE6 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE6 conversion [7] 0 STAGE7_COMPLETE_EN STAGE7 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE7 conversion [11:8] 0 Unused Set unused register bits = 0 [12] 0 TESTMODE Set test mode register bits = 0 at all times [15:13] Unused Set unused register bits = 0 1 Table 24. STAGE_LOW_LIMIT_INT Register Address Data Bit Default Type Name Description 0x008 [0] 0 R STAGE0_LOW_LIMIT_INT STAGE0 CDC conversion low limit interrupt result 1 indicates STAGE0_LOW_THRESHOLD value exceeded [1] 0 STAGE1_LOW_LIMIT_INT STAGE1 CDC conversion low limit interrupt result 1 indicates STAGE1_LOW_THRESHOLD value exceeded [2] 0 STAGE2_LOW_LIMIT_INT STAGE2 CDC conversion low limit interrupt result 1 indicates STAGE2_LOW_THRESHOLD value exceeded [3] 0 STAGE3_LOW_LIMIT_INT STAGE3 CDC conversion low limit interrupt result 1 indicates STAGE3_LOW_THRESHOLD value exceeded [4] 0 STAGE4_LOW_LIMIT_INT STAGE4 CDC conversion low limit interrupt result 1 indicates STAGE4_LOW_THRESHOLD value exceeded [5] 0 STAGE5_LOW_LIMIT_INT STAGE5 CDC conversion low limit interrupt result 1 indicates STAGE5_LOW_THRESHOLD value exceeded [6] 0 STAGE6_LOW_LIMIT_INT STAGE6 CDC conversion low limit interrupt result 1 indicates STAGE6_LOW_THRESHOLD value exceeded [7] 0 STAGE7_LOW_LIMIT_INT STAGE7 CDC conversion low limit interrupt result 1 indicates STAGE7_LOW_THRESHOLD value exceeded [15:8] Unused Set unused register bits = 0 1 Registers self-clear to 0 after readback, provided that the limits are not exceeded. Rev. 0 | Page 40 of 56 AD7143 1 Table 25. STAGE_HIGH_LIMIT_INT Register Address Data Bit Default Type Name Description 0x009 [0] 0 R STAGE0_HIGH_LIMIT_INT STAGE0 CDC conversion high limit interrupt result 1 indicates STAGE0_HIGH_THRESHOLD value exceeded [1] 0 STAGE1_HIGH_LIMIT_INT STAGE1 CDC conversion high limit interrupt result 1 indicates STAGE1_HIGH_THRESHOLD value exceeded [2] 0 STAGE2_HIGH_LIMIT_INT Stage2 CDC conversion high limit interrupt result 1 indicates STAGE2_HIGH_THRESHOLD value exceeded [3] 0 STAGE3_HIGH_LIMIT_INT STAGE3 CDC conversion high limit interrupt result 1 indicates STAGE3_HIGH_THRESHOLD value exceeded [4] 0 STAGE4_HIGH_LIMIT_INT STAGE4 CDC conversion high limit interrupt result 1 indicates STAGE4_HIGH_THRESHOLD value exceeded [5] 0 STAGE5_HIGH_LIMIT_INT STAGE5 CDC conversion high limit interrupt result 1 indicates STAGE5_HIGH_THRESHOLD value exceeded [6] 0 STAGE6_HIGH_LIMIT_INT STAGE6 CDC conversion high limit interrupt result 1 indicates STAGE6_HIGH_THRESHOLD value exceeded [7] 0 STAGE7_HIGH_LIMIT_INT STAGE7 CDC conversion high limit interrupt result 1 indicates STAGE7_HIGH_THRESHOLD value exceeded [15:8] Unused Set unused register bits = 0 1 Registers self-clear to 0 after readback, provided that the limits are not exceeded. 1 Table 26. STAGE_COMPLETE_LIMIT_INT Register Address Data Bit Default Type Name Description 0x00A [0] 0 R STAGE0_COMPLETE_STATUS_INT STAGE0 conversion complete register interrupt status 1 indicates STAGE0 conversion completed [1] 0 STAGE1_COMPLETE_STATUS_INT STAGE1 conversion complete register interrupt status 1 indicates STAGE0 conversion completed [2] 0 STAGE2_COMPLETE_STATUS_INT STAGE2 conversion complete register interrupt status 1 indicates STAGE0 conversion completed [3] 0 STAGE3_COMPLETE_STATUS_INT STAGE3 conversion complete register interrupt status 1 indicates STAGE0 conversion completed [4] 0 STAGE4_COMPLETE_STATUS_INT STAGE4 conversion complete register interrupt status 1 indicates STAGE0 conversion completed [5] 0 STAGE5_COMPLETE_STATUS_INT STAGE5 conversion complete register interrupt status 1 indicates STAGE0 conversion completed [6] 0 STAGE6_COMPLETE_STATUS_INT STAGE6 conversion complete register interrupt status 1 indicates STAGE0 conversion completed [7] 0 STAGE7_COMPLETE_STATUS_INT STAGE7 conversion complete register interrupt status 1 indicates STAGE0 conversion completed [15:8] 0 Unused 1 Registers self-clear to 0 after readback, provided that the limits are not exceeded. Rev. 0 | Page 41 of 56 AD7143 Table 27. CDC 16-Bit Conversion Data Registers Address Data Bit Default Type Name Description 0x00B [15:0] 0 R ADC_RESULT_S0 STAGE0 CDC 16-bit conversion data 0x00C [15:0] 0 R ADC_RESULT_S1 STAGE1 CDC 16-bit conversion data 0x00D [15:0] 0 R ADC_RESULT_S2 STAGE2 CDC 16-bit conversion data 0x00E [15:0] 0 R ADC_RESULT_S3 STAGE3 CDC 16-bit conversion data 0x00F [15:0] 0 R ADC_RESULT_S4 STAGE4 CDC 16-bit conversion data 0x010 [15:0] 0 R ADC_RESULT_S5 STAGE5 CDC 16-bit conversion data 0x011 [15:0] 0 R ADC_RESULT_S6 STAGE6 CDC 16-bit conversion data 0x012 [15:0] 0 R ADC_RESULT_S7 STAGE7 CDC 16-bit conversion data Table 28. Device ID Register Address Data Bit Default Type Name Description 0x017 [3:0] 0 R REVISION_CODE AD7143 revision code [15:4] E63 DEVID AD7143 device ID = 0xE63 Table 29. Proximity Status Register Address Data Bit Default Type Name Description 0x042 [0] 0 R STAGE0_PROXIMITY_STATUS STAGE0 proximity status register 1 indicates proximity detected on STAGE0 [1] 0 R STAGE1_PROXIMITY_STATUS STAGE1 proximity status register 1 indicates proximity detected on STAGE1 [2] 0 R STAGE2_PROXIMITY_STATUS STAGE2 proximity status register 1 indicates proximity detected on STAGE2 [3] 0 R STAGE3_PROXIMITY_STATUS STAGE3 proximity status register 1 indicates proximity detected on STAGE3 [4] 0 R STAGE4_PROXIMITY_STATUS STAGE4 proximity status register 1 indicates proximity detected on STAGE4 [5] 0 R STAGE5_PROXIMITY_STATUS STAGE5 proximity status register 1 indicates proximity detected on STAGE5 [6] 0 R STAGE6_PROXIMITY_STATUS STAGE6 proximity status register 1 indicates proximity detected on STAGE6 [7] 0 R STAGE7_PROXIMITY_STATUS STAGE7 proximity status register 1 indicates proximity detected on STAGE7 [15:8] Unused Set unused register bits = 0 Rev. 0 | Page 42 of 56 AD7143 BANK 2 REGISTERS All address values are expressed in hexadecimal format. Table 30. STAGE0 Configuration Registers Address Data Bit Default Type Name Description 0x080 [15:0] X R/W STAGE0_CONNECTION[6:0] STAGE0 CIN(6:0) connection setup (see Table 38) 0x081 [15:0] X R/W STAGE0_CONNECTION 7 STAGE0 CIN7 connection setup (see Table 39) 0x082 [15:0] X R/W STAGE0_AFE_OFFSET STAGE0 AFE offset control (see Table 40) 0x083 [15:0] X R/W STAGE0_SENSITIVITY STAGE0 sensitivity control (see Table 41) 0x084 [15:0] X R/W STAGE0_OFFSET_LOW STAGE0 initial offset low value 0x085 [15:0] X R/W STAGE0_OFFSET_HIGH STAGE0 initial offset high value 0x086 [15:0] X R/W STAGE0_OFFSET_HIGH_CLAMP STAGE0 offset high clamp value 0x087 [15:0] X R/W STAGE0_OFFSET_LOW_CLAMP STAGE0 offset low clamp value Table 31. STAGE1 Configuration Registers Address Data Bit Default Type Name Description 0x088 [15:0] X R/W STAGE1_CONNECTION[6:0] STAGE1 CIN(6:0) connection setup (see Table 38) 0x089 [15:0] X R/W STAGE1_CONNECTION 7 STAGE1 CIN7 connection setup (see Table 39) 0x08A [15:0] X R/W STAGE1_AFE_OFFSET STAGE1 AFE offset control (see Table 40) 0x08B [15:0] X R/W STAGE1_SENSITIVITY STAGE1 sensitivity control (see Table 41) 0x08C [15:0] X R/W STAGE1_OFFSET_LOW STAGE1 initial offset low value 0x08D [15:0] X R/W STAGE1_OFFSET_HIGH STAGE1 initial offset high value 0x08E [15:0] X R/W STAGE1_OFFSET_HIGH_CLAMP STAGE1 offset high clamp value 0x08F [15:0] X R/W STAGE1_OFFSET_LOW_CLAMP STAGE1 offset low clamp value Table 32. STAGE2 Configuration Registers Address Data Bit Default Type Name Description 0x090 [15:0] X R/W STAGE2_CONNECTION[6:0] STAGE2 CIN(6:0) connection setup (see Table 38) 0x091 [15:0] X R/W STAGE2_CONNECTION 7 STAGE2 CIN7 connection setup (see Table 39) 0x092 [15:0] X R/W STAGE2_AFE_OFFSET STAGE2 AFE offset control (see Table 40) 0x093 [15:0] X R/W STAGE2_SENSITIVITY STAGE2 sensitivity control (see Table 41) 0x094 [15:0] X R/W STAGE2_OFFSET_LOW STAGE2 initial offset low value 0x095 [15:0] X R/W STAGE2_OFFSET_HIGH STAGE2 initial offset high value 0x096 [15:0] X R/W STAGE2_OFFSET_HIGH_CLAMP STAGE2 offset high clamp value 0x097 [15:0] X R/W STAGE2_OFFSET_LOW_CLAMP STAGE2 offset low clamp value Rev. 0 | Page 43 of 56 AD7143 Table 33. STAGE3 Configuration Registers Address Data Bit Default Type Name Description 0x098 [15:0] X R/W STAGE3_CONNECTION[6:0] STAGE3 CIN(6:0) connection setup (see Table 38) 0x099 [15:0] X R/W STAGE3_CONNECTION 7 STAGE3 CIN7 connection setup (see Table 39) 0x09A [15:0] X R/W STAGE3_AFE_OFFSET STAGE3 AFE offset control (see Table 40) 0x09B [15:0] X R/W STAGE3_SENSITIVITY STAGE3 sensitivity control (see Table 41) 0x09C [15:0] X R/W STAGE3_OFFSET_LOW STAGE3 initial offset low value 0x09D [15:0] X R/W STAGE3_OFFSET_HIGH STAGE3 initial offset high value 0x09E [15:0] X R/W STAGE3_OFFSET_HIGH_CLAMP STAGE3 offset high clamp value 0x09F [15:0] X R/W STAGE3_OFFSET_LOW_CLAMP STAGE3 offset low clamp value Table 34. STAGE4 Configuration Registers Address Data Bit Default Type Name Description 0x0A0 [15:0] X R/W STAGE4_CONNECTION[6:0] STAGE4 CIN(6:0) connection setup (see Table 38) 0x0A1 [15:0] X R/W STAGE4_CONNECTION 7 STAGE4 CIN7 connection setup (see Table 39) 0x0A2 [15:0] X R/W STAGE4_AFE_OFFSET STAGE4 AFE offset control (see Table 40) 0x0A3 [15:0] X R/W STAGE4_SENSITIVITY STAGE4 sensitivity control (see Table 41) 0x0A4 [15:0] X R/W STAGE4_OFFSET_LOW STAGE4 initial offset low value 0x0A5 [15:0] X R/W STAGE4_OFFSET_HIGH STAGE4 initial offset high value 0x0A6 [15:0] X R/W STAGE4_OFFSET_HIGH_CLAMP STAGE4 offset high clamp value 0x0A7 [15:0] X R/W STAGE4_OFFSET_LOW_CLAMP STAGE4 offset low clamp value Table 35. STAGE5 Configuration Registers Address Data Bit Default Type Name Description 0x0A8 [15:0] X R/W STAGE5_CONNECTION[6:0] STAGE5 CIN(6:0) connection setup (see Table 38) 0x0A9 [15:0] X R/W STAGE5_CONNECTION 7 STAGE5 CIN7 connection setup (see Table 39) 0x0AA [15:0] X R/W STAGE5_AFE_OFFSET STAGE5 AFE offset control (see Table 40) 0x0AB [15:0] X R/W STAGE5_SENSITIVITY STAGE5 sensitivity control (see Table 41) 0x0AC [15:0] X R/W STAGE5_OFFSET_LOW STAGE5 initial offset low value 0x0AD [15:0] X R/W STAGE5_OFFSET_HIGH STAGE5 initial offset high value 0x0AE [15:0] X R/W STAGE5_OFFSET_HIGH_CLAMP STAGE5 offset high clamp value 0x0AF [15:0] X R/W STAGE5_OFFSET_LOW_CLAMP STAGE5 offset low clamp value Table 36. STAGE6 Configuration Registers Address Data Bit Default Type Name Description 0x0B0 [15:0] X R/W STAGE6_CONNECTION[6:0] STAGE6 CIN(6:0) connection setup (see Table 38) 0x0B1 [15:0] X R/W STAGE6_CONNECTION 7 STAGE6 CIN7 connection setup (see Table 39) 0x0B2 [15:0] X R/W STAGE6_AFE_OFFSET STAGE6 AFE offset control (see Table 40) 0x0B3 [15:0] X R/W STAGE6_SENSITIVITY STAGE6 sensitivity control (see Table 41) 0x0B4 [15:0] X R/W STAGE6_OFFSET_LOW STAGE6 initial offset low value 0x0B5 [15:0] X R/W STAGE6_OFFSET_HIGH STAGE6 initial offset high value 0x0B6 [15:0] X R/W STAGE6_OFFSET_HIGH_CLAMP STAGE6 offset high clamp value 0x0B7 [15:0] X R/W STAGE6_OFFSET_LOW_CLAMP STAGE6 offset low clamp value Rev. 0 | Page 44 of 56 AD7143 Table 37. STAGE7 Configuration Registers Address Data Bit Default Type Name Description 0x0B8 [15:0] X R/W STAGE7_CONNECTION[6:0] STAGE7 CIN(6:0) connection setup (see Table 38) 0x0B9 [15:0] X R/W STAGE7_CONNECTION 7 STAGE7 CIN7 connection setup (see Table 39) 0x0BA [15:0] X R/W STAGE7_AFE_OFFSET STAGE7 AFE offset control (see Table 40) 0x0BB [15:0] X R/W STAGE7_SENSITIVITY STAGE7 sensitivity control (see Table 41) 0x0BC [15:0] X R/W STAGE7_OFFSET_LOW STAGE7 initial offset low value 0x0BD [15:0] X R/W STAGE7_OFFSET_HIGH STAGE7 initial offset high value 0x0BE [15:0] X R/W STAGE7_OFFSET_HIGH_CLAMP STAGE7 offset high clamp value 0x0BF [15:0] X R/W STAGE7_OFFSET_LOW_CLAMP STAGE7 offset low clamp value Table 38. STAGEX Detailed CIN (0:6) Connection Setup Description (X = 0 to 6) Data Bit Default Type Name Description [1:0] X R/W CIN0_CONNECTION_SETUP CIN0 connection setup 00 = CIN0 not connected to CDC inputs 01 = CIN0 connected to CDC negative input 10 = CIN0 connected to CDC positive input 11 = CIN0 connected to BIAS (connect unused CIN inputs) [3:2] X R/W CIN1_CONNECTION_SETUP CIN1 connection setup 00 = CIN1 not connected to CDC inputs 01 = CIN1 connected to CDC negative input 10 = CIN1 connected to CDC positive input 11 = CIN1 connected to BIAS (connect unused CIN inputs) [5:4] X R/W CIN2_CONNECTION_SETUP CIN2 connection setup 00 = CIN2 not connected to CDC inputs 01 = CIN2 connected to CDC negative input 10 = CIN2 connected to CDC positive input 11 = CIN2 connected to BIAS (connect unused CIN inputs) [7:6] X R/W CIN3_CONNECTION_SETUP CIN3 connection setup 00 = CIN3 not connected to CDC inputs 01 = CIN3 connected to CDC negative input 10 = CIN3 connected to CDC positive input 11 = CIN3 connected to BIAS (connect unused CIN inputs) [9:8] X R/W CIN4_CONNECTION_SETUP CIN4 connection setup 00 = CIN4 not connected to CDC inputs 01 = CIN4 connected to CDC negative input 10 = CIN4 connected to CDC positive input 11 = CIN4 connected to BIAS (connect unused CIN inputs) [11:10] X R/W CIN5_CONNECTION_SETUP CIN5 connection setup 00 = CIN5 not connected to CDC inputs 01 = CIN5 connected to CDC negative input 10 = CIN5 connected to CDC positive input 11 = CIN5 connected to BIAS (connect unused CIN inputs) [13:12] X R/W CIN6_CONNECTION_SETUP CIN6 connection setup 00 = CIN6 not connected to CDC inputs 01 = CIN6 connected to CDC negative input 10 = CIN6 connected to CDC positive input 11 = CIN6 connected to BIAS (connect unused CIN inputs) [15:14] X Unused Rev. 0 | Page 45 of 56 AD7143 Table 39. STAGEX Detailed CIN7 Connection Setup Description Data Bit Default Type Name Description [1:0] X R/W CIN7_CONNECTION_SETUP CIN7 connection setup 00 = CIN7 not connected to CDC inputs 01 = CIN7 connected to CDC negative input 10 = CIN7 connected to CDC positive input 11 = CIN7 connected to BIAS (connect unused CIN inputs) [13:2] X R/W Unused [14] X R/W NEG_AFE_OFFSET_DISABLE Negative AFE offset enable control 0 = enable 1 = disable [15] X R/W POS_AFE_OFFSET_DISABLE Positive AFE offset enable control 0 = enable 1 = disable Table 40. STAGEX Detailed Offset Control Description (X = 0 to 7) Data Bit Default Type Name Description [6:0] X R/W NEG_AFE_OFFSET Negative AFE offset setting (20 pF range) 1 LSB value = 0.16 pF of offset [7] X R/W NEG_AFE_OFFSET_SWAP Negative AFE offset swap control 0 = NEG_AFE_OFFSET applied to CDC negative input 1 = NEG_AFE_OFFSET applied to CDC positive input [14:8] X R/W POS_AFE_OFFSET Positive AFE offset setting (20 pF range) 1 LSB value = 0.16 pF of offset [15] X R/W POS_AFE_OFFSET_SWAP Positive AFE offset swap control 0 = POS_AFE_OFFSET applied to CDC positive input 1 = POS_AFE_OFFSET applied to CDC negative input Table 41. STAGEX Detailed Sensitivity Control Description (X = 0 to 7) Data Bit Default Type Name Description [3:0] X R/W NEG_THRESHOLD_SENSITIVITY Negative threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [6:4] X R/W NEG_PEAK_DETECT Negative peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [7] X R/W Unused [11:8] X R/W POS_THRESHOLD_SENSITIVITY Positive threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [14:12] X R/W POS_PEAK_DETECT Positive peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [15] X R/W Unused Rev. 0 | Page 46 of 56 AD7143 BANK 3 REGISTERS All address values are expressed in hexadecimal format. Table 42. STAGE0 Results Registers Address Data Bit Default Type Name Description 0x0E0 [15:0] X R/W STAGE0_CONV_DATA STAGE0 CDC 16-bit conversion data (copy of data in STAGE0_CONV_DATA register) 0x0E1 [15:0] X R/W STAGE0_FF_WORD0 STAGE0 fast FIFO WORD0 0x0E2 [15:0] X R/W STAGE0_FF_WORD1 STAGE0 fast FIFO WORD1 0x0E3 [15:0] X R/W STAGE0_FF_WORD2 STAGE0 fast FIFO WORD2 0x0E4 [15:0] X R/W STAGE0_FF_WORD3 STAGE0 fast FIFO WORD3 0x0E5 [15:0] X R/W STAGE0_FF_WORD4 STAGE0 fast FIFO WORD4 0x0E6 [15:0] X R/W STAGE0_FF_WORD5 STAGE0 fast FIFO WORD5 0x0E7 [15:0] X R/W STAGE0_FF_WORD6 STAGE0 fast FIFO WORD6 0x0E8 [15:0] X R/W STAGE0_FF_WORD7 STAGE0 fast FIFO WORD7 0x0E9 [15:0] X R/W STAGE0_SF_WORD0 STAGE0 slow FIFO WORD0 0x0EA [15:0] X R/W STAGE0_SF_WORD1 STAGE0 slow FIFO WORD1 0x0EB [15:0] X R/W STAGE0_SF_WORD2 STAGE0 slow FIFO WORD2 0x0EC [15:0] X R/W STAGE0_SF_WORD3 STAGE0 slow FIFO WORD3 0x0ED [15:0] X R/W STAGE0_SF_WORD4 STAGE0 slow FIFO WORD4 0x0EE [15:0] X R/W STAGE0_SF_WORD5 STAGE0 slow FIFO WORD5 0x0EF [15:0] X R/W STAGE0_SF_WORD6 STAGE0 slow FIFO WORD6 0x0F0 [15:0] X R/W STAGE0_SF_WORD7 STAGE0 slow FIFO WORD7 0x0F1 [15:0] X R/W STAGE0_SF_AMBIENT STAGE0 slow FIFO ambient value 0x0F2 [15:0] X R/W STAGE0_FF_AVG STAGE0 fast FIFO average value 0x0F3 [15:0] X R/W STAGE0_PEAK_DETECT_WORD0 STAGE0 peak FIFO WORD0 value 0x0F4 [15:0] X R/W STAGE0_PEAK_DETECT_WORD1 STAGE0 peak FIFO WORD1 value 0x0F5 [15:0] X R/W STAGE0_MAX_WORD0 STAGE0 maximum value FIFO WORD0 0x0F6 [15:0] X R/W STAGE0_MAX_WORD1 STAGE0 maximum value FIFO WORD1 0x0F7 [15:0] X R/W STAGE0_MAX_WORD2 STAGE0 maximum value FIFO WORD2 0x0F8 [15:0] X R/W STAGE0_MAX_WORD3 STAGE0 maximum value FIFO WORD3 0x0F9 [15:0] X R/W STAGE0_MAX_AVG STAGE0 average maximum FIFO value 0x0FA [15:0] X R/W STAGE0_HIGH_THRESHOLD STAGE0 high threshold value 0x0FB [15:0] X R/W STAGE0_MAX_TEMP STAGE0 temporary maximum value 0x0FC [15:0] X R/W STAGE0_MIN_WORD0 STAGE0 minimum value FIFO WORD0 0x0FD [15:0] X R/W STAGE0_MIN_WORD1 STAGE0 minimum value FIFO WORD1 0x0FE [15:0] X R/W STAGE0_MIN_WORD2 STAGE0 minimum value FIFO WORD2 0x0FF [15:0] X R/W STAGE0_MIN_WORD3 STAGE0 minimum value FIFO WORD3 0x100 [15:0] X R/W STAGE0_MIN_AVG STAGE0 average minimum FIFO value 0x101 [15:0] X R/W STAGE0_LOW_THRESHOLD STAGE0 low threshold value 0x102 [15:0] X R/W STAGE0_MIN_TEMP STAGE0 temporary minimum value 0x103 [15:0] X R/W Unused Rev. 0 | Page 47 of 56 AD7143 Table 43. STAGE1 Results Registers Address Data Bit Default Type Name Description 0x104 [15:0] X R/W STAGE1_CONV_DATA STAGE1 CDC 16-bit conversion data (copy of data in STAGE1_CONV_DATA register) 0x105 [15:0] X R/W STAGE1_FF_WORD0 STAGE1 fast FIFO WORD0 0x106 [15:0] X R/W STAGE1_FF_WORD1 STAGE1 fast FIFO WORD1 0x107 [15:0] X R/W STAGE1_FF_WORD2 STAGE1 fast FIFO WORD2 0x108 [15:0] X R/W STAGE1_FF_WORD3 STAGE1 fast FIFO WORD3 0x109 [15:0] X R/W STAGE1_FF_WORD4 STAGE1 fast FIFO WORD4 0x10A [15:0] X R/W STAGE1_FF_WORD5 STAGE1 fast FIFO WORD5 0x10B [15:0] X R/W STAGE1_FF_WORD6 STAGE1 fast FIFO WORD6 0x10C [15:0] X R/W STAGE1_FF_WORD7 STAGE1 fast FIFO WORD7 0x10D [15:0] X R/W STAGE1_SF_WORD0 STAGE1 slow FIFO WORD0 0x10E [15:0] X R/W STAGE1_SF_WORD1 STAGE1 slow FIFO WORD1 0x10F [15:0] X R/W STAGE1_SF_WORD2 STAGE1 slow FIFO WORD2 0x110 [15:0] X R/W STAGE1_SF_WORD3 STAGE1 slow FIFO WORD3 0x111 [15:0] X R/W STAGE1_SF_WORD4 STAGE1 slow FIFO WORD4 0x112 [15:0] X R/W STAGE1_SF_WORD5 STAGE1 slow FIFO WORD5 0x113 [15:0] X R/W STAGE1_SF_WORD6 STAGE1 slow FIFO WORD6 0x114 [15:0] X R/W STAGE1_SF_WORD7 STAGE1 slow FIFO WORD7 0x115 [15:0] X R/W STAGE1_SF_AMBIENT STAGE1 slow FIFO ambient value 0x116 [15:0] X R/W STAGE1_FF_AVG STAGE1 fast FIFO average value 0x117 [15:0] X R/W STAGE1_CDC_WORD0 STAGE1 CDC FIFO WORD0 0x118 [15:0] X R/W STAGE1_CDC_WORD1 STAGE1 CDC FIFO WORD1 0x119 [15:0] X R/W STAGE1_MAX_WORD0 STAGE1 maximum value FIFO WORD0 0x11A [15:0] X R/W STAGE1_MAX_WORD1 STAGE1 maximum value FIFO WORD1 0x11B [15:0] X R/W STAGE1_MAX_WORD2 STAGE1 maximum value FIFO WORD2 0x11C [15:0] X R/W STAGE1_MAX_WORD3 STAGE1 maximum value FIFO WORD3 0x11D [15:0] X R/W STAGE1_MAX_AVG STAGE1 average maximum FIFO value 0x11E [15:0] X R/W STAGE1_HIGH_THRESHOLD STAGE1 high threshold value 0x11F [15:0] X R/W STAGE1_MAX_TEMP STAGE1 temporary maximum value 0x120 [15:0] X R/W STAGE1_MIN_WORD0 STAGE1 minimum value FIFO WORD0 0x121 [15:0] X R/W STAGE1_MIN_WORD1 STAGE1 minimum value FIFO WORD1 0x122 [15:0] X R/W STAGE1_MIN_WORD2 STAGE1 minimum value FIFO WORD2 0x123 [15:0] X R/W STAGE1_MIN_WORD3 STAGE1 minimum value FIFO WORD3 0x124 [15:0] X R/W STAGE1_MIN_AVG STAGE1 average minimum FIFO value 0x125 [15:0] X R/W STAGE1_LOW_THRESHOLD STAGE1 low threshold value 0x126 [15:0] X R/W STAGE1_MIN_TEMP STAGE1 temporary minimum value 0x127 [15:0] X R/W Unused Rev. 0 | Page 48 of 56 AD7143 Table 44. STAGE2 Results Registers Address Data Bit Default Type Name Description 0x128 [15:0] X R/W STAGE2_CONV_DATA STAGE2 CDC 16-bit conversion data (copy of data in STAGE2_CONV_DATA register) 0x129 [15:0] X R/W STAGE2_FF_WORD0 STAGE2 fast FIFO WORD0 0x12A [15:0] X R/W STAGE2_FF_WORD1 STAGE2 fast FIFO WORD1 0x12B [15:0] X R/W STAGE2_FF_WORD2 STAGE2 fast FIFO WORD2 0x12C [15:0] X R/W STAGE2_FF_WORD3 STAGE2 fast FIFO WORD3 0x12D [15:0] X R/W STAGE2_FF_WORD4 STAGE2 fast FIFO WORD4 0x12E [15:0] X R/W STAGE2_FF_WORD5 STAGE2 fast FIFO WORD5 0x12F [15:0] X R/W STAGE2_FF_WORD6 STAGE2 fast FIFO WORD6 0x130 [15:0] X R/W STAGE2_FF_WORD7 STAGE2 fast FIFO WORD7 0x131 [15:0] X R/W STAGE2_SF_WORD0 STAGE2 slow FIFO WORD0 0x132 [15:0] X R/W STAGE2_SF_WORD1 STAGE2 slow FIFO WORD1 0x133 [15:0] X R/W STAGE2_SF_WORD2 STAGE2 slow FIFO WORD2 0x134 [15:0] X R/W STAGE2_SF_WORD3 STAGE2 slow FIFO WORD3 0x135 [15:0] X R/W STAGE2_SF_WORD4 STAGE2 slow FIFO WORD4 0x125 [15:0] X R/W STAGE2_SF_WORD5 STAGE2 slow FIFO WORD5 0x137 [15:0] X R/W STAGE2_SF_WORD6 STAGE2 slow FIFO WORD6 0x138 [15:0] X R/W STAGE2_SF_WORD7 STAGE2 slow FIFO WORD7 0x139 [15:0] X R/W STAGE2_SF_AMBIENT STAGE2 slow FIFO ambient value 0x13A [15:0] X R/W STAGE2_FF_AVG STAGE2 fast FIFO average value 0x13B [15:0] X R/W STAGE2_CDC_WORD0 STAGE2 CDC FIFO WORD0 0x13C [15:0] X R/W STAGE2_CDC_WORD1 STAGE2 CDC FIFO WORD1 0x13D [15:0] X R/W STAGE2_MAX_WORD0 STAGE2 maximum value FIFO WORD0 0x13E [15:0] X R/W STAGE2_MAX_WORD1 STAGE2 maximum value FIFO WORD1 0x13F [15:0] X R/W STAGE2_MAX_WORD2 STAGE2 maximum value FIFO WORD2 0x140 [15:0] X R/W STAGE2_MAX_WORD3 STAGE2 maximum value FIFO WORD3 0x141 [15:0] X R/W STAGE2_MAX_AVG STAGE2 average maximum FIFO value 0x142 [15:0] X R/W STAGE2_HIGH_THRESHOLD STAGE2 high threshold value 0x143 [15:0] X R/W STAGE2_MAX_TEMP STAGE2 temporary maximum value 0x144 [15:0] X R/W STAGE2_MIN_WORD0 STAGE2 minimum value FIFO WORD0 0x145 [15:0] X R/W STAGE2_MIN_WORD1 STAGE2 minimum value FIFO WORD1 0x146 [15:0] X R/W STAGE2_MIN_WORD2 STAGE2 minimum value FIFO WORD2 0x147 [15:0] X R/W STAGE2_MIN_WORD3 STAGE2 minimum value FIFO WORD3 0x148 [15:0] X R/W STAGE2_MIN_AVG STAGE2 average minimum FIFO value 0x149 [15:0] X R/W STAGE2_LOW_THRESHOLD STAGE2 low threshold value 0x14A [15:0] X R/W STAGE2_MIN_TEMP STAGE2 temporary minimum value 0x14B [15:0] X R/W Unused Rev. 0 | Page 49 of 56 AD7143 Table 45. STAGE3 Results Registers Address Data Bit Default Type Name Description 0x14C [15:0] X R/W STAGE3_CONV_DATA STAGE3 CDC 16-bit conversion data (copy of data in STAGE3_CONV_DATA register) 0x14D [15:0] X R/W STAGE3_FF_WORD0 STAGE3 fast FIFO WORD0 0x14E [15:0] X R/W STAGE3_FF_WORD1 STAGE3 fast FIFO WORD1 0x14F [15:0] X R/W STAGE3_FF_WORD2 STAGE3 fast FIFO WORD2 0x150 [15:0] X R/W STAGE3_FF_WORD3 STAGE3 fast FIFO WORD3 0x151 [15:0] X R/W STAGE3_FF_WORD4 STAGE3 fast FIFO WORD4 0x152 [15:0] X R/W STAGE3_FF_WORD5 STAGE3 fast FIFO WORD5 0x153 [15:0] X R/W STAGE3_FF_WORD6 STAGE3 fast FIFO WORD6 0x154 [15:0] X R/W STAGE3_FF_WORD7 STAGE3 fast FIFO WORD7 0x155 [15:0] X R/W STAGE3_SF_WORD0 STAGE3 slow FIFO WORD0 0x156 [15:0] X R/W STAGE3_SF_WORD1 STAGE3 slow FIFO WORD1 0x157 [15:0] X R/W STAGE3_SF_WORD2 STAGE3 slow FIFO WORD2 0x158 [15:0] X R/W STAGE3_SF_WORD3 STAGE3 slow FIFO WORD3 0x159 [15:0] X R/W STAGE3_SF_WORD4 STAGE3 slow FIFO WORD4 0x15A [15:0] X R/W STAGE3_SF_WORD5 STAGE3 slow FIFO WORD5 0x15B [15:0] X R/W STAGE3_SF_WORD6 STAGE3 slow FIFO WORD6 0x15C [15:0] X R/W STAGE3_SF_WORD7 STAGE3 slow FIFO WORD7 0x15D [15:0] X R/W STAGE3_SF_AMBIENT STAGE3 slow FIFO ambient value 0x15E [15:0] X R/W STAGE3_FF_AVG STAGE3 fast FIFO average value 0x15F [15:0] X R/W STAGE3_CDC_WORD0 STAGE3 CDC FIFO WORD0 0x160 [15:0] X R/W STAGE3_CDC_WORD1 STAGE3 CDC FIFO WORD1 0x161 [15:0] X R/W STAGE3_MAX_WORD0 STAGE3 maximum value FIFO WORD0 0x162 [15:0] X R/W STAGE3_MAX_WORD1 STAGE3 maximum value FIFO WORD1 0x163 [15:0] X R/W STAGE3_MAX_WORD2 STAGE3 maximum value FIFO WORD2 0x164 [15:0] X R/W STAGE3_MAX_WORD3 STAGE3 maximum value FIFO WORD3 0x165 [15:0] X R/W STAGE3_MAX_AVG STAGE3 average maximum FIFO value 0x166 [15:0] X R/W STAGE3_HIGH_THRESHOLD STAGE3 high threshold value 0x167 [15:0] X R/W STAGE3_MAX_TEMP STAGE3 temporary maximum value 0x168 [15:0] X R/W STAGE3_MIN_WORD0 STAGE3 minimum value FIFO WORD0 0x169 [15:0] X R/W STAGE3_MIN_WORD1 STAGE3 minimum value FIFO WORD1 0x16A [15:0] X R/W STAGE3_MIN_WORD2 STAGE3 minimum value FIFO WORD2 0x16B [15:0] X R/W STAGE3_MIN_WORD3 STAGE3 minimum value FIFO WORD3 0x16C [15:0] X R/W STAGE3_MIN_AVG STAGE3 average minimum FIFO value 0x16D [15:0] X R/W STAGE3_LOW_THRESHOLD STAGE3 low threshold value 0x16E [15:0] X R/W STAGE3_MIN_TEMP STAGE3 temporary minimum value 0x16F [15:0] X R/W Unused Rev. 0 | Page 50 of 56 AD7143 Table 46. STAGE4 Results Registers Address Data Bit Default Type Name Description 0x170 [15:0] X R/W STAGE4_CONV_DATA STAGE4 CDC 16-bit conversion data (copy of data in STAGE4_CONV_DATA register) 0x171 [15:0] X R/W STAGE4_FF_WORD0 STAGE4 fast FIFO WORD0 0x172 [15:0] X R/W STAGE4_FF_WORD1 STAGE4 fast FIFO WORD1 0x173 [15:0] X R/W STAGE4_FF_WORD2 STAGE4 fast FIFO WORD2 0x174 [15:0] X R/W STAGE4_FF_WORD3 STAGE4 fast FIFO WORD3 0x175 [15:0] X R/W STAGE4_FF_WORD4 STAGE4 fast FIFO WORD4 0x176 [15:0] X R/W STAGE4_FF_WORD5 STAGE4 fast FIFO WORD5 0x177 [15:0] X R/W STAGE4_FF_WORD6 STAGE4 fast FIFO WORD6 0x178 [15:0] X R/W STAGE4_FF_WORD7 STAGE4 fast FIFO WORD7 0x179 [15:0] X R/W STAGE4_SF_WORD0 STAGE4 slow FIFO WORD0 0x17A [15:0] X R/W STAGE4_SF_WORD1 STAGE4 slow FIFO WORD1 0x17B [15:0] X R/W STAGE4_SF_WORD2 STAGE4 slow FIFO WORD2 0x17C [15:0] X R/W STAGE4_SF_WORD3 STAGE4 slow FIFO WORD3 0x17D [15:0] X R/W STAGE4_SF_WORD4 STAGE4 slow FIFO WORD4 0x17E [15:0] X R/W STAGE4_SF_WORD5 STAGE4 slow FIFO WORD5 0x17F [15:0] X R/W STAGE4_SF_WORD6 STAGE4 slow FIFO WORD6 0x180 [15:0] X R/W STAGE4_SF_WORD7 STAGE4 slow FIFO WORD7 0x181 [15:0] X R/W STAGE4_SF_AMBIENT STAGE4 slow FIFO ambient value 0x182 [15:0] X R/W STAGE4_FF_AVG STAGE4 fast FIFO average value 0x183 [15:0] X R/W STAGE4_CDC_WORD0 STAGE4 CDC FIFO WORD0 0x184 [15:0] X R/W STAGE4_CDC_WORD1 STAGE4 CDC FIFO WORD1 0x185 [15:0] X R/W STAGE4_MAX_WORD0 STAGE4 maximum value FIFO WORD0 0x186 [15:0] X R/W STAGE4_MAX_WORD1 STAGE4 maximum value FIFO WORD1 0x187 [15:0] X R/W STAGE4_MAX_WORD2 STAGE4 maximum value FIFO WORD2 0x188 [15:0] X R/W STAGE4_MAX_WORD3 STAGE4 maximum value FIFO WORD3 0x189 [15:0] X R/W STAGE4_MAX_AVG STAGE4 average maximum FIFO value 0x18A [15:0] X R/W STAGE4_HIGH_THRESHOLD STAGE4 high threshold value 0x18B [15:0] X R/W STAGE4_MAX_TEMP STAGE4 temporary maximum value 0x18C [15:0] X R/W STAGE4_MIN_WORD0 STAGE4 minimum value FIFO WORD0 0x18D [15:0] X R/W STAGE4_MIN_WORD1 STAGE4 minimum value FIFO WORD1 0x18E [15:0] X R/W STAGE4_MIN_WORD2 STAGE4 minimum value FIFO WORD2 0x18F [15:0] X R/W STAGE4_MIN_WORD3 STAGE4 minimum value FIFO WORD3 0x190 [15:0] X R/W STAGE4_MIN_AVG STAGE4 average minimum FIFO value 0x191 [15:0] X R/W STAGE4_LOW_THRESHOLD STAGE4 low threshold value 0x192 [15:0] X R/W STAGE4_MIN_TEMP STAGE4 temporary minimum value 0x193 [15:0] X R/W Unused Rev. 0 | Page 51 of 56 AD7143 Table 47. STAGE5 Results Registers Address Data Bit Default Type Name Description 0x194 [15:0] X R/W STAGE5_CONV_DATA STAGE5 CDC 16-bit conversion data (copy of data in STAGE5_CONV_DATA register) 0x195 [15:0] X R/W STAGE5_FF_WORD0 STAGE5 fast FIFO WORD0 0x196 [15:0] X R/W STAGE5_FF_WORD1 STAGE5 fast FIFO WORD1 0x197 [15:0] X R/W STAGE5_FF_WORD2 STAGE5 fast FIFO WORD2 0x198 [15:0] X R/W STAGE5_FF_WORD3 STAGE5 fast FIFO WORD3 0x199 [15:0] X R/W STAGE5_FF_WORD4 STAGE5 fast FIFO WORD4 0x19A [15:0] X R/W STAGE5_FF_WORD5 STAGE5 fast FIFO WORD5 0x19B [15:0] X R/W STAGE5_FF_WORD6 STAGE5 fast FIFO WORD6 0x19C [15:0] X R/W STAGE5_FF_WORD7 STAGE5 fast FIFO WORD7 0x19D [15:0] X R/W STAGE5_SF_WORD0 STAGE5 slow FIFO WORD0 0x19E [15:0] X R/W STAGE5_SF_WORD1 STAGE5 slow FIFO WORD1 0x19F [15:0] X R/W STAGE5_SF_WORD2 STAGE5 slow FIFO WORD2 0x1A0 [15:0] X R/W STAGE5_SF_WORD3 STAGE5 slow FIFO WORD3 0x1A1 [15:0] X R/W STAGE5_SF_WORD4 STAGE5 slow FIFO WORD4 0x1A2 [15:0] X R/W STAGE5_SF_WORD5 STAGE5 slow FIFO WORD5 0x1A3 [15:0] X R/W STAGE5_SF_WORD6 STAGE5 slow FIFO WORD6 0x1A4 [15:0] X R/W STAGE5_SF_WORD7 STAGE5 slow FIFO WORD7 0x1A5 [15:0] X R/W STAGE5_SF_AMBIENT STAGE5 slow FIFO ambient value 0x1A6 [15:0] X R/W STAGE5_FF_AVG STAGE5 fast FIFO average value 0x1A7 [15:0] X R/W STAGE5_CDC_WORD0 STAGE5 CDC FIFO WORD0 0x1A8 [15:0] X R/W STAGE5_CDC_WORD1 STAGE5 CDC FIFO WORD1 0x1A9 [15:0] X R/W STAGE5_MAX_WORD0 STAGE5 maximum value FIFO WORD0 0x1AA [15:0] X R/W STAGE5_MAX_WORD1 STAGE5 maximum value FIFO WORD1 0x1AB [15:0] X R/W STAGE5_MAX_WORD2 STAGE5 maximum value FIFO WORD2 0x1AC [15:0] X R/W STAGE5_MAX_WORD3 STAGE5 maximum value FIFO WORD3 0x1AD [15:0] X R/W STAGE5_MAX_AVG STAGE5 average maximum FIFO value 0x1AE [15:0] X R/W STAGE5_HIGH_THRESHOLD STAGE5 high threshold value 0x1AF [15:0] X R/W STAGE5_MAX_TEMP STAGE5 temporary maximum value 0x1B0 [15:0] X R/W STAGE5_MIN_WORD0 STAGE5 minimum value FIFO WORD0 0x1B1 [15:0] X R/W STAGE5_MIN_WORD1 STAGE5 minimum value FIFO WORD1 0x1B2 [15:0] X R/W STAGE5_MIN_WORD2 STAGE5 minimum value FIFO WORD2 0x1B3 [15:0] X R/W STAGE5_MIN_WORD3 STAGE5 minimum value FIFO WORD3 0x1B4 [15:0] X R/W STAGE5_MIN_AVG STAGE5 average minimum FIFO value 0x1B5 [15:0] X R/W STAGE5_LOW_THRESHOLD STAGE5 low threshold value 0x1B6 [15:0] X R/W STAGE5_MIN_TEMP STAGE5 temporary minimum value 0x1B7 [15:0] X R/W Unused Rev. 0 | Page 52 of 56 AD7143 Table 48. STAGE6 Results Registers Address Data Bit Default Type Name Description 0x1B8 [15:0] X R/W STAGE6_CONV_DATA STAGE6 CDC 16-bit conversion data (copy of data in STAGE6_CONV_DATA register) 0x1B9 [15:0] X R/W STAGE6_FF_WORD0 STAGE6 fast FIFO WORD0 0x1BA [15:0] X R/W STAGE6_FF_WORD1 STAGE6 fast FIFO WORD1 0x1BB [15:0] X R/W STAGE6_FF_WORD2 STAGE6 fast FIFO WORD2 0x1BC [15:0] X R/W STAGE6_FF_WORD3 STAGE6 fast FIFO WORD3 0x1BD [15:0] X R/W STAGE6_FF_WORD4 STAGE6 fast FIFO WORD4 0x1BE [15:0] X R/W STAGE6_FF_WORD5 STAGE6 fast FIFO WORD5 0x1BF [15:0] X R/W STAGE6_FF_WORD6 STAGE6 fast FIFO WORD6 0x1C0 [15:0] X R/W STAGE6_FF_WORD7 STAGE6 fast FIFO WORD7 0x1C1 [15:0] X R/W STAGE6_SF_WORD0 STAGE6 slow FIFO WORD0 0x1C2 [15:0] X R/W STAGE6_SF_WORD1 STAGE6 slow FIFO WORD1 0x1C3 [15:0] X R/W STAGE6_SF_WORD2 STAGE6 slow FIFO WORD2 0x1C4 [15:0] X R/W STAGE6_SF_WORD3 STAGE6 slow FIFO WORD3 0x1C5 [15:0] X R/W STAGE6_SF_WORD4 STAGE6 slow FIFO WORD4 0x1C6 [15:0] X R/W STAGE6_SF_WORD5 STAGE6 slow FIFO WORD5 0x1C7 [15:0] X R/W STAGE6_SF_WORD6 STAGE6 slow FIFO WORD6 0x1C8 [15:0] X R/W STAGE6_SF_WORD7 STAGE6 slow FIFO WORD7 0x1C9 [15:0] X R/W STAGE6_SF_AMBIENT STAGE6 slow FIFO ambient value 0x1CA [15:0] X R/W STAGE6_FF_AVG STAGE6 fast FIFO average value 0x1CB [15:0] X R/W STAGE6_CDC_WORD0 STAGE0 CDC FIFO WORD0 0x1CC [15:0] X R/W STAGE6_CDC_WORD1 STAGE6 CDC FIFO WORD1 0x1CD [15:0] X R/W STAGE6_MAX_WORD0 STAGE6 maximum value FIFO WORD0 0x1CE [15:0] X R/W STAGE6_MAX_WORD1 STAGE6 maximum value FIFO WORD1 0x1CF [15:0] X R/W STAGE6_MAX_WORD2 STAGE6 maximum value FIFO WORD2 0x1D0 [15:0] X R/W STAGE6_MAX_WORD3 STAGE6 maximum value FIFO WORD3 0x1D1 [15:0] X R/W STAGE6_MAX_AVG STAGE6 average maximum FIFO value 0x1D2 [15:0] X R/W STAGE6_HIGH_THRESHOLD STAGE6 high threshold value 0x1D3 [15:0] X R/W STAGE6_MAX_TEMP STAGE6 temporary maximum value 0x1D4 [15:0] X R/W STAGE6_MIN_WORD0 STAGE6 minimum value FIFO WORD0 0x1D5 [15:0] X R/W STAGE6_MIN_WORD1 STAGE6 minimum value FIFO WORD1 0x1D6 [15:0] X R/W STAGE6_MIN_WORD2 STAGE6 minimum value FIFO WORD2 0x1D7 [15:0] X R/W STAGE6_MIN_WORD3 STAGE6 minimum value FIFO WORD3 0x1D8 [15:0] X R/W STAGE6_MIN_AVG STAGE6 average minimum FIFO value 0x1D9 [15:0] X R/W STAGE6_LOW_THRESHOLD STAGE6 low threshold value 0x1DA [15:0] X R/W STAGE6_MIN_TEMP STAGE6 temporary minimum value 0x1DB [15:0] X R/W Unused Rev. 0 | Page 53 of 56 AD7143 Table 49. STAGE7 Results Registers Address Data Bit Default Type Name Description 0x1DC [15:0] X R/W STAGE7_CONV_DATA STAGE7 CDC 16-bit conversion data (copy of data in STAGE7_CONV_DATA register) 0x1DD [15:0] X R/W STAGE7_FF_WORD0 STAGE7 fast FIFO WORD0 0x1DE [15:0] X R/W STAGE7_FF_WORD1 STAGE7 fast FIFO WORD1 0x1DF [15:0] X R/W STAGE7_FF_WORD2 STAGE7 fast FIFO WORD2 0x1E0 [15:0] X R/W STAGE7_FF_WORD3 STAGE7 fast FIFO WORD3 0x1E1 [15:0] X R/W STAGE7_FF_WORD4 STAGE7 fast FIFO WORD4 0x1E2 [15:0] X R/W STAGE7_FF_WORD5 STAGE7 fast FIFO WORD5 0x1E3 [15:0] X R/W STAGE7_FF_WORD6 STAGE7 fast FIFO WORD6 0x1E4 [15:0] X R/W STAGE7_FF_WORD7 STAGE7 fast FIFO WORD7 0x1E5 [15:0] X R/W STAGE7_SF_WORD0 STAGE7 slow FIFO WORD0 0x1E6 [15:0] X R/W STAGE7_SF_WORD1 STAGE7 slow FIFO WORD1 0x1E7 [15:0] X R/W STAGE7_SF_WORD2 STAGE7 slow FIFO WORD2 0x1E8 [15:0] X R/W STAGE7_SF_WORD3 STAGE7 slow FIFO WORD3 0x1E9 [15:0] X R/W STAGE7_SF_WORD4 STAGE7 slow FIFO WORD4 0x1EA [15:0] X R/W STAGE7_SF_WORD5 STAGE7 slow FIFO WORD5 0x1EB [15:0] X R/W STAGE7_SF_WORD6 STAGE7 slow FIFO WORD6 0x1EC [15:0] X R/W STAGE7_SF_WORD7 STAGE7 slow FIFO WORD7 0x1ED [15:0] X R/W STAGE7_SF_AMBIENT STAGE7 slow FIFO ambient value 0x1EE [15:0] X R/W STAGE7_FF_AVG STAGE7 fast FIFO average value 0x1EF [15:0] X R/W STAGE7_CDC_WORD0 STAGE7 CDC FIFO WORD0 0x1F0 [15:0] X R/W STAGE7_CDC_WORD1 STAGE7 CDC FIFO WORD1 0x1F1 [15:0] X R/W STAGE7_MAX_WORD0 STAGE7 maximum value FIFO WORD0 0x1F2 [15:0] X R/W STAGE7_MAX_WORD1 STAGE7 maximum value FIFO WORD1 0x1F3 [15:0] X R/W STAGE7_MAX_WORD2 STAGE7 maximum value FIFO WORD2 0x1F4 [15:0] X R/W STAGE7_MAX_WORD3 STAGE7 maximum value FIFO WORD3 0x1F5 [15:0] X R/W STAGE7_MAX_AVG STAGE7 average maximum FIFO value 0x1F6 [15:0] X R/W STAGE7_HIGH_THRESHOLD STAGE7 high threshold value 0x1F7 [15:0] X R/W STAGE7_MAX_TEMP STAGE7 temporary maximum value 0x1F8 [15:0] X R/W STAGE7_MIN_WORD0 STAGE7 minimum value FIFO WORD0 0x1F9 [15:0] X R/W STAGE7_MIN_WORD1 STAGE7 minimum value FIFO WORD1 0x1FA [15:0] X R/W STAGE7_MIN_WORD2 STAGE7 minimum value FIFO WORD2 0x1FB [15:0] X R/W STAGE7_MIN_WORD3 STAGE7 minimum value FIFO WORD3 0x1FC [15:0] X R/W STAGE7_MIN_AVG STAGE7 average minimum FIFO value 0x1FD [15:0] X R/W STAGE7_LOW_THRESHOLD STAGE7 low threshold value 0x1FE [15:0] X R/W STAGE7_MIN_TEMP STAGE7 temporary minimum value 0x1FF [15:0] X R/W Unused Rev. 0 | Page 54 of 56 AD7143 OUTLINE DIMENSIONS 0.50 0.40 4.00 0.30 0.60 MAX BSC SQ 12 1 13 16 PIN 1 2.65 3.75 EXPOSED INDICATOR 2.50 SQ BSC SQ PAD 2.35 4 0.65 8 5 9 BSC 0.25 MIN TOP VIEW 1.95 BCS BOTTOM VIEW 12° MAX 0.80 MAX 0.65 TYP 1.00 0.85 0.05 MAX 0.80 0.02 NOM SEATING 0.30 COPLANARITY PLANE 0.20 REF 0.08 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC. Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Very Thin Quad (CP-16-13) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Serial Interface Description Package Description Package Option 1 2 AD7143ACPZ-1REEL −40°C to +85°C I C Interface 16-Lead LFCSP_VQ CP-16-13 1 2 AD7143ACPZ-1500RL7 −40°C to +85°C I C Interface 16-Lead LFCSP_VQ CP-16-13 1 2 EVAL-AD7143-1EBZ I C Interface Evaluation Board 1 Z = Pb-free part. Rev. 0 | Page 55 of 56 PIN 1 INDICATOR 031006-A AD7143 NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06472-0-1/07(0) Rev. 0 | Page 56 of 56