ANALOG DEVICES AD6657A

Quad IF Receiver Data Sheet AD6657A FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DRGND 11-bit, 200 MSPS output data rate per channel Integrated noise shaping requantizer AD6657A Performance with NSR enabled DCO±AB 14 11 VIN+A SNR: 76.0 dBFS in 40 MHz band to 70 MHz at 185 MSPS PIPELINE NOISE SHAPING DO±AB ADC REQUANTIZER VIN–A SNR: 73.6 dBFS in 60 MHz band to 70 MHz at 185 MSPS VCMA PORT A SNR: 72.8 dBFS in 65 MHz band to 70 MHz at 185 MSPS 14 11 VIN+B PIPELINE NOISE SHAPING D10±AB Performance with NSR disabled REQUANTIZER ADC VIN–B SNR: 66.5 dBFS to 70 MHz at 185 MSPS VCMB DCO±CD SFDR: 88 dBc to 70 MHz at 185 MSPS 14 11 VIN+C NOISE SHAPING PIPELINE DO±CD REQUANTIZER ADC Low power: 1.2 W at 185 MSPS VIN–C PORT B 1.8 V analog supply operation VCMC 14 11 VIN+D 1.8 V LVDS (ANSI-644 levels) output NOISE SHAPING PIPELINE D10±CD REQUANTIZER ADC VIN–D 1-to-8 integer clock divider VCMD Internal ADC voltage reference MODE REFERENCE 1.75 V p-p analog input range (programmable to 2.0 V p-p) CLOCK SYNC DIVIDER Differential analog inputs with 800 MHz bandwidth PDWN 95 dB channel isolation/crosstalk SERIAL PORT Serial port control User-configurable built-in self test (BIST) capability SCLK SDIO CSB CLK+ CLK– Energy saving power-down modes Figure 1. APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios Each ADC output is connected internally to an NSR block. The GENERAL DESCRIPTION integrated NSR circuitry allows for improved SNR performance The AD6657A is an 11-bit, 200 MSPS, quad channel intermediate in a smaller frequency band within the Nyquist bandwidth. The frequency (IF) receiver specifically designed to support multiple device supports two different output modes selectable via the antenna systems in telecommunication applications where high external MODE pin or the serial port interface (SPI). dynamic range performance, low power, and small size are desired. With the NSR feature enabled, the outputs of the ADCs are The device consists of four high performance ADCs and NSR processed such that the AD6657A supports enhanced SNR per- digital blocks. Each ADC consists of a multistage, differential formance within a limited portion of the Nyquist bandwidth pipelined architecture with integrated output error correction while maintaining an 11-bit output resolution. The NSR block logic. The ADC features a wide bandwidth switched capacitor can be programmed to provide a bandwidth of either 22%, 33%, sampling network within the first stage of the differential pipeline. or 36% of the sample clock. For example, with a sample clock An integrated voltage reference eases design considerations. A rate of 185 MSPS, the AD6657A can achieve up to 76.0 dBFS duty cycle stabilizer (DCS) compensates for variations in the SNR for a 40 MHz bandwidth in the 22% mode, up to 73.6 dBFS ADC clock duty cycle, allowing the converters to maintain SNR for a 60 MHz bandwidth in the 33% mode, or up to 72.8 dBFS excellent performance. SNR for a 65 MHz bandwidth in the 36% mode. (General Description continued on Page 3) Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. DATA MULTIPLEXER AND LVDS DRIVERS 09684-001 AD6657A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Channel/Chip Synchronization ................................................ 23 Applications ....................................................................................... 1 Digital Outputs ........................................................................... 24 Functional Block Diagram .............................................................. 1 Timing ......................................................................................... 24 General Description ......................................................................... 1 Noise Shaping Requantizer ........................................................... 25 Revision History ............................................................................... 2 22% BW Mode (>40 MHz at 184.32 MSPS) ........................... 25 Product Highlights ........................................................................... 3 33% BW Mode (>60 MHz at 184.32 MSPS) ........................... 26 Specifications ..................................................................................... 4 36% BW Mode (>65 MHz at 184.32 MSPS) ........................... 27 DC Specifications ......................................................................... 4 MODE Pin ................................................................................... 27 AC Specifications .......................................................................... 5 Built-In Self Test (BIST) and Output Test ................................... 28 Digital Specifications ................................................................... 7 BIST .............................................................................................. 28 Switching Specifications .............................................................. 9 Output Test Modes ..................................................................... 28 Timing Specifications ................................................................ 10 Serial Port Interface (SPI) .............................................................. 29 Absolute Maximum Ratings ..................................................... 11 Configuration Using the SPI ..................................................... 29 Thermal Characteristics ............................................................ 11 Hardware Interface ..................................................................... 29 ESD Caution ................................................................................ 11 Memory Map .................................................................................. 30 Pin Configuration and Function Descriptions ........................... 12 Reading the Memory Map Register Table ............................... 30 Typical Performance Characteristics ........................................... 14 Memory Map Register Table ..................................................... 31 Equivalent Circuits ......................................................................... 18 Memory Map Register Descriptions ........................................ 33 Theory of Operation ...................................................................... 19 Applications Information .............................................................. 35 ADC Architecture ...................................................................... 19 Design Guidelines ...................................................................... 35 Analog Input Considerations .................................................... 19 Packaging and Ordering Information ......................................... 36 Clock Input Considerations ...................................................... 21 Outline Dimensions ................................................................... 36 Power Dissipation and Standby Mode ..................................... 23 Ordering Guide .......................................................................... 36 REVISION HISTORY 10/11—Revision 0: Initial Version Rev. 0 | Page 2 of 36 Data Sheet AD6657A With the NSR block disabled, the ADC data is provided directly to (CSP_BGA) that is specified over the industrial temperature the output with a resolution of 11 bits. The AD6657A can achieve range of −40°C to +85°C. up to 66.5 dBFS SNR for the entire Nyquist bandwidth when PRODUCT HIGHLIGHTS operated in this mode. This allows the AD6657A to be used in 1. Four analog-to-digital converters (ADCs) are contained in telecommunication applications such as a digital predistortion a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball observation path where wider bandwidths are used. CSP_BGA package. After digital signal processing, multiplexed output data is 2. Pin selectable noise shaping requantizer (NSR) function routed into two 11-bit output ports such that the maximum that allows for improved SNR within a reduced bandwidth digital data rate (DDR) is 400 Mbps. These outputs are set at of up to 65 MHz at 185 MSPS. 1.8 V LVDS and support ANSI-644 levels. 3. LVDS digital output interface configured for low cost The AD6657A receiver digitizes a wide spectrum of IF frequencies. FPGA families. Each receiver is designed for simultaneous reception of a separate 4. 230 mW per ADC core power consumption. antenna. This IF sampling architecture greatly reduces component 5. Operation from a single 1.8 V supply. cost and complexity compared with traditional analog techniques 6. Standard SPI that supports various product features and or less integrated digital methods. functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage Flexible power-down options allow significant power savings. reference mode. Programming for device setup and control is accomplished 7. On-chip integer 1-to-8 input clock divider and multichip using a 3-wire SPI-compatible serial interface with numerous sync function to support a wide range of clocking schemes modes to support board level system testing. and multichannel subsystems. The AD6657A is available in a Pb-free, RoHS compliant, 144-ball, 10 mm × 10 mm chip scale package ball grid array Rev. 0 | Page 3 of 36 AD6657A Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, f = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless S otherwise noted. Table 1. Parameter Temperature Min Typ Max Unit RESOLUTION Full 11 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full −0.9 +0.1 +0.9 mV Gain Error Full +4 +11 +18 % FSR 1 Differential Nonlinearity (DNL) Full −0.4 ±0.1 +0.4 LSB 1 Integral Nonlinearity (INL) Full −0.55 ±0.17 +0.55 LSB MATCHING CHARACTERISTIC Offset Error Full −5 +3 +11 mV Gain Error Full 0 +2.1 +8 % FSR TEMPERATURE DRIFT Offset Error Full 2 ppm/°C Gain Error Full 40 ppm/°C ANALOG INPUT Input Range Full 1.4 1.75 2.0 V p-p Input Common-Mode Voltage Full 0.95 V Input Resistance (Differential) Full 20 kΩ 2 Input Capacitance Full 5 pF POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current 1 IAVDD Full 466 510 mA 1 IDRVDD (1.8 V LVDS) Full 170 183 mA POWER CONSUMPTION 1 Sine Wave Input Full 1145 1247 mW 3 Standby Power Full 129 mW Power-Down Power Full 3.8 10 mW 1 Measured with a 10 MHz, 0 dBFS sine wave, with 100 Ω termination on each LVDS output pair. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND). Rev. 0 | Page 4 of 36 Data Sheet AD6657A AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 2. 1 Parameter Temperature Min Typ Max Unit SIGNAL-TO-NOISE-RATIO (SNR)—NSR DISABLED fIN = 10 MHz 25°C 66.6 dBFS fIN = 50 MHz 25°C 66.5 dBFS f = 70 MHz 25°C 66.5 dBFS IN f = 170 MHz 25°C 66.3 dBFS IN Full 65.6 dBFS fIN = 250 MHz 25°C 65.9 dBFS SIGNAL-TO-NOISE-RATIO (SNR)—NSR ENABLED 22% BW Mode fIN = 10 MHz 25°C 76.0 dBFS fIN = 50 MHz 25°C 75.7 dBFS f = 70 MHz 25°C 75.7 dBFS IN f = 170 MHz 25°C 74.3 dBFS IN Full 72.9 dBFS fIN = 250 MHz 25°C 72.8 dBFS 33% BW Mode fIN = 10 MHz 25°C 73.6 dBFS f = 50 MHz 25°C 73.6 dBFS IN f = 70 MHz 25°C 73.3 dBFS IN fIN = 170 MHz 25°C 72.5 dBFS Full 71.3 dBFS fIN = 230 MHz 25°C 71.2 dBFS 36% BW Mode f = 10 MHz 25°C 72.8 dBFS IN f = 50 MHz 25°C 72.6 dBFS IN fIN = 70 MHz 25°C 72.6 dBFS fIN = 170 MHz 25°C 71.8 dBFS Full 70.7 dBFS f = 250 MHz 25°C 70.8 dBFS IN SIGNAL-TO-NOISE-AND DISTORTION (SINAD) fIN = 10 MHz 25°C 65.5 dBFS f = 50 MHz 25°C 65.5 dBFS IN f = 70 MHz 25°C 65.5 dBFS IN fIN = 170 MHz 25°C 65.3 dBFS Full 64.6 dBFS fIN = 250 MHz 25°C 64.8 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 10.6 Bits fIN = 50 MHz 25°C 10.6 Bits f = 70 MHz 25°C 10.6 Bits IN f = 170 MHz 25°C 10.6 Bits IN f = 250 MHz 25°C 10.5 Bits IN Rev. 0 | Page 5 of 36 AD6657A Data Sheet 1 Parameter Temperature Min Typ Max Unit WORST SECOND OR THIRD HARMONIC fIN = 10 MHz 25°C −94 dBc fIN = 50 MHz 25°C −91 dBc f = 70 MHz 25°C −88 dBc IN f = 170 MHz 25°C −90 dBc IN Full −80 dBc fIN = 250 MHz 25°C −83 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 10 MHz 25°C 94 dBc fIN = 50 MHz 25°C 91 dBc fIN = 70 MHz 25°C 88 dBc f = 170 MHz 25°C 90 dBc IN Full 80 dBc f = 250 MHz 25°C 83 dBc IN WORST OTHER HARMONIC (FOURTH THROUGH EIGHTH) f = 10 MHz 25°C −94 dBc IN f = 50 MHz 25°C −95 dBc IN fIN = 70 MHz 25°C −94 dBc fIN = 170 MHz 25°C −94 dBc Full −80 dBc f = 250 MHz 25°C −90 dBc IN TWO TONE SFDR (−7 dBFS) fIN1 = 169 MHz, fIN2 = 172 MHz 25°C 89 dBc 2 CROSSTALK Full 95 dB ANALOG INPUT BANDWIDTH 25°C 800 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 155 MHz with −1 dBFS on one channel and no input on the alternate channel. Rev. 0 | Page 6 of 36 Data Sheet AD6657A DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full AGND − 0.3 AVDD + 0.2 V High Level Input Voltage Full 1.2 2.0 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF SYNC INPUT Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 µA Low Level Input Current Full −100 +100 µA Input Resistance Full 12 16 20 kΩ Input Capacitance Full 1 pF 1 LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 40 132 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT (SCLK) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −92 −135 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT/OUTPUT (SDIO) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 38 128 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF Rev. 0 | Page 7 of 36 AD6657A Data Sheet Parameter Temperature Min Typ Max Unit 1 LOGIC INPUT (MODE) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT (PDWN) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS (LVDS) Differential Output Voltage (V) Full 247 454 mV OD Output Offset Voltage (V) Full 1.125 1.375 V OS 1 Pull up. 2 Pull down. Rev. 0 | Page 8 of 36 Data Sheet AD6657A SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 4. Parameter Temperature Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 MHz 1 Conversion Rate Full 40 185 200 MSPS 2 CLK Pulse Width High (t ) Full 2.7 ns CH 2 Aperture Delay (t ) Full 1.3 ns A Aperture Uncertainty (Jitter, tJ) Full 0.13 ps rms DATA OUTPUT PARAMETERS 2 Data Propagation Delay (t ) Full 3.0 4.0 4.9 ns PD 2 4.0 DCO Propagation Delay (tDCO) Full 3.1 4.9 ns 2 DCO to Data Skew (tSKEW) Full −41 +6.1 +33 ns Pipeline Delay (Latency) Full 9 Cycles With NSR Enabled Full 12 Cycles 3 Wake-Up Time (from Standby) Full 0.5 µs 3 Wake-Up Time (from Power Down) Full 310 µs OUT-OF-RANGE RECOVERY TIME Full 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 See Figure 2 for details. 3 Wake-up time is dependent on the value of the decoupling capacitors. Data Output Timing Diagram N – 1 t N + 4 A N + 5 N N + 3 VIN N + 1 N + 2 t CH t 1/f CL S CLK+ CLK– t DCO DCO+ DCO– t SKEW t PD D10+AB (MSB) D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B D10–AB (MSB) D0+AB (LSB) D0A D0B D0A D0B D0A D0B D0A D0B D0A D0B D0A D0B D0A D0B D0–AB (LSB) Figure 2. Data Output Timing (Timing for Channel C and Channel D Is Identical to Timing for Channel A and Channel B) Rev. 0 | Page 9 of 36 09684-002 AD6657A Data Sheet TIMING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless otherwise noted. Table 5. Parameter Description Min Typ Max Unit SYNC TIMING REQUIREMENTS See Figure 3 for details t SYNC to rising edge of CLK setup time 0.24 ns SSYNC t SYNC to rising edge of CLK hold time 0.40 ns HSYNC SPI TIMING REQUIREMENTS See Figure 60 for details, except where noted t Setup time between the data and the rising edge of SCLK 2 ns DS t Hold time between the data and the rising edge of SCLK 2 ns DH t Period of the SCLK 40 ns CLK tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns t SCLK pulse width high 10 ns HIGH t SCLK pulse width low 10 ns LOW t Time required for the SDIO pin to switch from an input to 10 ns EN_SDIO an output relative to the SCLK falling edge (not pictured in Figure 60) tDIS_SDIO Time required for the SDIO pin to switch from an output to 10 ns an input relative to the SCLK rising edge (not pictured in Figure 60) Sync Input Timing Diagram CLK+ t t SSYNC HSYNC SYNC Figure 3. SYNC Input Timing Requirements Rev. 0 | Page 10 of 36 09684-003 Data Sheet AD6657A ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. The values in Table 7 are per JEDEC JESD51-7 and JEDEC Parameter Rating is specified for a JESD25-5 for a 2S2P test board. Typical θJA AVDD to AGND −0.3 V to +2.0 V 4-layer printed circuit board (PCB) with a solid ground plane. DRVDD to AGND −0.3 V to +2.0 V As shown in Table 7, airflow improves heat dissipation, which VIN+x, VIN−x to AGND −0.3 V to AVDD + 0.2 V reduces θJA. In addition, metal in direct contact with the CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V package leads from metal traces, through holes, ground, and SYNC to AGND −0.3 V to AVDD + 0.2 V power planes reduces θ . JA VCMx to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to DRVDD + 0.2 V Table 7. SCLK to AGND −0.3 V to DRVDD + 0.2 V Airflow SDIO to AGND −0.3 V to DRVDD + 0.2 V 1 2 3 Package Type Velocity θJA θJC θJB Unit PDWN to AGND −0.3 V to DRVDD + 0.2 V 144-Ball CSP_BGA 0 m/s 26.9 8.9 6.6 °C/W MODE to AGND −0.3 V to DRVDD + 0.2 V 1 m/s 24.2 °C/W Digital Outputs to AGND −0.3 V to DRVDD + 0.2 V 2.5 m/s 23.0 °C/W DCO+AB, DCO−AB, DCO+CD, −0.3 V to DRVDD + 0.2 V 1 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). DCO−CD to AGND 2 Per MIL-STD 883, Method 1012.1. Operating Temperature Range −40°C to +85°C 3 Per JEDEC JESD51-8 (still air). (Ambient) The values in Table 8 are from simulations. The PCB is a JEDEC Maximum Junction Temperature 150°C multilayer board. Thermal performance for actual applications Under Bias requires careful inspection of the conditions in the application Storage Temperature Range −65°C to +150°C to determine whether they are similar to those assumed in these (Ambient) calculations. Stresses abovethose listed under Absolute Maximum Ratings Table 8. may cause permanent damage to the device. This is a stress Airflow rating only; functional operation of the device at these or any Package Type Velocity   Unit JB JT other conditions above those indicated in the operational 144-Ball CSP_BGA 0 m/s 14.4 0.23 °C/W section of this specification is not implied. Exposure to absolute 1 m/s 14.0 0.50 °C/W maximum ratingconditionsfor extended periodsmay affect 2.5 m/s 13.9 0.53 °C/W device reliability. ESD CAUTION Rev. 0 | Page 11 of 36 AD6657A Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 A AGND VIN+C VIN–C AGND AVDD CLK– CLK+ AVDD AGND VIN–B VIN+B AGND B AGND AGND VCMC AGND AVDD AVDD AVDD AVDD AGND VCMB AGND AGND C VIN+D AGND AGND CSB SDIO SCLK PDWN SYNC MODE AGND AGND VIN+A D VIN–D VCMD AGND AVDD AVDD AVDD AVDD AVDD AVDD AGND VCMA VIN–A E AGND AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AGND F AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND G DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND H DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD J D0–CD D2–CD D4–CD D6–CD D8–CD D10–CD D0–AB D2–AB D4–AB D6–AB D8–AB D10–AB K D0+CD D2+CD D4+CD D6+CD D8+CD D10+CD D0+AB D2+AB D4+AB D6+AB D8+AB D10+AB L D1–CD D3–CD D5–CD D7–CD D9–CD DCO–CD D1–AB D3–AB D5–AB D7–AB D9–AB DCO–AB M D1+CD D3+CD D5+CD D7+CD D9+CD DCO+CD D1+AB D3+AB D5+AB D7+AB D9+AB DCO+AB Figure 4. Pin Configuration (Top View) Table 9. Pin Function Descriptions Pin No. Mnemonic Type Description A5, A8, B5 to B8, D4 to AVDD Supply Analog Power Supply. 1.8 V nominal. D9, E2 to E11 AGND Ground Analog Ground. A1, A4, A9, A12, B1, B2, B4, B9, B11, B12, C2, C3, C10, C11, D3, D10, E1, E12, F1 to F12 H1 to H12 DRVDD Supply Digital Output Driver Supply. 1.8 V nominal. G1 to G12 DRGND Ground Digital Output Driver Ground. A7 CLK+ Input ADC Clock Input—True. A6 CLK− Input ADC Clock Input—Complement. C12 VIN+A Input Differential Analog Input Pin (+) for Channel A. D12 VIN−A Input Differential Analog Input Pin (−) for Channel A. D11 VCMA Output Common-Mode Level Bias Output for Analog Input Channel A. A11 VIN+B Input Differential Analog Input Pin (+) for Channel B. A10 VIN−B Input Differential Analog Input Pin (−) for Channel B. B10 VCMB Output Common-Mode Level Bias Output for Analog Input Channel B. A2 VIN+C Input Differential Analog Input Pin (+) for Channel C. A3 VIN−C Input Differential Analog Input Pin (−) for Channel C. B3 VCMC Output Common-Mode Level Bias Output for Analog Input Channel C. C1 VIN+D Input Differential Analog Input Pin (+) for Channel D. D1 VIN−D Input Differential Analog Input Pin (−) for Channel D. D2 VCMD Output Common-Mode Level Bias Output for Analog Input Channel D. K7 D0+AB Output Channel A and Channel B LVDS Output Data 0—True. J7 D0−AB Output Channel A and Channel B LVDS Output Data 0—Complement. M7 D1+AB Output Channel A and Channel B LVDS Output Data 1—True. L7 D1−AB Output Channel A and Channel B LVDS Output Data 1—Complement. K8 D2+AB Output Channel A and Channel B LVDS Output Data 2—True. J8 D2−AB Output Channel A and Channel B LVDS Output Data 2—Complement. M8 D3+AB Output Channel A and Channel B LVDS Output Data 3—True. L8 D3−AB Output Channel A and Channel B LVDS Output Data 3—Complement. K9 D4+AB Output Channel A and Channel B LVDS Output Data 4—True. J9 D4−AB Output Channel A and Channel B LVDS Output Data 4—Complement. Rev. 0 | Page 12 of 36 09684-004 Data Sheet AD6657A Pin No. Mnemonic Type Description M9 D5+AB Output Channel A and Channel B LVDS Output Data 5—True. L9 D5−AB Output Channel A and Channel B LVDS Output Data 5—Complement. K10 D6+AB Output Channel A and Channel B LVDS Output Data 6—True. J10 D6−AB Output Channel A and Channel B LVDS Output Data 6—Complement. M10 D7+AB Output Channel A and Channel B LVDS Output Data 7—True. L10 D7−AB Output Channel A and Channel B LVDS Output Data 7—Complement. K11 D8+AB Output Channel A and Channel B LVDS Output Data 8—True. J11 D8−AB Output Channel A and Channel B LVDS Output Data 8—Complement. M11 D9+AB Output Channel A and Channel B LVDS Output Data 9—True. L11 D9−AB Output Channel A and Channel B LVDS Output Data 9—Complement. K12 D10+AB Output Channel A and Channel B LVDS Output Data 10—True. J12 D10−AB Output Channel A and Channel B LVDS Output Data 10—Complement. M12 DCO+AB Output Data Clock LVDS Output for Channel A and Channel B—True. L12 DCO−AB Output Data Clock LVDS Output for Channel A and Channel B—Complement. K1 D0+CD Output Channel C and Channel D LVDS Output Data 0—True. J1 D0−CD Output Channel C and Channel D LVDS Output Data 0—Complement. M1 D1+CD Output Channel C and Channel D LVDS Output Data 1—True. L1 D1−CD Output Channel C and Channel D LVDS Output Data 1—Complement. K2 D2+CD Output Channel C and Channel D LVDS Output Data 2—True. J2 D2−CD Output Channel C and Channel D LVDS Output Data 2—Complement. M2 D3+CD Output Channel C and Channel D LVDS Output Data 3—True. L2 D3−CD Output Channel C and Channel D LVDS Output Data 3—Complement. K3 D4+CD Output Channel C and Channel D LVDS Output Data 4—True. J3 D4−CD Output Channel C and Channel D LVDS Output Data 4—Complement. M3 D5+CD Output Channel C and Channel D LVDS Output Data 5—True. L3 D5−CD Output Channel C and Channel D LVDS Output Data 5—Complement. K4 D6+CD Output Channel C and Channel D LVDS Output Data 6—True. J4 D6−CD Output Channel C and Channel D LVDS Output Data 6—Complement. M4 D7+CD Output Channel C and Channel D LVDS Output Data 7—True. L4 D7−CD Output Channel C and Channel D LVDS Output Data 7—Complement. K5 D8+CD Output Channel C and Channel D LVDS Output Data 8—True. J5 D8−CD Output Channel C and Channel D LVDS Output Data 8—Complement. M5 D9+CD Output Channel C and Channel D LVDS Output Data 9—True. L5 D9−CD Output Channel C and Channel D LVDS Output Data 9—Complement. K6 D10+CD Output Channel C and Channel D LVDS Output Data 10—True. J6 D10−CD Output Channel C and Channel D LVDS Output Data 10—Complement. M6 DCO+CD Output Data Clock LVDS Output for Channel C and Channel D—True. L6 DCO−CD Output Data Clock LVDS Output for Channel C and Channel D—Complement. C9 MODE Input Mode Select Pin. Logic low enables NSR; logic high disables NSR. C8 SYNC Input Digital Synchronization Pin. C7 PDWN Input Power-Down Input (Active High). C6 SCLK Input SPI Clock. C5 SDIO Input/Output SPI Data. C4 CSB Input SPI Chip Select (Active Low). Rev. 0 | Page 13 of 36 AD6657A Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32,000 sample, TA = 25°C, unless otherwise noted. 0 0 185MSPS 185MSPS 10.3MHz @ –1dBFS 140.3MHz @ –1dBFS SNR = 65.6dB (66.6dBFS) SNR = 65.4dB (66.4dBFS) –20 –20 SFDR = 94.0dBc SFDR = 90dBc –40 –40 –60 –60 SECOND HARMONIC THIRD HARMONIC THIRD HARMONIC SECOND HARMONIC –80 –80 –100 –100 –120 –120 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Single Tone FFT, f = 10.3 MHz Figure 8. Single Tone FFT, f = 140.3 MHz IN IN 0 0 185MSPS 185MSPS 50.3MHz @ –1dBFS 200.3MHz @ –1dBFS SNR = 65.6dB (66.6dBFS) SNR = 64.9dB (65.9dBFS) –20 –20 SFDR = 92.0dBc SFDR = 84dBc –40 –40 –60 –60 THIRD HARMONIC SECOND HARMONIC SECOND HARMONIC THIRD HARMONIC –80 –80 –100 –100 –120 –120 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Single Tone FFT, f = 50.3 MHz Figure 9. Single Tone FFT, f = 200.3 MHz IN IN 0 0 185MSPS 185MSPS 70.3MHz @ –1dBFS 230.3MHz @ –1dBFS SNR = 65.5dB (66.5dBFS) SNR = 66.1dB (65.1dBFS) –20 –20 SFDR = 88dBc SFDR = 84dBc –40 –40 –60 –60 SECOND HARMONIC SECOND HARMONIC THIRD HARMONIC THIRD HARMONIC –80 –80 –100 –100 –120 –120 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. Single Tone FFT, f = 70.3 MHz Figure 10. Single Tone FFT, f = 230.3 MHz IN IN Rev. 0 | Page 14 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09684-007 09684-006 09684-005 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09684-010 09684-009 09684-008 Data Sheet AD6657A 0 0 185MSPS 185MSPS 230.3MHz @ –1dBFS 247.3MHz @ –1dBFS NSR 33% BW MODE, TW = 17 SNR = 66dB (65dBFS) –20 –20 SNR = 70.8dB (72.5dBFS) SFDR = 83dBc SFDR = 93.7dBc –40 –40 SECOND HARMONIC –60 SECOND HARMONIC –60 THIRD HARMONIC THIRD HARMONIC –80 –80 –100 –100 –120 –120 –140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. Single Tone FFT, fIN = 247.3 MHz Figure 14. Single Tone FFT, fIN = 230.3 MHz, NSR Enabled in 33% BW Mode, Tuning Word = 17 0 0 185MSPS 185MSPS 305.3MHz @ –1dBFS 230.3MHz @ –1dBFS SNR = 64.9dB (65.9dBFS) NSR 36% BW MODE, TW = 14 –20 –20 SFDR = 80dBc SNR = 70.3dB (71.3dBFS) SFDR = 93.4dBc –40 –40 –60 THIRD HARMONIC –60 THIRD HARMONIC –80 SECOND HARMONIC –80 –100 –100 –120 –140 –120 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Single Tone FFT, fIN = 305.3 MHz Figure 15. Single Tone FFT, fIN = 230.3 MHz, NSR Enabled in 36% BW Mode, Tuning Word = 14 100 0 185MSPS 140.3MHz @ –1dBFS 90 NSR 22% BW MODE, TW = 28 –20 SFDR (dBFS) SNR = 73.4dB (74.9dBFS) 80 SFDR = 91dBc –40 SNR (dBFS) 70 60 –60 50 THIRD HARMONIC SFDR (dBc) –80 40 30 –100 SNR (dBc) 20 –120 10 –140 0 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 16. Single Tone SNR/SFDR vs. Input Amplitude (A ), Figure 13. Single Tone FFT, fIN = 140.3 MHz, NSR Enabled IN f = 70.3 MHz in 22% BW Mode, Tuning Word = 28 IN Rev. 0 | Page 15 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09684-013 09684-012 09684-011 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (dBc AND dBFS) –90 –85 –80 –75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 09684-016 09684-015 09684-014 AD6657A Data Sheet 100 100 90 95 SFDR (dBFS) SFDR (dBc) 80 90 SNR (dBFS) 70 85 60 80 50 75 SFDR (dBc) 40 70 SNR (dBFS) 30 65 SNR (dBc) 20 60 10 55 0 50 30.00 51.25 72.50 93.75 115.00 136.25 157.50 178.75 200.00 SAMPLE RATE (MSPS) INPUT AMPLITUDE (dBFS) Figure 17. Single Tone SNR/SFDR vs. Input Amplitude (AIN), Figure 20. Single Tone SNR/SFDR vs. Sample Rate (f ), S fIN = 140.3 MHz f = 70.3 MHz IN 95 95 SFDR (dBc) 90 90 85 SFDR (dBc) 85 80 80 75 70 75 65 SNR (dBFS) 70 SNR (dBFS) 60 65 55 60 50 30.00 51.25 72.50 93.75 115.00 136.25 157.50 178.75 200.00 SAMPLE RATE (MSPS) INPUT FREQUENCY (MHz) Figure 18. Single Tone SNR/SFDR vs. Input Frequency (fIN), Figure 21. Single Tone SNR/SFDR vs. Sample Rate (fS), 1.75 V p-p Full Scale fIN = 140.3 MHz 95 0 185MSPS 169.1MHz @ –7dBFS 90 172.1MHz @ –7dBFS –20 SFDR = 88.5dBc SFDR (dBc) 85 –40 80 –60 75 –80 70 SNR (dBFS) –100 65 60 –120 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 19. Single Tone SNR/SFDR vs. Input Frequency (f ), Figure 22. Two Tone FFT, fIN1 = 169.1 MHz and fIN2 = 172.1 MHz IN 2.0 V p-p Full Scale Rev. 0 | Page 16 of 36 SNR/SFDR (dBFS AND dBc) SNR/SFDR (dBFS AND dBc) SNR/SFDR (dBc AND dBFS) 60 60 –90 –85 80 80 –80 100 100 –75 120 120 –70 140 140 –65 160 160 –60 180 180 –55 200 200 –50 220 220 –45 240 240 –40 260 260 –35 280 280 –30 300 300 –25 320 320 –20 340 340 –15 360 360 –10 380 380 –5 0 400 400 09684-019 09684-018 09684-017 AMPLITUDE (dBFS) SNR/SFDR (dBFS AND dBc) SNR/SFDR (dBFS AND dBc) 09684-021 09684-020 09684-122 Data Sheet AD6657A 0 0.20 0.15 –20 0.10 SFDR (dBc) –40 0.05 IMD3 (dBc) –60 0 –0.05 –80 SFDR (dBFS) –0.10 –100 –0.15 IMD3 (dBFS) –0.20 –120 –90 –78 –66 –54 –42 –30 –18 –6 0 500 1000 1500 2000 INPUT AMPLITUDE (dBFS) OUTPUT CODE Figure 23. Two Tone SFDR/IMD3 vs. Input Amplitude (AIN), Figure 26. DNL, fIN = 30.3 MHz fIN1 = 169.1 MHz and fIN2 = 172.1 MHz 2,500,000 69 68 2,000,000 67 66 1,500,000 65 64 1,000,000 63 62 500,000 61 60 0 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 30 35 40 45 50 55 60 65 70 OUTPUT CODE DUTY CYCLE (%) Figure 24. Grounded Input Histogram Figure 27. SNR vs. Duty Cycle, fIN = 10.3 MHz 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 1500 2000 OUTPUT CODE Figure 25. INL, fIN = 30.3 MHz Rev. 0 | Page 17 of 36 NUMBER OF HITS INL ERROR (LSB) SFDR/IMD3 (dBc AND dBFS) 09684-125 09684-123 09684-124 DNL ERROR (LSB) SNR (dBFS) 09684-127 09684-126 AD6657A Data Sheet EQUIVALENT CIRCUITS AVDD 350Ω SCLK OR 30kΩ VIN PDWN Figure 28. Equivalent Analog Input Circuit Figure 32. Equivalent SCLK and PDWN Input Circuit AVDD AVDD 30kΩ AVDD AVDD 350Ω 0.9V CSB OR 15kΩ 15kΩ MODE CLK+ CLK– Figure 29. Equivalent Clock Input Circuit Figure 33. Equivalent CSB and MODE Input Circuit DRVDD DRVDD V+ V– DATAOUT– DATAOUT+ 350Ω SDIO V– V+ 30kΩ Figure 30. Equivalent LVDS Output Circuit Figure 34. Equivalent SDIO Circuit AVDD AVDD SYNC 0.9V 16kΩ 0.9V Figure 31. Equivalent SYNC Input Circuit Rev. 0 | Page 18 of 36 09684-022 08557-025 09684-024 09684-023 09684-028 09684-027 09684-026 Data Sheet AD6657A THEORY OF OPERATION A small resistor in series with each input can help reduce the ADC ARCHITECTURE peak transient current required from the output stage of the The AD6657A architecture consists of a quad front-end sample- driving source. A shunt capacitor can be placed across the and-hold circuit, followed by a pipelined, switched capacitor inputs to provide dynamic charging currents. This passive ADC. The quantized outputs from each stage are combined into network creates a low-pass filter at the ADC input; therefore, a final 14-bit result in the digital correction logic. Alternately, the precise values are dependent on the application. the 14-bit result can be processed through the NSR block before In intermediate frequency (IF) undersampling applications, it is sent to the digital correction logic. any shunt capacitors should be reduced. In combination with The pipelined architecture permits the first stage to operate on the driving source impedance, the shunt capacitors limit the a new input sample and the remaining stages to operate on the input bandwidth. For more information on this subject, see the preceding samples. Sampling occurs on the rising edge of the clock. AN-742 Application Note, Frequency Domain Response of Each stage of the pipeline, excluding the last, consists of a low Switched-Capacitor ADCs; AN-827 Application Note, A Resonant resolution flash ADC connected to a switched-capacitor digital- Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; to-analog converter (DAC) and an interstage residue amplifier and the Analog Dialogue article, “Transformer-Coupled Front-End (MDAC). The residue amplifier magnifies the difference between for Wideband A/D Converters” (see www.analog.com). the reconstructed DAC output and the flash input for the next BIAS stage in the pipeline. One bit of redundancy is used in each stage S S to facilitate digital correction of flash errors. The last stage C C S FB simply consists of a flash ADC. VIN+ C C PAR1 PAR2 The input stage of each channel contains a differential sampling circuit that can be ac- or dc-coupled in differential or single-ended S H S modes. The output staging block aligns the data, corrects errors, C S and passes the data to the output buffers. The output buffers are VIN– powered from a separate supply, allowing adjustment of the output C C PAR1 C FB PAR2 S drive current. During power-down, the output buffers go into a S BIAS high impedance state. Figure 35. Switched Capacitor Input The AD6657A quad IF receiver can simultaneously digitize four For best dynamic performance, match the source impedances channels, making it ideal for diversity reception and digital pre- driving the VIN+ and VIN− pins. distortion (DPD) observation paths in telecommunication systems. An internal differential reference buffer creates positive and Synchronization capability is provided to allow synchronized negative reference voltages that define the input span of the ADC timing between multiple channels or multiple devices. core. The span of the ADC core is set by this buffer to 2 × VREF. Programming and control of the AD6657A are accomplished Input Common Mode using a 3-wire SPI-compatible serial interface. The analog inputs of the AD6657A are not internally dc biased. ANALOG INPUT CONSIDERATIONS In ac-coupled applications, the user must provide this bias The analog input to the AD6657A is a differential switched externally. An on-board common-mode voltage reference is capacitor circuit that has been designed for optimum perfor- included in the design and is available from the VCMx pins. mance while processing a differential input signal. Optimum performance is achieved when the common-mode The clock signal alternatively switches the input between sample voltage of the analog input is set by the VCMx pin voltage mode and hold mode (see Figure 35). When the input is switched (typically 0.5 × AVDD). The VCMx pins must be decoupled to sample mode, the signal source must be capable of charging to ground by a 0.1 µF capacitor. the sample capacitors and settling within 1/2 of a clock cycle. Rev. 0 | Page 19 of 36 09684-029 AD6657A Data Sheet Differential Input Configurations The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies Optimum performance is achieved when driving the AD6657A below a few megahertz (MHz). Excessive signal power can also in a differential input configuration. For baseband applications, cause core saturation, which leads to distortion. the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve The output common-mode voltage of the ADA4938-2 is easily the true SNR performance of the AD6657A. For applications in set with the VCMx pin of the AD6657A (see Figure 36), and the which SNR is a key parameter, differential double balun coupling driver can be configured in a Sallen-Key filter topology to provide is the recommended input configuration (see Figure 38). In this band limiting of the input signal. configuration, the input is ac-coupled and the CML is provided to 15pF each input through a 33 Ω resistor. These resistors compensate 200Ω for losses in the input baluns to provide a 50 Ω impedance to 33Ω 15Ω 90Ω VIN– AVDD VIN 76.8Ω the driver. 5pF ADC In the double balun and transformer configurations, the value ADA4938-2 0.1µF of the input capacitors and resistors is dependent on the input 33Ω 15Ω VCM VIN+ 120Ω frequency and source impedance and may need to be reduced 15pF 200Ω or removed. Table 10 lists recommended values to set the RC network. At higher input frequencies, good performance can be Figure 36. Differential Input Configuration Using the ADA4938-2 achieved by using a ferrite bead in series with a resistor and For baseband applications where SNR is a key parameter, removing the capacitors. However, these values are dependent differential transformer coupling is the recommended input on the input signal and should be used as a starting guide only. configuration. An example is shown in Figure 37. To bias the Table 10. Example RC Network analog input, the VCM voltage can be connected to the center Frequency tap of the secondary winding of the transformer. Range R1 Series R2 Series C2 Shunt C2 (MHz) (Each) C1 Differential (Each) (Each) R2 0 to 100 33 Ω 5 pF 15 Ω 15 pF VIN+ R1 100 to 200 10 Ω 5 pF 10 Ω 10 pF 2V p-p 49.9Ω 1 C1 ADC 100 to 300 10 Ω Remove 66 Ω Remove R2 R1 1 In this configuration, R1 is a ferrite bead with a value of 10 Ω @ 100 MHz. VCM VIN– An alternative to using a transformer-coupled input at frequen- 0.1µF C2 cies in the second Nyquist zone is to use the AD8352 differential driver (see Figure 39). For more information, see the AD8352 Figure 37. Differential Transformer-Coupled Configuration data sheet. C2 0.1µF 0.1µF R1 R2 VIN+ 2V p-p 33Ω P S S P C1 ADC A 0.1µF 33Ω 0.1µF R1 R2 VCM VIN– C2 Figure 38. Differential Double Balun Input Configuration V CC 0.1µF 0.1µF 0Ω 16 8, 13 ANALOG INPUT 0.1µF R 11 1 VIN+ 200Ω 2 C ADC C R R D D G AD8352 3 200Ω 0.1µF 10 4 R VIN– VCM 5 14 ANALOG INPUT 0Ω 0.1µF 0.1µF 0.1µF Figure 39. Differential Input Configuration Using the AD8352 Rev. 0 | Page 20 of 36 09684-031 09684-030 09684-032 09684-033 Data Sheet AD6657A ANALOG XFMR 1:4 Z INPUT ETC4-1T-7 33Ω 0.1µF 0.1µF 121Ω 431nH 0.1µF INPUT 3.0kΩ 3.0pF 121Ω 0.1µF ADC Z = 50Ω INTERNAL INPUT Z 33Ω 0.1µF VCM Figure 40. 1:4 Transformer Passive Configuration 1000pF 180nH 220nH 1µH 15pF 165Ω VPOS AD6657A AD8376 301Ω 5.1pF 3.9pF VCM 3.0kΩ║3.0pF 165Ω 1nF 1µH 1nF 68nH 180nH 220nH 1000pF NOTES 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS). Figure 41. Active Front-End Configuration Using the AD8376 Figure 43 and Figure 44 show two preferred methods for clocking For the popular IF band of 140 MHz, Figure 40 shows an the AD6657A (at clock rates of up to 625 MHz). A low jitter clock example of a 1:4 transformer passive configuration where a source is converted from a single-ended signal to a differential differential inductor is used to resonate with the internal input signal using either an RF balun or an RF transformer. capacitance of the AD6657A. This configuration realizes excellent noise and distortion performance. Figure 41 shows an example The RF balun configuration is recommended for clock frequencies of an active front-end configuration using the AD8376 dual vari- between 125 MHz and 625 MHz, and the RF transformer config- able gain amplifier (VGA). This configuration is recommended uration is recommended for clock frequencies from 10 MHz to when signal gain is required. 200 MHz. The back-to-back Schottky diodes across the trans- former/balun secondary limit clock excursions into the AD6657A CLOCK INPUT CONSIDERATIONS to approximately 0.8 V p-p differential. This limit helps to prevent For optimum performance, clock the AD6657A sample clock the large voltage swings of the clock from feeding through to inputs, CLK+ and CLK−, with a differential signal. The signal is other portions of the AD6657A, yet preserves the fast rise and typically ac-coupled into the CLK+ and CLK− pins via a trans- fall times of the signal that are critical to a low jitter performance. former or capacitors. These pins are biased internally and require no external bias (see Figure 42). ADT1-1WT, 1:1Z AVDD 0.1µF 0.1µF XFMR CLOCK CLK+ INPUT 100Ω ADC 50Ω 1.2V 0.1µF CLK– CLK+ CLK– SCHOTTKY 0.1µF DIODES: HSMS2822 2pF 2pF Figure 43. Transformer-Coupled Differential Clock (Up to 200 MHz) Figure 42. Equivalent Clock Input Circuit 1nF 0.1µF CLOCK CLK+ Clock Input Options INPUT 50Ω ADC 0.1µF The AD6657A has a very flexible clock input structure. The 1nF CLK– clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. SCHOTTKY DIODES: Regardless of the type of signal being used, clock source jitter is HSMS2822 of the most concern (see the Jitter Considerations section). Figure 44. Balun-Coupled Differential Clock (Up to 625 MHz) Rev. 0 | Page 21 of 36 09684-036 09684-034 09684-035 09684-038 09684-037 AD6657A Data Sheet CLK+ can be driven directly from a CMOS gate. Although If a low jitter clock source is not available, another option is to the CLK+ input circuit supply is AVDD (1.8 V), this input is ac couple a differential PECL signal to the sample clock input designed to withstand input voltages of up to 3.6 V, making the pins, as shown in Figure 45. The AD9510/AD9511/AD9512/ selection of the drive logic voltage very flexible (see Figure 48). AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance. V CC OPTIONAL 0.1µF 0.1µF 1kΩ AD951x 100Ω CLOCK CLK+ CMOS DRIVER INPUT 0.1µF 0.1µF 1 50Ω 1kΩ CLOCK CLK+ ADC INPUT 0.1µF AD951x 100Ω ADC CLK– PECL DRIVER 0.1µF 0.1µF CLOCK CLK– 1 50Ω RESISTOR IS OPTIONAL. INPUT 240Ω 240Ω 50kΩ 50kΩ Figure 48. Single-Ended 3.3 V CMOS Input Clock (Up to 200 MHz) Figure 45. Differential PECL Sample Clock (Up to 625 MHz) Input Clock Divider The AD6657A contains an input clock divider with the ability to A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 46. The AD9510/ divide the input clock by integer values from 1 to 8. AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock The AD6657A clock divider can be synchronized using the drivers offer excellent jitter performance. external SYNC input. Bit 1 of Register 0x3A enables the clock divider to be resynchronized on every SYNC signal. A valid SYNC causes the clock divider to reset to its initial state. This 0.1µF 0.1µF CLOCK CLK+ synchronization feature allows multiple parts to have their clock INPUT AD951x dividers aligned to guarantee simultaneous input sampling. 100Ω ADC LVDS DRIVER 0.1µF 0.1µF CLOCK CLK– Clock Duty Cycle INPUT 50kΩ 50kΩ Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be Figure 46. Differential LVDS Sample Clock (Up to 625 MHz) sensitive to clock duty cycle. Commonly, a ±5% tolerance is In some applications, it may be acceptable to drive the sample required on the clock duty cycle to maintain dynamic perfor- clock inputs with a single-ended CMOS signal. In such applica- mance characteristics. tions, drive the CLK+ pin directly from a CMOS gate, and The AD6657A contains a DCS that retimes the nonsampling bypass the CLK− pin to ground with a 0.1 μF capacitor in (falling) edge, providing an internal clock signal with a nominal parallel with a 39 kΩ resistor (see Figure 47). 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the V CC AD6657A. Noise and distortion performance are nearly flat for OPTIONAL 0.1µF 0.1µF 1kΩ AD951x 100Ω CLOCK CLK+ a wide range of duty cycles with the DCS enabled. CMOS DRIVER INPUT 1 1kΩ 50Ω ADC Jitter in the rising edge of the input is of paramount concern and is not easily reduced by the internal stabilization circuit. The duty CLK– 0.1µF 39kΩ cycle control loop does not function for clock rates at less than 40 MHz nominally. The loop has a time constant associated with 1 50Ω RESISTOR IS OPTIONAL. it that must be considered in applications in which the clock Figure 47. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) rate can change dynamically. A wait time of 1.5 µs to 5 µs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. Rev. 0 | Page 22 of 36 09684-041 09684-040 09684-039 09684-042 Data Sheet AD6657A 1.5 0.60 Jitter Considerations 1.4 0.55 High speed, high resolution ADCs are sensitive to the quality of 1.3 0.50 1.2 I the clock input. The degradation in SNR from the low frequency AVDD 0.45 1.1 SNR (SNRLF) at a given input frequency (fIN) due to jitter (tJRMS) 1.0 0.40 can be calculated by 0.9 TOTAL POWER 0.35 0.8 2 (−SNR /10) LF SNR = −10log[(2π × f × t ) + 10 ] HF IN JRMS 0.30 0.7 0.25 0.6 In the equation, the rms aperture jitter represents the clock 0.5 0.20 input jitter specification. IF undersampling applications are 0.4 0.15 I DRVDD particularly sensitive to jitter, as shown in Figure 49. 0.3 0.10 0.2 80 0.05 0.1 0 0 0.05ps 30 40 50 60 70 80 90 100110120130140150160170180190 200 75 SAMPLING FREQUENCY (MSPS) Figure 50. Power and Current vs. Sampling Frequency 70 0.20ps By asserting PDWN (either through the SPI port or by asserting 65 the PDWN pin high), the AD6657A is placed in power-down mode. In this state, the ADC typically dissipates 4.5 mW. 0.50ps 60 During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the 55 1.00ps AD6657A to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and 1.50ps 50 should not exceed that supply voltage. 1 10 100 1k INPUT FREQUENCY (MHz) Low power dissipation in power-down mode is achieved by Figure 49. SNR vs. Input Frequency and Jitter shutting down the reference, reference buffer, biasing networks, In cases where aperture jitter may affect the dynamic range of and clock. Internal capacitors are discharged when entering the AD6657A, treat the clock input as an analog signal. Separate power-down mode and must be recharged when returning to power supplies for clock drivers should be separated from the normal operation. As a result, wake-up time is related to the ADC output driver supplies to avoid modulating the clock signal time spent in power-down mode; shorter power-down cycles with digital noise. Low jitter, crystal controlled oscillators make result in proportionally shorter wake-up times. the best clock sources. If the clock is generated from another type When using the SPI port interface, the user can place the ADC of source (by gating, dividing, or another method), it should be in power-down mode or standby mode. Standby mode allows retimed by the original clock at the last step. Refer to the AN-501 the user to keep the internal reference circuitry powered when Application Note and AN-756 Application Note for more informa- faster wake-up times are required. See the Memory Map Register tion about jitter performance as it relates to ADCs (available at Descriptions section for more details. www.analog.com). CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE The AD6657A has a SYNC input that offers the user flexible The power dissipated by the AD6657A is proportional to its clock synchronization options for synchronizing the clock divider. The rate (see Figure 50). The digital power dissipation does not vary clock divider sync feature is useful for guaranteeing synchronized significantly because it is determined primarily by the DRVDD sample clocks across multiple ADCs. supply and the bias current of the LVDS drivers. The SYNC input is internally synchronized to the sample clock; Reducing the capacitive load presented to the output drivers can however, to ensure that there is no timing uncertainty between minimize digital power consumption. The data in Figure 50 was multiple parts, externally synchronize the SYNC input signal to obtained using the same operating conditions as those used in the input clock signal, meeting the setup and hold times shown the Typical Performance Characteristics section, with a 5 pF in Table 5. Drive the SYNC input using a single-ended CMOS load on each output driver. type signal. Rev. 0 | Page 23 of 36 SNR (dBc) 09684-043 TOTAL POWER (W) CURRENT (A) 09684-050 AD6657A Data Sheet Minimize the length of the output data lines and minimize the DIGITAL OUTPUTS loads placed on them to reduce transients within the AD6657A The AD6657A output drivers are configured to interface with because these transients can degrade converter dynamic per- LVDS outputs using a DRVDD supply voltage of 1.8 V. The formance. output bits are DDR LVDS as shown in Figure 2. Applications that require the ADC to drive large capacitive loads or large The lowest typical conversion rate of the AD6657A is 40 MSPS. fanouts may require external buffers or latches. At clock rates below 40 MSPS, dynamic performance can degrade. As described in the AN-877 Application Note, Interfacing to Data Clock Output (DCO) High Speed ADCs via SPI, the data format can be selected for The AD6657A provides a data clock output (DCO) signal offset binary or twos complement when using the SPI control. intended for capturing the data in an external register. The output data for Channel A and Channel C is valid when DCO TIMING is high; the output data for Channel B and Channel D is valid The AD6657A provides latched data with a latency of when DCO is low (see Figure 2). nine clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Table 11. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode VIN+ − VIN− < −V − 0.5 LSB 000 0000 0000 100 0000 0000 REF VIN+ − VIN− = −VREF 000 0000 0000 100 0000 0000 VIN+ − VIN− = 0 100 0000 0000 000 0000 0000 VIN+ − VIN− = +VREF − 1.0 LSB 111 1111 1111 011 1111 1111 VIN+ − VIN− > +V − 0.5 LSB 111 1111 1111 011 1111 1111 REF Rev. 0 | Page 24 of 36 Data Sheet AD6657A NOISE SHAPING REQUANTIZER The AD6657A features a noise shaping requantizer (NSR) to allow Figure 51 to Figure 53 show the typical spectrum that can be higher than an 11-bit SNR to be maintained in a subset of the expected from the AD6657A in the 22% BW mode for three Nyquist band. The harmonic performance of the receiver is different tuning words. unaffected by the NSR feature. 0 185MSPS 140.3MHz @ –1dBFS When enabled, the NSR contributes an additional 0.6 dB of NSR 22% BW MODE, TW = 13 –20 SNR = 73.4dB (75.0dBFS) loss to the input signal, such that a 0 dBFS input is reduced to SFDR = 91dBc −0.6 dBFS at the output pins. –40 The NSR feature can be independently controlled per channel –60 via the SPI or via the MODE pin. THIRD HARMONIC –80 Two different bandwidth modes are provided; the mode can be selected from the SPI port. In each of the two modes, the center –100 frequency of the band can be tuned such that IFs can be placed anywhere in the Nyquist band. –120 22% BW MODE (>40 MHZ at 184.32 MSPS) –140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 The first bandwidth mode offers excellent noise performance FREQUENCY (MHz) over 22% of the ADC sample rate (44% of the Nyquist band) Figure 51. 22% BW Mode, Tuning Word = 13 and can be centered by setting the NSR mode bits in the NSR 0 185MSPS control register (Address 0x3C) to 000. In this mode, the useful 140.3MHz @ –1dBFS frequency range can be set using the 6-bit tuning word in the NSR 22% BW MODE, TW = 28 –20 SNR = 73.4dB (75.0dBFS) NSR tuning word register (Address 0x3E). SFDR = 91dBc –40 There are 57 possible tuning words (TW); each step is 0.5% of the ADC sample rate. The following three equations describe –60 the left band edge (f0), the channel center (fCENTER), and the right THIRD HARMONIC band edge (f1), respectively. –80 f = f × .005 × TW 0 ADC –100 f = f + 0.11 × f CENTER 0 ADC –120 f = f + 0.22 × f 1 0 ADC –140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) Figure 52. 22% BW Mode, Tuning Word = 28 (f /4 Tuning) S 0 185MSPS 140.3MHz @ –1dBFS NSR 22% BW MODE, TW = 41 –20 SNR = 73.4dB (75.0dBFS) SFDR = 91dBc –40 –60 THIRD HARMONIC –80 –100 –120 –140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) Figure 53. 22% BW Mode, Tuning Word = 41 Rev. 0 | Page 25 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09684-053 09684-052 09684-051 AD6657A Data Sheet 0 33% BW MODE (>60 MHZ AT 184.32 MSPS) 185MSPS 140.3MHz @ –1dBFS NSR 33% BW MODE, TW = 17 The second bandwidth mode offers excellent noise performance –20 SNR = 70.9dB (72.5dBFS) over 33% of the ADC sample rate (66% of the Nyquist band) SFDR = 91dBc –40 and can be centered by setting the NSR mode bits in the NSR control register (Address 0x3C) to 001. In this mode, the useful –60 frequency range can be set using the 6-bit tuning word in the THIRD HARMONIC NSR tuning word register (Address 0x3E). –80 There are 34 possible tuning words (TW); each step is 0.5% of –100 the ADC sample rate. The following three equations describe the left band edge (f0), the channel center (fCENTER), and the right –120 band edge (f1), respectively. –140 f = f × .005 × TW 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 0 ADC FREQUENCY (MHz) f = f + 0.165 × f CENTER 0 ADC Figure 56. 33% BW Mode, Tuning Word = 17 f = f + 0.33 × f 1 0 ADC Figure 54 to Figure 56 show the typical spectrum that can be expected from the AD6657A in the 33% BW mode for three different tuning words. 0 185MSPS 140.3MHz @ –1dBFS NSR 33% BW MODE, TW = 5 –20 SNR = 70.9dB (72.5dBFS) SFDR = 91dBc –40 –60 THIRD HARMONIC –80 –100 –120 –140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) Figure 54. 33% BW Mode, Tuning Word = 5 0 185MSPS 140.3MHz @ –1dBFS NSR 33% BW MODE, TW = 17 –20 SNR = 71.1dB (72.7dBFS) SFDR = 91dBc –40 –60 THIRD HARMONIC –80 –100 –120 –140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) Figure 55. 33% BW Mode, Tuning Word = 17 (f /4 Tuning) S Rev. 0 | Page 26 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09684-055 09684-154 AMPLITUDE (dBFS) 09684-056 Data Sheet AD6657A 0 36% BW MODE (>65 MHZ AT 184.32 MSPS) 185MSPS 140.3MHz @ –1dBFS NSR 36% BW MODE, TW = 28 The third bandwidth mode offers excellent noise performance –20 SNR = 70.4dB (72.0dBFS) over 36% of the ADC sample rate (72% of the Nyquist band) SFDR = 91dBc –40 and can be centered by setting the NSR mode bits in the NSR control register (Address 0x3C) to 010. In this mode, the useful –60 frequency range can be set using the 6-bit tuning word in the THIRD HARMONIC NSR tuning register (Address 0x3E). –80 There are 28 possible tuning words (TW); each step is 0.5% of –100 the ADC sample rate. The following three equations describe the left band edge (f0), the channel center (fCENTER), and the right –120 band edge (f1), respectively. –140 f = f × .005 × TW 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 0 ADC FREQUENCY (MHz) f = f + 0.18 × f CENTER 0 ADC Figure 59. 36% BW Mode, Tuning Word = 28 f = f + 0.36 × f 1 0 ADC MODE PIN Figure 57 to Figure 59 show the typical spectrum that can be The MODE pin input allows convenient control of the NSR expected from the AD6657A in the 36% BW mode for three feature. A logic low enables NSR mode and a logic high sets the different tuning words. receiver to a straight 11-bit mode with NSR disabled. By default, 0 185MSPS the MODE pin is pulled high internally to disable the NSR. 140.3MHz @ –1dBFS –20 NSR 36% BW MODE, TW = 0 Each channel can be individually configured to ignore the SNR = 70.4dB (72.0dBFS) SFDR = 91dBc MODE pin state by writing to Bit 4 of the NSR control register –40 at Address 0x3C. Use of the NSR control register in conjunction with the MODE pin allows for very flexible control of the NSR –60 THIRD HARMONIC feature on a per channel basis. –80 –100 –120 –140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) Figure 57. 36% BW Mode, Tuning Word = 0 0 185MSPS 140.3MHz @ –1dBFS –20 NSR 36% BW MODE, TW = 14 SNR = 70.4dB (72.0dBFS) SFDR = 91dBc –40 –60 THIRD HARMONIC –80 –100 –120 –140 0 9.25 18.50 27.75 37.00 46.25 55.50 64.75 74.00 83.25 92.50 FREQUENCY (MHz) Figure 58. 36% BW Mode, Tuning Word = 14 (f /4 Tuning) S Rev. 0 | Page 27 of 36 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09684-058 09684-057 AMPLITUDE (dBFS) 09684-059 AD6657A Data Sheet BUILT-IN SELF TEST (BIST) AND OUTPUT TEST The AD6657A includes built-in test features designed to verify The outputs are not disconnected during this test, so the PN the integrity of each channel and to facilitate board-level debug- sequence can be observed as it runs. The PN sequence can be ging. A built-in self test (BIST) feature is included that verifies continued from its last value or reset from the beginning, based the integrity of the digital datapath of the AD6657A. Various on the value programmed in Register 0x0E, Bit 2. The BIST output test options are also provided to place predictable values signature result varies based on the channel configuration. on the outputs of the AD6657A. OUTPUT TEST MODES BIST The output test options are shown in Table 13. When an output The BIST is a thorough test of the digital portion of the selected test mode is enabled, the analog section of the receiver is dis- AD6657A signal path. When enabled, the test runs from an connected from the digital back-end blocks, and the test pattern internal pseudorandom noise (PN) source through the digital is run through the output formatting block. Some of the test datapath starting at the ADC block output. The BIST sequence patterns are subject to output formatting. The seed value for the runs for 512 cycles and stops. The BIST signature value for the PN sequence tests can be forced if the PN reset bits are used to selected channel is written to Register 0x24 and Register 0x25. hold the generator in reset mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an If more than one channel is BIST enabled, the channel that analog signal (if present, the analog signal is ignored), but they is first according to alphabetical order is written to the BIST require an encode clock. For more information, see the AN-877 signature registers. For example, if Channel B and Channel C Application Note, Interfacing to High Speed ADCs via SPI. are BIST enabled, the results from Channel B are written to the BIST signature registers. Rev. 0 | Page 28 of 36 Data Sheet AD6657A SERIAL PORT INTERFACE (SPI) The AD6657A serial port interface (SPI) allows the user to con- During an instruction phase, a 16-bit instruction is transmitted. figure the receiver for specific functions or operations through a The first bit of the first byte in a serial data transfer frame indicates structured internal register space. The SPI provides added flexibility whether a read command or a write command is issued. Data and customization, depending on the application. Addresses are follows the instruction phase, and its length is determined by accessed via the serial port and can be written to or read from the W0 and W1 bits. All data is composed of 8-bit words. via the port. Memory is organized into bytes that can be further The instruction phase determines whether the serial frame is a divided into fields, which are documented in the Memory Map read or write operation, allowing the serial port to be used both section. For detailed operational information, see the AN-877 to program the chip and to read the contents of the on-chip Application Note, Interfacing to High Speed ADCs via SPI. memory. If the instruction is a read operation, the serial data input/output (SDIO) pin changes direction from an input to an CONFIGURATION USING THE SPI output at the appropriate point in the serial frame. Three pins define the SPI of the AD6657A: SCLK, SDIO, and Data can be sent in MSB first mode or in LSB first mode. MSB CSB (see Table 12). SCLK (a serial clock) is used to synchronize first is the default mode on power-up and can be changed via the read and write data presented from and to the AD6657A. the SPI port configuration register. For more information about SDIO (serial data input/output) is a bidirectional pin that allows this and other features, see the AN-877 Application Note, Inter- data to be sent to and read from the internal memory map facing to High Speed ADCs via SPI. registers. CSB (chip select bar) is an active low control that enables or disables the read and write cycles. HARDWARE INTERFACE Table 12. Serial Port Interface Pins The pins described in Table 12 constitute the physical interface between the user’s programming device and the serial port of Pin Function the AD6657A. The SCLK pin and the CSB pin function as SCLK Serial clock. Serial shift clock input. SCLK is used to synchronize serial interface reads and writes. inputs when using the SPI interface. The SDIO pin is SDIO Serial data input/output. Bidirectional pin that serves bidirectional, functioning as an input during the write phase as an input or an output, depending on the instruction and as an output during readback. being sent and the relative position in the timing frame. The SPI interface is flexible enough to be controlled by either CSB Chip select bar (active low). This control gates the read FPGAs or microcontrollers. One method for SPI configuration and write cycles. is described in detail in Application Note AN-812, Micro- The falling edge of the CSB pin, in conjunction with the rising controller-Based Serial Port Interface (SPI) Boot Circuit. edge of the SCLK pin, determines the start of the framing. An The SPI port should not be active during periods when the full example of the serial timing can be found in Figure 60 (for dynamic performance of the AD6657A is required. Because the symbol definitions, see Table 5). SCLK signal, the CSB signal, and the SDIO signal are typically CSB can be held low indefinitely, which permanently enables asynchronous to the ADC clock, noise from these signals can the device; this is called streaming. CSB can stall high between degrade AD6657A performance. If the on-board SPI bus is used bytes to allow for additional external timing. When CSB is tied for other devices, it may be necessary to provide buffers between high, SPI functions are placed in high impedance mode. this bus and the AD6657A to prevent these signals from transi- tioning at the receiver inputs during critical sampling periods. t t t t H DS HIGH CLK t t S DH t LOW CSB DON’T SCLK DON’T CARE CARE DON’T SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE CARE Figure 60. Serial Port Interface Timing Diagram Rev. 0 | Page 29 of 36 09684-054 AD6657A Data Sheet MEMORY MAP Logic Levels READING THE MEMORY MAP REGISTER TABLE An explanation of logic level terminology follows: Each row in the memory map register table has eight bit loca- tions (see Table 13). The memory map is roughly divided into  “Bit is set” is synonymous with “bit is set to Logic 1” or four sections: the chip configuration registers (Address 0x00 “writing Logic 1 for the bit.” and Address 0x01); the channel index and transfer registers  “Clear a bit” is synonymous with “bit is set to Logic 0” or (Address 0x05 and Address 0xFF); the ADC function registers, “writing Logic 0 for the bit.” including setup, control, and test (Address 0x08 to Address 0x25); Transfer Register Map and the digital feature control registers (Address 0x3A to Address 0x3E). Address 0x08 to Address 0x3E are shadowed. Writes to these addresses do not affect part operation until a transfer command The memory map register table (see Table 13) provides the is issued by writing 0x01 to Address 0xFF, thereby setting the default hexadecimal value for each hexadecimal address shown. transfer bit. This allows these registers to be updated internally The column with the heading (MSB) Bit 7 is the start of the and simultaneously when the transfer bit is set. The transfer bit default hexadecimal value given. The AN-877 Application Note, is autoclearing. Interfacing to High Speed ADCs via SPI, documents the functions controlled by Register 0x00 to Register 0xFF. The remaining Channel Specific Registers registers, Register 0x3A to Register 0x3E, are documented in Some channel setup functions, such as the NSR control func- the Memory Map Register Descriptions section. tion, can be programmed differently for each channel. In these Open Locations cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 13 All address and bit locations that are not included in Table 13 are as local. Local registers and bits can be accessed by setting the not currently supported for this device. Unused bits of a valid appropriate channel bits in Register 0x05. address location should be written with 0s. Writing to these locations is required only when part of an address location is If multiple channel bits are set, the subsequent write affects the open (for example, Address 0x18). If the entire address location registers of all selected channels. In a read cycle, select a single is open (for example, Address 0x13), this address location should channel only to read one of the registers. If multiple channels are not be written. selected during a SPI read cycle, the device returns the value for Channel A only. Registers and bits designated as global in Table 13 Default Values affect the entire device or the channel features for which there are After the AD6657A is reset, critical registers are loaded with no independent per channel settings. The settings in Register 0x05 default values. The default values for the registers are given in do not affect the global registers and bits. the memory map register table (see Table 13). Rev. 0 | Page 30 of 36 Data Sheet AD6657A MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 13 are not currently supported for this device. Table 13. Memory Map Registers Default Addr. Register (MSB) (LSB) Value (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments Chip Configuration Registers 0x00 SPI port Open LSB first Soft reset 1 Soft reset LSB first Open 0x18 Nibbles are 1 configuration mirrored so (global) that LSB first or MSB first mode is set correctly, regardless of shift mode. To control this register, all channel index bits in Register 0x05 must be set. 0x01 Chip ID 8-bit chip ID, Bits[7:0] 0x7B Read only. (global) AD6657A = 0x7B (default) Channel Index and Transfer Registers 0x05 Channel Enable Enable Open Open Channel D Channel C Channel B Channel A 0xCF Bits are set to index output output enable enable enable enable determine port for port for which Channel C Channel A channel on and and the chip Channel D Channel B receives the next write command; applies to local registers. 0xFF Transfer Open Open Open Open Open Open Open SW 0x00 Synchro- transfer nously 1 = on transfers 0 = off data from (default) the master shift register to the slave. ADC Function Registers 0x08 Power modes Open Open External Open Open Open Internal power-down 0x00 Determines power- mode (local) generic down pin 00 = normal operation modes of function (default) chip opera- (global) 01 = full power-down tion. 0 = full 10 = standby power- down 1 = standby 0x0B Clock divide Open Open Clock divide phase Clock divide ratio 0x00 (global) 000 = 0 input clock cycles delayed 000 = divide by 1 001 = 1 input clock cycle delayed 001 = divide by 2 010 = 2 input clock cycles delayed 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x0C Shuffle mode Open Open Open Open Open Open Shuffle mode enable 0x01 Enables or (local) 00 = shuffle disabled disables 01 = shuffle enabled shuffle mode. Rev. 0 | Page 31 of 36 AD6657A Data Sheet Default Addr. Register (MSB) (LSB) Value (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments 0x0D Test mode Open Open Reset Reset Open Output test mode 0x00 When set, (local) long PN short PN 000 = off (normal operation) the test data generator generator 001 = midscale short is placed on 0 = on 0 = on 010 = positive FS the output 1 = off 1 = off 011 = negative FS pins in place (default) (default) 100 = alternating checkerboard of normal 101 = PN sequence long data. 110 = PN sequence short 111 = 1/0 word toggle 0x0E BIST enable Open Open Open Open Open BIST reset Open BIST 0x00 When Bit 0 (local) 0 = on enable is set, the 1 = off 1 = on built-in self (default) 0 = off test function (default) is initiated. 0x10 Offset adjust Open Open Offset adjustment in LSBs from +127 to −128 0x00 Device offset (local) (twos complement format) trim. 011111 = +31 LSB 011110 = +30 LSB 011101 = +29 LSB … 000010 = +2 LSB 000001 = +1 LSB 000000 = 0 LSB … 111111 = −1 LSB 111110 = −2 LSB 111101 = −3 LSB … 100001 = −31 LSB 100000 = −32 LSB 0x14 Output mode Open Open Open Output Open Output Output format (local) 0x00 Configures (local) enable invert 00 = offset binary the outputs bar (local) 01 = twos and the (local) 1 = on complement format of 1 = off 0 = off the data. 0 = on 0x15 Output Open Open Open Open Output port LVDS drive current 0x01 Output adjust 0000 = 3.72 mA current (local) 0001 = 3.5 mA (default) adjustments. 0010 = 3.3 mA 0011 = 2.96 mA 0100 = 2.82 mA 0101 = 2.57 mA 0110 = 2.27 mA 0111 = 2.0 mA 1000 = 2.0 mA 0x16 Clock phase Invert Open Open Open Open Open Open Open 0x00 When Bit 7 control DCO clock is set, clock (local) 0 = off polarity is 1 = on reversed. 0x17 DCO output DCO Open Open Output port DCO clock delay 0x00 Enable DCO delay delay 00000 = 100 ps additional delay on the DCO pin delay and set (local) enable 00001 = 200 ps additional delay on the DCO pin the delay 0 = off 00010 = 300 ps additional delay on the DCO pin time. 1 = on … 11101 = 3.0 ns additional delay on the DCO pin 11110 = 3.1 ns additional delay on the DCO pin 11111 = 3.2 ns additional delay on the DCO pin 0x18 V select Open Open Open Internal V full-scale adjustment 0x00 Select REF REF (global) Main reference full-scale V adjustment adjustments REF 01111: internal 2.087 V p-p for V . REF … 00001: internal 1.772 V p-p 00000: internal 1.75 V p-p … 11111: internal 1.727 V p-p … 10000: internal 1.383 V p-p Rev. 0 | Page 32 of 36 Data Sheet AD6657A Default Addr. Register (MSB) (LSB) Value (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments 0x24 BIST BIST Signature[7:0] 0x00 Read only. signature LSB (local) 0x25 BIST signa- BIST Signature[15:8] 0x00 Read only. ture MSB (local) Digital Feature Control Registers 0x3A Sync control Open Open Open Open Open Clock divider Clock Master 0x00 Control (global) sync mode divider sync register to 0 = conti- sync enable synchronize nuous enable 0 = off the clock 1 = next sync 0 = off 1 = on divider. mode, next 1 = on rising edge of sync resets clock divider 0x3C NSR control Open Open Open MODE NSR mode NSR 0x00 Noise (local) pin 000 = 22% BW mode enable shaping disable 001 = 33% BW mode 0 = off requantizer 0 = 1 = on (NSR) 010 = 36% BW mode MODE (used only controls. pin used if 1 = Bit 4 = 1; MODE otherwise pin dis- ignored) abled 0x3E NSR tuning Open Open NSR tuning word 0x1C NSR word See the Noise Shaping Requantizer section. frequency (local) Equations for the tuning word are dependent on the NSR mode. tuning word. NSR Control (Register 0x3C) MEMORY MAP REGISTER DESCRIPTIONS Bits[7:5]—Reserved For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Bit 4—MODE Pin Disable Note, Interfacing to High Speed ADCs via SPI. Bit 4 specifies whether the selected channels are to be controlled Sync Control (Register 0x3A) by the MODE pin. Local registers act on the channels that are selected by the channel index register (Address 0x05). Bits[7:3]—Reserved Bit 2—Clock Divider Sync Mode Bits[3:1]—NSR Mode Bit 2 selects the mode of the clock divider sync function. When Bits[3:1] determine the bandwidth (BW) mode of the NSR. Bit 2 is low, continuous sync mode is enabled. When Bit 2 is When Bits[3:1] are set to 000, the NSR is configured for a 22% high, the clock divider is reset on the next rising edge of the BW mode that provides enhanced SNR performance over 22% sync signal. Subsequent rising edges of the sync signal are of the sample rate. When Bits[3:1] are set to 001, the NSR is ignored. configured for a 33% BW mode that provides enhanced SNR performance over 33% of the sample rate. When Bits[3:1] are Bit 1—Clock Divider Sync Enable set to 010, the NSR is configured for a 36% BW mode that pro- Bit 1 gates the sync pulse to the clock divider. The sync signal is vides enhanced SNR performance over 36% of the sample rate. enabled when Bit 1 is high and Bit 0 is high. This is continuous Bit 0—NSR Enable sync mode. The NSR is enabled when Bit 0 is high and disabled when Bit 0 Bit 0—Master Sync Enable is low. Bit 0 is ignored unless the MODE pin disable bit (Bit 4) Bit 0 must be high to enable any of the sync functions. If is set. the sync capability is not used, this bit should remain low to conserve power. Rev. 0 | Page 33 of 36 AD6657A Data Sheet NSR Tuning Word (Register 0x3E) there are 28 possible tuning words. For either mode, each step represents 0.5% of the ADC sample rate. For the equations used Bits[7:6]—Reserved to calculate the tuning word based on the BW mode of Bits[5:0]—NSR Tuning Word operation, see the Noise Shaping Requantizer section. The NSR tuning word sets the band edges of the NSR band. In 22% BW mode, there are 57 possible tuning words; in 33% BW mode, there are 34 possible tuning words; in 36% BW mode, Rev. 0 | Page 34 of 36 Data Sheet AD6657A APPLICATIONS INFORMATION VCMx Pins DESIGN GUIDELINES The VCMx pins are provided to set the common-mode level Before starting the design and layout of the AD6657A in a of the analog inputs. Decouple the VCMx pins to ground with a system, it is recommended that the designer become familiar 0.1 μF capacitor, as shown in Figure 37. with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. SPI Port Power and Ground Recommendations The SPI port should not be active during periods when the full dynamic performance of the AD6657A is required. Because the When connecting power to the AD6657A, it is recommended SCLK signal, the CSB signal, and the SDIO signal are typically that two separate 1.8 V supplies be used. Use one supply for asynchronous to the ADC clock, noise from these signals can analog (AVDD); use a separate supply for the digital outputs degrade AD6657A performance. If the on-board SPI bus is used (DRVDD). The AVDD and DRVDD supplies should be isolated for other devices, it may be necessary to provide buffers between with separate decoupling capacitors. Several different decoupling this bus and the AD6657A to prevent these signals from transi- capacitors can be used to cover both high and low frequencies. tioning at the receiver inputs during critical sampling periods. Locate these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. A single PCB ground plane is sufficient when using the AD6657A. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. Rev. 0 | Page 35 of 36 AD6657A Data Sheet PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 10.10 A1 BALL 10.00 SQ CORNER A1 BALL 9.90 12 11 10 9 8 7 6 5 4 3 2 1 CORNER A B C D 8.80 E BSC SQ F G H 0.80 J K L M TOP VIEW 0.60 BOTTOM VIEW REF DETAIL A * 1.40 MAX 0.65 MIN DETAIL A 0.25 MIN 0.50 COPLANARITY SEATING 0.45 0.20 PLANE 0.40 BALL DIAMETER * COMPLIANT WITH JEDEC STANDARDS MO-275-EEAB-1 WITH EXCEPTION TO PACKAGE HEIGHT. Figure 61. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-144-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD6657ABBCZ −40°C to +85°C 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-1 AD6657ABBCZRL −40°C to +85°C 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-1 AD6657AEBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. www.analog.com/AD6657A D09684-0-10/11(0) Rev. 0 | Page 36 of 36 10-21-2010-B