ANALOG DEVICES AD6654

14-Bit, 92.16 MSPS, 4-/6-Channel Wideband IF to Baseband Receiver AD6654 FEATURES APPLICATIONS SNR = 90 dB in 1.25 MHz bandwidth to Nyquist Multicarrier, multimode digital receivers SNR = 87 dB in 1.25 MHz bandwidth to 200 MHz GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, Integrated 14-bit, 92.16 MSPS ADC TD-SCDMA, WiMAX IF sampling frequencies to 200 MHz Micro and pico cell systems, software radios Internal 2.4 V reference, 2.2 V p-p analog input range Wireless local loop Internal differential track-and-hold analog input Smart antenna systems Processes 4/6 wideband carriers simultaneously In-building wireless telephony Fractional clock multiplier to 200 MHz Broadband data applications Programmable decimating FIR filters, interpolating Instrumentation and test equipment half-band filters and programmable AGC loops with 96 dB range Three 16-bit configurable parallel output ports User-configurable built-in self-test (BIST) capability 8-/16-bit microport and SPORT/SPI® serial port control FUNCTIONAL BLOCK DIAGRAM 4-CHANNEL AND 6-CHANNEL DIGITAL DOWN CONVERTER 14-BIT ADC FRONT END FIR1 FIR2 MRCF CIC5 CRCF LHB ENC+ HB1 HB2 DRCF NCO M = 1–32 M = 1–16 L = 1, 2 M = BYP, 2 M = BYP, 2 M = 1–16 INTERNAL ENC– TIMING FIR1 FIR2 MRCF CIC5 CRCF LHB DRCF HB1 HB2 14 NCO M = 1–32 M = 1–16 L = 1, 2 AIN+ M = 1–16 M = BYP, 2 M = BYP, 2 SHA ADC INPUT PA MATRIX AIN– FIR1 FIR2 MRCF CIC5 CRCF LHB HB1 HB2 DRCF NCO 2.4V M = 1–32 M = 1–16 L = 1, 2 M = BYP, 2 M = BYP, 2 M = 1–16 V REF V REF AGC PB PRN FIR1 FIR2 MRCF OVR CIC5 CRCF LHB GEN HB1 HB2 DRCF NCO (ADC OVERRANGE) M = 1–32 M = 1–16 L = 1, 2 M = BYP, 2 M = BYP, 2 M = 1–16 3 EXP PC EXP BITS (VGA LEVEL CONTROL) FIR1 FIR2 MRCF CIC5 CRCF LHB HB1 HB2 DRCF NCO PEAK/ M = 1–32 M = 1–16 L = 1, 2 M = BYP, 2 M = BYP, 2 M = 1–16 RMS MSMT FIR1 FIR2 MRCF CIC5 CRCF LHB HB1 HB2 DRCF NCO M = 1–32 M = 1–16 L = 1, 2 M = BYP, 2 M = BYP, 2 M = 1–16 (AVAILABLE IN 6-CHANNEL MODEL ONLY) AVDD, DRVDD, SYNC CLOCK 8-BIT/16-BIT MICROPORT SPORT/ M = DECIMATION VDDCORE, VDDIO, GND 0, 1, 2, 3 MULTIPLIER INTERFACE SPI INTERFACE L = INTERPOLATION Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved. DATA ROUTER MATRIX PARALLEL PORTS DATA ROUTING 05156-001 AD6654 TABLE OF CONTENTS General Description ......................................................................... 4 Input Crossbar Matrix ............................................................... 33 Product Highlights ....................................................................... 5 Numerically Controlled Oscillator (NCO) ................................. 34 Specifications..................................................................................... 6 NCO Frequency.......................................................................... 34 Recommended Operating Conditions ...................................... 6 Mixer............................................................................................ 35 ADC DC Specifications............................................................... 6 Bypass .......................................................................................... 35 ADC Digital Specifications ......................................................... 6 Clear Phase Accumulator on Hop ........................................... 35 ADC Switching Specifications.................................................... 7 Phase Dither................................................................................ 35 ADC AC Specifications ............................................................... 7 Amplitude Dither ....................................................................... 35 Electrical Characteristics............................................................. 8 NCO Frequency Hold-Off Register......................................... 35 Timing Characteristics ................................................................ 9 Phase Offset................................................................................. 35 Microport Timing Characteristics ........................................... 10 HOP Sync .................................................................................... 35 Serial Port Timing Characteristics........................................... 11 Fifth-Order CIC Filter ................................................................... 36 Timing Diagrams............................................................................ 12 Bypass .......................................................................................... 36 Absolute Maximum Ratings.......................................................... 18 CIC Rejection.............................................................................. 36 Thermal Characteristics ............................................................ 18 Example Calculations ................................................................ 37 Explanation of Test Levels......................................................... 18 FIR Half-Band Block...................................................................... 38 ESD Caution................................................................................ 18 3-Tap Fixed coefficient Filter (FIR1) ....................................... 38 Pin Configuration and Function Descriptions........................... 19 Decimate-by-2 Half-Band Filter (HB1) .................................. 38 Typical Performance Characteristics ........................................... 22 6-Tap Fixed Coefficient Filter (FIR2) ...................................... 39 ADC Equivalent Circuits............................................................... 25 Decimate-by-2 Half-Band Filter (HB2) .................................. 39 Terminology .................................................................................... 26 Intermediate Data Router.............................................................. 41 Theory of Operation ...................................................................... 27 Mono-Rate RAM Coefficient Filter (MRCF) ............................. 42 ADC Architecture ...................................................................... 27 Symmetry .................................................................................... 42 Application information ................................................................ 28 Clock Rate ................................................................................... 42 ADC Configuration Notes ........................................................ 28 Bypass .......................................................................................... 42 DDC Configuration Notes ........................................................ 29 Scaling.......................................................................................... 42 ADC Input Port Monitor Function.............................................. 31 Decimating RAM Coefficient Filter (DRCF) ............................. 43 Peak Detector Mode................................................................... 31 Bypass .......................................................................................... 43 Mean Power Mode ..................................................................... 31 Scaling.......................................................................................... 43 Threshold Crossing Mode......................................................... 32 Symmetry .................................................................................... 43 Additional Control Bits ............................................................. 32 Coefficient Offset ....................................................................... 43 Rev. 0 | Page 2 of 88 AD6654 Decimation Phase .......................................................................43 HOP ..............................................................................................58 Maximum Number of Taps Calculated....................................43 Serial Port Control ..........................................................................60 Programming DRCF Registers for Hardware Interface .....................................................................60 an Asymmetrical Filter...............................................................44 SPI Mode Timing........................................................................62 Programming DRCF Registers for a Symmetric Filter ..........44 SPORT Mode Timing.................................................................64 Channel RAM Coefficient Filter (CRCF) ....................................45 Programming Indirect Addressed Registers Bypass ...........................................................................................45 Using Serial Port..........................................................................67 Scaling...........................................................................................45 Connecting the AD6654 Serial Port to a Blackfin DSP.........69 Symmetry .....................................................................................45 Microport .........................................................................................70 Coefficient Offset ........................................................................45 Intel (Inm) Mode ........................................................................70 Decimation Phase .......................................................................45 Motorola (MNM) Mode ............................................................70 Maximum Number of TAPS Calculated..................................45 Accessing Multiple AD6654 Devices .......................................71 Programming CRCF Registers for an Memory Map ...................................................................................72 Asymmetrical Filter ....................................................................46 Reading the Memory Map Table...............................................72 Programming CRCF Registers for a Symmetrical Filter .......46 Bit Format ....................................................................................72 Interpolating Half-Band Filter.......................................................47 Open Locations ...........................................................................72 Output Data Router ........................................................................48 Default Values..............................................................................72 Interleaving Data.........................................................................48 Logic Levels..................................................................................72 Automatic Gain Control.................................................................49 Global Register Map ...................................................................74 AGC Loop ....................................................................................49 Input Port Register Map.............................................................76 Desired Signal Level Mode ........................................................50 Channel Register Map................................................................78 Desired Clipping Level Mode....................................................52 MRCF Coefficient Memory.......................................................79 AGC Synchronization.................................................................52 Output Port Register Map..........................................................82 SYNC Process ..............................................................................52 DDC Design Notes .........................................................................85 Parallel Port Output ........................................................................53 Outline Dimensions........................................................................87 Interleaved I/Q Mode .................................................................53 Ordering Guide ...........................................................................87 Parallel IQ Mode .........................................................................53 Master/Slave PCLK Modes ........................................................55 REVISION HISTORY Parallel Port Pin Functions ........................................................56 4/05—Revision 0: Initial Version User-Configurable Built-In Self-Test (BIST)...............................57 Chip Synchronization .....................................................................58 Start ...............................................................................................58 Rev. 0 | Page 3 of 88 AD6654 GENERAL DESCRIPTION The AD6654 is a mixed-signal IF-to-baseband receiver Following the CIC5 are two sets of filters. Each filter set consisting of a 14-bit, 92.16 MSPS analog-to-digital converter includes a nondecimating FIR filter and a decimate-by-2 half- (ADC) and a 4-/6-channel, multimode digital down-converter band filter. The FIR1 filter provides about 30 dB of rejection, (DDC) capable of processing up to six WCDMA (wideband while the HB1 provides about 77 dB of rejection. These two sets code division multiple access) channels. The AD6654 has been of filters can be used together to achieve a 107 dB stop-band optimized for the demanding filtering requirements of wide- alias rejection, or they can be individually bypassed to save band standards such as CDMA2000, UMTS, and TD-SCDMA, power. but is flexible enough to support wider standards such as The FIR2 filter provides about 30 dB of rejection, while the HB2 WiMAX. It is typically used as part of a radio system that filter provides about 65 dB of rejection. The filters can be used digitally demodulates and filters IF sampled signals. together to achieve more than 95 dB stop-band alias rejection, The ADC stage features a high performance track-and-hold or they can be individually bypassed to save power. FIR1 and input amplifier (T/H), integrated voltage reference, and 14-bit HB1 filters can run at the maximum ADC data port rate. In sampling resolution. Input signals up to 200 MHz can be contrast, FIR2 and HB2 can run with a maximum input rate of accurately digitized at encode rates up to 92.16 MSPS. The ADC 75 MSPS (input rate to FIR2 and HB2 filters). data outputs are internally routed directly into the DDC inputs, The programmable filtering is divided into three cascaded RAM where down-conversion, decimation and digital filtering are coefficient filters (RCFs) for flexible and power-efficient performed. An overrange (OVR) output bit provides indication filtering. The first filter in the cascade is the MRCF, consisting of excessive ADC input levels. An ADC data-ready (DR) output of a programmable nondecimating FIR. It is followed by bit provides a synchronized clock for the integrated DDC. programmable FIR filters (DRCF) with decimation from 1 to Data from the ADC is evaluated for peak or mean power in the 16. They can be used either together to provide high rejection input stage of the DDC, and the result is available to the user via filters, or independently to save power. The maximum input control register access. The DDC input stage also outputs 3-bit rate to the MRCF is one-fourth the PLL clock rate. level-indicator data (EXP) bits that can be used to control the The CRCF (Channel RCF) is the last programmable FIR filter gain of the external DVGA in 6 dB steps (up to 48 dB) to with programmable decimation from 1 to 16. It is typically used optimize signal amplitude into the ADC input. to meet the spectral mask requirements for the air standard of The DDC stage has the following signal processing stages: six interest. This could be an RRC, antialiasing filter or any other WCDMA-ready channels, each consisting of a frequency real data filter. Decimation in preceding blocks is used to keep translator, a fifth-order cascaded integrated comb filter, two sets the input rate of this stage as low as possible for the best filter of cascaded fixed coefficient FIR and half-band filters, three performance. cascaded programmable sum of product FIR filters, an The last filter stage in the chain is an interpolate-by-2 half-band interpolating half-band filter (IHB), and a digital automatic filter, which is used to up-sample the CRCF output to produce gain control (AGC) block. Multiple modes are supported for higher output oversampling. Signal rejection requirements for clocking data out of the chip. Programming is accomplished via this stage are relaxed, because preceding filters have already serial or microport interfaces. filtered the blockers and adjacent carriers. Frequency translation is accomplished with a 32-bit complex The DDC input port of the AD6654 has its own clock input numerically controlled oscillator (NCO). The NCO has greater used for latching the input data, as well as for providing the than 110 dBc SDFR. This stage translates a real input signal input for an onboard PLL clock multiplier. The output of the from an intermediate frequency (IF) to a baseband complex PLL clock is used for processing all filters and processing blocks digital output. Phase and amplitude dither can be enabled on- beyond the data router following CIC filter. The PLL clock can chip to improve spurious performance of the NCO. A 16-bit be programmed to have a maximum clock rate of 200 MHz. phase-offset word is available to create a known phase relation- Typically, the DDC input clock is driven directly from the ship between multiple AD6654 chips or channels. The NCO can integrated ADC’s data-ready (DR) output to ensure proper also be bypassed. synchronization. Following frequency translation is a fifth-order CIC filter with a A data routing block is used to distribute data from the CICs to programmable decimation between 1 and 32. This filter is used the various channel filters. This block allows multiple back-end to efficiently lower the sample rate, while providing sufficient filter chains to work together to process high bandwidth signals alias rejection at frequencies at higher offsets from the signal or to make even sharper filter transitions than a single channel of interest. Rev. 0 | Page 4 of 88 AD6654 can perform. It can also allow complex filtering operations to be Channel 5 are not available (see Figure 1). The 4-channel device achieved in the programmable filters. has the same DDC input port features, output ports, and memory map as the 6-channel device. On the 4-channel The digital AGC provides the user with scaled digital outputs version, the memory map section for Channel 4 and Channel 5 based on the rms level of the signal present at the output of the can be programmed and read back, but the two extra channels digital filters. The user can set the requested level and time are disabled internally. constant of the AGC loop for optimum performance of the postprocessor. This is a critical function in the base station for PRODUCT HIGHLIGHTS CDMA application, where the power level must be well 1. Integrated 14-bit, 92.16 MSPS ADC. controlled going into the RAKE receivers. It has programmable clipping and rounding control to provide different output 2. Track-and-hold amplifier analog input for excellent IF resolutions. sampling up to 200 MHz. The overall filter response for the AD6654 is the composite of 3. Four or six independent digital filtering channels. all the combined filter stages. Each successive filter stage is 4. RMS/peak power monitoring of the ADC data port and capable of narrower transition bandwidths, but requires a 96 dB range AGCs before the output ports. greater number of CLK cycles to calculate the output. The AD6654 features a fractional clock multiplier that uses the ADC 5. Three programmable RAM coefficient filters, three half- clock (which is slower than the DDC’s processing speed) to band filters, two fixed coefficient filters, and one fifth- produce a DDC master clock up to 200 MHz. This feature order CIC filter per channel. allows fractional multiplication of the input clock to allow the DDC to function at maximum speed while maintaining edge 6. Complex filtering by combining filtering capability of identity to the ADC clock. multiple channels. More decimation in the first filter stage minimizes overall 7. Three 16-bit parallel output ports operating at up to power consumption. Data from the device is interfaced to a 200 MHz clock. DSP/FPGA/baseband processor via high speed parallel ports 8. Blackfin®- and TigerSHARC®-compatible, 8-/16-bit (preferred), or a DSP-compatible microprocessor interface. microprocessor port. The AD6654 is available in 4-channel and 6-channel versions. 9. Synchronous serial communications port is compatible The primary focus of the data sheet is on the 6-channel part. with most serial interface standards: SPORT, SPI, and SSR. The only difference between the 6-channel and 4-channel devices is that, on the 4-channel version, Channel 4 and Rev. 0 | Page 5 of 88 AD6654 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Table 1. Parameter (Conditions) Temp Test Level Min Typ Max Unit 1 AVDD Full IV 4.75 5.0 5.25 V 2 DRVDD Full IV 3.0 3.3 3.6 V VDDCORE Full IV 1.65 1.8 1.95 V 2 VDDIO Full IV 3.0 3.3 3.6 V T IV −25 +25 +85 °C AMBIENT 1 Specified for dc supplies with linear rise-time <250 ms. 2 DRVDD and VDDIO can be operated from the same supply. ADC DC SPECIFICATIONS AVDD = 5.0 V, DRVDD = 3.3 V, VDDCORE = 1.8 V, VDDIO = 3.3 V, maximum rated sample rate, differential ENC and AIN, unless otherwise noted. Table 2. Parameter (Conditions) Temp Test Level Min Typ Max Unit RESOLUTION Full IV 14 Bits 1 INTERNAL VOLTAGE REFERENCE (V ) REF Output Voltage Full IV 2.4 V ANALOG INPUTS Differential Input Voltage Range Full IV 2.2 V p-p Differential Input Capacitance Full V 1.5 pF Differential Input Resistance Full V 1 kΩ Power Supply Rejection (PSRR) 25°C V ±1.0 mV/V 1 VREF is provided for setting the common-mode offset of a differential amplifier such as the AD8138 when a dc-coupled analog input is required. VREF should be buffered if used to drive additional circuit functions. ADC DIGITAL SPECIFICATIONS AVDD = 5.0 V, DRVDD = 3.3 V, VDDCORE = 1.8 V, VDDIO = 3.3 V, maximum rated sample rate, differential ADC input, unless otherwise noted. Table 3. Parameter (Conditions) Temp Test Level Min Typ Max Unit ENCODE INPUTS (ENC+, ENC−) Differential Input Voltage Full IV 0.4 V p-p Differential Input Resistance 25°C V 10 kΩ Differential Input Capacitance 25°C V 2.5 pF Rev. 0 | Page 6 of 88 AD6654 ADC SWITCHING SPECIFICATIONS AVDD = 5.0 V, DRVDD = 3.3 V, VDDCORE = 1.8 V, VDDIO = 3.3 V, maximum rated sample rate, differential input, unless otherwise noted. Table 4. Parameter (Conditions) Temp Test Level Min Typ Max Unit SWITCHING PERFORMANCE Maximum Conversion Rate Full II 92.16 MSPS Minimum Conversion Rate Full IV 30 MSPS 1 ENC Pulse Width High (t ) Full IV 5.154 5.425 ns ENCH 1 ENC Pulse Width Low (t ) Full IV 5.154 5.425 ns ENCL 1 Several internal timing parameters are a function of tENCL and tENCH, optimum performance will be achieved with 50/50 duty cycle. ADC AC SPECIFICATIONS AVDD = 5.0 V, DRVDD = 3.3 V, VDDCORE = 1.8 V, VDDIO = 3.3 V, maximum rated sample rate, differential input, unless otherwise noted. Table 5. Parameter (Conditions) Temp Test Level Min Typ Max Unit 1 SIGNAL-TO-NOISE RATIO (WITHOUT HARMONICS) Analog Input Frequency 37 MHz ADC (46.08 MHz BW) 25°C V 74.5 dB CDMA (1.25 MHz BW) Full II 88 90.0 dB WCDMA (5.0 MHz BW) 25°C V 84 dB Analog Input Frequency 70 MHz ADC (46.08 MHz BW) 25°C V 73.5 dB CDMA (1.25 MHz BW) Full II 87.5 89 dB WCDMA (5.0 MHz BW) 25°C V 83 dB Analog Input Frequency 150 MHz ADC (46.08 MHz BW) 25°C V 73 dB CDMA (1.25 MHz BW) 25°C V 88 dB WCDMA (5.0 MHz BW) 25°C V 82 dB Analog Input Frequency 200 MHz ADC (46.08 MHz BW) 25°C V 72 dB CDMA (1.25 MHz BW) 25°C V 87 dB WCDMA (5.0 MHz BW) 25°C V 81 dB 2 WORST HARMONIC (ANALOG INPUT @ −1 dBFS) 37 MHz Full II 85 93 dBc 70 MHz Full V 91 dBc 150 MHz Full V 71 dBc 200 MHz Full V 63 dBc 3 INTERMODULATION DISTORTION (TWO-TONES SEPARATED BY 1 MHz) Analog Input = 55/56 MHz 25°C V 90 dBc ANALOG INPUT BANDWIDTH 25°C V 270 MHz 1 Analog input = −1 dB below full scale. 2 Includes Harmonic 2 through Harmonic 6. 3 Analog input = each −7 dB below full scale. Rev. 0 | Page 7 of 88 AD6654 ELECTRICAL CHARACTERISTICS AVDD = 5.0 V, DRVDD = 3.3 V, VDDCORE = 1.8 V, VDDIO = 3.3 V, maximum rated sample rate, differential input, unless otherwise noted. Table 6. Parameter (Conditions) Temp Test Level Min Typ Max Unit LOGIC INPUTS (NOT 5 V TOLERANT) Logic Compatibility Full IV 3.3 V CMOS Logic 1 Voltage Full IV 2.0 3.6 V Logic 0 Voltage Full IV −0.3 +0.8 V Logic 1 Current Full IV 1 10 µA Logic 0 Current Full IV 1 10 µA Logic 1 Current (Inputs With Pull-Down) Full IV Logic 0 Current (Inputs With Pull-Up) Full IV Input Capacitance 25°C V 4 pF LOGIC OUTPUTS Logic Compatibility Full IV 3.3 V CMOS Logic 1 Voltage (I = 0.25 mA) Full IV 2.4 VDDIO − 0.2 V OH Logic 0 Voltage (I = 0.25 mA) Full IV 0.2 0.4 V OL SUPPLY CURRENTS 1 WCDMA (92.16 MSPS) EXAMPLE I 25°C V 275 mA AVDD I 25°C V 32 mA DRVDD IVDD 25°C V 460 mA IVDDIO 25°C V 60 mA 1 CDMA2000 (92.16 MSPS) EXAMPLE IAVDD 25°C V 275 mA IDRVDD 25°C V 32 mA IVDD 25°C V 435 mA I 25°C V 25 mA VDDIO 1, 2 TDS-CDMA (76.8 MSPS) EXAMPLE I 25°C V 275 mA AVDD I 25°C V 32 mA DRVDD I 25°C V 250 mA VDD IVDDIO 25°C V 15 mA TOTAL POWER DISSIPATION 1 WCDMA (92.16 MSPS) 25°C V 2.5 W 1 CDMA2000 (92.16 MSPS) 25°C V 2.3 W 1, 2 TDS-CDMA (76.8 MSPS) 25°C V 2.0 W 1 ADC input port, all six DDC channels, and the relevant signal processing blocks are active. 2 PLL is turned off for power savings. Rev. 0 | Page 8 of 88 AD6654 TIMING CHARACTERISTICS Table 7. 1, 2, 3 Parameter Temp Test Level Min Typ Max Unit CLK TIMING REQUIREMENTS tCLK CLK Period Full IV 10.85 ns tCLKL CLK Width Low Full IV 5.154 0.5 × tCLK ns tCLKH CLK Width High Full IV 5.154 0.5 × tCLK ns INPUT WIDEBAND DATA TIMING REQUIREMENTS tDEXP ↑CLK to EXP[2:0] Delay Full IV 5.98 10.74 ns PARALLEL OUTPUT PORT TIMING REQUIREMENTS (MASTER) t Full IV 1.77 3.86 ns DPREQ ↑PCLK to ↑Px REQ Delay (x = A, B, C) tDPP ↑PCLK to Px[15:0] Delay (x = A, B, C) Full IV 2.07 5.29 ns t Full IV 0.48 5.49 ns DPIQ ↑PCLK to Px IQ Delay (x = A, B, C) tDPCH ↑PCLK to Px CH[2:0] Delay (x = A, B, C) Full IV 0.38 5.35 ns tDPGAIN ↑PCLK to Px Gain Delay (x = A, B, C) Full IV 0.23 4.95 ns t Full IV 4.59 ns SPA Px ACK to ↑PCLK Setup Time (x = A, B, C) tHPA Px ACK to ↑PCLK Hold Time (x = A, B, C) Full IV 0.90 ns PARALLEL OUTPUT PORT TIMING REQUIREMENTS (SLAVE) t PCLK Period Full IV 5.0 ns PCLK t PCLK Low Period Full IV 1.7 0.5 × t ns PCLKL PCLK tPCLKH PCLK High Period Full IV 0.7 0.5 × tPCLK ns tDPREQ ↑PCLK to ↑Px REQ Delay (x = A, B, C) Full IV 4.72 8.87 ns tDPP ↑PCLK to Px[15:0] Delay (x = A, B, C) Full IV 4.8 8.48 ns t Full IV 4.83 10.94 ns DPIQ ↑PCLK to Px IQ Delay (x = A, B, C) tDPCH ↑PCLK to Px CH[2:0] Delay (x = A, B, C) Full IV 4.88 10.09 ns t Full IV 5.08 11.49 ns DPGAIN ↑PCLK to Px Gain Delay (x = A, B, C) t Full IV 6.09 ns SPA Px ACK to ↓PCLK Setup Time (x = A, B, C) tHPA Px ACK to ↓PCLK Hold Time (x = A, B, C) Full IV 1.0 ns MISC PINS TIMING REQUIREMENTS t RESET Width Low Full IV 30 ns RESET t IRP Full V 7.5 ns DIRP CPUCLK/SCLK to Delay t Full IV 0.87 ns SSYNC SYNC(0, 1, 2, 3) to ↑CLK Setup Time t Full IV 0.67 ns HSYNC SYNC(0, 1, 2, 3) to ↑CLK Hold Time 1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V, and the VDDIO range of 3.0 V to 3.6 V. 2 C = 40 pF on all outputs, unless otherwise noted. LOAD 3 These timing parameters are derived from the ADC ENC rate with DDC CLK driven directly from ADC DR output. Rev. 0 | Page 9 of 88 AD6654 MICROPORT TIMING CHARACTERISTICS Table 8. 1, 2 Parameter Temp Test Level Min Typ Max Unit MICROPORT CLOCK TIMING REQUIREMENTS tCPUCLK CPUCLK Period Full IV 10.0 ns tCPUCLKL CPUCLK Low Time Full IV 1.53 0.5 × tCPUCLK ns tCPUCLKH CPUCLK High Time Full IV 1.70 0.5 × tCPUCLK ns INM MODE WRITE TIMING (MODE = 0) 3 tSC Control to ↑CPUCLK Setup Time Full IV 0.80 ns 3 t Full IV 0.09 ns HC Control to ↑CPUCLK Hold Time t Full IV 0.76 ns SAM Address/Data to ↑CPUCLK Setup Time tHAM Address/Data to ↑CPUCLK Hold Time Full IV 0.20 ns t Full IV 3.51 6.72 ns DRDY ↑CPUCLK to RDY (DTACK) Delay tACC Write Access Time Full IV 3 × tCPUCLK 9 × tCPUCLK ns INM MODE READ TIMING (MODE = 0) 3 tSC Control to ↑CPUCLK Setup Time Full IV 1.00 ns 3 t Full IV 0.03 ns HC Control to ↑CPUCLK Hold Time t Full IV 0.80 ns SAM Address to ↑CPUCLK Setup Time tHAM Address to ↑CPUCLK Hold Time Full IV 0.20 ns t Full V 5.0 ns DD ↑CPUCLK to Data Delay t Full IV 4.50 6.72 ns DRDY ↑CPUCLK to RDY (DTACK) Delay tACC Read Access Time Full IV 3 × tCPUCLK 9 × tCPUCLK ns MNM MODE WRITE TIMING (MODE = 1) 3 tSC Control to ↑CPUCLK Setup Time Full IV 1.00 ns 3 t Full IV 0.00 ns HC Control to ↑CPUCLK Hold Time tSAM Address/Data to ↑CPUCLK Setup Time Full IV 0.00 ns t HAM Address/Data to ↑CPUCLK Hold Time Full IV 0.57 ns t Full IV 4.10 5.72 ns DDTACK ↑CPUCLK to DTACK (RDY) Delay tACC Write Access Time Full IV 3 × tCPUCLK 9 × tCPUCLK ns MNM MODE READ TIMING (MODE = 1) 3 tSC Control to ↑CPUCLK Setup Time Full IV 1.00 ns 3 t Full IV 0.00 ns HC Control to ↑CPUCLK Hold Time tSAM Address to ↑CPUCLK Setup Time Full IV 0.00 ns tHAM Address to ↑CPUCLK Hold Time Full IV 0.57 ns t CPUCLK to Data Delay Full V 5.0 ns DD t Full IV 4.20 6.03 ns DDTACK ↑CPUCLK to DTACK (RDY) Delay t Read Access Time Full IV 3 × t 9 × t ns ACC CPUCLK CPUCLK 1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V, and the VDDIO range of 3.0 V to 3.6 V. 2 C = 40 pF on all outputs, unless otherwise noted. LOAD 3 W R DS RD CS Specification pertains to control signals: R/ , (W ), , ( ), and . Rev. 0 | Page 10 of 88 AD6654 SERIAL PORT TIMING CHARACTERISTICS Table 9. 1, 2, 3 Parameter Temp Test Level Min Typ Max Unit SERIAL PORT CLOCK TIMING REQUIREMENTS tSCLK SCLK Period Full IV 10.0 ns tSCLKL SCLK Low Time Full IV 1.60 0.5 × tSCLK ns tSCLKH SCLK High Time Full IV 1.60 0.5 × tSCLK ns SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0) tSSDI SDI to ↑SCLK Setup Time Full IV 1.30 ns t Full IV 0.40 ns HSDI SDI to ↑SCLK Hold Time t Full IV 4.12 ns SSCS SCS to ↑SCLK Setup Time tHSCS SCS to ↑SCLK Hold Time Full IV −2.78 ns t Full IV 4.28 7.96 ns DSDO ↑SCLK to SDO Delay Time SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1) tSSDI SDI to ↑SCLK Setup Time Full IV 0.80 ns t Full IV 0.40 ns HSDI SDI to ↑SCLK Hold Time tSSRFS SRFS to ↓SCLK Setup Time Full IV 1.60 ns tHSRFS SRFS to ↓SCLK Hold Time Full IV −0.13 ns t Full IV 1.60 ns SSTFS STFS to ↓SCLK Setup Time tHSTFS STFS to ↓SCLK Hold Time Full IV −0.30 ns t SSCS SCS to ↑SCLK Setup Time Full IV 4.12 ns t Full IV −2.76 ns HSCS SCS to ↑SCLK Hold Time tDSDO ↑SCLK to SDO Delay Time Full IV 4.29 7.95 ns 1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V and 3.6 V. 2 CLOAD = 40 pF on all outputs, unless otherwise noted. 3 SCLK rise/fall time should be 3 ns maximum. Rev. 0 | Page 11 of 88 AD6654 TIMING DIAGRAMS RESET t RESL Figure 2. Reset Timing Requirements t CLKH CLK t CLKL Figure 3. CLK Switching Characteristics t CPUCLKH CPUCLK t CPUCLKL Figure 4. CPUCLK Switching Characteristics t SCLKH SCLK t SCLKL Figure 5. SCLK Switching Characteristics CLK t t SSYNC HSYNC SYNC [3:0] Figure 6. SYNC Timing Inputs t CLK t CLKL CLK t CLKH t DEXP EXPx [2:0] Figure 7. Gain Control Word Output Switching Characteristics Rev. 0 | Page 12 of 88 05156-002 05156-006 05156-005 05156-003 05156-004 05156-007 AD6654 PCLK t t SPA HPA PxACK t DPREQ PxREQ t t t t DPP DPP DPP DPP t t DPP DPP Px [15:0] I [15:0] Q [15:0] RSSI [11:0] I [15:0] Q [15:0] RSSI [11:0] t t PxIQ DPIQ DPIQ t t DPCH DPCH PxCH [2:0] = CHANNEL NO. PxCH [2:0] PxCH [2:0] = CHANNEL NO. t t DPGAIN DPGAIN PxGAIN Figure 8. Master Mode PxACK to PCLK Switching Characteristics PCLK PxACK TIED LOGIC HIGH ALL THE TIME t DPREQ PxREQ t t t t t t DPP DPP DPP DPP DPP DPP Px [15:0] RSSI [11:0] I [15:0] Q [15:0] RSSI [11:0] I [15:0] Q [15:0] PxIQ t t DPIQ DPIQ t t DPCH DPCH PxCH [2:0] PxCH [2:0] = CHANNEL NO. PxCH [2:0] = CHANNEL NO. t t DPGAIN DPGAIN PxGAIN Figure 9. Master Mode PxREQ to PCLK Switching Characteristics Rev. 0 | Page 13 of 88 05156-009 05156-008 AD6654 CPUCLK RD t t SC HC WR t t SC HC CS t t SAM HAM A [7:0] VALID ADDRESS t t SAM HAM D [15:0] VALID DATA t DRDY RDY t ACC NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM 3 TO 9 CPUCLK CYCLES. ACC Figure 10. INM Microport Write Timing Requirements CPUCLK t HC t SC RD WR t HC t SC CS t SAM t HAM A [7:0] VALID ADDRESS t DD D [15:0] VALID DATA t DRDY RDY t ACC NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM 3 TO 9 CPUCLK CYCLES. ACC Figure 11. INM Microport Read Timing Requirements Rev. 0 | Page 14 of 88 05156-011 05156-010 AD6654 CPUCLK t t HC SC DS t t SC HC R/W t t SC HC CS t t SAM HAM A [7:0] VALID ADDRESS t t SAM HAM D [15:0] VALID DATA t DDTACK DTACK t ACC NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM 3 TO 9 CPUCLK CYCLES. ACC Figure 12. MNM Microport Write Timing Requirements CPUCLK t t SC HC DS t t SC HC R/W t t SC HC CS t t SAM HAM A [7:0] VALID ADDRESS t DD VALID D [15:0] DATA t DDTACK DTACK t ACC NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM 3 TO 9 CPUCLK CYCLES. ACC Figure 13. MNM Microport Read Timing Requirements Rev. 0 | Page 15 of 88 05156-013 05156-012 AD6654 SCLK t SSCS t HSCS SCS SMODE LOGIC 1 t HSDI t SSDI SDI D0 D1 D2 D3 D4 D5 D6 D7 t HSRFS t SSRFS SRFS MODE LOGIC 1 Figure 14. SPORT Mode Write Timing Characteristics SCLK t SSCS t HSCS SCS SMODE LOGIC 1 t DSDO SDO D0 D1 D2 D3 D4 D5 D6 D7 t HSTFS t SSTFS STFS MODE LOGIC 1 Figure 15. SPORT Mode Read Timing Characteristics SCLK t t SSCS HSCS SCS SMODE LOGIC 1 t HSDI t SSDI SDI D0 D1 D2 D3 D4 D5 D6 D7 MODE LOGIC 0 Figure 16. SPI Mode Write Timing Characteristics Rev. 0 | Page 16 of 88 05156-016 05156-015 05156-014 AD6654 SCLK t t SSCS HSCS SCS SMODE LOGIC 0 t DSDO SDO D0 D1 D2 D3 D4 D5 D6 D7 LOGIC 0 MODE Figure 17. SPI Mode Read Timing Characteristics Rev. 0 | Page 17 of 88 05156-017 AD6654 ABSOLUTE MAXIMUM RATINGS Table 10. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any AVDD 0 to +7.0 V other conditions above those indicated in the operational DRVDD 0 to +4.0 V section of this specification is not implied. Exposure to absolute VDDCORE −0.3 V to +2.2 V maximum rating conditions for extended periods may affect VDDIO 0 to +4.0 V device reliability. Analog/Encode Input Voltage 0 to AVDD Analog Input Current 25 mA Digital Input Voltage −0.3 V to + 3.6 V (not 5 V THERMAL CHARACTERISTICS tolerant) 256 BGA, 17 mm sq. Digital Output Voltage −0.3 V to VDDIO + 0.3 V Operating Temperature Range −25°C to +85°C θ = 21°C/W, no airflow. JA (Ambient) Estimate based on JEDEC JC51-2 model using horizontally Junction Temperature Under Bias 150°C positioned 4-layer board. Storage Temperature Range −65°C to +150°C EXPLANATION OF TEST LEVELS Test Level Description I 100% production tested. II 100% production tested at 25°C. III Sample tested only. IV Parameter guaranteed by design and analysis. V Parameter is typical value only. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 18 of 88 AD6654 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 12 34 5 6 78 9 10 11 12 13 14 15 16 CPUCLK A DGND D14 D12 PC3 PCCH1 PA12 PAIQ PAGAIN PB6 CLK OVR AVDD AVDD AGND AGND A (SCLK) DS B D7 CHIPID3 CHIPID2 (RD, PC5 PA5 PA15 PAACK PB2 PB4 EXPC2 DNC AVDD AVDD AGND AGND B SRFS) R/W DTACK C CHIPID0 MODE PC0 PA3 PA9 PACH2 PB9 EXPC1 AVDD AVDD AVDD AGND AGND C (RDY, (WR, PB3 SDO) STFS) _ _ EXT MSB CS D PC6 PC2 PA1 PA7 PACH0 PB0 PB15 EXPC0 DRVDD AVDD AVDD AGND AGND D FILTER FIRST (SCS) VDD VDD VDD VDD E CHIPID1 IRP VDDIO PCACK VDDIO VDDIO VDDIO DRVDD AVDD AVDD AGND AGND E CORE CORE CORE CORE VDD VDD VDD F SMODE D13 D15 RESET D1 VDDIO VDDIO VDDIO DRVDD AVDD AVDD AGND C2 F CORE CORE CORE G DGND D8 D9 D2 D5 DGND DGND DGND DGND DGND DGND DRVDD AVDD AVDD AGND AGND G H D3 D11 D4 D10 A6 DGND DGND DGND DGND DGND DGND DRVDD AVDD AVDD AGND C1 H J DGND D6 D0 A7 A1 DGND DGND DGND DGND DGND DGND DRVDD AVDD AVDD AGND AGND J K A5 A4 A0 (SDI) A2 PC8 DGND DGND DGND DGND DGND DGND DRVDD AVDD AVDD AGND AGND K VDD VDD VDD L A3 PC12 PC11 PC15 PC10 VDDIO VDDIO VDDIO DRVDD AVDD AVDD AGND AIN– L CORE CORE CORE VDD VDD VDD M PC14 PC13 PC9 PC7 PCCH0 VDDIO VDDIO VDDIO DRVDD AVDD AVDD AGND AIN+ M CORE CORE CORE N PC1 PC4 PA13 PA8 PA0 PAREQ PB1 PBREQ DGND DGND DGND DRVDD AVDD AVDD AGND AGND N P PCIQ PCREQ PA14 PA10 PB10 PB7 PB8 PBCH1 PBACK PBCH0 SYNC2 DRVDD AVDD AVDD AGND AGND P R PCCH2 PCGAIN PA6 PA2 PACH1 PB13 PB11 PBCH2 PB14 PBGAIN SYNC1 DRVDD AGND AGND AGND ENC– R T DGND PA11 PA4 PCLK PB5 PB12 PBIQ DGND DNC SYNC0 SYNC3 DR AGND V AGND ENC+ T REF 12 34 5 6 78 9 10 11 12 13 14 15 16 DNC = DO NOT CONNECT Figure 18. 256 BGA Configuration (Top View) Table 11. Pin Function Descriptions Name Type Pin Number Function POWER SUPPLY AVDD Power See Table 12 5 V Analog ADC Core Supply. DRVDD Power See Table 12 3.3 V ADC Output Driver Supply. VDDCORE Power Table 12 1.8 V Digital DDC Core Supply. See VDDIO Power 3.3 V Digital DDC I/O Supply. See Table 12 DGND Ground Digital Core and I/O Ground. See Table 12 AGND Ground See Table 12 Analog ADC Ground. ADC INPUTS AIN+ Input M16 Differential Analog Input. AIN− Input L16 Differential Analog Input. ENC+ Input T16 Differential Encode Input. Conversion initiated on rising edge. ENC− Input R16 Differential Encode Input. ADC OUTPUTS DR Output T12 Data Ready. Inverted and delayed representation of ENC+ used for driving the DDC CLK input. OVR Output A12 Overange Bit. A logic high indicates analog input exceeds ±FS. V Output T14 2.4 V Fixed Internal Voltage Reference. Bypass to AGND with 0.1 µF chip capacitor. REF C1 Output H16 Compensation Pin for ADC Voltage Reference. Bypass to AGND with 0.1 µF chip capacitor. C2 Output F16 Compensation Pin for ADC Voltage Reference. Bypass to AGND with 0.1 µF chip capacitor. Rev. 0 | Page 19 of 88 05156-018 AD6654 Name Type Pin Number Function DDC INPUTS CLK Input A11 DDC Clock Input. SYNC0 Input T10 Synchronization Input 0. SYNC pins are independent of channels. SYNC1 Input R11 Synchronization Input 1. SYNC2 Input P11 Synchronization Input 2. SYNC3 Input T11 Synchronization Input 3. DDC OUTPUTS EXPC [2:0] Output D11, C11, B11 External VGA Gain Control Bits. GND all pins if not used. DDC OUTPUT PORTS PCLK Bi-dir T4 Parallel Output Port Clock. PCLK is bi-directional: master mode = output, slave mode = input. PADATA[15:0] Output See Table 12 Parallel Output Port A Data Bus. PACH[2:0] Output D8, R5, C8 Channel Indicator Output Port A. PAIQ Output A8 Parallel Port A I/Q Data Indicator. Logic 1 indicates I data on data bus. PAGAIN Output A9 Parallel Port A Gain Word Output Indicator. Logic 1 indicates gain word on data bus. PAACK Input B8 Parallel Port A Acknowledge (Active High). PAREQ Output N6 Parallel Port A Request (Active High). PBDATA[15:0] Output Parallel Output Port B Data Bus. See Table 12 PBCH[2:0] Output P10, P8, R8 Channel Indicator Output Port B. PBIQ Output T7 Parallel Port B I/Q Data Indicator. Logic 1 indicates I data on data bus. PBGAIN Output R10 Parallel Port B Gain Word Output Indicator. Logic 1 indicates gain word on data bus. PBACK Input P9 Parallel Port B Acknowledge (Active High). PBREQ Output N8 Parallel Port B Request (Active High) PCDATA[15:0] Output See Table 12 Parallel Output Port C Data Bus. PCCH[2:0] Output M5, A6, R1 Channel Indicator Output Port C. PCIQ Output P1 Parallel Port C I/Q Data Indicator. Logic 1 indicates I data on data bus. PCGAIN Output R2 Parallel Port C Gain word Output Indicator. Logic 1 indicates gain word on data bus. PCACK Input E5 Parallel Port C Acknowledge (Active High). PCREQ Output P2 Parallel Port C Request (Active High). MICROPORT CONTROL D[15:0] Bi-Dir Bidirectional Microport Data. This bus is three-stated when CS is high. See Table 12 A[7:0] Input See Table 12 Microport Address Bus. DS RD Input B4 Active Low Data Strobe, MODE = 1. Active low read strobe when MODE = 0. ( ) 1 DTACK (RDY) Output C3 Active Low Data Acknowledge, MODE = 1. Microport status pin when MODE = 0. Terminate to VDDIO through external 1 kΩ pull-up resistor. R/W (WR) Input C4 Read/Write Strobe, MODE = 1. Active low write strobe when MODE = 0. MODE Input C2 Mode Select. Logic 0 = Intel® mode, Logic 1 = Motorola mode. CS Input D3 Active Low Chip Select. Logic 1 three-states the microport data bus. CPUCLK Input A4 Microport CLK Input. (Input only.) CHIPID[3:0] Input C1, E1, B3, B2 Chip ID Input Pins. SERIAL PORT CONTROL SCLK Input A4 Serial Clock. Should have a rise/fall time of 3ns max. 1 SDO Output C3 Serial Port Data Output. Terminate to VDDIO through external 1 kΩ pull-up resistor. 2 SDI Input K3 Serial Port Data Input. STFS Input C4 Serial Transmit Frame Sync. SRFS Input B4 Serial Receive Frame Sync. SCS Input D3 Serial Chip Select. MSB_FIRST Input D2 Most Significant Bit_First. Selects MSB_FIRST into SDI pin, and MSB_FIRST out of SDO pin. Logic 1 = MSB_FIRST; Logic 0 = LSB_FIRST SMODE Input F1 Serial Mode Select. MISC PINS DNC ------- B12, T9 Do Not Connect. 1 IRP Output E2 Interrupt Pin (Active Low). Terminate to VDDIO through external 1 kΩ pull-up resistor. RESET Input F4 Master Reset, Active Low. EXT_FILTER Input D1 PLL Loop Filter (Analog Pin). Connect to VDDCORE through series 250 Ω and 0.01 µF capacitor. 1 Pins with internal pull-up resistor of nominal 70 kΩ. 2 Pins with internal pull-down resistor of nominal 70 kΩ. Rev. 0 | Page 20 of 88 AD6654 Table 12. Pin Listing for Power, Ground, and Data Buses Name Pin Number AVDD A13, A14, B13, B14, C12, C13, C14, D13, D14, E13, E14, F13, F14, G13, G14, H13, H14, J13, J14, K13, K14, L13, L14, M13, M14, N13, N14, P13, P14 AGND A15, A16, B15, B16, C15, C16, D15, D16, E15, E16, F15, G15, G16, H15, J15, J16, K15, K16, L15, M15, N15, N16, P15, P16, R13, R14, R15, T13, T15 DRVDD D12, E12, F12, G12, H12, J12, K12, L12, M12, N12, P12, R12 VDDIO E3, E9, E10, E11, F9, F10, F11, L6, L7, L8, M6, M7, M8 VDDCORE E4, E6, E7, E8, F6, F7, F8, L9, L10, L11, M9, M10, M11 DGND A1, G1, G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J1, J6, J7, J8, J9, J10, J11, K6, K7, K8, K9, K10, K11, N9, N10, N11, T1, T8 PADATA[15:0] N5, D6, R4, C6,T3, B6, R3, D7, N4, C7, P4, T2, A7, N3, P3, B7 PBDATA[15:0] D9, N7, B9, C9, B10, T5, A10, P6, P7, C10, P5, R7, T6, R6, R9, D10 PCDATA[15:0] C5, N1, D5, A5, N2, B5, D4, M4, K5, M3, L5, L3, L2, M2, M1, L4 D[15:0] J3, F5, G4, H1, H3, G5, J2, B1, G2, G3, H4, H2, A3, F2, A2, F3 A[7:0] K3, J5, K4, L1, K2, K1, H5, J4 Rev. 0 | Page 21 of 88 AD6654 TYPICAL PERFORMANCE CHARACTERISTICS 76 105 100 WORST OTHER SPUR 75 95 +25°C –25°C 74 90 85 73 +85°C HARMONICS 80 (SECOND, THIRD) 72 75 70 71 ENCODE = 92.16MSPS ENCODE = 92.16MSPS 65 AIN = –1dBFS AIN = –1dBFS TEMPERATURE = 25°C 70 60 10 30 50 70 90 110 130 150 170 190 0 20 40 60 80 100 120 140 160 180 200 AIN FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Figure 19. ADC Noise vs. Analog Frequency (46.08 MHz BW) Figure 22. Harmonics vs. Analog Frequency (IF) 120 110 dBFS 110 100 dBFS 100 90 ENCODE = 92.16MSPS 90 80 AIN = 70MHz ENCODE = 92.16MSPS TEMPERATURE = 25°C 80 AIN = 37.7MHz dBc 70 TEMPERATURE = 25°C 70 dBc 60 60 50 SFDR = 90dB 50 REFERENCE LINE 40 40 SFDR = 90dB REFERENCE LINE 30 30 20 20 10 10 0 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 ANALOG INPUT POWER LEVEL (dBFS) ANALOG INPUT POWER LEVEL (dBFS) Figure 23. Single Tone SFDR at 70 MHz Figure 20. Single Tone SFDR at 37.7 MHz 0 0 32k FFT AIN = –1dBFS SNR = 89dB (1.25MHz BW) –15 –15 32k FFT –30 –30 –45 –45 –60 –60 –75 –75 –90 –90 –105 –105 –120 –120 –135 –135 –150 –150 FREQUENCY (Hz) FREQUENCY (Hz) Figure 21. CDMA Single Tone AIN = 70 MHz; ENC = 92.16 MSPS Figure 24. CDMA Carrier AIN = 70 MHz; ENC = 92.16 MSPS Rev. 0 | Page 22 of 88 WORST CASE SPURIOUS (dBFS and dBc) SNR (dB) (dBFS) –1.25M –1.00M –750k –500k –250k 0 250k 500k 750k 1.00M 1.25M 05156-064 05156-071 05156-073 WORST CASE SPURIOUS (dBFS and dBc) WORST CASE HARMONIC (dBc) (dBFS) –1.25M –1.00M –750k –500k –250k 0 250k 500k 750k 1.00M 1.25M 05156-066 05156-072 05156-074 AD6654 0 0 32k FFT AIN = –1dBFS –15 SNR = 88dB (1.25MHz BW) –15 32k FFT –30 –30 –45 –45 –60 –60 –75 –75 –90 –90 –105 –105 –120 –120 –135 –135 –150 –150 FREQUENCY (Hz) FREQUENCY (Hz) Figure 25. CDMA Single Tone AIN = 151.5 MHz; ENC = 92.16 MSPS Figure 28. CDMA Carrier AIN = 151.5 MHz; ENC = 92.16 MSPS 0 0 32k FFT AIN = –1dBFS –15 SNR = 83dB (5MHz BW) –15 32k FFT –30 –30 –45 –45 –60 –60 –75 –75 –90 –90 –105 –105 –120 –120 –135 –135 –150 –150 FREQUENCY (Hz) FREQUENCY (Hz) Figure 26. WCDMA Single Tone AIN = 70 MHz; Encode = 92.16 MSPS Figure 29. WCDMA Carrier AIN = 70 MHz; Encode = 92.16 MSPS 0 0 32k FFT AIN = –1dBFS –15 SNR = 82dB (5MHz BW) –15 32k FFT –30 –30 –45 –45 –60 –60 –75 –75 –90 –90 –105 –105 –120 –120 –135 –135 –150 –150 FREQUENCY (Hz) FREQUENCY (Hz) Figure 27. WCDMA Single Tone AIN = 151.5 MHz; Encode = 92.16 MSPS Figure 30. WCDMA Carrier AIN = 151.5 MHz; Encode = 92.16 MSPS Rev. 0 | Page 23 of 88 (dBFS) (dBFS) (dBFS) –1.25M –3.5M –3.5M –1.00M –2.8M –2.8M –750k –2.1M –2.1M –500k –1.4M –1.4M –250k –700k –700k 0 0 0 700k 700k 250k 1.4M 1.4M 500k 2.1M 2.1M 750k 2.8M 2.8M 1.00M 3.5M 3.5M 1.25M 05156-068 05156-067 05156-065 (dBFS) (dBFS) (dBFS) –1.25M –3.5M –3.5M –1.00M –2.8M –2.8M –750k –2.1M –2.1M –500k –1.4M –1.4M –250k –700k –700k 0 0 0 700k 700k 250k 1.4M 1.4M 500k 2.1M 2.1M 750k 2.8M 2.8M 1.00M 3.5M 3.5M 1.25M 05156-084 05156-069 05156-083 AD6654 0 110 AIN = –7dBFS 100 –15 32k FFT F1 F2 90 dBFS –30 80 –45 70 –60 60 –75 50 dBc –90 SFDR = 90dB 40 REFERENCE LINE –105 30 –120 20 –135 10 –150 0 –77 –67 –57 –47 –37 –27 –17 –7 INPUT POWER LEVEL (F1 = F2 (dBFS)) FREQUENCY (Hz) Figure 31. CDMA Two Tones at 55 MHz and 56 MHz; ENC = 92.16 MSPS Figure 32. Two Tone SFDR at 55 MHz and 56 MHz Rev. 0 | Page 24 of 88 (dBFS) –1.25M –1.00M –750k –500k –250k 0 250k 500k 750k 1.00M 1.25M 05156-063 WORST CASE SPURIOUS (dBFS and dBc) 05156-070 AD6654 ADC EQUIVALENT CIRCUITS AVDD AVDD AVDD 2.4V V REF V REF AVDD AVDD 100µA CURRENT Figure 33. ADC 2.4 V Reference MIRROR C1, C2 LOADS Figure 35. ADC Compensation Pins, C1 and C2 AVDD AVDD AVDD AVDD V CH AVDD 10kΩ 10kΩ ENC+ ENC– T/H AIN+ BUF 10kΩ 10kΩ 500Ω V CL BUF V REF V CH AVDD 500Ω LOADS T/H AIN– BUF Figure 34. ADC Encode Inputs V CL Figure 36. ADC Analog Input Stage Rev. 0 | Page 25 of 88 05156-023 05156-024 05156-026 05156-025 AD6654 TERMINOLOGY Noise for Any Range Within the ADC Analog Bandwidth FS − SNR − SIGNAL ⎛ ⎞ dBm dBc dBFS The analog input frequency at which the spectral power of the ⎜ ⎟ 10 ⎝ ⎠ V = Z×10 fundamental frequency (as determined by the FFT analysis) is NOISE reduced by 3 dB. where Z is the input impedance, FS is the full scale of the device Differential Analog Input Resistance, for the frequency in question, SNR is the value for the particular Capacitance, and Impedance input level, and SIGNAL is the signal level within the ADC The real and complex impedances measured at each analog reported in dB below full scale. This value includes both input port. The resistance is measured statically, and the thermal and quantization noise. capacitance and differential input impedances are measured Power-Supply Rejection Ratio with a network analyzer. The ratio of a change in input offset voltage to a change in Differential Analog Input Voltage Range power-supply voltage. The peak-to-peak differential voltage that must be applied to Power-Supply Rise Time the converter to generate a full-scale response. Peak differential The time from when the dc supply is initiated until the supply voltage is computed by observing the voltage on a single pin output reaches the minimum specified operating voltage for the and subtracting the voltage from the other pin, which is 180° AD6654, measured at the supply pin(s) of the AD6654. out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180° and taking the peak measurement again. Processing Gain Then the difference is computed between both peak When the tuned channel occupies less bandwidth than the measurements. input signal, this rejection of out-of-band noise is referred to as processing gain. By using large decimation factors, processing Encode Pulse Width/Duty Cycle gain can improve the SNR of the ADC by 15 dB or more. Use Pulse width high is the minimum amount of time that the the following equation to estimate processing gain: ENCODE pulse should be left in Logic 1 state to achieve the ⎡ Sample _Rate / 2 ⎤ rated performance. Pulse width low is the minimum time Processing _Gain= 10 log ⎢ ⎥ ENCODE pulse should be left in the low state. Several internal Filter _Bandwidth ⎣ ⎦ timing parameters are a function of tENCL and tENCH, optimum Signal-to-Noise Ratio (Without Harmonics) performance will be achieved with 50/50 duty cycle. The ratio of the rms signal amplitude (set at 1 dB below full Harmonic Distortion, Second scale) to the rms value of the sum of all other spectral The ratio of the rms signal amplitude to the rms value of the components, excluding the first five harmonics and dc. second harmonic component, reported in dBc. Spurious-Free Dynamic Range (SFDR) Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo- third harmonic component, reported in dBc. nent might, or might not be, a harmonic. SFDR can be reported in dBc (degrades as signal level is lowered), or dBFS (always Full-Scale Input Power related back to converter full scale). Expressed in dBm. Computed using the following equation: 2 Two-Tone Intermodulation Distortion Rejection ⎛ ⎞ V FULL SCALE ⎜ RMS ⎟ The ratio of the rms value of either input tone to the rms value ⎜ ⎟ Z INPUT ⎜ ⎟ of the worst third-order intermodulation product, in dBc. Power = 10 log FULL SCALE ⎜ 0.001 ⎟ ⎜ ⎟ Two-Tone SFDR ⎜ ⎟ ⎝ ⎠ Ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component Minimum Conversion Rate might, or might not be, an IMD product. SFDR can be reported The encode rate at which the SNR of the lowest analog signal in dBc (degrades as signal level is lowered), or in dBFS (always frequency drops by no more than 3 dB below the guaranteed related back to converter full scale). limit. Worst Other Spur Maximum Conversion Rate Ratio of the rms signal amplitude to the rms value of the worst Encode rate at which parametric testing is performed. spurious component (excluding the second and third harmonic) reported in dBc. Rev. 0 | Page 26 of 88 AD6654 THEORY OF OPERATION The output of DAC1 is subtracted from the delayed analog ADC ARCHITECTURE signal at the input of TH3 to generate a first residue signal. TH2 The AD6654 analog-to-digital converter (ADC) front end provides an analog pipeline delay to compensate for the digital employs a 3-stage subrange architecture. This design approach delay of ADC1. achieves the required accuracy and speed, while maintaining low power consumption. The first residue signal is applied to a second conversion stage consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The The AD6654 front end has complementary analog input pins, second DAC requires 10 bits of precision, which is met by the AIN+ and AIN−, as shown in Figure 1. Each analog input is process with no trim. The input to TH5 is a second residue centered at 2.4 V and should swing ±0.55 V around this signal generated by subtracting the quantized output of DAC2 reference (see Figure 36). Because AIN+ and AIN− are 180° from the first residue signal held by TH4. TH5 drives a final out of phase, the differential full-scale analog input signal is 6-bit ADC3. 2.2 V p-p. The digital outputs from ADC1, ADC2, and ADC3 are added Both analog inputs are buffered prior to the first track-and- together and corrected in the digital error correction logic to hold, TH1. The high state of the ENCODE pulse places TH1 in generate the final output data. The latency of the ADC core is hold mode. The held value of TH1 is applied to the input of a four CLK cycles. The resulting 14-bit ADC data is internally 5-bit coarse ADC1. The digital output of ADC1 drives a 5-bit routed directly to the integrated DDC for processing by the digital-to-analog converter, DAC1. DAC1 requires 14 bits of 4/6 independent DDC channels. precision that is achieved through laser trimming. Rev. 0 | Page 27 of 88 AD6654 APPLICATION INFORMATION There are also benefits at the PCB level. First, differential inputs ADC CONFIGURATION NOTES have high common-mode rejection to stray signals such as Encoding the AD6654 ADC ground and power noise. Second, they provide good rejection to The AD6654 encode signal must be a high quality, extremely common-mode signals such as local oscillator feed-through. low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock The AD6654 analog input pins, AIN+ and AIN−, are centered phase noise. SNR performance can easily degrade by 3 dB to at 2.4 V, and the signal at each input should swing ±0.55 V 4 dB with 70 MHz analog input signals when using a high jitter around this voltage. Because AIN+ and AIN− are 180° out of clock source. See the AN-501, Aperture Uncertainty and ADC phase, the full-scale differential analog input signal is 2.2 V p-p. System Performance Application Note, for details. Each analog input connects through a 500 Ω resistor to the For optimum performance, the AD6654 ADC front end must 2.4 V bias voltage and to the input of a differential buffer, as be clocked differentially. The encode signals are usually ac- shown in Figure 36. The resistor network on the input properly coupled into the ENC+ and ENC− pins via a transformer or biases the followers for maximum linearity and range. capacitors. The ENCODE pins are biased internally and require Therefore, the analog source driving the AD6654 should be no additional bias. ac-coupled to the input pins. Because the differential input impedance of the AD6654 is 1 kΩ, the analog input power Figure 37 shows one preferred method for clocking the requirement is only −2 dBm, simplifying the driver amplifier in AD6654. The clock source (low jitter) is converted from single- many cases. To take full advantage of this high input ended to differential using an RF transformer. The back-to-back impedance, a 20:1 transformer is required. This is a large ratio Schottky diodes across the secondary of the transformer limit that could result in unsatisfactory performance. In this case, a clock excursions into the AD6654 to approximately 0.8 V p-p lower step-up ratio could be used. The recommended method differential. This helps prevent the large voltage swings of the for driving the analog input of the AD6654 is to use a 4:1 clock from feeding through to other portions of the AD6654, impedance ratio RF transformer. and limits the noise presented to the encode inputs. For example, if R is set to 60.4 Ω and R is set to 25 Ω, along T S T1-4T CLOCK ENC+ SOURCE with a 4:1 impedance ratio transformer, the input matches to a 0.1µF 50 Ω source with a full-scale drive of 4.8 dBm. Series resistors AD6654 (RS) on the secondary side of the transformer should be used to ENC– HSMS2812 isolate the transformer from A/D. This limits the amount of DIODES dynamic current from the A/D flowing back into the secondary Figure 37. Crystal Clock Oscillator-Differential Encode of the transformer. The 50 Ω impedance matching can also be incorporated on the secondary side of the transformer, as If a low jitter clock is available, another option is to ac-couple a shown in the evaluation board schematic. differential ECL/PECL signal to the encode input pins as shown in Figure 38. A device that offers excellent jitter performance is R ADT4-1WT S ANALOG INPUT AIN+ the MC100EL16 (or same family) from ON Semiconductor®. SIGNAL R T AD6654 VT R S AIN– 0.1µF 0.1µF ENC+ ECL/ PECL AD6654 Figure 39. Transformer-Coupled Analog Input Circuit ENC– 0.1µF In applications where dc-coupling, or additional gain is required, use a differential output op amp from Analog Devices, VT Inc., such as AD8351, to drive the AD6654 (Figure 40). The Figure 38. Differential ECL for Encode AD8351 op amp can be driven differentially, or configured to Driving the Analog Inputs provide single-ended-to-differential conversion. As with most high speed, high dynamic range ADCs, the analog input to the AD6654 front end is differential. Differential inputs improve on-chip performance, because signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. Rev. 0 | Page 28 of 88 05156-028 05156-027 05156-029 AD6654 100nF N is a predivide factor and can be 1, 2, 4, or 8. INHI 25Ω OPHI AIN+ M is a 5-bit number between 4 and 20 (inclusive). 25Ω BALANCE R G AD6654 AD8351 50Ω SOURCE The multiplication factor, M, is programmed using a 5-bit PLL 25Ω DIGITAL OPLO 100nF AIN– OUT INLO clock multiplier word in the ADC clock control register. A value V V OCM REF 25Ω outside the valid range of 4 to 20 bypasses the PLL clock 100nF multiplier and, therefore, the PLL clock is the same as the input clock. The predivide factor, N, is programmed using a 2-bit Figure 40. ADC Driving Application Using Differential Input ADC pre-PLL clock divider word in the ADC clock control R F register, as listed in Table 13. Table 13. PLL Clock Generation Predivider Control INHI 25Ω OPHI AIN+ 100nF R1 Predivide Word [1:0] Divide-By Value for the Clock SINGLE- 25Ω R G ENDED AD6654 AD8351 00 Divide-by-1, bypass 50Ω 25Ω DIGITAL SOURCE OPLO 100nF AIN– OUT 01 Divide-by-2 INLO V V OCM REF 10 Divide-by-4 25Ω 100nF 11 Divide-by-8 For best signal processing advantage, the user should program Figure 41. ADC Driving Application Using Single-Ended Input the clock multiplier to give a system clock output as close as DDC CONFIGURATION NOTES possible to, but not exceeding, 200 MHz. The internal blocks of the AD6654 that run off the PLL clock are rated to run at a PLL Clock Multiplier maximum of 200 MHz. The default power-up state for the PLL In the AD6654, the input clock rate must be the same as the clock multiplier is the bypass state, where CLK is passed on as input data rate. In a typical digital down-converter architecture, the PLL clock. the clock rate is a limitation on the number of filter taps that can be calculated in the programmable RAM coefficient filters ADC Gain Control (MRCF, DRCF, and CRCF). For slower ADC clock rates (or for The DDC input port has individual, high speed gain control any clock rate), this limitation can be overcome by using a PLL logic circuitry. Such gain control circuitry is useful in applica- clock multiplier to provide a higher clock rate to the RCF filters. tions that involve large dynamic-range inputs. The AD6654 gain Using this clock multiplier, the internal signal processing clock control logic allows programmable upper and lower thresholds rate can be increased up to 200 MHz. The CLK signal is used as and a programmable dwell-time counter for temporal an input to the PLL clock multiplier. hysteresis. PLL CLOCK GENERATION The DDC input port has a 3-bit output from the gain control 1 ADC_CLK block. The operation is controlled by the gain control enable bit 0 in the gain control register of the DDC input port. Logic 1 in PLL CLOCK CLK DIVIDE BY N MULTIPLIER 0 this bit programs the EXP[2:0] pins as gain control outputs. PLL_CLK (1, 2, 4 OR 8) (4x TO 20x) 1 Function BYPASS_PLL 2 5 1 FOR BYPASS The gain control block features a programmable upper thresh- NM old register and a lower threshold register. The ADC input data is compared to both these registers. If ADC input data is larger Figure 42. PLL Clock Generation than the upper threshold register, then the gain control output The PLL clock multiplier is programmable and uses the input is decremented by 1. If the ADC input data is smaller than the clock rates between 30 MHz and 92.16 MHz to give a system lower threshold register, then the gain control output is incre- clock rate (output) of as high as 200 MHz. mented by 1. The output clock rate is given by When decrementing the gain control output, the change is CLK× M immediate. But when incrementing the output, a dwell-time PLL _ CLK= register is used to delay the change. If the ADC input is larger N than the upper threshold register value, the gain control output where: is immediately decremented to prevent overflow. CLK is the input port clock rate. When the ADC input is lower than the lower threshold register, M is a 5-bit programmable multiplication factor. a dwell timer is loaded with the value in the programmable 20-bit dwell-time register. The counter decrements once every Rev. 0 | Page 29 of 88 05156-031 05156-062 05156-030 AD6654 input clock cycle, as long as the input signal remains below the Note that any gain changes that are initiated during the relinear- lower threshold register value. If the counter reaches 1, the gain ization period are ignored. For example, if the AD6654 detects control output is incremented by 1. If the signal goes above the that a gain adjustment is required during the relinearization lower threshold register value, the gain adjustment is not made, period of a previous gain adjustment, then the new adjustment and the normal comparison to lower and upper threshold is ignored. registers is initiated once again. Therefore, the dwell timer provides temporal hysteresis and prevents the gain from Setting Up the Gain Control Block continuously switching. To set up the gain control block for the input port, the individ- ual upper threshold registers and lower threshold registers In a typical application, if the ADC signal goes below the lower should be written with appropriate values. The 10-bit values threshold for a time greater than the dwell time, then the gain written into upper and lower threshold registers are compared control output is incremented by 1. Gain control bits control the to the 10 MSBs of the absolute magnitude calculated using the gain ranging block, which appears before the ADC in the signal input port data. The 20-bit dwell-time register should have the chain. With each increment of the gain control output, gain in appropriate number of clock cycles to provide temporal the gain-ranging block is increased by 6.02 dB. This increases hysteresis. the dynamic range of the input signal into the ADC by 6.02 dB. This gain is compensated for in the AD6654 by relinearizing, as A 6-bit relinearization pipeline delay word is set to synchronize explained in the Relinearization section. Therefore, the AD6654 with the settling delay in the external gain-ranging circuitry. can increase the dynamic range of the ADC by 42 dB, provided Finally, the gain control enable bit is written with Logic 1 to that the gain-ranging block can support it. activate the gain control block. On enabling, the gain control output bits are made 000 (output on EXP[2:0] pins), which Relinearization represent the minimum gain for the external gain-ranging The gain in the gain-ranging block (external) is compensated circuitry and corresponding minimum attenuation during for by relinearizing, using the exponent bits EXP[2:0] of the relinearization. The normal functioning takes over, as explained input port. For this purpose, the gain control bits are connected previously in this section. to the EXP[2:0] bits, providing an attenuation of 6.02 dB for FROM every increase in the gain control output. After the gain in the MEMORY UPPER external gain-ranging block and the attenuation in the AD6654 MAP THRESHOLD DECREASE (using EXP bits), the signal gain is essentially unchanged. The REGISTER EXTERNAL GAIN B COMPARE DEC only change is the increase in the dynamic range of the ADC. A> B FROM INPUT A EXP [2:0] PORTS EXP GEN INCREASE External gain-ranging blocks have a delay associated with EXTERNAL GAIN B changing the gain of the signal. Typically, these delays can be COMPARE DWELL FROM INC A A< B TIMER up to 14 clock cycles. The gain change in the AD6654 (via MEMORY LOWER MAP EXP[2:0]) must be synchronized with the gain change in the THRESHOLD REGISTER gain-ranging block (external). This is allowed in the AD6654 by Figure 43. Gain Control Block Diagram providing a flexible delay, programmable 6-bit word in the gain control register. The value in this 6-bit word gives the delay in input clock cycles. A programmable pipeline delay given by the 6-bit value (maximum delay of 63 clock cycles) is placed between the gain control output and the EXP[2:0] input. Therefore, the external gain-ranging block’s settling delays are compensated for in the AD6654. Rev. 0 | Page 30 of 88 05156-032 AD6654 ADC INPUT PORT MONITOR FUNCTION TO FROM The AD6654 provides a power monitor function that can INTERRUPT MEMORY CONTROLLER MAP monitor the DDC input stream and gather statistics about the POWER MONITOR DOWN IS COUNT = 1? PERIOD REGISTER COUNTER received signal in a signal chain. This function block can LOAD operate in one of three modes measuring the following over a FROM TO CLEAR programmable period of time: INPUT MEMORY MAGNITUDE POWER MONITOR PORTS MAP STORAGE HOLDING • Peak power REGISTER REGISTER LOAD LOAD • Mean power • Number of samples crossing a threshold COMPARE A> B These functions are controlled via the 2-bit power monitor Figure 44. ADC Input Peak Detector Block Diagram function select bits in the power monitor control register of the DDC input port. The DDC input port can be set for different MEAN POWER MODE modes, but only one function can be active at a time. The three Control Bits 01 modes of operation can function continuously over a program- In this mode, the magnitude of the input port signal is mable time period. This time period is programmed as the integrated (by adding an accumulator) over a programmable number of input clock cycles in a 24-bit ADC monitor period register (AMPR). An internal magnitude storage register (MSR) time period (given by AMPR) to give the integrated magnitude is used to monitor, accumulate, or count, depending on the of the input signal. This mode is set by programming Logic 1 in mode of operation. the power monitor function select bits in the power monitor control register of the DDC input port. The 24-bit AMPR, PEAK DETECTOR MODE representing the period over which integration is performed, must be programmed before activating this mode. Control Bits 00 The magnitude of the input port signal is monitored over a After enabling this mode, the value in the AMPR is loaded into programmable time period (given by AMPR) to give the peak a monitor period timer, and the countdown is immediately value detected. This mode is set by programming Logic 0 in the started. The 15-bit magnitude of input signal is right-shifted by power monitor function select bits in the power monitor nine bits to give 6-bit data. This 6-bit data is added to the control register of the DDC input port. The 24-bit AMPR must contents of a 24-bit holding register, thereby performing an be programmed before activating this mode. accumulation. The integration continues until the monitor period timer reaches a count of 1. After enabling this mode, the value in the AMPR is loaded into a monitor period timer and the countdown is started. The When the monitor period timer reaches a count of 1, the value magnitude of the input signal is compared to the MSR, and the in the MSR is transferred to the power monitor holding register greater of the two is updated back into the MSR. The initial (after some formatting), which can be read through the micro- value of the MSR is set to the current ADC input signal magni- port or the serial port. The monitor period timer is reloaded tude. This comparison continues until the monitor period timer with the value in the AMPR, and the countdown is started. reaches a count of 1. Also, the first input sample signal magnitude is updated in the MSR, and the accumulation continues with the subsequent When the monitor period timer reaches a count of 1, the value input samples. If the interrupt is enabled, an interrupt is in the MSR is transferred to the power monitor holding register, generated, and the interrupt status register is updated when the which can be read through the microport or the serial port. The AMPR reaches a count of 1. Figure 45 illustrates the mean monitor period timer is reloaded with the value in the AMPR, power monitoring logic. and the countdown is started. Also, the magnitude of the first input sample is updated in the MSR, and the comparison and The value in the MSR is a floating-point number with 4 MSBs update procedure, as explained above, continues. If the and 20 LSBs. If the 4 MSBs are EXP and the 20 LSBs are MAG, interrupt is enabled, an interrupt is generated, and the interrupt the value in dBFS can be decoded using the following equation: status register is updated when the AMPR reaches a count of 1. ⎡ ⎤ ⎛MAG⎞ Figure 44 is a block diagram of the peak detector logic. The MeanPower= 10 log 2−() EXP−1 ⎜ ⎟ ⎢ ⎥ 20 MSR contains the absolute magnitude of the peak detected by ⎝ 2 ⎠ ⎣ ⎦ the peak detector logic. Rev. 0 | Page 31 of 88 05156-033 AD6654 TO FROM ADDITIONAL CONTROL BITS INTERRUPT MEMORY CONTROLLER MAP POWER MONITOR DOWN IS COUNT = 1? For additional flexibility in the power monitoring process, two PERIOD REGISTER COUNTER control bits are provided in the power monitor control register. LOAD The two control bits are the disable monitor period timer bit TO FROM CLEAR LOAD INPUT MEMORY and the clear-on-read bit. These options have the same function POWER MONITOR PORTS MAP ACCUMULATOR HOLDING in all three modes of operation. REGISTER Disable Monitor Period Timer Bit Figure 45. ADC Input Mean Power Monitoring Block Diagram When the disable monitor period timer bit is written with THRESHOLD CROSSING MODE Logic 1, the timer continues to run but does not cause the contents of the MSR to be transferred to the holding register Control Bits 10 when the count reaches 1. This function of transferring the In this mode of operation, the magnitude of the input port MSR to the power monitor holding register and resetting the signal is monitored over a programmable time period (given MSR is now controlled by a read operation on the microport or by AMPR) to count the number of times it crosses a certain serial port. programmable threshold value. This mode is set by program- ming Logic 1x (where x is a don’t care bit) in the power monitor When a microport or serial port read is performed on the function select bits in the power monitor control register of the power monitor holding register, the MSR value is transferred to DDC input port. Before activating this mode, the user needs to the holding register. After the read operation, the timer is program the 24-bit AMPR and the 10-bit upper threshold register reloaded with the AMPR value. If the timer reaches 1 before the of the DDC input port. The same upper threshold register is microport or serial port read, the MSR value is not transferred used for both power monitoring and gain control (see the ADC to the holding register, as in normal operation. The timer still Gain Control section). generates an interrupt on the AD6654 interrupt pin and updates the interrupt status register. An interrupt appears on the IRP After entering this mode, the value in the AMPR is loaded into pin, if interrupts are enabled in the interrupt enable register. a monitor period timer, and the countdown is started. The magnitude of the input signal is compared to the upper Clear-on-Read Bit threshold register (programmed previously) on each input clock This control bit is valid only when the disable monitor period cycle. If the input signal has a magnitude greater than the upper timer bit is Logic 1. When both of these bits are set, a read threshold register, then the MSR register is incremented by 1. operation to either the microport or the serial port reads the The initial value of the MSR is set to 0. This comparison and MSR value, and the monitor period timer is reloaded with the incrementing of the MSR register continues until the monitor AMPR value. The MSR is cleared (written with current input period timer reaches a count of 1. signal magnitude in peak power and mean power modes; written with a 0 in threshold crossing mode), and normal When the monitor period timer reaches a count of 1, the value operation continues. in the MSR is transferred to the power monitor holding register, which can be read through the microport or the serial port. The When the monitor period timer is disabled and the clear-on- monitor period timer is reloaded with the value in the AMPR, read bit is set, a read operation to the power monitor holding and the countdown is started. The MSR register is also cleared register clears the contents of the MSR and, therefore, the power to a value of 0. If interrupts are enabled, an interrupt is gener- monitor loop restarts. ated, and the interrupt status register is updated when the AMPR reaches a count of 1. Figure 46 illustrates the threshold If the clear-on-read bit is Logic 0, the read operation to the crossing logic. The value in the MSR is the number of samples microport or serial port does not clear the MSR value after it is that have an amplitude greater than the threshold register. transferred into the holding register. The value from the previous monitor time period persists, and it continues to be TO FROM INTERRUPT MEMORY compared, accumulated, or incremented, based on new input CONTROLLER MAP POWER MONITOR DOWN IS COUNT = 1? PERIOD REGISTER COUNTER signal magnitude values. LOAD TO FROM CLEAR LOAD INPUT MEMORY POWER MONITOR A PORTS MAP COMPARE COMPARE HOLDING A> B A> B REGISTER FROM MEMORY B MAP UPPER THRESHOLD REGISTER Figure 46. ADC Input Threshold Crossing Block Diagram Rev. 0 | Page 32 of 88 05156-034 05156-035 AD6654 INPUT CROSSBAR MATRIX Each channel has a separate selection for individual control. The AD6654 has one ADC input port and six channels. Each Cross bar mux selection enables each channel to select its input channel can individually select its input source from either the signal source. real ADC input port, or from an internally generated pseudo random sequence (referred to as a PN sequence) generator. Table 14 gives the valid combinations of cross bar mux select Each channel has an input crossbar matrix to facilitate selection values and the corresponding input signal selections. of the input signal source. The selection of input signal for a particular channel is made Table 14. Cross Bar Mux Selection Bits using a 4-bit cross bar mux select word in the ADC input Cross Bar Mux Select Bits Input Signal Selection control register. 0010 ADC input drives the channel. 0100 Internal PN sequence drives the channel. Rev. 0 | Page 33 of 88 AD6654 NUMERICALLY CONTROLLED OSCILLATOR (NCO) Each channel consists of an independent complex NCO and a The NCO frequency word can be calculated using following the complex mixer. This processing stage is comprised of a digital equation: tuner consisting of three multipliers and a 32-bit complex NCO. mod(f , f ) CH CLK The NCO serves as a quadrature local oscillator capable of 32 NCO _ FREQ= 2 producing an NCO frequency of between –CLK/2 and +CLK/2 f CLK with a resolution of CLK/232 in the complex mode, where CLK where: is the input clock frequency. NCO_FREQ is the 32-bit twos complement number represent- The frequency word used for generating the NCO is a 32-bit ing the NCO frequency register. word. This word is used to generate a 20-bit phase word. A 16-bit phase offset word is added to this phase word. 18 bits of f is the desired carrier frequency. CH this phase word are used to generate the sine and cosine of the required NCO frequency. The amplitude of the sine and cosine f is the clock rate for the channel under consideration. CLK are represented using 17 bits. The worst-case spurious signal mod( ) is a remainder function. For example, mod(110, 100) = from the NCO is better than −100 dBc for all output 10 and, for negative numbers, mod(−32, 10) = −2. frequencies. Note that this equation applies to the aliasing of signals in the Because all the filtering in the AD6654 is low-pass filtering, the digital domain (that is, aliasing introduced when digitizing carrier of interest is tuned down to dc (frequency = 0 Hz). This analog signals). is illustrated in Figure 47. Once the signal of interest is tuned down to dc, the unwanted adjacent carriers can be rejected For example, if the carrier frequency is 100 MHz and the clock using the low-pass filtering that follows. frequency is 80 MHz, NCO FREQUENCY mod(f , f ) 20 CH DK = = 0.25 The NCO frequency value is given by the 32-bit twos comple- f 80 CLK ment number entered in the NCO frequency register. Frequencies between −CLK/2 and +CLK/2 (with +CLK/2 This, in turn, converts to 0x4000 0000 in the 32-bit twos excluded) are represented using this frequency word: complement representation for NCO_FREQ. 0x8000 0000 represents a frequency given by −CLK/2. 0x0000 0000 represents dc (frequency is 0 Hz). 32 0x7FFF FFFF represents CLK/2 − CLK/2 . WIDEBAND INPUT SPECTRUM (–fsample/2 TO +fsample/2) SIGNAL OF INTEREST IMAGE SIGNAL OF INTEREST –fs/2 –7fs/16 –3fs/8 –5fs/16 –fs/4 –3fs/16 –fs/8 –fs/16 DC fs/16 fs/8 3fs/16 fs/4 5fs/16 3fs/8 7fs/16 fs/2 WIDEBAND INPUT SPECTRUM (30MHz FROM HIGH SPEED ADC) NCO TUNES SIGNAL TO SIGNAL OF INTEREST AFTER FREQUENCY TRANSLATION SIGNAL OF INTEREST IMAGE –fs/2 –7fs/16 –3fs/8 –5fs/16 –fs/4 –3fs/16 –fs/8 –fs/16 DC fs/16 fs/8 3fs/16 fs/4 5fs/16 3fs/8 7fs/16 fs/2 FREQUENCY TRANSLATION (SINGLE 1MHz CHANNEL TUNED TO BASEBAND) Figure 47. Frequency Translation Principle Using the NCO and Mixer Rev. 0 | Page 34 of 88 05156-036 AD6654 If the carrier frequency is 70 MHz and the clock frequency is AMPLITUDE DITHER 80 MHz, then: Amplitude dither can be used to improve spurious performance of the NCO. Amplitude dither is enabled by writing Logic 1 in mod(f , f ) 10 CH CLK = = 0.125 the amplitude dither enable bit of the NCO control register of f 80 CLK the channel under consideration. Random amplitude is added to the LSBs of the sine and cosine amplitudes, when this feature This, in turn, converts to 0xE000 0000 in the twos complement is enabled. Amplitude dither improves performance by random- 32-bit representation. izing the amplitude quantization errors within the angular-to- MIXER Cartesian conversion of the NCO. This option might reduce spurs at the expense of a slightly raised noise floor. Amplitude The NCO is accompanied by a mixer. Its operation is similar to dither and phase dither can be used together, separately, or not an analog mixer. It performs the down-conversion of real input at all. signals by using the NCO frequency as a local oscillator. This mixer performs a real mixer operation (with two multipliers). NCO FREQUENCY HOLD-OFF REGISTER The mixer adjusts its operation based on the input signal When the NCO frequency registers are written by the micro- provided to each individual channel. port or serial port, data is passed to a shadow register. Data can BYPASS be moved to the main registers when the channel comes out of sleep mode, or when a sync hop occurs. In either event, a The NCO and the mixer can be individually bypassed in each counter can be loaded with the NCO frequency hold-off channel by writing Logic 1 in the NCO bypass bit in the NCO register value. The 16-bit unsigned integer counter starts control register of the channel under consideration. counting down, clocked by the input port clock selected at the CLEAR PHASE ACCUMULATOR ON HOP crossbar mux. When the counter reaches 0, the new frequency value in the shadow register is written to the NCO frequency When clear, the NCO accumulator bit of the NCO control register. Writing 1 in this hold-off register updates the NCO register is set (Logic 1), the NCO phase accumulator is cleared frequency register as soon as the start sync or hop sync occurs. prior to a frequency hop. Refer to the Chip Synchronization See the Chip Synchronization section for details. section for details on frequency hopping. This ensures a consistent phase of the NCO on each hop. The NCO phase PHASE OFFSET offset is unaffected by this setting and is still in effect. If phase- The phase offset register can be written with a value that is continuous hopping is needed, this bit should be cleared (NCO added as an offset to the phase accumulator of the NCO. This accumulator is not cleared). The last phase in the NCO phase 16-bit register is interpreted as a 16-bit unsigned integer. A register is the initiating point for the new frequency. 0x0000 in this register corresponds to a 0 radian offset and a 16 PHASE DITHER 0xFFFF corresponds to an offset of 2π × (1 − 1/2 ) radians. This register allows multiple NCOs (multiple channels) to be The AD6654 provides a phase dither option for improving the synchronized to produce complex sinusoids with a known and spurious performance of the NCO. Writing Logic 1 in the phase steady phase difference. dither enable bit of the NCO control register of individual channels enables phase dither. When phase dither is enabled, HOP SYNC random phase is added to the LSBs of the phase accumulator of A hop sync should be issued to the channel, when the NCO the NCO. When phase dither is enabled, spurs due to phase frequency of that channel needs to be changed from one truncation in the NCO are randomized. frequency to another. See the Chip Synchronization section for The energy from these spurs is spread into the noise floor and details. the spurious free dynamic range is increased at the expense of a very slight decrease in the SNR. The choice of whether to use phase dither in a system is ultimately decided by the system goals. If lower spurs are desired at the expense of a slightly raised noise floor, phase dither should be employed. If a low noise floor is desired and higher spurs can be tolerated or filtered by subsequent stages, then phase dither is not needed. Rev. 0 | Page 35 of 88 AD6654 FIFTH-ORDER CIC FILTER not performed. In bypass mode, the output of the CIC filter is The signal processing stage immediately after the NCO is a CIC the same as the input of the CIC filter. filter stage. This stage implements a fixed coefficient, decimat- ing, cascade integrated comb filter. The input rate to this filter is CIC REJECTION the same as the data rate at the input port; the output rate from Table 15 illustrates the amount of bandwidth as a percentage of this stage is dependent on the decimation factor. the data rate into the CIC stage, which can be protected with f various decimation rates and alias rejection specifications. The IN f = CIC maximum input rate into the CIC is 150 MHz (the same as the M CIC maximum input port data rate). The data can be scaled to any The decimation ratio, M , can be programmed from 2 to 32 other allowable sample rate. CIC (only integer values). The 5-bit word in the CIC decimation Table 15 can be used to decide the minimum decimation register is used to set the CIC decimation factor. A binary value required in the CIC stage to preserve a certain bandwidth. The of one less than the decimation factor is written into this CIC5 stage can protect a much wider bandwidth to any given register. The decimation ratio of 1 can be achieved by bypassing rejection, when a decimation ratio lower than that identified in the CIC filter stage. The frequency response of the filter is given the table is used. The table helps to calculate an upper boundary by the following equations. The gain and pass-band droop of on decimation, MCIC, given the desired filter characteristics. the CIC should be calculated by these equations. Both parame- ters can be offset in the RCF stage. Table 15. SSB CIC5 Alias Rejection Table (f = 1) IN 5 −M CIC MCIC5 −60 dB −70 dB −80 dB −90 dB −100 dB ⎛ ⎞ 1 1− Z ⎜ ⎟ H(z)= × −1 () S +5 ⎜ ⎟ 2 8.078 6.393 5.066 4.008 3.183 CIC 1− Z 2 ⎝ ⎠ 3 6.367 5.110 4.107 3.297 2.642 5 4 5.022 4.057 3.271 2.636 2.121 ⎛ M ⎞ ⎛ ⎞ CIC× f ⎜ ⎟ 5 4.107 3.326 2.687 2.170 1.748 ⎜ ⎟ SIN ⎜ ⎟ ⎜ ⎟ f 6 3.463 2.808 2.270 1.836 1.480 1 IN ⎝ ⎠ ⎜ ⎟ H( f )= × (S + 5) 7 2.989 2.425 1.962 1.588 1.281 CIC ⎜ ⎛ ⎞ ⎟ 2 f ⎜ ⎟ SIN π ⎜ ⎟ 8 2.627 2.133 1.726 1.397 1.128 ⎜ ⎟ ⎜ ⎟ f IN ⎝ ⎠ ⎝ ⎠ 9 2.342 1.902 1.540 1.247 1.007 10 2.113 1.716 1.390 1.125 0.909 where: 11 1.924 1.563 1.266 1.025 0.828 fIN is the data input rate to the channel under consideration. 12 1.765 1.435 1.162 0.941 0.760 S , the scale factor, is a programmable unsigned integer CIC 13 1.631 1.326 1.074 0.870 0.703 between 0 and 20. 14 1.516 1.232 0.998 0.809 0.653 15 1.416 1.151 0.932 0.755 0.610 The attenuation of the data into the CIC stage should be con- 16 1.328 1.079 0.874 0.708 0.572 trolled in 6 dB increments. For the best dynamic range, SCIC 17 1.250 1.016 0.823 0.667 0.539 should be set to the smallest value possible (lowest attenuation 18 1.181 0.960 0.778 0.630 0.509 possible) without creating an overflow condition. This can be 19 1.119 0.910 0.737 0.597 0.483 accomplished safely using the following equation, where 20 1.064 0.865 0.701 0.568 0.459 input_level is the largest possible fraction of the full-scale value 21 1.013 0.824 0.667 0.541 0.437 at the input port. This value is output from the NCO stage and 22 0.967 0.786 0.637 0.516 0.417 pipelined into the CIC filter. 23 0.925 0.752 0.610 0.494 0.399 5 S = ceil() log() M × input _ level − 5 24 0.887 0.721 0.584 0.474 0.383 2 CIC CIC 25 0.852 0.692 0.561 0.455 0.367 5 26 0.819 0.666 0.540 0.437 0.353 (M ) CIC OL = ×input _level CIC 27 0.789 0.641 0.520 0.421 0.340 S + 5 CIC 2 28 0.761 0.618 0.501 0.406 0.328 29 0.734 0.597 0.484 0.392 0.317 BYPASS 30 0.710 0.577 0.468 0.379 0.306 The fifth-order CIC filter can be bypassed when no decimation 31 0.687 0.559 0.453 0.367 0.297 is required of it. When it is bypassed, the scaling operation is 32 0.666 0.541 0.439 0.355 0.287 Rev. 0 | Page 36 of 88 AD6654 EXAMPLE CALCULATIONS In the −100 dB column in Table 15, find the value greater than or equal to the pass-band percentage of the clock rate. Then Goal: Implement a filter with an input sample rate of 100 MHz find the corresponding rate decimation factor (M ). For an requiring 100 dB of alias rejection for a ±1.4 MHz pass band. CIC MCIC of 6, the frequency that has −100 dB of alias rejection is Solution: First determine the percentage of the sample rate that 1.48%, which is slightly larger than the 1.4% calculated. is represented by the pass band. Therefore, for this example, the maximum bound on CIC decimation rate is 6. A higher MCIC means less alias rejection 1.4 MHz than the 100 dB required. BW = 100× = 1.4 FRACTION 100 MHz Rev. 0 | Page 37 of 88 AD6654 FIR HALF-BAND BLOCK The output of the CIC filter is pipelined into the FIR HB (half- DECIMATE-BY-2 HALF-BAND FILTER (HB1) band) block. Each channel has two sets of cascading fixed The next stage of the FIR-HB block is a decimate-by-2 half- coefficient FIR and fixed coefficient half-band filters. The half- band filter. The 11-tap, symmetrical, fixed coefficient HB1 filter band filters decimate by 2. Each of these filters (FIR1, HB1, has low power consumption due to its polyphase implementa- FIR2, and HB2) is described in the following sections. tion. The filter has 22 bits of input and output data with 10-bit coefficients. Table 16 lists the coefficients of the half-band filter. 3-TAP FIXED COEFFICIENT FILTER (FIR1) The normalized coefficients used in the implementation and The 3-tap FIR filter is useful in certain filter configurations in the 10-bit decimal equivalent value of the coefficients are also which extra alias protection is needed for the decimating HB1 listed. Other coefficients are 0s. filter. It is a simple sum-of-products FIR filter with three filter Table 16. Fixed Coefficients for HB1 Filter taps and 2-bit fixed coefficients. Note that this filter does not Coefficient Normalized Decimal Coefficient decimate. The coefficients of this symmetric filter are {1, 2, 1}. Number Coefficient (10-Bit) The normalized coefficients used in the implementation are C1, C11 0.013671875 7 {0.25, 0.5, 0.25}. C3, C9 −0.103515625 −53 C5, C7 0.58984375 302 The user can either use or bypass this filter. Writing Logic 0 to the FIR1 enable bit in the FIR-HB control register bypasses this C6 1 512 fixed coefficient filter. The filter is useful only in certain filter Similar to the FIR1 filter, this filter can be used or bypassed. configurations and bypassing it for other applications results in Writing Logic 0 to the HB1 enable bit in the FIR-HB control power savings. register bypasses this fixed coefficient HB filter. The filter is 0 useful only in certain filter configurations and bypassing it for 0.34 0.66 –8.33 other applications results in power savings. For example, it is FIR1 RESPONSE –16.67 useful in narrow-band and wideband output applications in –25.00 which more filtering is required, as compared to very wide –33.33 bandwidth applications in which a higher output rate might –41.67 prohibit the use of a decimating filter. The response of the filter –50.00 is shown in Figure 49. –58.33 The input sample rate of this filter is the same as the CIC filter –66.67 output rate and is given by –75.00 –81 –83.33 f IN –91.67 f = HB1 M –100.00 CIC 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FRACTION OF FIR1 INPUT SAMPLE RATE where: Figure 48. FIR1 Filter Response to the Input Rate of the Filter fIN is the input rate to the channel. M is the decimation ratio in the CIC filter stage. CIC This filter runs at the same sample rate as the CIC filter output rate and is given by 0 0.43 0.57 –10 f IN –20 f = FIR1 M –30 CIC –40 where: –50 HB1 RESPONSE f is the input rate to the channel. IN –60 M is the decimation ratio in the CIC filter stage. CIC –70 –77 –80 The maximum input and output rates for this filter are –90 150 MHz. –100 –110 –120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FRACTION OF HB1 INPUT SAMPLE RATE Figure 49. HB1 Filter Response to the Input Rate of the Filter Rev. 0 | Page 38 of 88 dBc 05156-037 dBc 05156-038 AD6654 The filter has a maximum input sample rate of 150 MHz and, This filter runs at a sample rate given by one of the following when filter is not bypassed, the maximum output rate is equations: 75 MHz. f = f , if HB1 is bypassed FIR2 HB1 The filter has a ripple of 0.0012 dB and rejection of 77 dB. For f HB1 an alias rejection of 77 dB, the alias-protected bandwidth is 14% fFIR2 = , if HB1 is not bypassed of the filter input sample rate. The bandwidth of the filter for a 2 ripple of 0.00075 dB is also the same as the alias-protected where: bandwidth, due to the nature of half-band filters. The 3 dB bandwidth of this filter is 44% of the filter input sample rate. fHB1 is the input rate of the HB1 filter. For example, if the sample rate into the filter is 50 MHz, then fFIR2 is the input rate of the FIR2 filter. the alias-protected bandwidth of the HB1 filter is 7 MHz. If the The maximum input and output rate for this filter is 75 MHz. bandwidth of the required carrier is greater than 7 MHz, then The response of the FIR2 filter is shown in Figure 51. HB1 might not be useful. 0 0 0.39 0.61 0.43 0.57 –8.33 –10 –16.67 –20 –25.00 FIR2 RESPONSE –30 –30 –33.33 –40 –41.67 –50 –50.00 –60 –58.33 –70 FIR1 + HB1 RESPONSE –66.67 –80 –75.00 –90 –83.33 –100 –107 –91.67 –110 –100.00 –120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FRACTION OF FIR2 INPUT SAMPLE RATE FRACTION OF HB1 INPUT SAMPLE RATE Figure 51. FIR2 Filter Response to the Input Rate of the Filter Figure 50. Composite Response of FIR1 and HB1 Filters to Their Input Rate DECIMATE-BY-2 HALF-BAND FILTER (HB2) 6-TAP FIXED COEFFICIENT FILTER (FIR2) The second stage of the second cascade of the FIR-HB block is a Following the first cascade of the FIR1 and HB1 filters is the decimate-by-2 half-band filter. The 27-tap, symmetric, fixed second cascade of the FIR2 and HB2 filters. The 6-tap, fixed coefficient HB2 filter has low power consumption due to its coefficient FIR2 filter is useful in providing extra alias polyphase implementation. The filter has 20 bits of input and protection for the decimating HB2 filter in certain filter output data with 12-bit coefficients. The normalized configurations. It is a simple sum-of-products FIR filter with coefficients used in the implementation and the 10-bit decimal six filter taps and 5-bit fixed coefficients. Note that this filter equivalent value of the coefficients are listed in Table 18. Other does not decimate. The normalized coefficients used in the coefficients are 0s. implementation and the 5-bit decimal equivalent value of the coefficients are listed in Table 17. Table 18. HB2 Filter Fixed Coefficients Table 17. 6-Tap FIR2 Filter Coefficients Coefficient Normalized Decimal Coefficient Number Coefficient (12-Bit) Coefficient Normalized Decimal Coefficient C1, C27 0.00097656 2 Number Coefficient (5-Bit) C3, C25 −0.00537109 −11 C0, C5 −0.125 −2 C1, C4 0.1875 3 C5, C23 0.015 32 C2, C3 0.9375 15 C7, C21 −0.0380859 −78 C9, C19 0.0825195 169 The user can either use or bypass this filter. Writing Logic 0 to C11, C17 −0.1821289 −373 FIR2 enable bit in the FIR-HB control register bypasses this C13, C15 0.6259766 1282 fixed coefficient filter. The filter is useful only in certain filter configurations and bypassing it for other applications results in C14 1 2048 power savings. The filter is especially useful in increasing the Similar to the HB1 filter, this filter can either be used or stop-band attenuation of the HB2 filter that follows. Therefore, bypassed. Writing Logic 0 to the HB1 enable bit in the FIR-HB it is optimal to use both FIR2 and HB2 in a configuration. Rev. 0 | Page 39 of 88 dBc 05156-039 dBc 05156-040 AD6654 control register bypasses this fixed coefficient HB filter. The The input to the filter has a maximum of 75 MHz. The filter is useful only in certain filter configurations and bypassing maximum output rate when not bypassed is 37.5 MHz. it for other applications results in power savings. For example, The filter has a ripple of 0.00075 dB and rejection of 81 dB. For the filter is useful in narrow-band applications in which more an alias rejection of 81 dB, the alias-protected bandwidth is 33% filtering is required, as compared to wide-band applications, in of the filter input sample rate. The bandwidth of the filter for a which a higher output rate might prohibit the use of a decimat- ripple of 0.00075 dB is the same as alias-protected bandwidth, ing filter. The response of the HB2 filter is shown in Figure 52. due to the nature of half-band filters. The 3 dB bandwidth of 0.01 0.34 0.66 this filter is 47% of the filter input sample rate. For example, if –9.99 the sample rate into the filter is 25 MHz, then the alias- –19.99 protected bandwidth of the HB2 filter is 8.25 MHz (33% of –29.99 25 MHz). If the bandwidth of the required carrier is greater –39.99 than 8.25 MHz, then HB2 might not be useful. –49.99 0.01 –60.00 –65 0.34 0.66 –9.99 –70.00 –19.99 –80.00 HB2 RESPONSE –29.99 –90.00 –39.99 –100.00 –49.99 –110.00 –60.00 –120.00 FIR2 + HB2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 –70.00 RESPONSE FRACTION OF HB2 INPUT SAMPLE RATE –80.00 –90 Figure 52. HB2 Filter Response to the Input Rate of the Filter –90.00 –100.00 The filter input sample rate is the same as the FIR2 filter output –110.00 rate and is given by one of the following equations: –120.00 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 fHB2 = fFIR2 = fHB1, if HB1 is bypassed FRACTION OF HB2 INPUT SAMPLE RATE Figure 53. Composite Response of FIR2 and HB2 Filters to Their Input Rates f HB1 f = f = , if HB1 is not bypassed HB2 FIR2 2 where: f is the input rate of the FIR2 filter. FIR2 f is the input rate of the HB2 filter. HB2 f is the input rate of the HB1 filter. HB1 Rev. 0 | Page 40 of 88 dBc 05156-041 dBc 05156-042 AD6654 INTERMEDIATE DATA ROUTER Following the FIR-HB cascade filters is the intermediate data Allowing different channel back ends to select different channel router. This data router consists of muxes that allow the I and Q front ends is useful in the polyphase implementation of filters. data from any channel front end (input port + NCO + CIC + When multiple AD6654 channels are used to process a single FIRHB) to be processed by any channel back end (MRCF + carrier, a single-channel front end feeds more than one channel DRCF + CRCF). The choice of channel front end is made by back end. After processing through the channel back ends (RCF programming a 3-bit MRCF data select word in the MRCF filters), the data is interleaved back from all the polyphased control register. The valid values for this word and their channels. corresponding settings are listed in Table 19. Table 19. Data Router Select Settings MRCF Data Select[2:0] Data Source 000 Channel 0 001 Channel 1 010 Channel 2 011 Channel 3 1x0 Channel 4 1x1 Channel 5 Rev. 0 | Page 41 of 88 AD6654 MONO-RATE RAM COEFFICIENT FILTER (MRCF) The MRCF is a programmable sum-of-products FIR filter. This Because this filter is nondecimating, the input and output rates filter block comes after the first data router and before the are both the same and equal to one of the following: DRCF and CRCF programmable filters. It consists of a maxi- fMRCF = fHB2, if HB2 is not bypassed mum of eight taps with 6-bit programmable coefficients. Note that this block does not decimate and is used as a helper filter f HB2 for the DRCF and CRCF filters that follow in the signal chain. f = , if HB2 is not bypassed MRCF 2 The number of filter taps that are to be calculated is program- If fPLLCLK is the PLL clock and if mable using the 3-bit number-of-taps word in the MRCF control register of the channel under consideration. The 3-bit f PLLCLK fMRCF × NTAPS <= , word programmed is one less than the number of filter taps. 2 The coefficients themselves are programmed in eight MRCF coefficient memory registers for individual channels. The input then half of the PLL clock can be used for processing (power and output data to the block are both 20-bit. savings). Otherwise, the PLL clock should be used. SYMMETRY BYPASS Though the MRCF filter does not require symmetrical filters, if The MRCF filter can be used in normal operation or bypassed the filter is symmetrical, then the symmetry bit in the MRCF using the MRCF bypass bit in the MRCF control register. When control register should be set. When this bit is set, only half of the filter is bypassed, the output of the filter is the same as the the impulse response needs to be programmed into the MRCF input of the filter. Bypassing the MRCF filter when not required coefficient memory registers. For example, if the number of results in power savings. filter taps is equal to five or six and the filter is symmetrical, SCALING then only three coefficients need to be written into the coeffi- cient memory. For both symmetrical and asymmetrical filters, The output of the MRCF filter can be scaled by using the 2-bit the number of filter taps is limited to eight. MRCF scaling word in the MRCF control register. Table 20 shows the valid values for the 2-bit word and their CLOCK RATE corresponding settings. The MRCF filter runs on an internal high speed PLL clock. This Table 20. MRCF Scaling Factor Settings clock rate can be as high as 200 MHz. If the half clock rate bit in MRCF Scale Word[1:0] Scaling Factor the MRCF control register is set, then only half the PLL clock 00 18.06 dB attenuation rate is used (maximum of 100 MHz). This results in power 01 12.04 dB attenuation savings, but can only be used if certain conditions are met. 10 6.02 dB attenuation 11 No scaling, 0 dB Rev. 0 | Page 42 of 88 AD6654 DECIMATING RAM COEFFICIENT FILTER (DRCF) Following the MRCF is the programmable DRCF FIR filter. COEFFICIENT OFFSET This filter can calculate up to 64 asymmetrical filter taps or up More than one set of filter coefficients can be loaded into to 128 symmetrical filter taps. The filter is also capable of a coefficient RAM at any given time (given sufficient RAM programmable decimation rate from 1 to 16. A flexible space). The coefficient offset can be used in this case to access coefficient offset feature allows loading multiple filters into the the two or more different filters. By changing the coefficient coefficient RAM and changing the filters on the fly. The offset, the filter coefficients being accessed can be changed on decimation phase feature allows a polyphase implementation, the fly. This decimal offset value is programmed in the DRCF where multiple AD6654 channels are used for processing a coefficient offset register. When this value is changed during the single carrier. calculation of a particular output data sample, the sample calculation is completed using the old coefficients, and the new The DRCF filter has 20-bit input and output data and 14-bit coefficient offset from the next data sample calculation is used. coefficient data. The number of filter taps to calculate is programmable and is set in the DRCF taps register. The value DECIMATION PHASE of the number of taps minus one is written to this register. When more than one channel of AD6654 is used to process one For example, a value of 19 in the register corresponds to carrier, polyphase implementation of corresponding channels’ 20 filter taps. DRCF or CRCF is possible using the decimation phase feature. The decimation rate is programmable using the 4-bit DRCF This feature can be used only under certain conditions. The decimation rate word in the DRCF control register. Again, the decimation phase is programmed using the 4-bit DRCF value written is the decimation rate minus one. decimation phase word of the DRCF control register. BYPASS MAXIMUM NUMBER OF TAPS CALCULATED The DRCF filter can be used in normal operation or bypassed The output rate of the DRCF filter is given by using the DRCF bypass bit in the DRCF control register. When f the DRCF filter is bypassed, no scaling is applied and the output MRCF f = DRCF of the filter is the same as the input to the DRCF filter. M DRCF SCALING where: The output of the DRCF filter can be scaled using the 2-bit fMRCF is the data rate out of the MRCF filter and into the DRCF DRCF scaling word in the DRCF control register. Table 21 lists filter. the valid values for the 2-bit word and their corresponding M is the decimation rate in the DRCF filter. DRCF settings. The DRCF filter consists of two multipliers (one each for the Table 21. DRCF Scaling Factor Settings I and Q paths). Each multiplier, working at the high speed clock DRCF Scale Word[1:0] Scaling Factor rate (PLL clock), can do one multiply (or one tap) per high 00 18.06 dB attenuation speed clock cycle. Therefore, the maximum number of filter 01 12.04 dB attenuation taps that can be calculated (symmetrical or asymmetrical filter) 10 6.02 dB attenuation is given by 11 No scaling, 0 dB ⎛ ⎞ f PLLCLK Maximum Number of Taps = ceil⎜ ⎟ − 1 SYMMETRY ⎜ ⎟ f ⎝ DRCF ⎠ The DRCF filter does not require symmetrical filters. However, if the filter is symmetrical, then the symmetry bit in the DRCF where: control register should be set. When this bit is set, only half of f is the high speed internal processing clock generated by PLLCLK the impulse response needs to be programmed into the DRCF the PLL clock multiplier. coefficient memory registers. For example, if the number of fDRCF is the output rate of the DRCF filter, previously calculated. filter taps is equal to 15 or 16 and the filter is symmetrical, then only eight coefficients need to be written into the coefficient memory. Because a total of 64 taps can be written into the memory registers, the DRCF can perform 64 asymmetrical filter taps or 128 symmetrical filter taps. Rev. 0 | Page 43 of 88 AD6654 PROGRAMMING DRCF REGISTERS FOR PROGRAMMING DRCF REGISTERS FOR A AN ASYMMETRICAL FILTER SYMMETRIC FILTER To program the DRCF registers for an asymmetrical filter: To program the DRCF registers for a symmetrical filter: 1. Write NTAPS – 1 in the DRCF taps register, where 1. Write NTAPS – 1 in the DRCF taps register, where NTAPS is the number of filter taps. The absolute NTAPS is the number of filter taps. The absolute maximum value for NTAPS is 64 in asymmetrical filter maximum value for NTAPS is 128 in symmetric filter mode. mode. 2. Write 0 for the DRCF coefficient offset register. 2. Write ceil(64 – NTAPS/2) for the DRCF coefficient offset register, where the ceil function takes the closest integer 3. Write 0 for the symmetrical filter bit in the DRCF control greater than or equal to the argument. register. 3. Write 1 for the symmetrical filter bit in the DRCF control 4. Write the start address for the coefficient RAM, typically register. equal to the coefficient offset register in the DRCF start address register. 4. Write the start address for the coefficient RAM, typically equal to coefficient offset register, in the DRCF start 5. In the DRCF stop address register, write the stop address address register. for the coefficient RAM, typically equal to the following: 5. Write the stop address for the coefficient RAM, typically Coefficient Offset + NTAPS − 1 equal to ceil(NTAPS/2) – 1, in the DRCF stop address register. 6. Write all coefficients in reverse order (start with last coefficient) to the DRCF coefficient memory register. If in 6. Write all coefficients to the DRCF coefficient memory 8-bit microport mode or serial port mode, write the lower register, starting with the middle of the filter and working byte of the memory register first and then the higher byte. towards the end of the filter. When coefficients are After each write access to the DRCF coefficient memory numbered 0 to NTAPS – 1, the middle coefficient is given register, the internal RAM address is incremented starting by the coefficient number ceil(NTAPS/2). If in 8-bit with the start address and ending with the stop address. microport mode or serial port mode, write the lower byte of the memory register first and then the higher byte. Note that each write or read access increments the internal After each write access to the DRCF coefficient memory RAM address. Therefore, all coefficients should be read first register, the internal RAM address is incremented starting before reading them back. Also, for debugging purposes, each with the start address and ending with the stop address. RAM address can be written individually by making the start and stop addresses the same. Therefore, to program one RAM Note that each write or read access increments the internal location, the user writes the address of the RAM location to RAM address. Therefore, all coefficients should be read first both the start and stop address registers, and then writes the before reading them back. Also, for debugging purposes, each coefficient memory register. RAM address can be written individually by making the start and stop addresses the same. Therefore, to program one RAM location, the user writes the address of the RAM location to both the start and stop address registers, and then writes the coefficient memory register. Rev. 0 | Page 44 of 88 AD6654 CHANNEL RAM COEFFICIENT FILTER (CRCF) Following the DRCF is the programmable decimating CRCF Because a total of 64 taps can be written into the memory FIR filter. The only difference between the DRCF and CRCF registers, the CRCF can perform 64 asymmetrical filter taps or filters is the coefficient bit width. The DRCF has 14-bit 128 symmetrical filter taps. coefficients, while the CRCF has 20-bit coefficients. COEFFICIENT OFFSET This filter can calculate up to 64 asymmetrical filter taps or up More than one set of filter coefficients can be loaded into the to 128 symmetrical filter taps. The filter is capable of a coefficient RAM at any time (given sufficient RAM space). The programmable decimation rate from 1 to 16. The flexible coefficient offset can be used in this case to access the two or coefficient offset feature allows loading multiple filters into the more different filters. By changing the coefficient offset, the coefficient RAM and changing the filters on the fly. The filter coefficients being accessed can be changed on the fly. decimation phase feature allows for a polyphase implementa- This decimal offset value is programmed in the CRCF tion in which multiple AD6654 channels are used to process a coefficient offset register. When this value is changed during single carrier. the calculation of a particular output data sample, the sample calculation is completed using the old coefficients and the new The CRCF filter has 20-bit input and output data and 20-bit coefficient offset is brought into effect from the next data coefficient data. The number of filter taps to calculate is sample calculation. programmable and is set in the CRCF taps register. The value of the number of taps minus one is written to this register. For DECIMATION PHASE example, a value of 19 in the register corresponds to 20 filter When more than one channel of the AD6654 is used to process taps. The decimation rate is programmable using the 4-bit one carrier, polyphase implementation of the corresponding CRCF decimation rate word in the CRCF control register. channels’ DRCF or CRCF is possible using the decimation Again, the value written is the decimation rate minus one. phase feature. This feature can be used only under certain BYPASS conditions. The decimation phase is programmed using the 4-bit CRCF decimation phase word of the CRCF control The CRCF filter can be used in normal operation or bypassed register. using the CRCF bypass bit in the CRCF control register. When the CRCF filter is bypassed, no scaling is applied and the output MAXIMUM NUMBER OF TAPS CALCULATED of the filter is the same as the input to the CRCF filter. The output rate of the CRCF filter is given by SCALING f DRCF The output of the CRCF filter can be scaled using the 2-bit f = CRCF M CRCF CRCF scaling word in the CRCF control register. Table 22 shows the valid values for the 2-bit word and the corresponding where: settings. | ∑ | is the sum of all coefficients (in normalized COEFF form) used to calculate the FIR filter. fDRCF is the data rate out of the DRCF filter and into the CRCF filter. Table 22. CRCF Scaling Factor Settings MCRCF is the decimation rate in the CRCF filter. CRCF Scale Word[1:0] Scaling Factor 00 18.06 dB attenuation The CRCF filter consists of two multipliers (one each for the 01 12.04 dB attenuation I and Q paths). Each multiplier, working at the high speed clock 10 6.02 dB attenuation rate (PLL clock), can multiply (or tap once). Therefore, the 11 No scaling, 0 dB maximum number of filter taps that can be calculated (symmetrical or asymmetrical filter) is given by SYMMETRY ⎛ f ⎞ The CRCF filter does not require symmetrical filters. However, PLLCLK ⎜ ⎟ Maximum Number of Taps = ceil − 1 ⎜ ⎟ if the filter is symmetrical, then the symmetry bit in the CRCF f CRCF ⎝ ⎠ control register should be set. When this bit is set, only half the fPLLCLK is the high speed internal processing clock generated by impulse response needs to be programmed into the CRCF the PLL clock multiplier. coefficient memory registers. For example, if the number of f is the output rate of the CRCF filter as previously CRCF filter taps is equal to 15 or 16 and the filter is symmetric, then calculated. only eight coefficients need to be written into the coefficient memory. Rev. 0 | Page 45 of 88 AD6654 PROGRAMMING CRCF REGISTERS FOR AN PROGRAMMING CRCF REGISTERS FOR A ASYMMETRICAL FILTER SYMMETRICAL FILTER To program the CRCF registers for an asymmetrical filter: To program the CRCF registers for a symmetrical filter: 1. Write NTAPS – 1 in the CRCF taps register, where NTAPS 1. Write NTAPS – 1 in the CRCF taps register, where NTAPS is the number of filter taps. The absolute maximum value is the number of filter taps. The absolute maximum value for NTAPS is 64 in asymmetrical filter mode. for NTAPS is 128 in symmetrical filter mode. 2. Write 0 for the CRCF coefficient offset register. 2. Write ceil(64 – NTAPS/2) for the CRCF coefficient offset register, where the ceil function takes the closest integer 3. Write 0 for the symmetrical filter bit in the CRCF control greater than or equal to the argument. register. 3. Write 1 for the symmetrical filter bit in the CRCF control 4. In the CRCF start address register, write the start address register. for the coefficient RAM, typically equal to the coefficient offset register. 4. In the CRCF start address register, write the start address for the coefficient RAM, typically equal to the coefficient 5. In the CRCF stop address register, write the stop address offset register. for the coefficient RAM, typically equal to the following: 5. In the CRCF stop address register, write the stop address Coefficient Offset + NTAPS – 1 for the coefficient RAM, typically equal to ceil(NTAPS/2) – 1. 6. Write all coefficients in reverse order (start with last coefficient) to the CRCF coefficient memory register. In 6. Write all coefficients to the CRCF coefficient memory 8 bit microport mode or serial port mode, write the lower register, starting with middle of the filter and working byte of the memory register first and then the higher byte. towards the end of the filter. When coefficients are In 16-bit microport mode, write the lower 16-bits of the numbered 0 to NTAPS – 1, the middle coefficient is given CRCF memory register first and then the high four bits. by the coefficient number ceil(NTAPS/2). In 8-bit After each write access to the CRCF coefficient memory microport mode or serial port mode, write the lower byte register, the internal RAM address is incremented starting of the memory register first and then the higher byte. In with the start address and ending with the stop address. 16-bit microport mode, write the lower 16-bits of the CRCF memory register first and then the high four bits. Note that each write or read access increments the internal After each write access to the CRCF coefficient memory RAM address. Therefore, all coefficients should be read first register, the internal RAM address is incremented starting before reading them back. Also, for debugging purposes, each with the start address and ending with the stop address. RAM address can be written individually by making the start and stop addresses the same. Therefore, to program one RAM Note that each write or read access increments the internal location, the user writes the address of the RAM location to RAM address. Therefore, all coefficients should be read first both the start and stop address registers, and then writes the before reading them back. Also, for debugging purposes, each coefficient memory register. RAM address can be written individually by making the start and stop addresses the same. Therefore, to program one RAM location, the user writes the address of the RAM location to both the start and stop address registers, and then writes the coefficient memory register. Rev. 0 | Page 46 of 88 AD6654 INTERPOLATING HALF-BAND FILTER The AD6654 has interpolating half-band FIR filters that The image rejection of this filter is about 55 dB, but is sufficient immediately follow the CRCF programmable FIR filters and because the image is from the desired signal, not an interfering precede the second data router. Each interpolating half-band signal. Note that the interpolating half-band filter can be filter takes 22-bit I and 22-bit Q data from the preceding CRCF enabled by writing Logic 1 to Bit 9 of the MRCF control and outputs rounded 22-bit I and 22-bit Q data to the second registers. data router. A 10-tap fixed coefficient filter is implemented in The frequency response of the interpolating half-band FIR is this stage. The maximum input rate into this block is 17 MHz. shown in Table 23 with respect to the chip rate. The input rate Consequently, the maximum output is constrained to 34 MHz. to this filter is 2× the chip rate, and the output rate is 4× the The normalized coefficients used in the implementation and chip rate. the 10-bit decimal equivalent value of the coefficients are listed in Table 23. Other coefficients are 0. 0 0.75 1.25 Table 23. Interpolating HB Filter Fixed Coefficients Coefficient Normalized Decimal Coefficient –20 Number Coefficient (10-Bit) C1, C11 0.02734375 14 INTERPOLATING –40 HALF-BAND C3, C9 −0.12890625 −66 FILTER RESPONSE –53 C5, C7 0.603515625 309 –60 C6 1 512 The half-band filters interpolate the incoming data by 2×. For a –80 channel running at 2× the chip rate, the half-band can be used to output channel data at 4× the chip rate. The interpolation operation creates an image of the baseband signal, which is –100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 filtered out by the half-band filter. FREQUENCY AS FRACTION OF INPUT RATE Figure 54. Interpolating Half-Band Frequency Response Rev. 0 | Page 47 of 88 dBc 05156-043 AD6654 OUTPUT DATA ROUTER The output data router circuit precedes the six AGCs of the The same coefficients are programmed into both of the final output block and immediately follows interpolating half- channels’ RCF filters, and the decimation phases are set to 0 band filters. This block consists of two subblocks. The first and 1. The decimation phases can be set to 0 for one channel block is responsible for combining (interleaving) data from and 1 for the second channel in the pair. This causes the first more than one channel into a single stream of data. The second channel to produce the even outputs of the filter, and the block performs complex filter completion, as explained later in second to produce the odd outputs of the filter. The streams this section. The combined data is passed on to the AGCs. are then recombined (interleaved) to produce the desired 9.216 MHz output rate. The benefit is that now each channel’s CH0 AGC0 RCF has time to calculate twice as many taps, because it has a AGC0 lower output rate. The interleaving function is a simple time-multiplexing func- CH1 AGC1 tion, with lower data rate on the input side and higher data rate AGC1 PARALLEL on the output side. The output data rate is the sum of all input PORT A stream data rates that are combined. CH2 AGC2 AGC2 The channels that need to be combined are programmable with STREAM sufficient flexibility. Table 24 gives the combinations that are PARALLEL CONTROL PORT B possible using a 4-bit word (stream control bits) in the Parallel CH3 AGC3 Port Control 2 register. AGC3 Table 24. Stream Control Bit Combinations and Selections PARALLEL Stream Number of CH4 AGC4 PORT C Control Bits Output Streams Streams AGC4 0000 Ch 0, Ch 1 combined; Ch 2, Ch 3, 5 Ch 4, Ch 5 independent 0001 Ch 0, Ch 1, Ch 2 combined; Ch 3, 4 CH5 AGC5 AGC5 Ch 4, Ch 5 independent 0010 Ch 0, Ch 1, Ch 2, Ch 3 combined; 3 Ch 4, Ch 5 independent Figure 55. Block Diagram of the Output Data Router 0011 Ch 0, Ch 1, Ch 2, Ch 3, Ch 4 2 combined; Ch 5 independent INTERLEAVING DATA 0100 Ch 0, Ch 1, Ch 2, Ch 3, Ch 4, Ch 5 1 In some cases, filtering using a single channel is insufficient. For combined such setups, it is advantageous to combine the filtering 0101 Ch 0, Ch 1, Ch 2 combined; Ch 3, 2 resources of multiple channels rather than using filtering Ch 4, Ch 5 combined resources from a single channel. 0110 Ch 0, Ch 1 combined; Ch 2, Ch 3 3 combined; Ch 4, Ch 5 combined Multiple channels can be set up to co-process the ADC input 0111 Ch 0, Ch 1 combined; Ch 2, Ch 3 3 port data with the same NCO and filter setups. The decimation combined; Ch 4, Ch 5 independent phase values in one of the RCF filters are set such that the 1000 Ch 0, Ch 1, Ch 2 combined; Ch 3, 3 channel’s filters are exactly out of phase with each other. In the Ch 4 combined; Ch 5 independent data router, these multiple channels are interleaved (combined) 1001 Ch 0, Ch 1, Ch 2, Ch 3 combined; 2 Ch 4, Ch 5 combined to form a single stream of data. Because each individual channel Any other Independent channels 6 is decimated more than it would have been if a single channel state were filtering, more number-of-filter taps can be calculated. This is best illustrated with an example: Two channels need to work together to produce a filter at an output rate of 9.216 MHz, when the input rate is 92.16 MHz. Each channel is decimated by a factor of 20 (total decimation) to achieve the desired output rate of 4.608 MHz each. This compares to a decimation of 10, if a single channel were working towards filtering. Rev. 0 | Page 48 of 88 05156-044 AD6654 AUTOMATIC GAIN CONTROL truncation of bits below the output range. Overflow is caused by The AD6654 is equipped with six independent automatic gain clipping errors when the output signal exceeds the output range. control (AGC) loops that directly follow the second data router Modulation error occurs when the output gain varies while and immediately precede the parallel output ports. Each AGC receiving data. circuit has 96 dB of range. It is important that the decimating filters of the AD6654 preceding the AGC reject unwanted The desired signal level should be set based on the probability signals, so that each AGC loop is operating only on the carrier density function of the signal, so that the errors due to under- of interest, and carriers at other frequencies do not affect the flow and overflow are balanced. The gain and damping values ranging of the loop. of the loop filter should be set, so that the AGC is fast enough to track long-term amplitude variations of the signal that might The AGC compresses the 22-bit complex output from the cause excessive underflow or overflow, but slow enough to second data router into a programmable word size of 4 to 8, 10, avoid excessive loss of amplitude information due to the 12, or 16 bits. Because the small signals from the lower bits are modulation of the signal. pushed in to higher bits by adding gain, the clipping of the lower bits does not compromise the SNR of the signal of AGC LOOP interest. The AGC loop is implemented using a log-linear architecture. It The AGC maintains a constant mean power on the output contains four basic operations: power calculation, error calcula- despite the level of the signal of interest, allowing operation in tion, loop filtering, and gain multiplication. environments where the dynamic range of the signal exceeds The AGC can be configured to operate in either desired signal the dynamic range of the output resolution. The output width of level mode or desired clipping level mode. The mode is set by the AGC is set by writing a 3-bit AGC word-length word in the the AGC clipping error bit of the AGC control register. The AGC control register of the individual channel’s memory map. AGC adjusts the gain of the incoming data according to how far The AGC can be bypassed, if needed, and, when bypassed, the it is from a given desired signal level or desired clipping level, 24-bit complex input word remains truncated to a 16-bit value depending on the selected mode of operation. that is output through the parallel port output. The six AGCs Two data paths to the AGC loop are provided: one before the available on the AD6654 are programmable through the six clipping circuitry and one after the clipping circuitry, as shown channel memory maps. AGCs corresponding to individual in Figure 56. For the desired signal level mode, only the I/Q channels can be bypassed by writing Logic 1 to the AGC bypass path prior to the clipping is used. For the desired clipping level bit in the AGC control register. mode, the difference of the I/Q signals from before and after the Three sources of error can be introduced by the AGC function: clipping circuitry is used. underflow, overflow, and modulation. Underflow is caused by I I CLIP 22 PROGRAMMABLE GAIN MULTIPLIER BITS BIT WIDTH Q Q CLIP USED ONLY FOR DESIRED CLIPPING LEVEL MODE 2 2 MEAN SQUARE (I + Q ) 2× AVERAGE 1 – 16384 SAMPLES POWER OF 2 DECIMATE 1 – 4096 SAMPLES SQUARE ROOT log (x) 2 E ERROR R DESIRED THRESHOLD ERROR –1 Kz G (z) = K1 GAIN –1 –2 1 – (1 + P)z + Pz K2 GAIN P POLE Figure 56. Block Diagram of the AGC Rev. 0 | Page 49 of 88 05156-045 AD6654 where: DESIRED SIGNAL LEVEL MODE In this mode of operation, the AGC strives to maintain the M is the decimation ratio (1 to 4,096). CIC output signal at a programmable set level. The desired signal N is the number of averaged samples programmed as a AVG level mode is selected by writing Logic 0 into the AGC clipping multiple of the decimation ratio (1, 2, 3, or 4). error enable bit of the AGC control register. The loop finds the square (or power) of the incoming complex data signal by For example, if a decimation ratio MCIC is 1,000 and NAVG is 3 squaring I and Q and adding them. (decimation of 1,000 and averaging of 3,000 samples), then the actual gain due to averaging and decimation is 3,000 or The AGC loop has an average and decimate block. This average 69.54 dB (log (3000)). Because attenuation is implemented as a 2 and decimate operation takes place on power samples and bit-shift operation, only multiples of 6.02 dB attenuations are before the square root operation. This block can be pro- possible. S in this case is 12, corresponding to 72.24 dB. This CIC grammed to average from 1 to 16,384 power samples, and the way, SCIC scaling always attenuates more than is sufficient to decimate section can be programmed to update the AGC once compensate for the gain in the average and decimate sections every 1 to 4,096 samples. The limitation on the averaging and, therefore, prevents overflows in the AGC loop. But it is operation is that the number of averaged power samples should also evident that the SCIC scaling induces a gain error (the be a multiple of the decimation value (1×, 2×, 3×, or 4×). difference between gain due to CIC and attenuation provided by scaling) of up to 6.02 dB. This error should be compensated The averaging and decimation effectively means that the AGC for in the request signal level, as explained later in this section. can operate over averaged power of 1 to 16,384 output samples. Updating the AGC once every 1 to 4,096 samples and operating A logarithm to the Base 2 is applied to the output from the on average power facilitates the implementation of the loop average and decimate sections. These decimated power samples filter with slow time constants, where the AGC error converges are converted to rms signal samples by applying a square root slowly and makes infrequent gain adjustments. It is also useful operation. This square root is implemented using a simple shift when the user wants to keep the gain scaling constant over a operation in the logarithmic domain. The rms samples obtained frame of data or a stream of symbols. are subtracted from the request signal level R specified in the AGC desired level register, leaving an error term to be Due to the limitation that the number of average samples must processed by the loop filter, G(z). be a multiple of the decimation value, only the multiple numbers 1, 2, 3, or 4 are programmed. This is set using the The user sets this programmable Request Signal Level R accord- AGC average samples word in the AGC average sample register. ing to the output signal level that is desired. The Request Signal These averaged samples are then decimated with decimation Level R is programmable from −0 dB to −23.99 dB in steps of ratios programmable from 1 to 4,096. This decimation ratio is 0.094 dB. defined in the 12-bit AGC update decimation register. The request signal level should also compensate for errors, if The average and decimate operations are tied together and any, due to the CIC scaling, as previously explained in this implemented using a first-order CIC filter and FIFO registers. section. Therefore, the request signal level is offset by the Gain and bit growth are associated with CIC filters and depend amount of error induced in CIC, given by on the decimation ratio. To compensate for the gain associated Offset = 10 × log(M × N − S × 3.01 dB with these operations, attenuation scaling is provided before the CIC AVG CIC CIC filter. where Offset is in dB. This scaling operation accounts for the division associated with Continuing the previous example, this offset is given by the averaging operation as well as the traditional bit growth in CIC filters. Because this scaling is implemented as a bit-shift Offset = 72.24 − 69.54 = 2.7 dB operation, only coarse scaling is possible. Fine scaling is imple- So the request signal level is given by mented as an offset in the request level, as explained later in this section. The attenuation scaling, S , is programmable from 0 CIC (DSL− Offset) ⎡ ⎤ to 14 using a 4-bit CIC scale word in the AGC average samples R=− ceil × 0.094 dBFS ⎢ ⎥ register and is given by 0.094 ⎣ ⎦ S = ceil[log (M × N )] where: CIC 2 CIC AVG R is the request signal level. DSL (desired signal level) is the output signal level that the user desires. Rev. 0 | Page 50 of 88 AD6654 Therefore, in the previous example, if the desired signal level is error threshold register, using floating-point representation. It −13.8 dB, the request level R is programmed to be −16.54 dB, consists of four exponent bits and eight mantissa bits. Exponent bits compensating for the offset. are in steps of 6.02 dB and mantissa bits are in steps of 0.024 dB. For example, 0111’10001001 represents 7 × 6.02 + 137 × 0.024 = This request signal level is programmed in the 8-bit AGC 45.428 dB. desired level register. This register has a floating-point representation, where the 2 MSBs are exponent bits and the The user defines the open-loop Pole P and Gain K, which also 6 LSBs are mantissa bits. The exponent is in steps of 6.02 dB, directly impact the placement of the closed-loop poles and filter and the mantissa is in steps of 0.094 dB. For example, a value characteristics. These closed-loop poles, P and P , are the roots 1 2 10’100101 represents 2 × 6.02 + 37 × 0.094 = 15.518 dB. of the denominator of the previous closed-loop transfer function and are given by The AGC provides a programmable second-order loop filter. The programmable parameters Gain 1 (K ), Gain 2 (K ), Error 1 2 2 () 1+ P− K ±(1+ P− K) − 4P Threshold E, and Pole P completely define the loop filter P ,P = 1 2 characteristics. The error term after subtracting the request 2 signal level is processed by the loop filter, G(z). The open loop Typically, the AGC loop performance is defined in terms of its poles of the second-order loop filter are 1 and P, respectively. time constant or settling time. In this case, the closed-loop poles The loop filter parameters, Pole P and Gain K, allow the should be set to meet the time constants required by the AGC adjustment of the filter time constant that determines the loop. window for calculating the peak-to-average ratio. The relationship between the time constant and the closed-loop Depending on the value of the error term that is obtained after poles that can be used for this purpose is subtracting the request signal level from the actual signal level, either Gain Value K1 or Gain Value K2 is used. If the error is less ⎡ ⎤ M CIC than the programmable threshold E, K1 or K2 is used. This P = exp⎢ ⎥ 1,2 SampleRate×τ allows a fast loop when the error term is high (large ⎢ 1,2⎥ ⎣ ⎦ convergence steps required), and a slower loop function when where τ1, 2 are the time constants corresponding to Pole P1 and the error term is smaller (almost converged). Pole P 2. The open-loop gain used in the second-order loop G(z) is given The time constants can also be derived from settling times as by one of the following equations: given by K = K1, if Error < Error Threshold 2% settling time 5% settling time τ= or K = K2, if Error > Error Threshold 4 3 The open-loop transfer function for the filter, including the gain MCIC (CIC decimation is from 1 to 4,096), and either the settling parameter, is time or time constant are chosen by the user. The sample rate is the sample rate of the stream coming into the AGC. If channels −1 Kz were interleaved in the output data router, then the combined G (z)= −1 −2 1−() 1+ P z + Pz sample rate into the AGC should be considered. This rate should be used in the calculation of poles in the previous If the AGC is properly configured in terms of offset in the equation, where the sample rate is mentioned. request level, then there are no gains in the AGC loop except for K, the filter gain. Under these circumstances, a closed-loop The loop filter output corresponds to the signal gain that is expression for the AGC loop is given by updated by the AGC. Because all computation in the loop filter is done in logarithmic domain (to the Base 2) of the samples, −1 G(z) Kz the signal gain is generated using the exponent (power of 2) of G (z)= = CLOSED −1 −2 the loop filter output. 1+ G(z) 1+() K− 1− P z + Pz The gain multiplier gives the product of the signal gain with Program K1 and K2 (the gain parameters) and Pole P through both the I and Q data entering the AGC section. This signal AGC loop Gain 1 and Gain 2, and AGC pole location registers gain is applied as a coarse 4-bit scaling and then as a fine scale from 0 to 0.996 in steps of 0.0039 using 8-bit representation. For 8-bit multiplier. Therefore, the applied signal gain is from 0 to example, 1000 1001 represent (137/256 = 0.535156). The error 96.3 dB in steps of 0.024 dB. The initial signal gain is program- threshold value is programmable between 0 dB and 96.3 dB in mable using the AGC signal gain register. This register is again a steps of 0.024 dB. This value is programmed in the 12-bit AGC Rev. 0 | Page 51 of 88 AD6654 4 exponent plus 8 mantissa bit floating-point representation AGC SYNCHRONIZATION similar to the error threshold. This is taken as the initial gain When the AGC output is connected to a RAKE receiver, the value before the AGC loop starts operating. RAKE receiver can synchronize the average and update section to update the average power for AGC error calculation and loop The products of the gain multiplier are the AGC scaled outputs filtering. This external sync signal synchronizes the AGC with a 19-bit representation. These are, in turn, used as I and Q changes to the RAKE receiver and makes sure that the AGC for calculating the power, and the AGC error and loop are gain word does not change over a symbol period, which, filtered to produce the signal gain for the next set of samples. therefore, provides a more accurate estimation. This synchroni- These AGC scaled outputs can be programmed to have 4-, 5-, zation is accomplished by setting the appropriate bits of the 6-, 7-, 8-, 10-, 12-, or 16-bit widths by using the AGC output AGC control register. word-length word in the AGC control register. The AGC scaled outputs are truncated to the required bit widths by using the Sync Select Alternatives clipping circuitry, as shown in Figure 56. The AGC can receive a sync as follows: Average Samples Setting • Channel sync: The sync signal is used to synchronize the NCO of the channel under consideration. Though it is complicated to express the exact effect of the number of averaging samples by using equations, intuitively it • Pin sync: Selects one of the four SYNC pins. has a smoothing effect on the way the AGC loop addresses a • Sync now bit: Through the AGC control register. sudden increase or a spike in the signal level. If averaging of When the channel sync select bit of the AGC control register is four samples is used, the AGC addresses a sudden increase in Logic 1, the AGC receives the sync signal used by the NCO of signal level more slowly compared to no averaging. The same the corresponding channel for the start. When this bit is Logic 0, applies to the manner in which the AGC addresses a sudden the pin sync defined by the 2-bit SYNC pin select word in the decrease in the signal level. AGC control register provides the sync to the AGC. Apart from DESIRED CLIPPING LEVEL MODE these two methods, the AGC control register also has a sync now bit that can be used to provide a sync to the AGC by Each AGC can be configured so that the loop locks onto a writing to this register through the microport or serial port. desired clipping level or a desired signal level. Desired clipping level mode is selected by writing Logic 1 in the AGC clipping SYNC PROCESS error mode bit in the AGC control register. For signals that tend Regardless of how a sync signal is received, the syncing process to exceed the bounds of the peak-to-average ratio, the desired is the same. When a sync is received, a start hold-off counter is clipping level option provides a way to prevent truncating those loaded with the 16-bit value in the AGC hold-off register, which signals and still provide an AGC that attacks quickly and settles initiates the countdown. The countdown is based on the ADC to the desired output level. The signal path for this mode of input clock. When the count reaches 1, a sync is initiated. When operation is shown with dotted lines in Figure 56; the operation a sync is initiated, the CIC decimation filter dumps the current is similar to the desired signal level mode. value to the square root, error estimation, and loop filter blocks. First, the data from the gain multiplier is truncated to a lower After dumping the current value, it starts working toward the resolution (4, 5, 6, 7, 8, 10, 12, or 16 bits) as set by the AGC next update value. Additionally on a sync, AGC can be initial- output word-length word in the AGC control register. An error ized, if the initialize AGC on sync bit is set in the AGC control term (for both I and Q) is generated that is the difference register. During initialization, the CIC accumulator is cleared between the signals before and after truncation. This term is and new values for CIC decimation, number of averaging passed to the complex squared magnitude block, for averaging samples, CIC scale, signal gain, open-loop Gain K1 and Gain K2, and decimating the update samples and taking their square root and the Pole P parameter are loaded from their respective to find rms samples as in desired signal level mode. In place of registers. When the initialize on sync bit is cleared, these the request desired signal level, a desired clipping level is parameters are not loaded from the registers. subtracted, leaving an error term to be processed by the second- This sync process is also initiated when a channel comes out of order loop filter. sleep by using the start sync to the NCO. An additional feature is the first sync only bit in the AGC control register. When this The rest of the loop operates the same way as the desired signal bit is set, only the first sync initiates the process and the remain- level mode. This way, the truncation error is calculated and the ing sync signals are ignored. This is useful when syncing using a AGC loop operates to maintain a constant truncation error pin sync. A sync is required only on the first pulse on this pin. level. The only register setting that is different from the desired These additional features make AGC synchronization more signal level mode settings is that the desired clipping level is flexible and applicable to varied circumstances stored in the AGC desired level registers instead of in the request signal level. Rev. 0 | Page 52 of 88 AD6654 PARALLEL PORT OUTPUT The AD6654 incorporates three independent 16-bit parallel When an output data sample is available for output from an ports for output data transfer. The three parallel output ports AGC, the parallel port initiates the transfer by pulling the share a common clock, PCLK. Each port consists of a 16-bit PxREQ signal high. In response, the processor receiving the data bus, request signal, acknowledge signal, three channel data needs to pull the PxACK signal high, acknowledging that it indicator pins, one I/Q indicator pin, one gain word indicator is ready to receive the signal. In Figure 57, PxACK is already pin, and a common shared PCLK pin. The parallel ports can be pulled high and, therefore, the 16-bit I data is output on the configured to function in master mode or slave mode. By data bus on the next PCLK rising edge after PxREQ is driven default, the parallel ports are in slave mode on power-up. logic high. The PxIQ signal also goes high to indicate that I data is available on the data bus. The next PCLK cycle brings the Each parallel port can output data from any or all of the AGCs, Q data onto the data bus. In this cycle, the PxIQ signal is driven using the 1-bit enable bit for each AGC in the parallel port low. When I data and Q data are output, the channel indicator control register. Even when the AGC is not required for a pins PxCH[2:0] indicate the data source (AGC number). certain channel, the AGC can be bypassed, but the data is still received from the bypassed AGC. The parallel port Figure 57 is the timing diagram for interleaved I/Q mode with functionality is programmable through the two parallel port the AGC gain word disabled. Figure 58 is a similar timing control registers. diagram with the AGC gain word. In the PCLK cycle after the Q data, the AGC gain word is output on the data bus and the Each parallel port can be programmed individually to operate PxGAIN signal is pulled high to indicate that the gain word is in either interleaved I/Q mode or parallel I/Q mode. The mode available on the parallel port. Therefore, a minimum of three or is selected using a 1-bit data format bit in the parallel port four PCLK cycles are required to output one sample of output control register. In both modes, the AGC gain word output can data on the parallel port without or with the AGC gain word, be enabled using a 1-bit append gain bit in the parallel port respectively. control register for individual output ports. There are six enable bits per output port, one for each AGC in the corresponding PARALLEL I/Q MODE parallel port. In this mode, eight bits of I data and eight bits of Q data are simultaneously output on the data bus during one PCLK cycle. INTERLEAVED I/Q MODE The I byte is the most significant byte of the port, while the Parallel port channel mode is selected by writing a 0 to the data Q byte is the least significant byte. The PAIQ and PBIQ output format bit for the parallel port in consideration. In this mode, indicator pins are set high during the PCLK cycle. Note that if I and Q words from the AGC are output on the same 16-bit data data from multiple AGCs are output consecutively, the PAIQ bus on a time-multiplexed basis. The 16-bit I word is output and PBIQ output indicator pins remain high until data from all followed by the 16-bit Q word. The specific AGCs output by the channels is output. The PACH[2:0] and PBCH[2:0] pins provide port are selected by setting individual bits for each of the AGCs a 3-bit binary value indicating the source (AGC number) of the in the parallel port control register. Figure 57 shows the timing data currently being output. Figure 59 is the timing diagram for diagram for the interleaved I/Q mode. parallel I/Q mode. PCLK PxACK t DPREQ PxREQ t DPP Px [15:0] I [15:0] Q [15:0] t DPIC PxIQ t DPCH PxCH [2:0] PxCH [2:0] = CHANNEL NO. LOGIC LOW ‘0’ PxGAIN Figure 57. Interleaved I/Q Mode Without an AGC Gain Word Rev. 0 | Page 53 of 88 05156-046 AD6654 PCLK PxACK t DPREQ PxREQ t DPP 0000 + Px [15:0] I[15:0] Q[15:0] GAIN [11:0] t DPIQ PxIQ t DPCH PxCH [2:0] PxCH [2:0] = CHANNEL # t DPGAIN PxGAIN Figure 58. Interleaved I/Q Mode with an AGC Gain Word PCLK PxACK t DPREQ PxREQ t DPP I [15:8] Px [15:0] Q [15:8] t DPIQ PxIQ t DPCH PxCH [2:0] = PxCH [2:0] AGC NO. LOGIC LOW 0 PxGAIN Figure 59. Parallel I/Q Mode Without an AGC Gain Word I/Q data, the AGC gain word is output on the data bus, and the When an output data sample is available for output from an PxGAIN signal is pulled high to indicate that the gain word is AGC, the parallel port initiates the transfer by pulling the available on the parallel port. During this PCLK cycle, the PxIQ PxREQ signal high. In response, the processor receiving the signal is pulled low to indicate that I/Q data is not available on data needs to pull the PxACK signal high, acknowledging that it the data bus. Therefore, in parallel I/Q mode, a minimum of is ready to receive the signal. In Figure 59, the PxACK is already two PCLK cycles is required to output one sample of output pulled high and, therefore, the 8-bit I data and 8-bit Q data are data on the parallel port without and with the AGC gain word, simultaneously output on the data bus on the next PCLK rising respectively. edge after PxREQ is driven logic high. The PxIQ signal also goes high to indicate that I/Q data is available on the data bus. The order of data output is dependent on when data arrives at When I/Q data is being output, the channel indicator pins the port, which is a function of total decimation rate, DRCF/ PxCH[2:0] indicate the data source (AGC number). CRCF decimation phase, and start hold-off values. Priority order from highest to lowest is, AGC0, AGC1, AGC2, AGC3, Figure 59 is the timing diagram for parallel I/Q mode with the AGC4, and AGC5 for both parallel I/Q and interleaved modes AGC gain word disabled. Figure 60 is a similar timing diagram of output. with the AGC gain word enabled. In the PCLK cycle after the Rev. 0 | Page 54 of 88 05156-048 05156-047 AD6654 selected by setting the PCLK master mode bit in the Parallel MASTER/SLAVE PCLK MODES Port Control 2 register. The parallel ports can operate in either master or slave mode. The mode is set via PCLK master mode bit in the Parallel Port PLL _ CLK rate PCLK rate= Control 2 register. The parallel ports power up in slave mode to PCLK divisor avoid possible contentions on the PCLK pin. In slave mode, external circuitry provides the PCLK signal. In master mode, PCLK is an output derived by dividing Slave mode PCLK signals can be either synchronous or PLL_CLK down by the PCLK divisor. The PCLK divisor can asynchronous. The maximum slave mode PCLK frequency is have a value of 1, 2, 4, or 8, depending on the 2-bit PCLK also 200 MHz. divisor word setting in the Parallel Port Control 2 register. The highest PLCK rate in master mode is 200 MHz. Master mode is PCLK PxACK t DPREQ PxREQ t DPP I [15:8] 0000 + Px [15:0] Q [15:8] GAIN [11:0] t DPIQ PxIQ t DPCH PxCH [2:0] PxCH [2:0] = CHANNEL # t DPGAIN PxGAIN Figure 60. Parallel I/Q Mode with an AGC Gain Word Rev. 0 | Page 55 of 88 05156-049 AD6654 PARALLEL PORT PIN FUNCTIONS Table 25 describes the functions of the pins used by the parallel ports. Table 25. Parallel Port Pin Functions Pin Name I/O Function PCLK I/O Parallel Clock. PCLK can operate as a master or as a slave. This setting is dependent on the 1-bit PCLK master mode bit in the Parallel Port Control 2 register. As an output (master mode), the maximum frequency is CLK/N, where CLK is the AD6654 clock and N is an integer divisor of 1, 2, 4, or 8. As an input (slave mode), it can be asynchronous or synchronous relative to the AD6654 CLK. This pin powers up as an input to avoid possible contentions. Parallel port output pins change on the rising edge of PCLK. PAREQ, PBREQ, O Active High Output. Synchronous to PCLK. A logic high on this pin indicates that data is available to be PCREQ shifted out of the port. When an acknowledge signal is received, data starts shifting out and this pin remains high until all pending data has been shifted out. PAACK, PBACK, I Active High Asynchronous Input. Applying a logic low on this pin inhibits parallel port data shifting. Applying PCACK a logic high to this pin when REQ is high causes the parallel port to shift out data according to the programmed data mode. ACK is sampled on the rising edge of PCLK. Assuming that REQ is asserted, the latency from the assertion of ACK to data appearing at the parallel port output is no more than 1.5 PCLK cycles. ACK can be continuously held high; in this case, when data becomes available, shifting begins 1 PCLK cycle after the assertion of REQ (see Figure 57, Figure 58, Figure 59, and Figure 60). PAIQ, PBIQ, PCIQ Parallel Output Gain Data Indicators High whenever I data is present on the parallel port data bus; otherwise low. In parallel I/Q mode, both I data and Q data are available at the same time and, therefore, the PxIQ signal is pulled high. PAGAIN, PBGAIN, Parallel Output Gain Word Indicators. High whenever the AGC gain word is present on the parallel port data PCGAIN bus; otherwise low. PACH[2:0], PBCH[2:0], Channel Indicator Output Ports. These pins identify data in both of the parallel port modes. The 3-bit value PCCH[2:0] identifies the source of the data (AGC number) on the parallel port when it is being shifted out. PADATA[15:0], Parallel Output Port Data Bus. Output format is twos complement. In parallel I/Q mode, 8-bit data is present; PBDATA[15:0], in interleaved I/Q mode, 16-bit data is available. PCDATA[15:0] Rev. 0 | Page 56 of 88 AD6654 USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST) accumulated. When the disable signature generation bit is Each channel of AD6654 includes a BIST block. The BIST, written with Logic 0, the BIST timer is counted down and a along with an internal test signal (pseudo random test input signature register is written with the accumulated output of the signal), can be used to generate a signature. This signature can AD6654 channel. be compared with a known good device and an untested device to see if the untested device is functional. When the BIST timer expires, the signature register for I and Q paths can be read back to compare it with the signature register BIST timer bits in the BIST control register can be programmed from a known good device. with a timer value that determines the number of clock cycles that the output of the channels (output of AGC) have Rev. 0 | Page 57 of 88 AD6654 CHIP SYNCHRONIZATION repeated, that is, the soft synchronization register needs to be The AD6654 offers two types of synchronization: start sync and written twice. hop sync. Start sync is used to bring individual channels out of sleep after programming. It can also be used while AD6654 is Start with Pin Sync operational to resynchronize the internal clocks. Hop sync is Four sync pins (SYNC0, SYNC1, SYNC2, and SYNC3) provide used to change or update the NCO frequency tuning word and very accurate synchronization among channels. Each channel the NCO phase offset word. can be programmed to monitor any of the four sync pins. Two methods can be used to initiate a start sync or hop sync: To start the channels with a pin sync: • Soft sync is provided by the memory map registers and is 1. Write the channel register to enable one more channels, if applied to channels directly through the microport or serial the channels are inactive. port interface. 2. Write the NCO start hold-off counter registers with the • Pin sync is provided using four hard-wired SYNC[3:0] pins. 16 appropriate value (greater than 0 and less than 2 ). Each channel is programmed to listen to one of these SYNC pins and do a start sync or a hop sync when a signal is 3. Program the channel NCO control registers to monitor received on these pins. the appropriate SYNC pins. The pin synchronization configuration register (Address 0x04) 4. Write the start synchronization enable bit and SYNC pin is used to make pin synchronization even more flexible. The enable bits high in the pin synchronization configuration part can be programmed to be edge-sensitive or level-sensitive register. This starts the countdown of the start hold-off for SYNC pins. In edge-sensitive mode, a rising edge on the counter. When the count reaches 1, the channels are SYNC pins is recognized as a synchronization event. activated or resynchronized. START HOP Start refers to the startup of an individual channel or chip, or of Hop is a jump from one NCO frequency and/or phase offset to multiple chips. If a channel is not used, it should be put into a new NCO frequency and/or phase offset. This change in sleep mode to reduce power dissipation. Following a hard reset frequency and/or phase offset can be synchronized via micro- (low pulse on the RESET pin), all channels are placed into sleep processor control (soft sync) or via an external sync signal mode. Alternatively, channels can be manually put to sleep by (pin sync). writing 0 to the sleep register. Hop with Soft Sync Start with Soft Sync The AD6654 can synchronize a change in NCO frequency The AD6654 can synchronize channels or chips under micro- and/or phase offset of multiple channels or chips under processor control. The start hold-off counter, in conjunction microprocessor control. The NCO hop hold-off counter, in with the soft start enable bit and the channel enable bits, enables conjunction with the soft hop enable bit and the channel enable this synchronization. bits, enables this synchronization. To synchronize the start of multiple channels via micro- To synchronize the hop of multiple channels via microprocessor processor control: control: 1. Write the channel enable register to enable one or more 1. Write the NCO frequency register(s) or phase offset channels, if the channels are inactive. register(s) to the new value. 2. Write the NCO start hold-off counter registers with the 2. Write the NCO frequency hold-off counter registers with 16 16 appropriate value (greater than 0 and less than 2 ). the appropriate value (greater than 0 and less than 2 ). 3. Write the soft sync channel enable bit(s) and soft start 3. Write 0x00 to the soft synchronization configuration synchronization enable bit high in the soft synchroniza- register. tion configuration register. This starts the countdown by 4. Write the soft hop synchronization enable bit and the the start hold-off counter. When the count reaches 1, the corresponding soft sync channel enable bits high in the channels are activated or resynchronized. soft synchronization configuration register. This starts the Note: When using SPI or SPORT for programming these countdown by the frequency hold-off counter. When the registers, the last step in the above procedure needs to be Rev. 0 | Page 58 of 88 AD6654 count reaches 1, the new frequency and/or phase offset is To control the hop of channel NCO frequencies: loaded into the NCO. 1. Write the NCO frequency register(s) or phase offset Note: When using SPI or SPORT for programming these register(s) to the new value. registers, the last step in the above procedure needs to be 2. Write the NCO frequency hold-off counter(s) to the repeated, that is, the soft synchronization register needs to be 16 written twice. appropriate value (greater than 0 and less than 2 ). Hop with Pin Sync 3. Program the channel NCO control registers to monitor the appropriate SYNC pins. Four sync pins (SYNC0, SYNC1, SYNC2, and SYNC3) provide very accurate synchronization among channels. Each channel 4. Write the hop synchronization enable bit and SYNC pin can be programmed to look at any of the four sync pins. enable bits high in the pin synchronization configuration register. This enables the countdown of the frequency hold-off counter. When the count reaches 1, the new frequency and/or phase offset is loaded into the NCO. Rev. 0 | Page 59 of 88 AD6654 SERIAL PORT CONTROL The AD6654 serial port allows all memory to be accessed The first word for serial transfer is the internal register address. (programmed or readback) serially in one-byte words. Either In LSB first mode, the address is the lower-most address for the serial port or microport can be used (but not both) at any given block transfer (subsequent addresses are generated by internal time. Serial port control is selected using the SMODE pin (0 = increment). In MSB first, the address is highest address for the microport, 1 = serial port). Two serial port modes are available. block transfer (subsequent addresses are generated by internal An SPI-compatible port is provided as well as a SPORT. The decrement). choice of SPI or SPORT mode is selected using the MODE pin The second word of serial transfer contains a one-bit read/write (0 = SPI, 1 = SPORT). indicator (1 = read, 0 = write), and seven bits to define the Each individual byte of serial data (address, instruction and number of data bytes to be transferred (N). For a single data data) may be shifted in either MSB first or LSB first using the byte transfer (N = 1); one byte is shifted into SDI for a write MSBFIRST pin (1 = MSB first, 0 = LSB first). The serial chip transfer, or shifted out of SDO for a read transfer, and the cycle select (SCS) pin is brought low to access the device for serial is complete. For a block transfer, N write/read operations are performed, and the internal register address increments control. When the pin is held high, serial programming is SCS (MSBFIRST = 0) or decrements (MSBFIRST = 1) after each inhibited. data byte is clocked into SDI for a write operation, or after each HARDWARE INTERFACE data byte is clocked out of SDO for a read operation. The pins described in Table 26 comprise the physical interface Figure 61 to Figure 64 illustrate a three byte block transfer between the user’s programming device and the serial port of through the serial port. Read and write operations with the AD6654. All serial pins are inputs except for SDO, which is MSBFIRST high and low are shown. Please note that the figures an open-drain output and should be pulled high by an external show the sequence for write/read transfer, and actual data pull-up resistor (suggested value 1 kΩ). should be shifted in or out based upon the status of the MSBFIRST pin. The operation details are common to both SPI A complete read or write cycle requires a minimum of three and SPORT modes except for the use of framing signals and bytes to transfer, consisting of address word, instruction word, timing. Individual mode details follow. In single byte transfer and data-word(s). As many as 127 data-words can be mode, the count in the second byte would be reduced to one, transferred during a block transfer cycle. All address, and the number of data bytes would be reduced to one. instruction, and data-word(s) must be formatted LSB first or MSB first to match the state of the MSBFIRST pin. Table 26. Serial Port Pins Pin Function SCLK Serial Clock in Both SPI and SPORT Modes. Should have a rise/fall time of 3 ns max. MSBFIRST Indicates whether the first bit shifted in or out of the serial port is the MSB (1) or LSB (0) for both instruction and data- words. Also indicates if the first instruction word (address) is a block start or a block end for multiple byte transfers. This pin also controls the functionality when programming indirectly addressed registers. STFS Serial Transmit Frame Sync in SPORT Mode. STFS is not used in SPI mode. SRFS Serial Receive Frame Sync in SPORT Mode. SRFS is not used in SPI mode. SDI Serial Data Input in Both Modes. Serial data is clocked in on the rising edge of SCLK. SDO Serial Data Output in Both Modes. Serial data is clocked out on the rising edge of SCLK. SCS Active-Low Serial Chip Select in Both Modes. SMODE Serial Mode. Part is programmed through the serial port when this pin is high. MODE Mode Pin. Selects between SPI (0) and SPORT (1) modes. Rev. 0 | Page 60 of 88 AD6654 MSBFIRST SCS DATA TO BLOCK END DATA TO BLOCK END DATA TO BLOCK END BLOCK END ADDRESS WR + COUNT (3) ADDRESS ADDRESS – 1 ADDRESS – 2 SDI 0xaa 0x03 aa aa – 1 aa – 2 SDO MODE Figure 61. Serial Write of Three Bytes with MSBFIRST = 1 (All Words are Written MSB first) MSBFIRST SCS BLOCK START DATA TO BLOCK START DATA TO BLOCK START DATA TO BLOCK START ADDRESS WR + COUNT (3) ADDRESS ADDRESS + 1 ADDRESS + 2 SDI 0xaa 0x03 aa aa + 1 aa + 2 SDO MODE Figure 62. Serial Write of Three Bytes with MSBFIRST = 0 (All Words are Written LSB First) MSBFIRST SCS BLOCK END ADDRESS RD + COUNT (3) 0xaa 0x83 SDI DATA FROM BLOCK END DATA FROM BLOCK END DATA FROM BLOCK END ADDRESS ADDRESS – 1 ADDRESS – 2 aa aa – 1 aa – 2 SDO MODE Figure 63. Serial Read of Three Bytes with MSBFIRST = 1 (All Words are Written or Read MSB First) Rev. 0 | Page 61 of 88 05156-077 05156-076 05156-075 AD6654 MSBFIRST SCS BLOCK START RD + COUNT (3) ADDRESS SDI 0xaa 0x83 DATA FROM BLOCK START DATA FROM BLOCK START DATA FROM BLOCK START ADDRESS ADDRESS + 1 ADDRESS + 2 SDO aa aa + 1 aa + 2 MODE Figure 64. Serial Read of Three Bytes with MSBFIRST = 0 (All Words are Written or Read LSB First) SPI Write SPI MODE TIMING Data on the SDI pin is registered on the rising edge of SCLK. In SPI mode, the SCLK should run only when data is being During a write, the serial port accumulates eight input bits transferred and SCS is logic low. If SCLK runs when SCS is logic of data before transferring one byte to the internal registers. high, the internal shift register continues to run and instruction Figure 65 and Figure 66 show one byte block transfer for words or data are lost. No external framing is necessary. The writing in MSBFIRST and LSBFIRST modes. SCS pin can be pulled low once for each byte of transfer, or kept low for the whole length of the transfer. MSBFIRST SCLK SCS SMODE BLOCK END ADDRESS WRITE BLOCK COUNT (Nx) A7 A6 A5 A4 A3 A2 A1 A0 0 N6N5 N4N3 N2N1 N0 D7D6 D5D4 D3D2 D1D0 SDI SDO MODE Figure 65. SPI Write MSBFIRST = 1 Rev. 0 | Page 62 of 88 05156-078 05156-079 AD6654 MSBFIRST SCLK SCS SMODE BLOCK END ADDRESS BLOCK COUNT (Nx) WRITE SDI A0 A1 A2 A3 A4 A5 A6 A7 N0 N1 N2 N3 N4 N5 N6 0 D0 D1 D2 D3 D4 D5 D6 D7 SDO MODE Figure 66. SPI Write MSBFIRST = 0 SPI Read Register readback data shifts out on the rising edge of SCLK. The SDO pin is in a high impedance state at all times except During a typical read operation, a one byte address and one during a read cycle. byte instruction are written to the serial port to instruct the internal control logic as to which registers are to be accessed. MSBFIRST SCLK SCS SMODE BLOCK END ADDRESS READ BLOCK COUNT (Nx) SDI A7 A6 A5 A4 A3 A2 A1 A0 1 N6 N5 N4 N3 N2 N1 N0 SDO D7 D6 D5 D4 D3 D2 D1 D0 MODE Figure 67. SPI Read MSBFIRST = 1 Rev. 0 | Page 63 of 88 05156-080 05156-058 AD6654 MSBFIRST SCLK SCS SMODE BLOCK START ADDRESS BLOCK COUNT (Nx) READ A0 A1 A2 A3 A4 A5 A6 A7 N0 N1 N2 N3 N4 N5 N6 1 SDI SDO D0 D1 D2 D3 D4 D5 D6 D7 MODE Figure 68. SPI Read MSBFIRST = 0 SPORT Write SPORT MODE TIMING Serial data is sampled on the rising edge of SCLK. The data In SPORT mode, the SCLK continuously runs, and the external should be MSB or LSB first, depending on the polarity of the SRFS and STFS signals are used to frame the data. Incoming MSBFIRST pin. The serial port begins to sample data on the framing signals SRFS (receive) and STFS (transmit) are sampled rising edge of SCLK after SRFS is detected on the falling edge of on the falling edges of SCLK. All input and output data must be SCLK. Once all 8-bits of one byte are shifted in, the data is transmitted or received in 8-bit segments starting with the transferred to the internal bus. rising edge after SRFS or STFS is sampled. MSBFIRST SCLK SCS SMODE SRFS BLOCK START ADDRESS WRITE BLOCK COUNT (Nx) SDI A7 A6 A5 A4 A3 A2 A1 A0 0 N6N5 N4N3 N2N1 N0 D7D6 D5D4 D3D2 D1D0 STFS SDO MODE Figure 69. SPORT Write MSBFIRST = 1 Rev. 0 | Page 64 of 88 05156-081 05156-059 AD6654 MSBFIRST SCLK SCS SMODE SRFS BLOCK START ADDRESS BLOCK COUNT (Nx) WRITE SDI A0 A1 A2 A3 A4 A5 A6 A7 N0 N1 N2 N3 N4 N5 N6 0 D0 D1 D2 D3 D4 D5 D6 D7 STFS SDO MODE Figure 70. SPORT Write MSBFIRST = 0 readback. STFS must be asserted for every 8-bit readback and is SPORT Read sampled on the falling edge of SCLK. Data is shifted out on the For a typical SPORT read operation, the user must write an rising edge of SCLK. The SDO pin is in a high impedance state address byte and instruction byte to the serial port to instruct at all times except during a read operation. the internal control logic as to which registers are to be MSBFIRST SCLK SCS SMODE SRFS BLOCK START ADDRESS READ BLOCK COUNT (Nx) A7 A6 A5 A4 A3 A2 A1 A0 1 N6 N5 N4 N3 N2 N1 N0 SDI STFS D7 D6 D5 D4 D3 D2 D1 D0 SDO MODE Figure 71. SPORT Read MSBFIRST = 1 Rev. 0 | Page 65 of 88 05156-082 05156-060 AD6654 MSBFIRST SCLK SCS SMODE SRFS BLOCK START ADDRESS BLOCK COUNT (Nx) READ SDI A0 A1 A2 A3 A4 A5 A6 A7 N0 N1 N2 N3 N4 N5 N6 1 STFS SDO D0 D1 D2 D3 D4 D5 D6 D7 MODE Figure 72. SPORT Read MSBFIRST = 0 Rev. 0 | Page 66 of 88 05156-061 AD6654 PROGRAMMING INDIRECT ADDRESSED REGISTERS MSBFIRST Mode Using Single Byte Block Transfers SerialWrite(0x98); //CRCF Start Address USING SERIAL PORT SerialWrite(0x01); This section gives examples for programming CRCF coefficient SerialWrite(0x00); RAM (with an indirect addressing scheme) using the serial port SerialWrite(0x99); //CRCF Final Address (either SPI or SPORT modes). Though the following specific SerialWrite(0x01); SerialWrite(N-1); //N is the number of coefficients examples are for CRCF coefficient RAM programming, they can be extended to other indirect addressed registers like DRCF for (i=0 ; i < N; i++) { //writing registers coefficient RAM. There are four possible programming scenarios, SerialWrite(0x9E); //MSB written first and examples are given for all scenarios using two commands: SerialWrite(0x01); SerialWrite(data) and SerialRead. These commands signify an 8- //data bits[23:16] SerialWrite(coeff[i] >> 16 & 0xFF); bit write to, or an 8-bit read from, the serial port (SPI or SPORT). SerialWrite(0x9D); SerialWrite(8-bit number): is an 8-bit write to SPI or SPORT. In SerialWrite(0x01); //data bits[15:8] SPI mode, the SCLK is toggled eight times while SCS is pulled low. SerialWrite(coeff[i] >> 8 & 0xFF); SCS In SPORT mode, is pulled low, SRFS is held high for one SerialWrite(0x9C); //LSB written last SCLK cycle, and eight bits of data are shifted into the SDI pin SerialWrite(0x01); following the SRFS pulse. Though the 8-bit number argument //data bits[7:0] SerialWrite(coeff[i] & 0xFF); shown in the following code is always shown MSBFIRST, it is written with MSB shifting into the device first in MSBFIRST } mode, and it is written with LSB shifting into the device first in SerialWrite(0x98); //CRCF Start Address LSBFIRST mode. SerialWrite(0x01); SerialWrite(0x00); SerialRead(): is an 8-bit read from the SDO pin in SPI or SPORT SerialWrite(0x99); //CRCF Final Address SCS modes. In SPI mode, the SCLK toggles eight times while is SerialWrite(0x01); SCS low. In SPORT mode, is pulled low, STFS is held high for one SerialWrite(N-1); //N is the number of coefficients SCLK cycle, and then the eight bits of data that shifted out on for (i=0 ; i < N; i++) { //reading registers SDO following the STFS pulse are read. The data shifted out SerialWrite(0x9E); //MSB readback first should be interpreted based on the polarity of the MSBFIRST pin. SerialWrite(0x81); //data bits[23:16] Coeff[i] = SerialRead() << 16; SerialWrite(0x9D); SerialWrite(0x81); //data bits[15:8] Coeff[i] |= SerialRead() << 8; SerialWrite(0x9C); //LSB readback last SerialWrite(0x81); //data bits[7:0] Coeff[i] |= SerialRead(); } Rev. 0 | Page 67 of 88 AD6654 LSBFIRST Mode Using Single Byte Block Transfers MSBFIRST Mode Using Multi Byte Block Transfers SerialWrite(0x98); //CRCF Start Address SerialWrite(0x99); //CRCF Final Address SerialWrite(0x01); SerialWrite(0x02); SerialWrite(0x00); SerialWrite(N-1); //N is the number of coefficients SerialWrite(0x00); SerialWrite(0x99); //CRCF Final Address SerialWrite(0x01); for (i=0 ; i < N; i++) { //writing registers SerialWrite(N-1); //N is the number of coefficients SerialWrite(0x9E); for (i=0 ; i < N; i++) { // writing registers SerialWrite(0x03); //data bits[23:16] SerialWrite(0x9C); //LSB written first SerialWrite(0x01); SerialWrite(coeff[i] >> 16 & 0xFF); //data bits[7:0] //data bits[15:8] SerialWrite(coeff[i] & 0xFF); SerialWrite(coeff[i] >> 8 & 0xFF); //data bits[7:0] SerialWrite(0x9D); SerialWrite(coeff[i] & 0xFF); SerialWrite(0x01); //data bits[15:8] } SerialWrite(coeff[i] >> 8 & 0xFF); SerialWrite(0x9E); //MSB written last SerialWrite(0x99); //CRCF Final Address SerialWrite(0x01); SerialWrite(0x02); //data bits[23:16] SerialWrite(N-1); //N is the number of coefficients SerialWrite(coeff[i] >> 16 & 0xFF); SerialWrite(0x00); } for (i=0 ; i < N; i++) { //reading registers SerialWrite(0x98); //CRCF Start Address SerialWrite(0x9E); SerialWrite(0x01); SerialWrite(0x00); SerialWrite(0x83); //data bits[23:16] SerialWrite(0x99); //CRCF Final Address Coeff[i] = SerialRead() << 16; SerialWrite(0x01); //data bits[15:8] SerialWrite(N-1); //N is the number of coefficients Coeff[i] |= SerialRead() << 8; //data bits[7:0] for (i=0 ; i < N; i++) { //reading registers Coeff[i] |= SerialRead(); SerialWrite(0x9C); //LSB readback first } SerialWrite(0x81); //data bits[7:0] LSBFIRST Mode Using Multi Byte Block Transfers Coeff[i] = SerialRead(); SerialWrite(0x98); //CRCF Start Address SerialWrite(0x02); SerialWrite(0x9D); SerialWrite(0x00); SerialWrite(0x81); SerialWrite(N-1); //N is the number of coefficients //data bits[15:8] Coeff[i] |= SerialRead() << 8; for (i=0 ; i < N; i++) { //writing registers SerialWrite(0x9E); //MSB readback last SerialWrite(0x81); SerialWrite(0x9C); //data bits[23:16] SerialWrite(0x03); Coeff[i] |= SerialRead() << 16; //data bits[7:0] SerialWrite(coeff[i] & 0xFF); } //data bits[15:8] SerialWrite(coeff[i] >> 8 & 0xFF); //data bits[23:16] SerialWrite(coeff[i] >> 16 & 0xFF); } SerialWrite(0x98); //CRCF Start Address SerialWrite(0x02); SerialWrite(0x00); SerialWrite(N-1); //N is the number of coefficients for (i=0 ; i < N; i++) { //reading registers SerialWrite(0x9C); SerialWrite(0x83); //data bits[7:0] Coeff[i] = SerialRead(); //data bits[15:8] Coeff[i] |= SerialRead() << 8; //data bits[23:16] Coeff[i] |= SerialRead() << 16; } Rev. 0 | Page 68 of 88 AD6654 In SPORT mode, the Blackfin provides the SCLK, SRFS, and CONNECTING THE AD6654 SERIAL PORT TO A STFS signals, as shown in Figure 74. BLACKFIN DSP In SPI mode, the Blackfin DSP must act as a master to the SCLK SCK SRFS TFS AD6654 by providing the SCLK. SDO is an open-drain output, VDDIO RFS STFS so that multiple slave devices can be connected together. SDI DT Figure 73 shows a typical connection. GND DR SDO BLACKFIN AD6654 SCLK SCS SCK PF2 SPISS SRFS PROGRAMMABLE FLAG VDDIO AND STFS MODE SMODE SDI MOSI GND MISO SDO BLACKFIN AD6654 Figure 74. SPORT Mode Serial Port Connections to Blackfin SCS (MASTER) PF2 (SLAVE) PROGRAMMABLE FLAG MODE SMODE Figure 73. SPI Mode Serial Port Connection to Blackfin DSP Rev. 0 | Page 69 of 88 05156-054 05156-055 AD6654 MICROPORT access. When the internal read or write access is complete, the The microport on the AD6654 can be used for programming RDY pin is pulled high. Because the RDY pin is an open-drain the part, reading register values, and reading output data (I, Q, output with a weak internal pull-up resistor (70 kΩ), an and RSSI words). external pull-up resistor is recommended (see the DDC Design Note that, at any given point in time, either the microport or the Notes section). Figure 10 and Figure 11 are the timing diagrams serial port can be active, but not both. Some of the balls on the for read and write cycles using the microport in INM mode. package are shared between the microport and the serial port For an asynchronous write operation in Intel (INM) mode, the and have dual functionality based on the SMODE pin. The CPUCLK should be running. Set up the data and address buses. microport is selected by pulling the SMODE pin low (ground). Pull the WR signal low and then pull the CS signal low. The Both read and write operations can be performed using the RDY goes low to indicate that the access is taking place inter- microport. The direct addressing scheme is used and any nally. When RDY goes high, the write cycle is complete and CS internal register can be accessed using an 8-bit address. The can be pulled high to disable the microport. data bus can be either 8-bit or 16-bit as set by the chip I/O For an asynchronous read operation on the Intel mode micro- access control register. Microport operation is synchronous to port, set up the address bus and three-state the data bus. Pull CPUCLK, which must be supplied external to the AD6654 part. RD CS the signal low and then pull the signal low. The RDY CPUCLK should be less than CLK and 100 MHz. goes low to indicate an internal access. When RDY goes low, The microport can operate in Intel mode (separate read and valid data is available on the data bus for read. write strobes) or in Motorola mode (single read/write strobe). The MODE pin is used to select between Intel (INM, MODE = MOTOROLA (MNM) MODE 0) and Motorola (MNM, MODE = 1) modes. Some AD6654 The programming port performs synchronous Motorola-style pins have dual functionality based on the MODE pin. Table 27 reads and writes on the positive edge of CPUCLK when RESET lists the pin functions for both modes. is inactive (active low signal). The A[7:0] bus provides the Table 27. Microport Programming Pins address to access and the D[15:0] bus (D[7:0], if the 8-bit data Pin Name Intel Mode Motorola Mode bus is used) is externally driven with data during a write (driven W RESET RESET RESET by the AD6654 during a read). Motorola mode uses the R/ line to indicate the type of access (Logic 1 = read, Logic 0 = SMODE Logic 0 Logic 0 DS MODE Logic 0 Logic 1 write), and the active low data strobe ( ) signal is used to A[7:0] A[7:0] A[7:0] indicate valid data. D[15:0] D[15:0] D[15:0] The chip select (CS) is an active-low input that signals when an R/W (WR) WR R/W access is active on its programming port pins. When the read/ DS (RD) RD DS write cycle is complete, the AD6654 drives DTACK low. The DTACK (RDY) RDY DTACK DTACK CS DS signal goes high again after either the or signal CS CS CS DTACK is driven high. Because the pin is an open-drain output with a weak internal pull-up resistor (70 kΩ), an external pull- INTEL (INM) MODE up resistor is recommended (see the DDC Design Notes The programming port performs synchronous Intel-style reads section). Figure 12 and Figure 13 are the timing diagrams for and writes on the positive edge of the CPUCLK input when read and write cycles using the microport in MNM mode. RESET is inactive (active low signal). The CPUCLK pin is For an asynchronous write operation on the Motorola mode driven by the programming device (CPUCLK of DSP or microport, the CPUCLK should be running. Set up the data and FPGA). During a write access, the A[7:0] address bus provides W DS address buses. Pull the R/ and signals low and then pull the address for access, and the D[15:0] bus (D[7:0] if the 8-bit CS DTACK the signal low. The goes low after a few clock cycles data bus is used) is driven by the programming device. The data CS to indicate that the write access is complete and that can be bus is driven by the AD6654 during a read operation. Intel pulled high to disable the microport. For an asynchronous read mode uses separate read (RD) and write (WR) active low data operation on the Motorola mode microport, set up the address strobes to indicate both the type of access and the valid data for bus and three-state the data bus. Pull the RD signal low and that access. then pull the CS signal low. The DTACK goes low after a few CS The chip select ( ) is an active-low input that signals when an clock cycles to indicate that valid data is on the data bus. access is active on its programming port pins. During an access, the AD6654 drives RDY low to indicate that it is performing the Rev. 0 | Page 70 of 88 AD6654 of the CHIPID pins (hardwired to the part). If the CHIPID bits ACCESSING MULTIPLE AD6654 DEVICES and the CHIPID pins have the same value, then a write/read If multiple AD6654 devices are on a single board, the microport access is completed; otherwise, the access is ignored. pins for these devices can be shared. In this configuration, a single programming device (DSP, FPGA, or microcontroller) To program multiple devices using the same microport control can program all AD6654 devices connected to it. and data buses, the devices should have separate CHIPID pin configurations. A write/read access can be made only on the Each AD6654 has four CHIPID pins that can be connected in intended chip; all other chips would ignore the access. 16 different ways. During a write/read access, the internal circuitry checks to see if the CHIPID bits in the chip I/O access control register (Address 0x02) are the same as the logic levels Rev. 0 | Page 71 of 88 AD6654 MEMORY MAP READING THE MEMORY MAP TABLE OPEN LOCATIONS Each row in the memory map table has four address locations. All locations marked as open are currently not used. When The memory map is roughly divided into four regions: global required, these locations should be written with 0s. Writing to register map (Address 0x00 to Address 0x0B), input port these locations is required only when part of an address location register map (Address 0x0C to Address 0x67), channel register is open (for example, Address 0x78). If the whole address map (Address 0x68 to Address 0xBB), and output port register location is open (for example, Address 0x00), then this address map (Address 0xBC to Address 0xE7). The channel register location does not need to be written. If the open locations are map is shared by all six channels, and access to individual read back using the microport or serial port, the readback value channels is given by the channel I/O access control register is undefined (each bit can be independently 1 or 0), and these (Address 0x02). bits have no significance. In the memory map in Table 28, the addresses are given in the If an address location has more than one register or has one right column. The column with the heading Byte 0 has the register with some open bits, then the order of these registers is address given in the right column. The column Byte 1 has the as given in Table 28. For example, Address 0x33 reads address given by 1 more than the address listed in the right Open <7:5>, Port A Signal Monitor <4:0>. column (address offset of 1). Similarly, the address offset for the Byte 2 column is 2, and for the Byte 3 column is 3. For example, The open <7:5> is located at Bits <7:5> and the Port A signal the second row lists 0x04 as the address in the right column. monitor <4:0> is located at Bits <4:0>. The pin synchronization configuration register has Address 0x04, the soft synchronization configuration register has Another example is Address 0x35: Address 0x05, and Address 0x06 and Address 0x07 are Open <15:10>, Port A Upper Threshold <9:0> reserved/open. Here, Bits <7:2> of Address 0x35 are open <15:10>. Bits <1:0> BIT FORMAT of Address 0x35 and Bits <7:0> of Address 0x34 make up the All registers are in little-endian format. For example, if a register Port A upper threshold <9:0> register (Bit 1 of Address 0x35 is takes 24 bits or three address locations, then the most signifi- the MSB of the Port A upper threshold register). cant byte is at the highest address location and the least significant byte is at a lowest address location. In all registers, DEFAULT VALUES the least significant bit is Bit 0 and the most significant bit is Coming out of reset, some of the address locations (but not all) Bit 7. For example, the NCO frequency <31:0> register is are loaded with default values. When available, the default 32 bits wide. Bit 0 (LSB) of this register is written at Bit 0 of values for the registers are given in the table. If the default value Address 0x70 and Bit 32 (MSB) of this register is written at is not listed, then the address location is in an undefined state Bit 7 of Address 0x73. RESET (Logic 0 or Logic 1) on . When referring to a register that takes up multiple address LOGIC LEVELS locations, it is referred to by the address location of the most In the explanation of various registers, “bit is set” is significant byte of the register. For example, the text reads, synonymous with “bit is set to Logic 1” or “writing Logic 1 for “Port A dwell timer at Address 0x2A.” Note that only the four the bit.” Similarly “clear a bit” is synonymous with “bit is set to most significant bits of this register are at this location, and this Logic 0” or “writing Logic 0 for the bit.” register also takes up Addresses 0x29 and 0x28. Rev. 0 | Page 72 of 88 AD6654 Table 28. Memory Map 8-Bit Hex 8-Bit Hex Address Byte 3 Byte 2 Byte 1 Byte 0 Address 0x03 Open <7:6>, Channel Open <7:6>, Channel I/O Chip I/O Access Control Open <7:0> 0x00 Enable <5:0> Access Control <5:0> <7:0> (default 0x00) 0x07 Open <15:11>, Reserved <10:0> (default 0x06FC) Soft Synchronization Pin Synchronization 0x04 Configuration <7:0> Configuration <7:0> 0x0B Interrupt Mask <15:0> Interrupt Status <15:0> (read only, default 0x00) 0x08 ADC Input Port Register Map— Addresses 0x0C to 0x57 0x0F ADC Input Control <31:0> 0x0C 0x13 Open <15:0> ADC CLK Control <15:0> (default 0x0000) 0x10 0x4B ADC Gain Control <7:0> Open <23:20>, ADC Dwell Timer <19:0> 0x48 0x4F Open <7:0> ADC Power Monitor Period <23:0> 0x4C 0x53 Open <7:5>, ADC Signal ADC Power Monitor Output <23:0> 0x50 Monitor <4:0> 0x57 Open <15:10>, ADC Lower Threshold <9:0> Open <15:10>, ADC Upper Threshold <9:0> 0x54 Channel Register Map—Addresses 0x68 to 0xBB 0x6B Open <15:0> Open <15:9>, NCO Control <8:0> 0x68 0x6F NCO Start Hold-Off Counter <15:0> NCO Frequency Hold-Off Counter <15:0> 0x6C 0x73 NCO Frequency <31:0> (default 0x0000 0000) 0x70 0x77 Open <15:0> NCO Phase Offset <15:0> (default 0x0000) 0x74 0x7B Open <7:1>, CIC Bypass <0> Open <7:5>, CIC Open <7:5>, CIC Scale Open <7:4>, FIR-HB 0x78 Decimation <4:0> Factor <4:0> Control <3:0> 0x7F Open <15:0> Open <15:13>, MRCF Control <12:0> 0x7C 0x83 Open <7:6>, MRCF Open <7:6>, MRCF Open <7:6>, MRCF Open <7:6>, MRCF 0x80 Coefficient 3 <5:0> Coefficient 2 <5:0> Coefficient 1 <5:0> Coefficient 0 <5:0> 0x87 Open <7:6>, MRCF Open <7:6>, MRCF Open <7:6>, MRCF Open <7:6>, MRCF 0x84 Coefficient 7 <5:0> Coefficient 6 <5:0> Coefficient 5 <5:0> Coefficient 4 <5:0> 0x8B Open <15:13>, DRCF Control Register <12:0> Open <7:6>, DRCF Open <7>, DRCF Taps 0x88 Coefficient Offset <5:0> <6:0> 0x8F Open <15:0> Open <7:6>, DRCF Final Open <7:6>, DRCF Start 0x8C Address <5:0> Address <5:0> 0x93 Open<15:0> Open<15:14>, DRCF Coefficient Memory <13:0> 0x90 0x97 Open <15:13>, CRCF Control Register <12:0> Open <7:6>, CRCF Open <7>, CRCF Taps 0x94 Coefficient Offset <5:0> <6:0> 0x9B Open <15:0> Open <7:6>, CRCF Final Open <7:6>, CRCF Start 0x98 Address <5:0> Address <5:0> 0x9F Open <7:0> Open <23:20>, CRCF Coefficient Memory <19:0> 0x9C 0xA3 Open <15:11>, AGC Control Register <10:0> AGC Hold-Off Register <15:0> 0xA0 0xA7 Open <15:12>, AGC Update Decimation <11:0> Open <15:12>, AGC Signal Gain <11:0> 0xA4 0xAB Open <15:12>, AGC Error Threshold <11:0> Open <7:6>, AGC Average AGC Pole Location <7:0> 0xA8 Samples <5:0> 0xAF Open <7:0> AGC Desired Level <7:0> AGC Loop Gain2 <7:0> AGC Loop Gain1 <7:0> 0xAC 0xB3 Open <7:0> BIST I Path Signature Register <23:0> (read only) 0xB0 0xB7 Open <7:0> BIST Q Path Signature Register <23:0> (read only) 0xB4 0xBB Open <15:0> BIST Control <15:0> 0xB8 Output Port Register Map—Addresses 0xBC to 0xE7 0xBF Open <7:0> Parallel Port Output Control <23:0> 0xBC 0xC3 Open <15:0> Open <15:10>, Output Port Control <9:0> 0xC0 0xC7 AGC0, I Output <15:0> (read only) AGC0, Q Output <15:0> (read only) 0xC4 0xCB AGC1, I Output <15:0> (read only) AGC1, Q Output <15:0> (read only) 0xC8 0xCF AGC2, I Output <15:0> (read only) AGC2, Q Output <15:0> (read only) 0xCC 0xD3 AGC3, I Output <15:0> (read only) AGC3, Q Output <15:0> (read only) 0xD0 0xD7 AGC4, I Output <15:0> (read only) AGC4, Q Output <15:0> (read only) 0xD4 0xDB AGC5, I Output <15:0> (read only) AGC5, Q Output <15:0> (read only) 0xD8 0xDF Open <15:12>, AGC0 RSSI Output <11:0> (read only) Open <15:12>, AGC1 RSSI Output <11:0> (read only) 0xDC 0xE3 Open <15:12>, AGC2 RSSI Output <11:0> (read only) Open <15:12>, AGC3 RSSI Output <11:0> (read only) 0xE0 0xE7 Open <15:12>, AGC4 RSSI Output <11:0> (read only) Open <15:12>, AGC5 RSSI Output <11:0> (read only) 0xE4 Rev. 0 | Page 73 of 88 AD6654 one channel has access, the read access is given to the channel GLOBAL REGISTER MAP with the lowest channel number. Chip I/O Access Control Register <7:0> <7>: Synchronous Microport Bit. When this bit is set, the For example, if both Channel 4 and Channel 2 have access bits W DS set, then read access is given to Channel 2. microport assumes that its control signals (such as R/ , , CS and ,) are synchronous to the CPUCLK. When cleared, Channel Enable Register <5:0> asynchronous control signals are assumed, and the microport <5>: Channel 5 Enable Bit. When this bit is set, Channel 5 logic control signals are resynchronized with CPUCLK inside the is enabled. When this bit is cleared, Channel 5 is disabled and AD6654 part. Synchronous microport (when bit is set) has the the channel’s logic does not consume any power. On power-up, advantage of requiring a fewer number of clock cycles for this bit comes up with Logic 0 and the channel is disabled. A read/write access. start sync does not start Channel 5, unless this bit is set before <6>: This bit is open. issuing the start sync. <5:2>: Chip ID Bits. The chip ID bits are used to compare <4>: Channel 4 Enable Bit. Similar to Bit <5> for Channel 4. against the chip ID input pins (CHIPID), enabling or disabling <3>: Channel 3 Enable Bit. Similar to Bit <5> for Channel 3. I/O access for this specific chip. When more than one AD6654 part is sharing the microport, different CHIPID pins can be <2>: Channel 2 Enable Bit. Similar to Bit <5> for Channel 2. used to differentiate among the parts. A particular part gives I/O access only when the CHIPID pins have the same value as <1>: Channel 1 Enable Bit. Similar to Bit <5> for Channel 1. these chip ID bits. <0>: Channel 0 Enable Bit. Similar to Bit <5> for Channel 0. <1>: This bit is open. Pin Synchronization Configuration <7:0> <0>: Byte Mode Bit. The byte mode bit selects the bit width for <7>: Hop Synchronization Enable Bit. This bit is a global enable the microport operation. Table 29 shows details. for any hop synchronization involving SYNC pins. When this Table 29. Microport Data Bus Width Selection bit is set, hop synchronization is enabled for all channels that are programmed for pin synchronization. When this bit is Chip Access Control Register <0> Microport Data Bus Bit Width cleared, hop synchronization is not performed for any channel 0 (default) 8-bit mode, using D <7:0> that is programmed for pin synchronization. 1 16-bit mode, using D <15:0> <6>: Start Synchronization Enable Bit. This bit is a global enable for any start synchronization involving SYNC pins. When this Channel I/O Access Control Register <5:0> bit is set, start synchronization is enabled for all channels that These bits enable/disable the channel I/O access capability. are programmed for pin synchronization. When this bit is cleared, start synchronization is not performed for any channel <5>: Channel 5 Access Bit. When the Channel 5 access bit is set that is programmed for pin synchronization. to Logic 1, any I/O write operation (from either the microport or the serial port) that addresses a register located within the <5>: First Sync Only Bit. When this bit is set, the NCO synchro- channel register map updates the Channel 5 registers. Similarly, nization logic recognizes only the first synchronization event as for a read operation, the contents of the desired address in the valid. All other requests for synchronization events are ignored channel register map are output when this bit is set to Logic 1. as long as this bit is set. When cleared, all synchronization events are acted upon. <4>: Channel 4 Access Bit. Similar to Bit <5> for Channel 4. <4>: Edge-Sensitivity Bit. When this bit is set, the rising edge on <3>: Channel 3 Access Bit. Similar to Bit <5> for Channel 3. the SYNC pin(s) is detected as a synchronization event (edge- <2>: Channel 2 Access Bit. Similar to Bit <5> for Channel 2. sensitive detection). When cleared, Logic 1 on the SYNC pin(s) is detected as a synchronization event (level-sensitive <1>: Channel 1 Access Bit. Similar to Bit <5> for Channel 1. detection). <0>: Channel 0 Access Bit. Similar to Bit <5> for Channel 0. <3>: Enable Synchronization from SYNC3 Bit. When this bit is set, the SYNC3 pin can be used for synchronization. When this Note: If the access bits are set for more than one channel, during bit is cleared, the SYNC3 pin is ignored. This is a global enable write access all channels with access are written with the same for all SYNC pins, and each individual channel selects which data. This is especially useful when more than one channel has pin it listens to. similar configurations. During a read operation, if more than Rev. 0 | Page 74 of 88 AD6654 <2>: Enable Synchronization from SYNC2 Bit. Similar to update interrupt enable bit is cleared, then this bit is not set (not Bit <3> for the SYNC2 pin. updated). An interrupt is not generated in this case. <1>: Enable Synchronization from SYNC1 Bit. Similar to Note: For Bits <15:10>, no interrupt is generated, if the new Bit <3> for the SYNC1 pin. RSSI word is the same as the previous RSSI word. <0>: Enable Synchronization from SYNC0 Bit. Similar to <14>: AGC4 RSSI Update Interrupt Bit. Similar to Bit <15> for Bit <3> for the SYNC0 pin. the AGC4. Soft Synchronization Configuration <7:0> <13>: AGC3 RSSI Update Interrupt Bit. Similar to Bit <15> for the AGC3. <7>: Soft Hop Synchronization Enable Bit. When this bit is set, hop synchronization is enabled for all channels selected using <12>: AGC2 RSSI Update Interrupt Bit. Similar to Bit <15> for Bit 5 through Bit 0. When this bit is cleared, hop synchroniza- the AGC2. tion is not performed for any channels selected using Bit 5 to Bit 0. <11>: AGC1 RSSI Update Interrupt Bit. Similar to Bit <15> for the AGC1. <6>: Soft Start Synchronization Enable Bit. When this bit is set, start synchronization is enabled for all channels selected using <10>: AGC0 RSSI Update Interrupt Bit. Similar to Bit <15> for Bit 5 through Bit 0. When this bit is cleared, start synchronization the AGC0. is not performed for any channels selected using Bit 5 to Bit 0. <9>: Channel 5 Data Ready Interrupt Bit. This bit is set to Bits <5:0> form the SOFT_SYNC control bits. These bits can be Logic 1 whenever the channel BIST signature registers are written to by the controller to initiate the synchronization of a loaded with data. The conditions required for setting this bit are selected channel. that the channel BIST signature registers are programmed for BIST signature generation and the Channel 5 data ready enable <5>: Soft Sync Channel 5 Enable Bit. When this bit is set, it bit in the interrupt enable register is cleared. If the Channel 5 enables Channel 5 to receive a hop sync or start sync, as defined data ready enable bit in the interrupt enable register is set, the by Bit 7 and Bit 6, respectively. When cleared, Channel 5 does AD6654 does not set this bit on signature generation and an not receive any soft sync. interrupt is not generated. <4>: Soft Sync Channel 4 Enable Bit. Similar to Bit <5> for <8>: Channel 4 Data Ready Interrupt Bit. Similar to Bit <9> for Channel 4. Channel 4. <3>: Soft Sync Channel 3 Enable Bit. Similar to Bit <5> for <7>: Channel 3 Data Ready Interrupt Bit. Similar to Bit <9> for Channel 3. Channel 3. <2>: Soft Sync Channel 2 Enable Bit. Similar to Bit <5> for <6>: Channel 2 Data Ready Interrupt Bit. Similar to Bit <9> for Channel 2. Channel 2. <1>: Soft Sync Channel 1 Enable Bit. Similar to Bit <5> for <5>: Channel 1 Data Ready Interrupt Bit. Similar to Bit <9> for Channel 1. Channel 1. <0>: Soft Sync Channel 0 Enable Bit. Similar to Bit <5> for <4>: Channel 0 Data Ready Interrupt Bit. Similar to Bit <9> for Channel 0. Channel 0. <10:0>: Reserved. <3>: Reserved. This bit must be written with Logic 0. <10:9>: Reserved. This bit must be written with Logic 1. <2>: ADC Port Power Monitoring Interrupt Bit. This bit is set by the AD6654 whenever the ADC port power monitor <8:0>: Reserved. This bit must be written with Logic 0. interrupt enable bit is set and the ADC port power monitor Interrupt Status Register <15:0> timer runs out (end of the ADC port power monitor period). If the ADC port power monitor interrupt enable bit is cleared, the This register is read only. AD6654 does not set this bit and does not generate an interrupt. <15>: AGC5 RSSI Update Interrupt Bit. If the AGC5 update <1>: Reserved. This bit must be written with Logic 0. interrupt enable bit is set, this bit is set by the AD6654 whenever AGC5 updates a new RSSI word (the new word <0>: Reserved. This bit must be written with Logic 0. should be different from the previous word). If the AGC5 Rev. 0 | Page 75 of 88 AD6654 Interrupt Enable Register <15:0> INPUT PORT REGISTER MAP <15>: AGC5 RSSI Update Enable Bit. When this bit is set, the ADC Input Control Register <27:0> AGC5 RSSI update interrupt is enabled, allowing an interrupt These bits are general control bits for the ADC input logic. to be generated when the RSSI word is updated. <27>: PN Active Bit. When this bit is set, the pseudorandom When this bit is cleared, an interrupt cannot be generated for number generator is active. When this bit is cleared, the PN this event. Also, see the Interrupt Status Register <15:0> section. generator is disabled and the seed is set to its default value. <14>: AGC4 RSSI Update Enable Bit. Similar to Bit <15> for <26>: EXP Lock Bit. When this bit is set along with the PN the AGC4. active bit, then the EXP signal for pseudorandom input is <13>: AGC3 RSSI Update Enable Bit. Similar to Bit <15> for locked to 000 (giving full-scale input). When this bit is cleared, the AGC3. EXP bits for pseudorandom input are randomly generated input data bits. <12>: AGC2 RSSI Update Enable Bit. Similar to Bit <15> for the AGC2. <25> Reserved. This bit must be written with Logic 0. <11>: AGC1 RSSI Update Enable Bit. Similar to Bit <15> for <24> Reserved. This bit must be written with Logic 0. the AGC1. <23:20>: Channel 5 Cross Bar Mux Select Bits. These bits select <10>: AGC0 RSSI Update Enable Bit. Similar to Bit <15> for the source of input data for Channel 5. See Table 30. the AGC0. Table 30. Input Data Source Selection Cross Bar Mux Select Bits Configuration <9>: Channel 5 Data Ready Enable Bit. When this bit is set, the 0010 ADC port drives input (real) Channel 5 data ready interrupt is enabled, allowing an interrupt 0100 PN sequence drives input (real) to be generated when Channel 5 BIST signature registers are updated. When this bit is cleared, an interrupt cannot be <19>: Reserved. This bit must be written with Logic 0. generated for this event. <18:16>: Channel 4 Cross Bar Mux Select Bits. Similar to bits <8>: Channel 4 Data Ready Enable Bit. Similar to Bit <9> for <22:20>, but for Channel 4. Channel 4. <15>: Reserved. This bit must be written with Logic 0. <7>: Channel 3 Data Ready Enable Bit. Similar to Bit <9> for <14:12>: Channel 3 Cross Bar Mux Select Bits. Similar to Channel 3. Bits <22:20> for Channel 3. <6>: Channel 2 Data Ready Enable Bit. Similar to Bit <9> for <11>: Reserved. This bit must be written with Logic 0. Channel 2. <10:8>: Channel 2 Cross Bar Mux Select Bits. Similar to <5>: Channel 1 Data Ready Enable Bit. Similar to Bit <9> for Bits <22:20> for Channel 2. Channel 1. <7>: Reserved. This bit must be written with Logic 0. <4>: Channel 0 Data Ready Enable Bit. Similar to Bit <9> for Channel 0. <6:4>: Channel 1 Cross Bar Mux Select Bits. Similar to Bits <22:20> for Channel 1. <3>: Reserved. This bit must be written with Logic 0. <3>: Reserved. This bit must be written with Logic 0. <2>: ADC Port Power Monitoring Enable Bit. When this bit is set to Logic 1, the ADC port power monitoring interrupt is <2:0>: Channel 0 Cross Bar Mux Select Bits. Similar to enabled, allowing an interrupt to be generated when ADC port Bits <22:20> for Channel 0. power monitoring registers are updated. When set to Logic 1, the ADC port power monitoring interrupt is disabled. ADC CLK Control Register <11:0>. These bits control the ADC clocks and internal PLL clock. <1>: Reserved. This bit must be written with Logic 0. <11>: Reserved. This bit must be written with Logic 0. <0>: Reserved. This bit must be written with Logic 0. Rev. 0 | Page 76 of 88 AD6654 <10>: ADC Port CLK Invert Bit. When this bit is set, the ADC Port Power Monitor Period <23:0> inverted ADC port clock is used to register ADC input data into This register is used in the power monitoring logic to set the the part. When this bit is cleared, the clock is used as is, without period of time for which ADC input data is monitored. This any inversion or phase change. value represents the monitor period in number of ADC port clock cycles. <9>: Reserved. This bit must be written with Logic 0. ADC Port Power Monitor Output <23:0> <8>: Reserved. This bit must be written with Logic 0. This register is read only and contains the current status of the <7:6>: ADC Pre PLL Clock Divider Bits.: These bits control the power monitoring logic output. The output is dependent on the PLL clock divider. The PLL clock is derived from the ADC data power monitoring mode selected. When the power monitor port CLK. block is enabled, this register is updated at the end of each Table 31. Divide-by Values for PLL Clock Divider Bits power monitor period. This register is updated even if an PLL Clock Divider Bits <12:11> Divide-by Value interrupt signal is not generated. 00 Divide by 1, bypass 01 Divide by 2 ADC Port Upper Threshold <9:0> 10 Divide by 4 This register serves the dual purpose of specifying the upper 11 Divide by 8 threshold value in the gain control block and in the power <5:1>: PLL Clock Multiplier Bits. These bits control the PLL monitoring block, depending on which block is active. ADC clock multiplier. The output of the PLL clock divider is port input data having a magnitude greater than this value multiplied with the binary value of these bits. Valid range for triggers a gain change in the gain control block. ADC port input the multiplier is from 4 to 20. A value outside this range powers data having a magnitude greater than this value is monitored in down the PLL, resulting in the PLL clock being the same as the the power monitoring block (in peak detect or threshold ADC data port CLK. crossing mode). The value of the register is compared with the absolute magnitude of the input port data. <0>: This bit is open. ADC Port Lower Threshold <9:0> ADC Port Gain Control <7:0> This register is used in the gain control block and represents the <7>: This bit is open. magnitude of the lower threshold for ADC port input data. Any <6:1>: This 6-bit word specifies the relinearization pipe delay to ADC input data having a magnitude below the lower threshold be used in the ADC input gain control block. The decimal initiates the dwell time counter. The value of the register is representation of these bits is the number of input clock cycle compared with the absolute magnitude of the input port data. pipeline delays between the external EXP data output and the ADC Port Signal Monitor <4:0> internal application of relinearization based on EXP. This register controls the functions of the power monitoring <0>: Gain Control Enable Bit. This bit controls the configura- block. tion of the EXP<2:0> bits for the ADC input port. When the gain control enable bit is Logic 1, the EXP<2:0> bits are <4>: Disable Power Monitor Period Timer Bit. When this bit is configured as outputs. When this bit is cleared, the EXP<2:0> set, the power monitor period timer no longer controls the bits are inputs. update of the power monitor holding register. A user read to the power monitor holding register updates this register. When this ADC Port Dwell Timer <19:0> bit is cleared, the power monitor period register controls the This register is used to set the dwell time for the gain control timer and, therefore, controls the update rate of the power block. When the gain control block is active and detects a monitor holding register. decrease in the signal level below the lower threshold value <3>: Clear-on-Read Bit. When this bit is set, the power monitor (programmable), a dwell-time counter is initiated to provide holding register is cleared every time this register is read. This temporal hysteresis. Doing so prevents the gain from being bit controls whether the power monitoring function is cleared continuously switched. Note that the dwell timer is turned on after a read of the power monitor period register. If this bit is only after a drop below the lower threshold is detected in the set, the monitoring function is cleared after the read. If this bit signal level. is Logic 0, the monitoring function is not cleared. This bit is a don’t care bit, if the disable integration counter bit is cleared. Rev. 0 | Page 77 of 88 AD6654 <2:1>: Monitor Function Select Bits. Table 32 describes the bit is cleared, the accumulator is not cleared and phase function of these bits. continuous hops are implemented. Table 32. Monitor Function Select Bits <1>: Phase Dither Enable Bit. When this bit is set, phase Monitor Function Select Function Enabled dithering in the NCO is enabled. When this bit is cleared, phase 00 Peak detect mode dithering is disabled. 01 Mean power monitor mode <0>: Amplitude Dither Enable Bit. When this bit is set, 10 Threshold crossing mode amplitude dithering in the NCO is enabled. When this bit is 11 Invalid selection cleared, amplitude dithering is disabled. <0>: Monitor Enable Bit. When this bit is set, the power Channel Start Hold-Off Counter <15:0> monitoring function is enabled and operates as selected by Bit 2 to Bit 1 of the signal monitor register. When this bit is cleared, When a start synchronization (software or hardware) occurs on the power monitoring function is disabled and the signal the channel, the value in this register is loaded into a down- monitor register bits <2:1> are don’t care bits. These bits default counter. When the counter has finished counting down to 0, the to 0 on power-up. channel operation is started. CHANNEL REGISTER MAP NCO Frequency Hop Hold-Off Counter <15:0> Channel control registers are common to all six channels, and When a hop sync occurs, a counter is loaded with the NCO access to specific channels is determined by the channel I/O frequency hold-off register value. The 16-bit counter starts access register (Address 0x02). counting down. When it reaches 0, the new frequency value in the shadow register is written to the NCO frequency register. NCO Control <15:0> (See the NCO Frequency Hold-Off Register section.) These bits control the NCO operation. NCO Frequency <31:0> <8:7>: NCO Sync Start Select Bits. These bits determine which The value in this register is used to program the NCO tuning SYNC input pin is used by this channel for a start synchroniza- frequency. The value to be programmed is given by the tion operation. Table 33 describes the selection. following equation: Table 33. Sync Start Select Bits NCO _ FREQUENCY 32 NCO Frequency Register= × 2 SYNC Pin Used for Start CLK NCO Control <8:7> Synchronization 00 SYNC0 where: 01 SYNC1 NCO_FREQUENCY is the desired NCO tuning frequency. 10 SYNC2 CLK is the ADC clock rate. 11 SYNC3 The value given by the equation should be loaded into the <6:5>: NCO Sync Hop Select Bits. These bits determine which register in binary format. SYNC input pin is used by this channel for a hop synchroniza- tion operation. Table 34 describes the selection. NCO Phase Offset <15:0> Table 34. Sync Hop Select Bits The value in the register is loaded into the phase accumulator of SYNC Pin Used for Hop the NCO block every time a start sync or hop sync is received NCO Control <6:5> Synchronization by the channel. This allows individual channels to be started 00 SYNC0 with a known nonzero phase. The NCO phase offset is not 01 SYNC1 loaded on a hop sync, if Bit <2> of the NCO control register 10 SYNC2 (clear phase accumulator on hop) is cleared. This NCO offset 11 SYNC3 register value is interpreted as a 16-bit unsigned integer. A <4>: This bit is open. 0x0000 in this register corresponds to a 0 radian offset, and a 16 0xFFFF corresponds to an offset of 2π (1 − 1/(2 )) radians. <3>: NCO Bypass Bit. When this bit is set, the NCO is bypassed and shuts down for power savings. This bit can be used for CIC Bypass <0> power savings, when NCO frequency of dc or 0 Hz is required. When this bit is set, the entire CIC filter is bypassed. The output When this bit is cleared, the NCO operates as programmed. of CIC filter is driven straight from the input without any change. When this bit is cleared, the CIC filter operates in <2>: Clear NCO Accumulator Bit. When this bit is set, the clear normal mode as programmed. Writing Logic 1 to this bit NCO accumulator bit synchronously clears the phase disables both the CIC decimation and CIC scaling operations. accumulator on all frequency hops in this channel. When this Rev. 0 | Page 78 of 88 AD6654 <8>: This bit is open. CIC Decimation <4:0> This 5-bit word specifies the CIC filter decimation value <7>: Half-Rate Bit. When this bit is set, the MRCF filter minus 1. A value of 0x00 is a decimation of 1 (bypass), and operates using half the PLL clock rate. This is used for power 0x1F is a decimation of 32. Writing a value of 0 in this register savings when there is sufficient time to complete MRCF bypasses CIC filtering, but does not bypass the CIC scaling filtering using only half the PLL clock rate. When this bit is operation. cleared, the MRCF filter operates at the full PLL clock rate. See the Mono-Rate RAM Coefficient Filter (MRCF) section. CIC Scale Factor <4:0> <6:4>: MRCF Number of Taps Bits. This 3-bit word should be This 5-bit word specifies the CIC filter scale factor used to written with one less than the number of taps that are calculated compensate for the gain provided by the CIC filter. The by the MRCF filter. The filter length is given by the decimal recommended value is given by the following equation: value of this register plus 1. A value of 0 represents a 1-tap filter CIC ScaleRegister=ceil(5× log (M ))− 5 2 CIC and maximum value of 7 represents an 8-tap filter. where: <3:2>: MRCF Scale Factor Bits. The output of the MRCF filter is scaled according to the value of these bits. Table 36 describes MCIC is the decimation rate of the CIC (one more than the value the attenuation corresponding to each setting. in the CIC decimation register). Table 36. MRCF Scale Factor ceil operation gives the closest integer greater than or equal to MRCF Scale<1:0> Scale Factor the argument. 00 18.06 dB attenuation (left-shift 3 bits) The valid range for this register is decimal 0 to 20. 01 12.04 dB attenuation (left-shift 2 bits) 10 6.02 dB attenuation (left-shift 1 bit) FIR-HB Control <3:0> 11 No scaling (0 dB) <3>: FIR1 Enable Bit. When this bit is set, the FIR1 fixed <1>: This bit is open. coefficient filter is enabled. When cleared, FIR1 is bypassed. <0>: MRCF Bypass Bit. When this bit is set, the MRCF filter is <2>: HB1 Enable Bit. When this bit is set, the HB1 half-band bypassed and, therefore, the output of the MRCF is the same as filter is enabled. When cleared, HB1 is bypassed. its input. When this bit is cleared, the MRCF has normal <1>: FIR2 Enable Bit. When this bit is set, the FIR2 fixed operation as programmed by its control register. coefficient filter is enabled. When cleared, FIR2 is bypassed. MRCF COEFFICIENT MEMORY <0>: HB2 Enable Bit. When this bit is set, the HB2 half-band The MRCF coefficient memory consists of eight coefficients, filter is enabled. When cleared, HB2 is bypassed. each six bits wide. The memory extends from Address 0x80 to Address 0x87. The coefficients should be written in twos MRCF Control Register <12:0> complement format. <12:10>: MRCF Data Select Bits. These bits are used to select the input source for the MRCF filter. Each MRCF filter can be DRCF Control Register <11:0> driven by output from the HB2 filter of any channel independ- <11>: DRCF Bypass Bit. When this bit is set, the DRCF filter is ently. Table 35 shows the selections available. bypassed and, therefore, its output is the same as its input. Table 35. MRCF Data Select Bits When this bit is cleared, the DRCF has normal operation as MRCF Data Select<2:0> MRCF Input Source programmed by the rest of this control register. 000 MRCF input taken from Channel 0 <10>: Symmetry Bit. When this bit is set, it indicates that the 001 MRCF input taken from Channel 1 DRCF is implementing a symmetrical filter and only half the 010 MRCF input taken from Channel 2 impulse response needs to be written into the DRCF coefficient 011 MRCF input taken from Channel 3 RAM. When this bit is cleared, the filter is asymmetrical and 1x0 MRCF input taken from Channel 4 complete impulse response of the filter should be written to the 1x1 MRCF input taken from Channel 5 coefficient RAM. When this filter is symmetrical, it can imple- <9>: Interpolating Half-Band Enable Bit. When this bit is set, ment up to 128 filter taps. the interpolating half-band filter, driven by the output of the <9:8>: DRCF Multiply Accumulate Scale Bits. The output of the CRCF block, is enabled. When cleared, the interpolating half- band filter is bypassed, and its output is the same as its input. DRCF filter is scaled according to the value of these bits. The interpolating half-band filter doubles the data rate. Table 37 lists the attenuation corresponding to each setting. Rev. 0 | Page 79 of 88 AD6654 Table 37. DRCF Multiply Accumulate Scale Bits CRCF Control Register <11:0> DRCF Scale <1:0> Scale Factor <11>: CRCF Bypass Bit. When this bit is set, the DRCF filter is 00 18.06 dB attenuation (left-shift 3 bits) bypassed and, therefore, its output is the same as its input. 01 12.04 dB attenuation (left-shift 2 bits) When this bit is cleared, the CRCF has normal operation as 10 6.02 dB attenuation (left-shift 1 bit) programmed by its control register. 11 No scaling (0 dB) <10>: Symmetry Bit. When this bit is set, it indicates that the <7:4>: DRCF Decimation Rate. This 4-bit word should be CRCF is implementing a symmetrical filter and only half the written with one less than the decimation rate of the DRCF impulse response needs to be written into the CRCF coefficient filter. A value of 0 represents a decimation rate of 1 (no rate RAM. When this bit is cleared, the filter is asymmetrical and change), and the maximum value of 15 represents a decimation the complete impulse response of the filter should be written of 16. Filtering can be implemented regardless of the into the coefficient RAM. When this filter is symmetrical, it can decimation rate. implement up to 128 filter taps. <3:0>: DRCF Decimation Phase Bits. This 4-bit word represents <9:8>: CRCF Multiply Accumulate Scale Bits. The output of the the decimation phase used by the DRCF filter. The valid range CRCF filter is scaled according to the value of these bits. is 0 up to MDRCF − 1, where MDRCF is the decimation rate of the Table 38 lists the attenuation corresponding to each setting. DRCF filter. This word is primarily used for synchronization of Table 38. CRCF Multiply Accumulate Scale Bits multiple channels of the AD6654, when more than one channel CRCF Scale<1:0> Scale Factor is used for filtering one signal (one carrier). 00 18.06 dB attenuation (left-shift 3 bits) DRCF Coefficient Offset <7:0> 01 12.04 dB attenuation (left-shift 2 bits) 10 6.02 dB attenuation (left-shift 1 bit) This register is used to specify which section of the 64-word 11 No scaling (0 dB) coefficient memory is used for a filter. It can be used to select between multiple filters that are loaded into memory and <7:4>: CRCF Decimation Rate. This 4-bit word should be writ- referenced by this pointer. This register is shadowed, and the ten with one less than the decimation rate of the CRCF filter. A filter pointer is updated every time a new filter is started. This value of 0 represents a decimation rate of 1 (no rate change) and allows the coefficient offset to be written even while a filter is the maximum value of 15 represents a decimation of 16. being computed without disturbing operation. The next sample Filtering operation is done regardless of the decimation rate. comes out of the DRCF with the new filter. <3:0>: CRCF Decimation Phase. This 4-bit word represents the DRCF Taps <6:0> decimation phase used by the CRCF filter. The valid range is 0 This register is written with one less than the number of taps to MCRCF − 1, where MCRCF is the decimation rate of the that are calculated by the DRCF filter. The filter length is given CRCF filter. This word is primarily used for synchronization of by the decimal value of this register plus 1. A value of 0 multiple channels of the AD6654, when more than one channel represents a 1-tap filter, and a value of 0x28 (40 decimal) is used for filtering one signal (one carrier). represents a 41-tap filter. CRCF Coefficient Offset <5:0> DRCF Start Address <5:0> This register is used to specify which section of the 64-word This register is written with the starting address of the DRCF coefficient memory is used for a filter. It can be used to select coefficient memory to be updated. between multiple filters that are loaded into memory and referenced by this pointer. This register is shadowed, and the DRCF Final Address <5:0> filter pointer is updated every time a new filter is started. This allows the coefficient offset to be written even while a filter is This register is written with the ending address of the DRCF being computed without disturbing operation. The next sample coefficient memory to be updated. comes out of the CRCF with the new filter. DRCF Coefficient Memory <13:0> CRCF Taps <6:0> DRCF Memory. This memory consists of 64 words, and each This register is written with one less than the number of taps word is 14 bits wide. The data written to this memory space is that are calculated by the CRCF filter. The filter length is given expected to be 14-bit, twos complement format. See the by the decimal value of this register plus 1. A value of 0 repre- Decimating RAM Coefficient Filter (DRCF) section for the sents a 1-tap filter, and a value of 0x28 (40 decimal) represents a method to program the coefficients into the coefficient 41-tap filter. memory. Rev. 0 | Page 80 of 88 AD6654 When Bit 2 = 0, the above-mentioned parameters are not CRCF Coefficient Memory updated, and the CIC filter is not cleared. In both cases, an CRCF Memory. This memory has 64 words that have 20 bits AGC update sample is output from the CIC filter and the each. The memory contains the CRCF filter coefficients. The decimator starts operating towards the next output sample data written to this memory space is 20-bit in twos complement whenever a sync occurs. format. See the Channel RAM Coefficient Filter (CRCF) section for the method to program the coefficients into the coefficient <1>: First Sync Only. This bit is used to ignore repetitive memory. synchronization signals. In some applications, the synchroniza- tion signal occurs periodically. If this bit is cleared, each AGC Control Register <10:0> synchronization request resynchronizes the AGC. If this bit is <10>: Channel Sync Select Bit. When this bit is set, the AGC set, only the first occurrence causes the AGC to synchronize uses the sync signal from the channel for its synchronization. and updates the AGC gain values periodically, depending on When this bit is cleared, the SYNC pin used for synchronization the decimation factor of the AGC CIC filter. is defined by Bit 9 to Bit 8 of this register. <0>: AGC Bypass Bit. When this bit is set, the AGC section is <9:8>: SYNC Pin Select Bits. When Bit 10 of this register is bypassed. The N-bit representation from the interpolating half- cleared, these bits specify the SYNC pin used by AGC for band filters is still reduced to a lower bit width representation as synchronization. These bits are don’t care when Bit 10 of the set by Bit 7 to Bit 5 of the AGC control register. A truncation at AGC control register is set to Logic 1. the output of the AGC accomplishes this task. Table 39. SYNC Pin Select Bits AGC Hold-Off Register <15:0> AGC Control Bits <9:8> SYNC Pin Used by AGC The AGC hold-off counter is loaded with the value written to 00 SYNC0 this address when either a soft sync or pin sync comes into the 01 SYNC1 channel. The counter begins counting down. When it reaches 1, 10 SYNC2 a sync is sent to the AGC. This sync might or might not initial- 11 SYNC3 ize the AGC, as defined by the control word. The AGC loop is <7:5>: AGC Word Length Control Bits. These bits define the updated with a new sample from the CIC filter whenever a sync word length of the AGC output. The output word can be 4 to 8, occurs. If this register is Logic 1, the AGC is immediately 10, 12, or 16 bits wide. Table 40 shows the possible selections. updated when the sync occurs. If this register is Logic 0, the AGC cannot be synchronized. Table 40. AGC Word Length Control Bits AGC Control Bits <7:5> Output Word Length (Bits) AGC Update Decimation <11:0> 000 16 This 12-bit register sets the AGC decimation ratio from 1 to 001 12 4096. An appropriate scaling factor should be set to avoid loss 010 10 of bits. The decimation ratio is given by the decimal value of the 011 8 AGC update decimation<11:0> register contents plus 1, that is, 100 7 12’0x000 describes a decimation ratio of 1, and 12’0xFFF 101 6 describes a decimation ratio of 4096. 110 5 111 4 AGC Signal Gain <11:0> <4>: AGC Mode Bit. When this bit is cleared, the AGC operates This register is used to set the initial value for a signal gain used to maintain a desired signal level. When this bit is set, it in the gain multiplier. This 12-bit value sets the initial signal operates to maintain a constant clipping level. See the gain in the range of 0 dB and 96.296 dB in steps of 0.024 dB. Automatic Gain Control section for details about these modes. Initial signal gain (SG) in dB should be converted to a register setting using the following formula: <3>: AGC Sync Now Bit. This bit is used to synchronize a particular AGC, regardless of the channel, through the ⎡ ⎤ SG programming ports (microport or serial port). When this bit is RegisterValue=round × 256 ⎢ ⎥ 20 log (2) set, the AGC block updates a new output sample (RSSI sample) ⎣ 10 ⎦ and starts working toward a new update sample. AGC Error Threshold <11:0> <2>: Initialize on Sync Bit. This bit is used to determine This 12-bit register is the comparison value used to determine whether or not the AGC should initialize on a sync. When this which loop gain value (K1 or K2) to use for optimum operation. bit is set, during a synchronization the CIC filter is cleared and When the magnitude-of-error signal is less than the AGC error new values for CIC decimation, number of averaging samples, threshold value, then K1 is used; otherwise, K2 is used. The word CIC scale, Signal Gain K, and the Pole P parameter are loaded. Rev. 0 | Page 81 of 88 AD6654 format of the AGC error threshold register is four bits to the left AGC Loop Gain 1 <7:0> of the binary point and eight bits to the right. This 8-bit register is used to define K1, the open-loop gain. Its value can be set from 0 to 0.996 in steps of 0.0039. This value of See the Automatic Gain Control section for details. K is updated in the AGC loop each time the AGC is initialized. When the magnitude-of-error signal in the loop is less than the ⎡ Error Threshold⎤ Register Value= round ×256 ⎢ ⎥ AGC error threshold, then K is used by the loop. K is updated 1 1 20 log (2) ⎢ ⎥ 10 ⎣ ⎦ only when the AGC is initialized. AGC Average Samples <5:0> I Path Signature Register <15:0> This 6-bit register contains the scale used for the CIC filter and This 16-bit signature register is for the I path of the channel the number of power samples to be averaged before being sent logic. The signature register records data on the networks that to the CIC filter. leave the channel logic, just before entering the second data router. <5:2>: CIC Scale. This 4-bit word defines the scale used for the CIC filter. Each increment of this word increases the CIC scale Q Path Signature Register <15:0> by 6.02 dB. This 16-bit signature register is for the Q path of the channel <1:0>: Number of AGC Average Samples. This defines the logic. The signature register records data on the networks that number of samples to be averaged before they are sent to the leave the channel logic, just before entering the second data CIC decimating filter. See Table 41. router. Table 41. Number of AGC Average Samples BIST Control <15:0> AGC Average Samples <1:0> Number of Samples Taken <15>: Disable Signature Generation Bit. When this bit is active 00 1 high, the signature registers do not produce a pseudorandom 01 2 output value, but instead directly load the 24-bit input data. 10 3 When this bit is cleared, the signature register produces a 11 4 pseudorandom output for every clock cycle that it is active. See the User-Configurable Built-In Self-Test (BIST) section for details. AGC Pole Location <7:0> This 8-bit register is used to define P, the open-loop filter pole <14:0>: BIST Timer Bits. The <14:0> bits of this register form a location. Its value can be set from 0 to 0.996 in steps of 0.0039. 15-bit word that is loaded into the BIST timer. After loading the BIST timer, the signature register is enabled for operation while This value of P is updated in the AGC loop each time the AGC the timer is actively counting down. See the User-Configurable is initialized. This open-loop pole location directly impacts the Built-In Self-Test (BIST) section for details. closed-loop pole locations, as explained in the Automatic Gain Control section. OUTPUT PORT REGISTER MAP AGC Desired Level <7:0> This part of the memory map deals with the output data and This register contains the desired signal level or desired clipping controls for parallel output ports. level, depending on operational mode. This desired request Parallel Port Output Control <23:0> level (R) can be set in dB from 0 to 23.99 in steps of 0.094 dB. The request level (R) in dB should be converted to a register <23>: Port C Append RSSI Bit. When this bit is set, an RSSI setting using the following formula: word is appended to every I/Q output sample, regardless of whether the RSSI word is updated in the AGC. When this bit is ⎡ ⎤ R cleared, an RSSI word is appended to an I/Q output sample only Register Value= round × 64 ⎢ ⎥ when the RSSI word is updated. The RSSI word is not output for 20 log (2) ⎢ 10 ⎥ ⎣ ⎦ subsequent I/Q samples until the next time the RSSI is updated AGC Loop Gain 2 <7:0> in the AGC. This 8-bit register is used to define K2, the second possible <22>: Port C, Data Format Bit. When this bit is set, the port is open-loop gain. Its value can be set from 0 to 0.996 in steps of configured for 8-bit parallel I/Q mode. When cleared, the port 0.0039. This value of K2 is updated each time the AGC is is configured for 16-bit interleaved I/Q mode. See the Parallel initialized. When the magnitude-of-error signal in the loop is Port Output section for details. greater than the AGC error threshold, then K is used by the 2 loop. K is updated only when the AGC is initialized. <21>: Port C, AGC5 Enable Bit. When this bit is set, AGC5 2 data (I/Q data) is output on parallel Output Port C (data bus). Rev. 0 | Page 82 of 88 AD6654 When this bit is cleared, AGC5 data does not appear on Output <3>: Port A, AGC3 Enable Bit. Similar to Bit 5 for AGC3. Port C. <2>: Port A, AGC2 Enable Bit. Similar to Bit 5 for AGC2. <20>: Port C, AGC4 Enable Bit. Similar to Bit 21 for AGC4. <1>: Port A, AGC1 Enable Bit. Similar to Bit 5 for AGC1. <19>: Port C, AGC3 Enable Bit. Similar to Bit 21 for AGC3. <0>: Port A, AGC0 Enable Bit. Similar to Bit 5 for AGC0. <18>: Port C, AGC2 Enable Bit. Similar to Bit 21 for AGC2. Output Port Control <9:0> <17>: Port C, AGC1 Enable Bit. Similar to Bit 21 for AGC1. <9:8>: PCLK Divisor Bits. When a parallel port is in master mode, the PCLK is derived from the PLL_CLK. These bits <16>: Port C, AGC0 Enable Bit. Similar to Bit 21 for AGC0. define the value of the divisor used to divide the PLL_CLK to obtain the PCLK. These bits are don’t care in slave mode. <15>: Port B Append RSSI Bit. When this bit is set, an RSSI word is appended to every I/Q output sample, regardless of Table 42. PCLK Divisor Bits whether the RSSI word is updated in the AGC. When this bit is PCLK Divisor <7:6> Divisor Value cleared, an RSSI word is appended to an I/Q output sample only 00 1 when the RSSI word is updated. The RSSI word is not output for 01 2 subsequent I/Q samples until the next time the RSSI is updated 10 4 in the AGC. 11 8 <14>: Port B, Data Format Bit. When this bit is set, the port is <7>: PCLK Master Mode Bit. When the PCLK master mode bit configured for 8-bit parallel I/Q mode. When this bit is cleared, is set, the PCLK pin is configured as an output and the PCLK is the port is configured for 16-bit interleaved I/Q mode. See the driven by the PLL_CLK. Data is transferred out of the AD6654 Parallel Port Output section. synchronous to this output clock. When this bit is cleared, the PCLK pin is configured as an input. The user is required to <13>: Port B, AGC5 Enable Bit. When this bit is set, AGC5 data provide a PCLK, and data is transferred out of the AD6654 (I/Q data) is output on Parallel Output Port A (data bus). When synchronous to this input clock. On power-up, this bit is cleared this bit is cleared, AGC5 data does not appear on Output Port to avoid contention on the PCLK pin. C. <6:4>: Reserved. These bits must be written with Logic 0. <12>: Port B, AGC4 Enable Bit. Similar to Bit 13 for AGC4. <3:0>: Stream Control Bits. These bits are described in Table 43. <11>: Port B, AGC3 Enable Bit. Similar to Bit 13 for AGC3. Table 43. Stream Control Bits <10>: Port B, AGC2 Enable Bit. Similar to Bit 13 for AGC2. Stream Control Output Streams (str0, str1, str2, Number of <9>: Port B, AGC1 Enable Bit. Similar to Bit 13 for AGC1. Bits str3, str4, str5) Streams 0000 Ch 0 and Ch 1 combined; Ch 2, Ch 3, 5 <8>: Port B, AGC0 Enable Bit. Similar to Bit 13 for AGC0. Ch 4, Ch 5 independent 0001 Ch 0, Ch 1, Ch 2 combined; Ch 3, Ch 4, 4 <7>: Port A Appended RSSI Bit. When this bit is set, an RSSI Ch 5 independent word is append to every I/Q output sample, regardless of 0010 Ch 0, Ch 1, Ch 2, Ch 3 combined; Ch 4, 3 whether the RSSI word is updated in the AGC. When this bit is Ch 5 independent cleared, an RSSI word is appended to an I/Q output sample only 0011 Ch 0, Ch 1, Ch 2, Ch 3, Ch 4 combined; 2 when the RSSI word is updated. The RSSI word is not output for Ch 5 independent subsequent I/Q samples until the next time RSSI is updated 0100 Ch 0, Ch 1, Ch 2, Ch 3, Ch 4, Ch 5 1 again in the AGC. combined 0101 Ch 0, Ch 1, Ch 2 combined; Ch 3, Ch 4, 2 <6>: Port A, Data Format Bit. When this bit is set, the port is Ch 5 combined configured for 8-bit parallel I/Q mode. When this bit is cleared, 0110 Ch 0, Ch 1 combined; Ch 2, Ch 3 3 the port is configured for 16-bit interleaved I/Q mode. See the combined; Ch 4, Ch 5 combined Parallel Port Output section. 0111 Ch 0, Ch 1 combined; Ch 2, Ch 3 4 combined; Ch 4, Ch 5 independent <5>: Port A, AGC5 Enable Bit. When this bit is set, AGC5 data 1000 Ch 0, Ch 1 , Ch 2 combined; Ch 3, Ch 4 3 (I/Q data) is output on parallel output Port A (data bus). When combined; Ch 5 independent this bit is cleared, AGC5 data does not appear on output Port C. 1001 Ch 0, Ch 1, Ch 2, Ch 3 combined; Ch 4, 2 Ch 5 combined. <4>: Port A, AGC4 Enable Bit. Similar to Bit 5 for AGC4. Default Independent channels 6 Rev. 0 | Page 83 of 88 AD6654 AGC0, I Output <15:0> AGC4, Q Output <15:0> This read-only register provides the latest in-phase output This read-only register provides the latest quadrature-phase sample from AGC0. Note that AGC0 might be bypassed, and output sample from AGC4. Note that AGC4 might be bypassed that AGC0 here is representative of the datapath only. and that AGC4 here is representative of the datapath only. AGC0, Q Output <15:0> AGC5, I Output <15:0> This read-only register provides the latest quadrature-phase This read-only register provides the latest in-phase output output sample from AGC0. Note that AGC0 might be bypassed, sample from AGC5. Note that AGC5 might be bypassed and and that AGC0 here is representative of the datapath only. that AGC5 here is representative of the datapath only. AGC1, I Output <15:0> AGC5, Q Output <15:0> This read-only register provides the latest in-phase output This read-only register provides the latest quadrature-phase sample from AGC1. Note that AGC1 might be bypassed and output sample from AGC5. Note that AGC5 might be bypassed that AGC1 here is representative of the datapath only. and that AGC5 here is representative of the datapath only. AGC1, Q Output <15:0> AGC0, RSSI Output <11:0> This read-only register provides the latest quadrature-phase This read-only register provides the latest RSSI output sample output sample from AGC1. Note that AGC1 might be bypassed from AGC0. This register is updated only when AGC0 is and that AGC1 here is representative of the datapath only. enabled and operating. AGC2, I Output <15:0: AGC1, RSSI Output <11:0> This read-only register provides the latest in-phase output This read-only register provides the latest RSSI output sample sample from AGC2. Note that AGC2 might be bypassed and from AGC1. This register is updated only when AGC1is that AGC2 here is representative of the datapath only. enabled and operating. AGC2, Q Output <15:0> AGC2, RSSI Output <11:0> This read-only register provides the latest quadrature-phase This read-only register provides the latest RSSI output sample output sample from AGC2. Note that AGC2 might be bypassed from AGC2. This register is updated only when AGC2 is and that AGC2 here is representative of the datapath only. enabled and operating. AGC3, I Output <15:0> AGC3, RSSI Output <11:0> This read-only register provides the latest in-phase output This read-only register provides the latest RSSI output sample sample from AGC3. Note that AGC3 might be bypassed and from AGC3. This register is updated only when AGC3 is that AGC3 here is representative of the datapath only. enabled and operating. AGC3, Q Output <15:0> AGC4, RSSI Output <11:0> This read-only register provides the latest quadrature-phase This read-only register provides the latest RSSI output sample output sample from AGC3. Note that AGC3 might be bypassed from AGC4. This register is updated only when AGC4 is and that AGC3 here is representative of the datapath only. enabled and operating. AGC4, I Output <15:0> AGC5, RSSI Output <11:0> This read-only register provides the latest in-phase output This read-only register provides the latest RSSI output sample sample from AGC4. Note that AGC4 might be bypassed and from AGC5. This register is updated only when AGC5 is that AGC4 here is representative of the datapath only. enabled and operating. Rev. 0 | Page 84 of 88 AD6654 DDC DESIGN NOTES The following guidelines describe circuit connections, layout • By default, the PLL CLK is disabled. It can be enabled by requirements, and programming procedures for the AD6654. programming the PLL multiplier and divider bits in the The designer should review these guidelines before starting the ADC CLK control register. When the PLL CLK is enabled system design and layout. by programming this register, it takes about 50 µs to 200 µs to settle down. While the PLL loop settles down, the voltage • The AD6654 requires the following power-up sequence. at the EXT_FILTER pin increases from 0 V to VDDCORE The VDDCORE (1.8 V) is required to settle into nominal (1.8 V) and settles there. Channel registers and output port voltage levels before the VDDIO attains the minimum. registers (Address 0x68 to Address 0xE7) should not be pro- grammed before the PLL loop settles down. • The DDC input clock (CLK) and input (EXP) pins EXP[2:0] are not 5 V tolerant. Care should be taken to drive these • To reset the AD6654, the user must provide a minimum pins within the limits of VDDIO (3.0 V to 3.6 V). This is pulse of 30 ns to the RESET pin. The RESET pin should be easily accomplished by using the ADC data ready (DR) connected to GND (or pulled low) during power-up of the output to drive the DDC clock (CLK) input. part. The RESET pin can be pulled high after the power supplies have settled to nominal values (1.8 V and • The number format used in this part is twos complement. 3.3 V). At this point, a pulse (pull low and high again) All input ports and output ports use twos complement data should be provided to give a reset to the part. format. The formats for individual internal registers are given in the memory map description of these registers. • The CPUCLK (SCLK) is the clock used for programming via the microport (serial port). This clock needs to be DTACK • In both microport and serial port operation, the provided by the designer to the part (slave clock). The IRP (RDY, SDO) and pins are open-drain outputs and designer should ensure that this clock’s frequency is less should be terminated externally to VDDIO through a 1 kΩ than or equal to the frequency of the CLK signal. Addi- pull-up resistor. tionally, the frequency of the CPUCLK (SCLK) should 3.3V always be less than 100 MHz. AD6654 3.3V • The microport data bus is 16 bits wide. Both 8-bit and 16-bit modes are available using this part. If 8-bit mode is 1kΩ DTACK (RDY, SDO) used, the MSB of the data bus (D[15:8]) can be left floating 1kΩ or connected to GND. IRP • The output parallel port has a 1-clock cycle overhead. If two Figure 75. DTACK, SDO, IRP Pull-Up Resistor Circuit channels (with the same data rates) are output on one output port in 16-bit interleaved I/Q mode along with an • A simple RC circuit is used on the EXT_FILTER pin to AGC word, this requires three clock cycles for one sample balance the internal RC circuit on this pin and maintain a from each channel (one clock each for I data, Q data, and good PLL clock lock. The recommended circuit is given in gain data). Therefore, the total number of clock cycles Figure 76. It is further recommended that this RC circuit be required to output the data is 3 clocks/channel × 2 channels placed as close as possible to the AD6654 part. This layout + 1 (overhead) = 7 clock cycles. The number of clock cycles consideration ensures that the PLL clock is clean and the required for each channel can be 3 (interleaved I + Q + gain PLL lock is closely maintained. word), or 2 (parallel I /Q + gain) or 2 (interleaved I + Q) or VDD CORE 1 (interleaved I/Q). Designers should make sure that suffi- cient time is allowed to output these channels on one output 0.01µF port. Also note that the I, Q, and gain for a particular 250Ω EXT_FILTER channel come out on a single output port and cannot be divided among output ports. AD6654 • When CRCF and DRCF filters are disabled, the coefficient memory cannot be read back, because the clock to the Figure 76. EXT_FILTER Circuit for PLL Clock coefficient RAM is also cut off. Rev. 0 | Page 85 of 88 05156-057 05156-056 AD6654 microport initiates a second access. This is a problem while • In the Intel mode microport, the beginning of a read and writing or reading from coefficient RAM, where each access write access is indicated by the RDY pin going low. The writes to or reads from a different RAM address. This can access is complete only when the RDY pin goes high. In the be fixed by writing to one coefficient RAM address at a Motorola mode microport, the completion of a read and time, that is, the coefficient start and stop address registers DTACK write access is indicated by the pin going low. In have the same value. both modes, CS, RD (DS), and WR (R/W) should be active until access is complete; otherwise, an incomplete access SCS • In SPI mode programming, the pin must go high results. (inactive) after writing or reading each byte (eight clock cycles on the SCLK pin). CS • In both Intel and Motorola modes, if is held low even after microport read or write access is complete, the Rev. 0 | Page 86 of 88 AD6654 OUTLINE DIMENSIONS A1 CORNER 17.20 INDEX AREA 17.00 SQ 16 14 12 10 8 6 4 2 16.80 15 13 11 9 7 5 3 1 A B C BALL A1 D CORNER E 15.00 F BSC SQ G H TOP VIEW J 1.00 K BSC L M N P R T BOTTOM VIEW DETAIL A * 1.85 * 1.31 1.71 DETAIL A 1.21 1.40 1.10 * 0.30 MIN 0.70 COPLANARITY 0.60 0.20 0.50 SEATING PLANE BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192-AAF-1 EXCEPT FOR DIMENSIONS INDICATED BY A "*" SYMBOL. Figure 77. 256-Lead Chip Scale Package Ball Grid Array [CSPBGA] (BC-256-2) Dimensions shown in millimeters ORDERING GUIDE Active Model Temperature Range Channels Package Description Package Option AD6654BBC −25°C to +85°C 6 256-Lead CSPBGA (Ball Grid Array) BC-256-2 1 AD6654BBCZ −25°C to +85°C 6 256-Lead CSPBGA (Ball Grid Array) BC-256-2 AD6654CBC −25°C to +85°C 4 256-Lead CSPBGA (Ball Grid Array) BC-256-2 1 AD6654CBCZ −25°C to +85°C 4 256-Lead CSPBGA (Ball Grid Array) BC-256-2 AD6654/PCB 6 Evaluation Board with AD6654 and Software 1 Z = Pb-free part. Rev. 0 | Page 87 of 88 AD6654 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05156–0–4/05(0) Rev. 0 | Page 88 of 88