ANALOG DEVICES AD6649

IF Diversity Receiver Data Sheet AD6649 FEATURES APPLICATIONS SNR = 73.4 dBFS in a 95 MHz bandwidth at Communications 185 MHz A and 245.76 MSPS Diversity radio systems IN SFDR = 85 dBc at 185 MHz A and 250 MSPS Multimode digital receivers (3G) IN Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS TD-SCDMA, WiMax, WCDMA, A and 250 MSPS CDMA2000, GSM, EDGE, LTE IN Total power consumption: 1 W with fixed-frequency NCO, General-purpose software radios 95 MHz FIR filter Broadband data applications 1.8 V supply voltages GENERAL DESCRIPTION LVDS (ANSI-644 levels) outputs The AD6649 is a mixed-signal intermediate frequency (IF) receiver Integer 1-to-8 input clock divider (625 MHz maximum input) consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital Integrated dual-channel ADC downconverter (DDC). The AD6649 is designed to support Sample rates of up to 250 MSPS communications applications, where low cost, small size, wide IF sampling frequencies to 400 MHz bandwidth, and versatility are desired. Internal ADC voltage reference Flexible input range The dual ADC cores feature a multistage, differential pipelined 1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal) architecture with integrated output error correction logic. Each ADC clock duty cycle stabilizer ADC features wide bandwidth inputs supporting a variety of 95 dB channel isolation/crosstalk user-selectable input ranges. An integrated voltage reference Integrated wideband digital processor eases design considerations. A duty cycle stabilizer is provided to 32-bit complex numerically controlled oscillator (NCO) compensate for variations in the ADC clock duty cycle, allowing FIR filter with 2 modes the converters to maintain excellent performance. Real output from an f /4 output NCO S Amplitude detect bits for efficient AGC implementation Energy saving power-down modes Decimated, interleaved real LVDS data outputs FUNCTIONAL BLOCK DIAGRAM AVDD FDA DRVDD THRESHOLD DETECT AD6649 SELECTABLE I FIR OR+ FILTER VIN+A OR– ADC DIGITAL D13+/D13– INTERLEAVING VIN–A Q SELECTABLE FIR DC D0+/D0– FILTER CORRECTION REFERENCE 32-BIT f /4 CLK+ DIVIDE 1 S TUNING NCO NCO TO 8 CLK– DUTY DCO+ DCO CYCLE DC Q SELECTABLE GENERATION STABILIZER DCO– CORRECTION FIR FILTER MULTICHIP VIN–B SYNC SYNC ADC VIN+B PROGRAMMING DATA I SELECTABLE FIR FILTER THRESHOLD DETECT SPI AGND FDB PDWN OEB SDIO SCLK CSB Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. DDR LVDS OUTPUT BUFFER 09635-001 AD6649 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 NCO and FIR Filter Modes ....................................................... 22 Applications ....................................................................................... 1 f /4 Fixed-Frequency NCO ....................................................... 22 S General Description ......................................................................... 1 Numerically Controlled Oscillator (NCO) ................................. 23 Functional Block Diagram .............................................................. 1 Frequency Translation ............................................................... 23 Revision History ............................................................................... 2 NCO Synchronization ............................................................... 23 Product Highlights ........................................................................... 3 NCO Amplitude and Phase Dither .......................................... 23 Specifications ..................................................................................... 4 FIR Filters ........................................................................................ 24 ADC DC Specifications ................................................................. 4 FIR Synchronization .................................................................. 24 ADC AC Specifications ................................................................. 5 Filter Performance ...................................................................... 24 Digital Specifications ..................................................................... 6 Output NCO ............................................................................... 25 Switching Specifications ................................................................ 8 ADC Overrange and Gain Control .............................................. 26 Timing Specifications .................................................................. 9 ADC Overrange (OR) ................................................................ 26 Absolute Maximum Ratings .......................................................... 10 Gain Switching ............................................................................ 26 Thermal Characteristics ............................................................ 10 DC Correction ................................................................................ 27 ESD Caution ................................................................................ 10 Channel/Chip Synchronization .................................................... 28 Pin Configuration and Function Descriptions ........................... 11 Serial Port Interface (SPI) .............................................................. 29 Typical Performance Characteristics ........................................... 13 Configuration Using the SPI ..................................................... 29 Equivalent Circuits ......................................................................... 16 Hardware Interface ..................................................................... 29 Theory of Operation ...................................................................... 17 SPI Accessible Features .............................................................. 30 ADC Architecture ...................................................................... 17 Memory Map .................................................................................. 31 Analog Input Considerations .................................................... 17 Reading the Memory Map Register Table ............................... 31 Voltage Reference ....................................................................... 19 Memory Map Register Table ..................................................... 32 Clock Input Considerations ...................................................... 19 Memory Map Register Description ......................................... 36 Power Dissipation and Standby Mode ..................................... 20 Applications Information .............................................................. 39 Digital Outputs ........................................................................... 21 Design Guidelines ...................................................................... 39 Overrange (OR) .......................................................................... 21 Outline Dimensions ....................................................................... 40 Digital Processing ........................................................................... 22 Ordering Guide .......................................................................... 40 Numerically Controlled Oscillator (NCO) ............................. 22 REVISION HISTORY 9/11—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 4 Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 8 Changes to Table 8 .......................................................................... 11 Added Overrange (OR) Section ................................................... 21 Changes to Channel/Chip Synchronization Section ................. 28 Change to the NCO/FIR SYNC Pin Control (Register 0x59) .. 38 4/11—Revision 0: Initial Version Rev. A | Page 2 of 40 Data Sheet AD6649 ADC data outputs are internally connected directly to the digital greatly reduces component cost and complexity compared with downconverter (DDC) of the receiver. The digital receiver has traditional analog techniques or less integrated digital methods. two channels and provides processing flexibility. Each receive In diversity applications, the output data format is real due to channel has four cascaded signal processing stages: a 32-bit the final NCO, which shifts the output center frequency to f /4. S frequency translator (numerically controlled oscillator (NCO)), Flexible power-down options allow significant power savings, an optional sample rate converter, a fixed FIR filter, and an f /4 S when desired. fixed-frequency NCO. Programming for setup and control is accomplished using a 3-pin In addition to the receiver DDC, the AD6649 has several SPI-compatible serial interface. functions that simplify the automatic gain control (AGC) The AD6649 is available in a 64-lead LFCSP and is specified over function in the system receiver. The programmable threshold the industrial temperature range of −40°C to +85°C. This detector allows monitoring of the incoming signal power using product is protected by a U.S. patent. the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes PRODUCT HIGHLIGHTS high. Because this threshold indicator has low latency, the user 1. Integrated dual, 14-bit, 250 MSPS ADCs. can quickly turn down the system gain to avoid an overrange 2. Integrated wideband filter and 32-bit complex NCO. condition at the ADC input. 3. Fast overrange and threshold detect. After digital processing, data is routed directly to the 14-bit 4. Proprietary differential input maintains excellent SNR output port. These outputs operate at ANSI or reduced swing performance for input frequencies of up to 400 MHz. LVDS signal levels. 5. SYNC input allows synchronization of multiple devices. 6. 3-pin, 1.8 V SPI port for register programming and register The AD6649 receiver digitizes a wide spectrum of IF frequencies. readback. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture Rev. A | Page 3 of 40 AD6649 Data Sheet SPECIFICATIONS ADC DC SPECIFICATIONS 1 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, duty cycle stabilizer (DCS) enabled, NCO enabled, FIR filter enabled, unless otherwise noted. Table 1. Parameter Temperature Min Typ Max Unit RESOLUTION Full 14 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±10 mV Gain Error Full −5.5 +2.5 %FSR MATCHING CHARACTERISTIC Offset Error Full ±13 mV Gain Error Full ±2.5 %FSR TEMPERATURE DRIFT Offset Error Full ±5 ppm/°C Gain Error Full ±100 ppm/°C INPUT REFERRED NOISE VREF = 1.0 V 25°C 1.32 LSB rms ANALOG INPUT Input Span Full 1.75 V p-p 2 Input Capacitance Full 2.5 pF 3 Input Resistance Full 20 kΩ Input Common-Mode Voltage Full 0.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current 4 I Full 271 275 mA AVDD 4 I (Fixed-Frequency NCO, 95 MHz FIR Filter) Full 283 300 mA DRVDD 4 I (Tunable-Frequency NCO, 100 MHz FIR Filter) Full 375 mA DRVDD POWER CONSUMPTION Sine Wave Input (Fixed-Frequency NCO, 95 MHz FIR Filter) Full 997 1035 mW Sine Wave Input (Tunable-Frequency NCO, 100 MHz FIR Filter) Full 1163 mW 5 Standby Power Full 104 mW Power-Down Power Full 10 mW 1 A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters section for more details. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Measured with a 185 MHz, full-scale sine wave input on both channels and an NCO frequency of 62.5 MHz (f /4). S 5 Standby power is measured with a dc input and the CLK pin inactive (set to AVDD or AGND). Rev. A | Page 4 of 40 Data Sheet AD6649 ADC AC SPECIFICATIONS 1 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, NCO enabled, FIR filter enabled, unless otherwise noted. Table 2. 2 Parameter Temperature Min Typ Max Unit 3 SIGNAL-TO-NOISE RATIO (SNR) f = 30 MHz 25°C 74.5 dBFS IN f = 90 MHz 25°C 74.2 dBFS IN f = 140 MHz 25°C 73.9 dBFS IN f = 185 MHz 25°C 73.4 dBFS IN Full 70.9 dBFS f = 220 MHz 25°C 72.9 dBFS IN SIGNAL-TO-NOISE AND DISTORTION (SINAD) f = 30 MHz 25°C 73.4 dBFS IN f = 90 MHz 25°C 73.0 dBFS IN f = 140 MHz 25°C 72.3 dBFS IN f = 185 MHz 25°C 71.7 dBFS IN Full 68.7 dBFS f = 220 MHz 25°C 71.0 dBFS IN WORST SECOND OR THIRD HARMONIC f = 30 MHz 25°C −92 dBc IN f = 90 MHz 25°C −88 dBc IN f = 140 MHz 25°C −85 dBc IN f = 185 MHz 25°C −85 dBc IN Full −80 dBc f = 220 MHz 25°C −89 dBc IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 30 MHz 25°C 92 dBc IN f = 90 MHz 25°C 88 dBc IN f = 140 MHz 25°C 85 dBc IN f = 185 MHz 25°C 85 dBc IN 80 Full f = 220 MHz 25°C 84 dBc IN WORST OTHER HARMONIC OR SPUR f = 30 MHz 25°C −95 dBc IN f = 90 MHz 25°C −94 dBc IN f = 140 MHz 25°C −93 dBc IN f = 185 MHz 25°C −93 dBc IN Full −80 dBc f = 220 MHz 25°C −84 dBc IN TWO-TONE SFDR f = 184.12 MHz, 187.12 MHz (−7 dBFS) 25°C 88 dBc IN 4 CROSSTALK Full 95 dB ANALOG INPUT BANDWIDTH 25°C 1000 MHz 1 A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters section for more details. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 3 SNR specifications are for filtered 95 MHz bandwidth. 4 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel. Rev. A | Page 5 of 40 AD6649 Data Sheet DIGITAL SPECIFICATIONS 1 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full +10 +22 µA Low Level Input Current Full −22 −10 µA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS/LVDS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −5 +5 µA Low Level Input Current Full −5 +5 µA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ 2 LOGIC INPUT (CSB) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −5 +5 µA Low Level Input Current Full −80 −45 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 3 LOGIC INPUT (SCLK) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 µA Low Level Input Current Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF 2 LOGIC INPUT/OUTPUT (SDIO) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 µA Low Level Input Current Full −5 +5 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF 3 LOGIC INPUTS (OEB, PDWN) High Level Input Voltage Full 1.22 2.1 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full 45 70 µA Low Level Input Current Full −5 +5 µA Rev. A | Page 6 of 40 Data Sheet AD6649 Parameter Temperature Min Typ Max Unit Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS FDA and FDB High Level Output Voltage I = 50 µA Full 1.79 V OH I = 0.5 mA Full 1.75 V OH Low Level Output Voltage I = 1.6 mA Full 0.2 V OL I = 50 µA Full 0.05 V OL LVDS Data and OR Outputs Differential Output Voltage (V ), ANSI Mode Full 250 350 450 mV OD Output Offset Voltage (V ), Full 1.15 1.22 1.35 V OS ANSI Mode Differential Output Voltage (V ), Reduced Swing Mode Full 150 200 280 mV OD Output Offset Voltage (V ), Full 1.15 1.22 1.35 V OS Reduced Swing Mode 1 A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters section for more details. 2 Pull-up. 3 Pull-down. Rev. A | Page 7 of 40 AD6649 Data Sheet SWITCHING SPECIFICATIONS Table 4. Parameter Temperature Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 MHz 1 Conversion Rate Full 40 250 MSPS CLK Period—Divide-by-1 Mode (t ) Full 4.0 ns CLK CLK Pulse Width High (t ) CH Divide-by-1 Mode, DCS Enabled Full 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 1.9 2.0 2.1 ns Divide-by-3 Through Divide-by-8 Modes, DCS Enabled Full 0.8 ns DATA OUTPUT PARAMETERS (DATA, OR) Data Propagation Delay (t ) Full 4.8 ns PD DCO Propagation Delay (t ) Full 5.5 ns DCO DCO-to-Data Skew (t ) Full 0.3 0.7 1.1 ns SKEW Pipeline Delay—Fixed-Frequency NCO, 95 MHz FIR Filter (Latency) Full 23 Cycles Pipeline Delay—Tunable-Frequency NCO, 100 MHz FIR Filter (Latency) Full 43 Cycles Aperture Delay (t ) Full 1.0 ns A Aperture Uncertainty (Jitter, t ) Full 0.1 ps rms J Wake-Up Time (from Standby) Full 10 µs Wake-Up Time (from Power-Down) Full 250 µs OUT-OF-RANGE RECOVERY TIME Full 3 Cycles 1 Conversion rate is the clock rate after the divider. Rev. A | Page 8 of 40 Data Sheet AD6649 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS t SYNC to the rising edge of CLK setup time 0.3 ns SSYNC t SYNC to the rising edge of CLK hold time 0.4 ns HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK 2 ns DS t Hold time between the data and the rising edge of SCLK 2 ns DH t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S t Hold time between CSB and SCLK 2 ns H t Minimum period that SCLK should be in a logic high state 10 ns HIGH t Minimum period that SCLK should be in a logic low state 10 ns LOW t Time required for the SDIO pin to switch from an input to an output 10 ns EN_SDIO relative to the SCLK falling edge t Time required for the SDIO pin to switch from an output to an input 10 ns DIS_SDIO relative to the SCLK rising edge Timing Diagrams t t CH CLK CLK+ CLK– t DCO DCO+ DCO– t SKEW t PD D0+ TO D13+ CHA0 CHB0 CHA1 CHB1 CHA2 CHB2 CHA3 CHB3 CHA4 CHB4 CHA5 CHB5 CHA6 CHB6 D0– TO D13– Figure 2. Interleaved LVDS Mode Data Output Timing CLK+ t t SSYNC HSYNC SYNC Figure 3. SYNC Timing Inputs Rev. A | Page 9 of 40 09635-016 09635-002 AD6649 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating THERMAL CHARACTERISTICS Electrical The exposed paddle must be soldered to the ground plane for AVDD to AGND −0.3 V to +2.0 V the LFCSP package. Soldering the exposed paddle to the DRVDD to AGND −0.3 V to +2.0 V customer board increases the reliability of the solder joints, VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V maximizing the thermal capability of the package. CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance SYNC to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V Airflow Package Velocity CSB to AGND −0.3 V to DRVDD + 0.3 V 1, 2 1, 3 1, 4 Type (m/sec) θ θ θ Unit JA JC JB SCLK to AGND −0.3 V to DRVDD + 0.3 V 64-Lead LFCSP 0 26.8 1.14 10.4 °C/W SDIO to AGND −0.3 V to DRVDD + 0.3 V 9 mm × 9 mm 1.0 21.6 °C/W OEB to AGND −0.3 V to DRVDD + 0.3 V (CP-64-4) 2.0 20.2 °C/W PDWN to AGND −0.3 V to DRVDD + 0.3 V 1 D0−/D0+ through D13−/D13+ −0.3 V to DRVDD + 0.3 V Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). to AGND 3 Per MIL-Std 883, Method 1012.1. 4 FDA/FDB to AGND −0.3 V to DRVDD + 0.3 V Per JEDEC JESD51-8 (still air). OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V Typical θ is specified for a 4-layer PCB with solid ground JA DCO+/DCO− to AGND −0.3 V to DRVDD + 0.3 V plane. As shown in Table 7, airflow increases heat dissipation, Environmental which reduces θ . In addition, metal in direct contact with the JA Operating Temperature Range −40°C to +85°C package leads from metal traces, through holes, ground, and (Ambient) power planes, reduces the θ . JA Maximum Junction Temperature 150°C Under Bias ESD CAUTION Storage Temperature Range −65°C to +125°C (Ambient) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 10 of 40 Data Sheet AD6649 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR CLK+ 1 48 PDWN CLK– 2 47 OEB SYNC 3 46 CSB FDA 4 45 SCLK FDB 5 44 SDIO DNC 6 43 OR+ AD6649 DNC 7 42 OR– D0– (LSB) 8 41 D13+ (MSB) TOP VIEW D0+ (LSB) 9 40 D13– (MSB) (Not to Scale) DRVDD 10 39 D12+ D1– 11 38 D21– D1+ 12 37 DRVDD D2– 13 36 D11+ D2+ 14 35 D11– D3– 15 34 D10+ D3+ 16 33 D10– NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 4. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View) Table 8. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type Description ADC Power Supplies 10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal). 49, 50, 53, 54, 59, 60, 63, 64 AVDD Supply Analog Power Supply (1.8 V Nominal). 6, 7, 55, 56, 58 DNC Do Not Connect. Do not connect to this pin. 0 AGND, Ground Analog Ground. The exposed thermal paddle on the bottom of the Exposed Paddle package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation. ADC Analog 51 VIN+A Input Differential Analog Input Pin (+) for Channel A. 52 VIN−A Input Differential Analog Input Pin (−) for Channel A. 62 VIN+B Input Differential Analog Input Pin (+) for Channel B. 61 VIN−B Input Differential Analog Input Pin (−) for Channel B. 57 VCM Output Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled to ground using a 0.1 μF capacitor. 1 CLK+ Input ADC Clock Input—True. 2 CLK− Input ADC Clock Input—Complement. ADC Fast Detect Outputs 4 FDA Output Channel A Fast Detect Indicator (CMOS Levels). 5 FDB Output Channel B Fast Detect Indicator (CMOS Levels). Digital Input 3 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 9 D0+ (LSB) Output Channel A/Channel B LVDS Output Data 0—True. 8 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement. 12 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 11 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 14 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 13 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 16 D3+ Output Channel A/Channel B LVDS Output Data 3—True. Rev. A | Page 11 of 40 D4– 17 64 AVDD D4+ 18 63 AVDD DRVDD 19 62 VIN+B D5– 20 61 VIN–B D5+ 21 60 AVDD D6– 22 59 AVDD D6+ 23 58 DNC DCO– 24 57 VCM DCO+ 25 56 DNC D7– 26 55 DNC D7+ 27 54 AVDD DRVDD 28 53 AVDD D8– 29 52 VIN–A D8+ 30 51 VIN+A D9– 31 50 AVDD AVDD D9+ 32 49 09635-004 AD6649 Data Sheet Pin No. Mnemonic Type Description 15 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 18 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 17 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 21 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 20 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 23 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 22 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 27 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 26 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 30 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 29 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 32 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 31 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 34 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 33 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 36 D11+ Output Channel A/Channel B LVDS Output Data 11—True. 35 D11− Output Channel A/Channel B LVDS Output Data 11—Complement. 39 D12+ Output Channel A/Channel B LVDS Output Data 12—True. 38 D12− Output Channel A/Channel B LVDS Output Data 12—Complement. 41 D13+ (MSB) Output Channel A/Channel B LVDS Output Data 13—True. 40 D13− (MSB) Output Channel A/Channel B LVDS Output Data 13—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange—True. 42 OR− Output Channel A/Channel B LVDS Overrange—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK Input SPI Serial Clock. 44 SDIO Input/Output SPI Serial Data Input/Output. 46 CSB Input SPI Chip Select (Active Low). Output Enable Bar and Power- Down 47 OEB Input/Output Output Enable Bar Input (Active Low). 48 PDWN Input/Output Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby (see Table 14). Rev. A | Page 12 of 40 Data Sheet AD6649 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, T = 25°C, fixed-frequency NCO, 95 MHz BW FIR filter, unless otherwise noted. In the FFT plots that follow, the location of the second A and third harmonics is noted when they fall in the pass band of the filter. A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters section for more details. 0 0 f = 250MSPS S f = 250MSPS S f = 30.1MHz @ –1.0dBFS IN f = 185.1MHz @ –1.0dBFS IN –20 –20 SNR = 72dB (74.5dBFS) SNR = 70.5dB (73.0dBFS) SFDR = 92dBc (IN-BAND) SFDR = 84.5dBc (IN-BAND) –40 –40 –60 –60 THIRD HARMONIC –80 SECOND HARMONIC –80 THIRD HARMONIC –100 –100 –120 –120 –140 –140 0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. AD6649 Single-Tone FFT with f = 30.1 MHz Figure 8. AD6649 Single-Tone FFT with f = 185.1 MHz IN IN 0 0 f = 250MSPS f = 250MSPS S S f = 90.1MHz @ –1.0dBFS f = 220.1MHz @ –1.0dBFS IN IN –20 SNR = 71.6dB (74.1dBFS) –20 SNR = 69.8dB (72.3dBFS) SFDR = 87.5dBc (IN-BAND) SFDR = 84dBc (IN-BAND) –40 –40 –60 –60 SECOND HARMONIC THIRD HARMONIC –80 –80 SECOND HARMONIC THIRD HARMONIC –100 –100 –120 –120 –140 –140 0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. AD6649 Single-Tone FFT with f = 90.1 MHz Figure 9. AD6649 Single-Tone FFT with f = 220.1 MHz IN IN 0 0 f = 250MSPS S f = 250MSPS S f = 305.1MHz @ –1.0dBFS IN f = 140.1MHz @ –1.0dBFS IN –20 –20 SNR = 68.5dB (71.0dBFS) SNR = 71.1dB (73.6dBFS) SFDR = 83.5dBc (IN-BAND) SFDR = 85dBc (IN-BAND) –40 –40 SECOND HARMONIC –60 –60 SECOND HARMONIC THIRD HARMONIC –80 –80 THIRD HARMONIC –100 –100 –120 –120 –140 –140 0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. AD6649 Single-Tone FFT with f = 140.1 MHz Figure 10. AD6649 Single-Tone FFT with f = 305.1 MHz IN IN Rev. A | Page 13 of 40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09635-114 09635-113 09635-112 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09635-117 09635-216 09635-215 AD6649 Data Sheet 120 0 SFDR (dBFS) 100 –20 SFDR (dBc) SNR (dBFS) 80 –40 IMD3 (dBc) 60 –60 40 –80 SFDR (dBc) SFDR (dBFS) 20 –100 SNR (dBc) IMD3 (dBFS) 0 –120 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –9.5 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 11. AD6649 Single-Tone SNR/SFDR vs. Input Amplitude (A ) Figure 14. AD6649 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) IN IN with f = 90.1 MHz with f = 184.12 MHz, f = 187.12 MHz, f = 250 MSPS IN IN1 IN2 S 0 100 250MSPS 89.12MHz @ –7.0dBFS 95 –20 92.12MHz @ –7.0dBFS SFDR = 88dBc (96.5dBFS) SFDR (dBc) 90 –40 85 –60 80 –80 75 SNR (dBFS) –100 70 –120 65 –140 50 100 150 200 250 300 350 400 450 0 10 20 30 40 50 60 70 80 90 100 110 120 FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 12. AD6649 Single-Tone SNR/SFDR vs. Input Frequency (f ) Figure 15. AD6649 Two-Tone FFT with f = 89.12 MHz, f = 92.12 MHz, IN IN1 IN2 f = 250 MSPS S 0 0 250MSPS 184.12MHz @ –7.0dBFS –20 187.12MHz @ –7.0dBFS –20 SFDR = 85dBc (93.5dBFS) SFDR (dBc) –40 –40 IMD3 (dBc) –60 –60 –80 –80 –100 SFDR (dBFS) –100 –120 IMD3 (dBFS) –140 –120 0 10 20 30 40 50 60 70 80 90 100 110 120 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –9.5 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 13. AD6649 Two-Tone SFDR/IMD3 vs. Input Amplitude (A ) Figure 16. AD6649 Two-Tone FFT with f = 184.12 MHz, IN IN1 with f = 89.12 MHz, f = 92.12 MHz, f = 250 MSPS f = 187.12 MHz, f = 250 MSPS IN1 IN2 S IN2 S Rev. A | Page 14 of 40 SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBFS and dBc) SNR/SFDR (dBc AND dBFS) –100 –95 –90 –85 –80 –75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 09635-118 09635-119 09635-120 SFDR/IMD3 (dBc AND dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09635-123 09635-122 09635-121 Data Sheet AD6649 6000 100 1.32 LSB rms 16,378 TOTAL HITS 95 5000 90 4000 SFDR CHANNEL A (dBc) 85 3000 SFDR CHANNEL B (dBc) SNR CHANNEL A (dBFS) SNR CHANNEL B (dBFS) 80 2000 75 1000 70 0 SAMPLE RATE (MSPS) OUTPUT CODE ) with Figure 17. AD6649 Single-Tone SNR/SFDR vs. Sample Rate (f Figure 18. AD6649 Grounded Input Histogram S f = 90.1 MHz IN Rev. A | Page 15 of 40 SNR/SFDR (dBFS/dBc) 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 09635-124 NUMBER OF HITS N – 5 N – 4 N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 09635-125 AD6649 Data Sheet EQUIVALENT CIRCUITS AVDD 350Ω SCLK, PDWN, OR OEB 26kΩ VIN Figure 19. Equivalent Analog Input Circuit Figure 23. Equivalent SCLK, PDWN, or OEB Input Circuit AVDD AVDD AVDD AVDD 26kΩ 0.9V 350Ω CSB 15kΩ 15kΩ CLK+ CLK– Figure 20. Equivalent Clock Input Circuit Figure 24. Equivalent CSB Input Circuit DRVDD AVDD AVDD V+ V– DATAOUT– DATAOUT+ SYNC 0.9V V– V+ 16kΩ 0.9V Figure 21. Equivalent LVDS Output Circuit Figure 25. Equivalent SYNC Input Circuit DRVDD 350Ω SDIO 26kΩ Figure 22. Equivalent SDIO Circuit Rev. A | Page 16 of 40 09635-008 09635-010 09635-011 09635-009 09635-025 09635-014 09635-012 Data Sheet AD6649 THEORY OF OPERATION must be capable of charging the sampling capacitors and settling The AD6649 has two analog input channels, two filter channels, within 1/2 clock cycle. and two digital output channels. The intermediate frequency (IF) input signal passes through several stages before appearing A small resistor in series with each input can help reduce the at the output port(s) as a filtered and optionally decimated peak transient current required from the output stage of the digital signal. driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive The dual ADC design can be used for diversity reception of signals, network creates a low-pass filter at the ADC input; therefore, where the ADCs operate identically on the same carrier but from the precise values are dependent on the application. two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample frequencies In intermediate frequency (IF) undersampling applications, the from dc to 300 MHz using appropriate low-pass or band-pass shunt capacitors should be reduced. In combination with the filtering at the ADC inputs with little loss in ADC performance. driving source impedance, the shunt capacitors limit the input Operation to 400 MHz analog input is permitted but occurs at bandwidth. Refer to the AN-742 Application Note, Frequency the expense of increased ADC noise and distortion. Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Synchronization capability is provided to allow synchronized Switched-Capacitor ADCs; and the Analog Dialogue article, timing between multiple devices. “Transformer-Coupled Front-End for Wideband A/D Converters,” Programming and control of the AD6649 are accomplished for more information on this subject. using a 3-pin SPI-compatible serial interface. BIAS ADC ARCHITECTURE S S C The AD6649 architecture consists of a dual front-end sample- C S FB VIN+ and-hold circuit, followed by a pipelined switched-capacitor C C PAR1 PAR2 ADC. The quantized outputs from each stage are combined into S a final 14-bit result in the digital correction logic. The pipelined H S architecture permits the first stage to operate on a new input C S sample and the remaining stages to operate on the preceding VIN– C samples. Sampling occurs on the rising edge of the clock. C PAR1 C FB PAR2 S S Each stage of the pipeline, excluding the last, consists of a low BIAS resolution flash ADC connected to a switched-capacitor digital- Figure 26. Switched-Capacitor Input to-analog converter (DAC) and an interstage residue amplifier For best dynamic performance, the source impedances driving (MDAC). The MDAC magnifies the difference between the recon- VIN+ and VIN− should be matched, and the inputs should be structed DAC output and the flash input for the next stage in differentially balanced. the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply Input Common Mode consists of a flash ADC. The analog inputs of the AD6649 are not internally dc biased. In ac-coupled applications, the user must provide this bias The input stage of each channel contains a differential sampling externally. Setting the device so that V = 0.5 × AVDD (or circuit that can be ac- or dc-coupled in differential or single- CM 0.9 V) is recommended for optimum performance. An on-board ended modes. The output staging block aligns the data, corrects common-mode voltage reference is included in the design and is errors, and passes the data to the output buffers. The output buffers available from the VCM pin. Using the VCM output to set the are powered from a separate supply, allowing digital output noise to input common mode is recommended. Optimum performance be separated from the analog core. During power-down, the is achieved when the common-mode voltage of the analog input output buffers go into a high impedance state. is set by the VCM pin voltage (typically 0.5 × AVDD). The ANALOG INPUT CONSIDERATIONS VCM pin must be decoupled to ground by a 0.1 µF capacitor, as The analog input to the AD6649 is a differential switched- described in the Applications Information section. This capacitor circuit that has been designed for optimum performance decoupling capacitor should be placed close to the pin to while processing a differential input signal. minimize the series resistance and inductance between the part and this capacitor. The clock signal alternatively switches the input between sample mode and hold mode (see the configuration shown in Figure 26). When the input is switched into sample mode, the signal source Rev. A | Page 17 of 40 09635-034 AD6649 Data Sheet Differential Input Configurations At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve Optimum performance is achieved while driving the AD6649 the true SNR performance of the AD6649. For applications where in a differential input configuration. For baseband applications, SNR is a key parameter, differential double balun coupling is the AD8138, ADA4937-2, ADA4938-2, and ADA4930-2 the recommended input configuration (see Figure 30). In this differential drivers provide excellent performance and a flexible configuration, the input is ac-coupled and the CML is provided interface to the ADC. to each input through a 33 Ω resistor. These resistors compensate The output common-mode voltage of the ADA4930-2 is easily for losses in the input baluns to provide a 50 Ω impedance to set with the VCM pin of the AD6649 (see Figure 27), and the the driver. driver can be configured in a Sallen-Key filter topology to In the double balun and transformer configurations, the value of provide band-limiting of the input signal. the input capacitors and resistors is dependent on the input fre- 15pF quency and source impedance. Based on these parameters the 200Ω value of the input resistors and capacitors may need to be 33Ω 15Ω 90Ω VIN– 76.8Ω adjusted or some components may need to be removed. Table 9 VIN 5pF displays recommended values to set the RC network for different ADC ADA4930-2 input frequency ranges. However, these values are dependent on 0.1µF 33Ω 15Ω VCM VIN+ the input signal and bandwidth and should be used only as a 120Ω 15pF starting guide. Note that the values given in Table 9 are for each 200Ω 33Ω R1, R2, C2, and R3 component shown in Figure 28 and Figure 30. 0.1µF Table 9. Example RC Network Figure 27. Differential Input Configuration Using the ADA4930-2 Frequency R1 C1 R2 C2 R3 Range Series Differential Series Shunt Shunt For baseband applications where SNR is a key parameter, (MHz) (Ω) (pF) (Ω) (pF) (Ω) differential transformer coupling is the recommended input 0 to 100 33 8.2 0 15 49.9 configuration. An example is shown in Figure 28. To bias the 100 to 250 15 3.9 0 8.2 49.9 analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use an amplifier with variable C2 gain. The AD8375 or AD8376 digital variable gain amplifier R3 R2 VIN+ (DVGAs) provides good performance for driving the AD6649. R1 Figure 29 shows an example of the AD8376 driving the AD6649 2V p-p 49.9Ω C1 ADC through a band-pass antialiasing filter. R2 R1 VCM VIN– 1000pF 180nH 220nH 33Ω 1µH R3 0.1µF 0.1µF 165Ω VPOS 15pF C2 AD8376 5.1pF 3.9pF 301Ω VCM 2.5kΩ║2pF 165Ω 1nF Figure 28. Differential Transformer-Coupled Configuration 1µH 1nF 68nH AD6649 The signal characteristics must be considered when selecting 180nH 220nH 1000pF a transformer. Most RF transformers saturate at frequencies NOTES below a few megahertz. Excessive signal power can also cause ® 1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (COILCRAFT 0603LS). core saturation, which leads to distortion. 2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. Figure 29. Differential Input Configuration Using the AD8376 C2 R3 0.1µF 0.1µF R1 R2 VIN+ 2V p-p 33Ω P S S P C1 ADC A 0.1µF 33Ω 0.1µF R1 R2 VCM VIN– 33Ω R3 0.1µF C2 Figure 30. Differential Double Balun Input Configuration Rev. A | Page 18 of 40 09635-040 09635-039 09635-041 09635-115 Data Sheet AD6649 VOLTAGE REFERENCE ADC 25Ω A stable and accurate voltage reference is built into the AD6649. 390pF 390pF CLOCK The full-scale input range can be adjusted by varying the reference CLK+ INPUT voltage via SPI. The input span of the ADC tracks reference voltage 390pF CLK– changes linearly. SCHOTTKY 25Ω DIODES: CLOCK INPUT CONSIDERATIONS HSMS2822 For optimum performance, the AD6649 sample clock inputs, Figure 33. Balun-Coupled Differential Clock (Up to 625 MHz) CLK+ and CLK−, should be clocked with a differential signal. If a low jitter clock source is not available, another option is to The signal is typically ac-coupled into the CLK+ and CLK− pins ac couple a differential PECL signal to the sample clock input pins via a transformer or via capacitors. These pins are biased as shown in Figure 34. The AD9510, AD9511, AD9512, AD9513, internally (see Figure 31) and require no external bias. If the AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, inputs are floated, the CLK− pin is pulled low to prevent spurious AD9523, AD9524, and ADCLK905/ADCLK907/ADCLK925 clock clocking. drivers offer excellent jitter performance. AVDD 0.9V 0.1µF 0.1µF CLOCK CLK+ INPUT CLK+ CLK– ADC AD95xx 100Ω PECL DRIVER 0.1µF 0.1µF 4pF 4pF CLOCK CLK– INPUT 240Ω 240Ω 50kΩ 50kΩ Figure 34. Differential PECL Sample Clock (Up to 625 MHz) Figure 31. Simplified Equivalent Clock Input Circuit A third option is to ac-couple a differential LVDS signal to the Clock Input Options sample clock input pins, as shown in Figure 35. The AD9510, The AD6649 has a very flexible clock input structure. Clock AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, input can be a CMOS, LVDS, LVPECL, or sine wave signal. AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers Regardless of the type of signal being used, clock source jitter offer excellent jitter performance. is of the most concern, as described in the Jitter Considerations section. 0.1µF 0.1µF Figure 32 and Figure 33 show two preferable methods for clocking CLOCK CLK+ INPUT the AD6649 (at clock rates of up to 625 MHz). A low jitter clock ADC AD95xx 100Ω source is converted from a single-ended signal to a differential LVDS DRIVER 0.1µF 0.1µF CLOCK CLK– signal using an RF balun or RF transformer. INPUT 50kΩ 50kΩ The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recom- Figure 35. Differential LVDS Sample Clock (Up to 625 MHz) mended for clock frequencies from 10 MHz to 200 MHz. The Input Clock Divider back-to-back Schottky diodes across the transformer secondary The AD6649 contains an input clock divider with the ability to limit clock excursions into the AD6649 to approximately 0.8 V p-p divide the input clock by integer values between 1 and 8. The differential. This limit helps prevent the large voltage swings of duty cycle stabilizer (DCS) is enabled by default on power-up. the clock from feeding through to other portions of the AD6649 while preserving the fast rise and fall times of the signal, which The AD6649 clock divider can be synchronized using the external are critical to low jitter performance. SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock divider to be resynchronized on every SYNC signal or only on ® Mini-Circuits ADC the first SYNC signal after the register is written. A valid SYNC ADT1-1WT, 1:1Z 390pF 390pF causes the clock divider to reset to its initial state. This synchro- XFMR CLOCK CLK+ INPUT nization feature allows multiple parts to have their clock dividers 100Ω 50Ω 390pF aligned to guarantee simultaneous input sampling. CLK– SCHOTTKY DIODES: HSMS2822 Figure 32. Transformer-Coupled Differential Clock (Up to 200 MHz) Rev. A | Page 19 of 40 09635-044 09635-048 09635-049 09635-051 09635-050 AD6649 Data Sheet Clock Duty Cycle ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators make Typical high speed ADCs use both clock edges to generate a the best clock sources. If the clock is generated from another type variety of internal timing signals and, as a result, may be sensitive to of source (by gating, dividing, or another method), it should be clock duty cycle. Commonly, a ±5% tolerance is required on the retimed by the original clock at the last step. clock duty cycle to maintain dynamic performance characteristics. Refer to the AN-501 Application Note, Aperture Uncertainty The AD6649 contains a duty cycle stabilizer (DCS) that retimes and ADC System Performance, and the AN-756 Application the nonsampling (falling) edge, providing an internal clock Note, Sampled Systems and the Effects of Clock Phase Noise and signal with a nominal 50% duty cycle. This allows the user to Jitter, for more information about jitter performance as it relates provide a wide range of clock input duty cycles without affecting to ADCs. the performance of the AD6649. POWER DISSIPATION AND STANDBY MODE Jitter on the rising edge of the input clock is still of paramount concern and is not reduced by the duty cycle stabilizer. The duty As shown in Figure 37, the power dissipated by the AD6649 is cycle control loop does not function for clock rates less than proportional to its sample rate. The data in Figure 37 was taken 40 MHz nominally. The loop has a time constant associated using the same operating conditions as those used for the Typical with it that must be considered when the clock rate can change Performance Characteristics. dynamically. A wait time of 1.5 µs to 5 µs is required after a 1.0 0.5 dynamic clock frequency increase or decrease before the DCS 0.9 loop is relocked to the input signal. During the time period that 0.4 0.8 the loop is not locked, the DCS loop is bypassed, and internal 0.7 TOTAL POWER device timing is dependent on the duty cycle of the input clock 0.3 0.6 signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS 0.5 I AVDD circuit is recommended to maximize ac performance. 0.4 0.2 Jitter Considerations 0.3 I DRVDD 0.2 High speed, high resolution ADCs are sensitive to the quality of 0.1 the clock input. The degradation in SNR at a given input 0.1 frequency (f ) due to jitter (t ) can be calculated by IN J 0 0 40 60 80 100 120 140 160 180 200 220 250 (/SNR /10) 2 LF SNR = −10 log[(2π × f × t ) + 10 ] HF IN JRMS ENCODE FREQUENCY (MSPS) Figure 37. AD6649 Power and Current vs. Sample Rate In the equation, the rms aperture jitter represents the root- mean-square of all jitter sources, which include the clock input, By asserting PDWN (either through the SPI port or by asserting the analog input signal, and the ADC aperture jitter specification. the PDWN pin high), the AD6649 is placed in power-down IF undersampling applications are particularly sensitive to jitter, mode. In this state, the ADC typically dissipates 10 mW. During as shown in Figure 36. power-down, the output drivers are placed in a high impedance 80 state. Asserting the PDWN pin low returns the AD6649 to its normal operating mode. Note that PDWN is referenced to the 75 digital output driver supply (DRVDD) and should not exceed that supply voltage. 70 Low power dissipation in power-down mode is achieved by 0.05ps shutting down the reference, reference buffer, biasing networks, 65 0.20ps 0.50ps and clock. Internal capacitors are discharged when entering 1.00ps power-down mode and then must be recharged when returning 1.50ps 60 MEASURED to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down 55 cycles result in proportionally shorter wake-up times. 50 When using the SPI port interface, the user can place the ADC 1 10 100 1000 in power-down mode or standby mode. Standby mode allows INPUT FREQUENCY (MHz) the user to keep the internal reference circuitry powered when Figure 36. SNR (95 MHz BW) vs. Input Frequency and Jitter faster wake-up times are required. See the Memory Map Register The clock input should be treated as an analog signal in cases Description section and the AN-877 Application Note, Interfacing where aperture jitter may affect the dynamic range of the AD6649. to High Speed ADCs via SPI, for additional details. Power supplies for clock drivers should be separated from the Rev. A | Page 20 of 40 SNR (dBFS) 09635-140 TOTAL POWER (W) SUPPLY CURRENT (A) 09635-037 Data Sheet AD6649 Timing DIGITAL OUTPUTS The AD6649 provides latched data with a pipeline delay of 23 or 43 The AD6649 output drivers can be configured for either ANSI input sample clock cycles, depending on the mode of operation. LVDS or reduced drive LVDS using a 1.8 V DRVDD supply. Data outputs are available one propagation delay (t ) after the PD As detailed in the AN-877 Application Note, Interfacing to High rising edge of the clock signal. Speed ADCs via SPI, the data format can be selected for offset The length of the output data lines and loads placed on them binary, twos complement, or gray code when using the SPI should be minimized to reduce transients within the AD6649. control. These transients can degrade converter dynamic performance. Digital Output Enable Function (OEB) The lowest typical conversion rate of the AD6649 is 40 MSPS. At The AD6649 has a flexible three-state ability for the digital clock rates below 40 MSPS, dynamic performance may degrade. output pins. The three-state mode is enabled using the OEB pin or through the SPI interface. If the OEB pin is low, the output Data Clock Output (DCO) data drivers are enabled. If the OEB pin is high, the output data The AD6649 also provides data clock output (DCO) intended drivers are placed in a high impedance state. This OEB function for capturing the data in an external register. Figure 2 shows a is not intended for rapid access to the data bus. Note that OEB graphical timing diagram of the AD6649 output modes. is referenced to the digital output driver supply (DRVDD) and OVERRANGE (OR) should not exceed that supply voltage. The overrange indicator is asserted when an overrange is When using the SPI interface, the data and fast detect outputs of detected on the input of the AD6649. The overrange condition each channel can be independently three-stated by using the is determined at the output of the pipeline ADC and, therefore, output enable bar bit (Bit 4) in Register 0x14. Because the is subject to a latency of 10 ADC clocks. An overrange at the input output data is interleaved, if only one of the two channels is is indicated by this bit, 10 clock cycles after it occurs. disabled, the data of the remaining channel is repeated in both the rising and falling output clock cycles. Table 10. Output Data Format VIN+ − VIN−, Input (V) Input Span = 1.75 V p-p (V) Offset Binary Output Mode Twos Complement Mode (Default) OR VIN+ − VIN– <–0.875 00 0000 0000 0000 10 0000 0000 0000 1 VIN+ − VIN– –0.875 00 0000 0000 0000 10 0000 0000 0000 0 VIN+ − VIN– 0 10 0000 0000 0000 00 0000 0000 0000 0 VIN+ − VIN– +0.875 11 1111 1111 1111 01 1111 1111 1111 0 VIN+ − VIN– >+0.875 11 1111 1111 1111 01 1111 1111 1111 1 Rev. A | Page 21 of 40 AD6649 Data Sheet DIGITAL PROCESSING Two fixed-coefficient FIR filters provide filtering capability. A The AD6649 includes a digital processing section that provides low latency FIR or a high performance FIR can be selected. It filtering. This digital processing section includes a numerically removes the negative frequency images to avoid aliasing negative controlled oscillator (NCO), a selectable FIR filter (high perfor- frequencies for real outputs. Figure 38, Figure 39, and Figure 40 mance or low latency), and a second coarse NCO (f /4 fixed S show the progression of a 95 MHz bandwidth signal through the value) for output frequency translation (complex to real). These filter stages when using the fixed-frequency NCO and 95 MHz FIR blocks can be configured in several modes to implement a filter with a sample rate of 245.76 MSPS. The tunable-frequency signal processing function. Refer to Figure 1 for the functional NCO can be used instead and operates in a similar fashion. In block diagram of the AD6649. these modes, the output is centered at 61.44 MHz, assuming a NUMERICALLY CONTROLLED OSCILLATOR (NCO) 245.76 MSPS sample rate. Frequency translation is accomplished with an NCO shared f /4 FIXED-FREQUENCY NCO S between the two channels. Amplitude and phase dither can be A fixed-frequency f /4 NCO is provided to translate the filtered, enabled on chip to improve the noise and spurious performance of S decimated signal from dc to f /4 to allow a real output. The f /4 the NCO. S S NCO is required in all operation modes because complex Because the filtering prevents usage of part of the Nyquist output from the part is not supported. spectrum, a means is needed to translate the sampled input REAL ADC INPUT spectrum into the usable range of the decimation filter. To achieve this, a 32-bit, tuning, complex NCO is provided. This NCO/mixer allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. –108.94 –61.44 –13.94 0 13.94 61.44 108.94 122.88 When using the low latency FIR, the NCO must be tuned to f /4 S Figure 38. Example AD6649 Real 95 MHz Bandwidth Input Signal Centered at (0x40000000). This prevents unwanted aliases from falling back 61.44 MHz (f = 245.76 MHz) ADC into the band of interest. COMPLEX ADC OUTPUT/NCO OUTPUT NCO AND FIR FILTER MODES The NCO and FIR blocks can be used in two modes depending on the bandwidth and latency requirement of the application. The two modes of operation of these blocks are summarized in Table 11. –122.88 –75.38 –47.5 0 47.5 75.38 122.88 Table 11. Signal Path Modes Figure 39. Example AD6649 95 MHz Bandwidth Input Signal Tuned to DC Using the NCO (NCO Frequency = 61.44 MHz) Output Bandwidth at TUNED NCO OUTPUT Mode FIR 245.76 MSPS Fixed-Frequency NCO, Low latency 95 MHz 95 MHz FIR Filter (default) Tunable-Frequency NCO, High performance 99.5 MHz 100 MHz FIR Filter 0 13.94 61.44 108.94 122.88 Figure 40. Example AD6649 95 MHz Bandwidth Output Signal Tuned to f /4 S (NCO Frequency = 61.44 MHz) Rev. A | Page 22 of 40 09635-247 09635-042 09635-043 Data Sheet AD6649 NUMERICALLY CONTROLLED OSCILLATOR (NCO) NCO SYNCHRONIZATION FREQUENCY TRANSLATION The AD6649 NCOs within a single part or across multiple parts This processing stage comprises a digital tuner consisting of can be synchronized using the external SYNC input. Bit 0 and a 32-bit complex numerically controlled oscillator (NCO). The Bit 1 of Register 0x58 allow the NCO to be resynchronized on NCO is always enabled. This NCO block accepts a real input every SYNC signal or only on the first SYNC signal after the from the ADC stage and outputs a frequency translated register is written. A valid SYNC causes the NCO to restart at complex (I and Q) output. the programmed phase offset value. The NCO frequency is programmed in Register 0x52 through NCO AMPLITUDE AND PHASE DITHER Register 0x55. These four 8-bit registers make up a 32-bit unsigned frequency programming word. Frequencies between The NCO block contains amplitude and phase dither to improve −CLK/2 and +CLK/2 are represented using the following the spurious performance. Amplitude dither improves perfor- frequency words: mance by randomizing the amplitude quantization errors within the angular-to-Cartesian conversion of the NCO. This option • 0x80000000 represents a frequency given by −CLK/2. reduces spurs at the expense of a slightly raised noise floor. With • 0x00000000 represents dc (frequency = 0 Hz). amplitude dither enabled, the NCO has an SNR of greater than 32 • 0x7FFFFFFF represents CLK/2 − CLK/2 . 93 dB and an SFDR of greater than 115 dB. With amplitude dither Use the following equation to calculate the NCO frequency: disabled, the SNR is increased to greater than 96 dB at the cost of SFDR performance, which is reduced to 100 dB. The NCO Mod( f , f ) 32 CLK NCO_FREQ= 2 × amplitude and phase dither are recommended and can be enabled f CLK by setting Bit 1 and Bit 2 in Register 0x51. where: NCO_FREQ is a 32-bit twos complement number representing the NCO frequency register. f is the desired carrier frequency in hertz. f is the AD6649 ADC clock rate in hertz. CLK Rev. A | Page 23 of 40 AD6649 Data Sheet FIR FILTERS The two FIR filters that can be used are either a 47-tap, high part in this mode, set SPI Register 0x50 to 0xB0. When operating performance, fixed-coefficient FIR filter or a 21-tap, low latency, in this mode, the NCO must be placed at f /4, and the low latency S fixed-coefficient FIR filter. These filters are useful in providing NCO select bit (Bit 0) in Register 0x5A must be set. It is important alias protection at the device output. The high performance FIR to note that a −1.0 dBFS input level at the analog inputs corresponds is a simple sum-of-products FIR filter with 47 filter taps and to an output level of −2.5 dBFS when using the low latency FIR 21-bit fixed coefficients. Note that this filter does not decimate. filter. This output level reduction is a result of the −1.5 dB pass- The normalized coefficients used in the implementation and the band attenuation in the FIR filter in this mode and does not decimal equivalent value of the coefficients are listed in Table 12. result in loss in the dynamic range of the converter. 0 Table 12. High Performance FIR Filter Coefficients Coefficient Normalized Decimal Coefficient Number Coefficient (21-Bit) –1 C0, C46 −0.0001335 −140 C1, C45 −0.0009689 −1016 C2, C44 −0.0024185 −2536 –2 C3, C43 −0.0019341 −2028 C4, C42 0.0023584 2473 C5, C41 0.0051260 5375 –3 C6, C40 −0.0009680 −1015 C7, C39 −0.0086231 −9042 C8, C38 −0.0011368 −1192 –4 0 30.72 61.44 92.16 122.88 C9, C37 0.0142097 14900 FILTER RESPONSE (MHz) C10, C36 0.0064697 6784 Figure 41. Low Latency FIR Filter Composite Response at 245.76 MSPS C11, C35 −0.0207596 −21768 (Fixed-Frequency NCO, 95 MHz FIR Filter Mode) C12, C34 −0.0161047 −16887 –1.000 C13, C33 0.0274601 28794 C14, C32 0.0310631 32572 C15, C31 −0.0348339 −36526 –1.125 C16, C30 −0.0557785 −58488 C17, C29 0.0415993 43620 C18, C28 0.0986786 103472 –1.250 C19, C27 −0.0463982 −48652 C20, C26 −0.1893501 −198548 C21, C25 0.0505829 53040 –1.375 C22, C24 0.6113434 641040 C23 0.9171314 961682 –1.500 0 30.72 61.44 92.16 122.88 FIR SYNCHRONIZATION FILTER RESPONSE (MHz) Figure 42. Low Latency FIR Filter Pass-Band Response at 245.76 MSPS The AD6649 filters within a single part or across multiple parts can (Fixed-Frequency NCO, 95 MHz FIR Filter Mode) be synchronized using the external SYNC input. The filters can be configured to be resynchronized on every SYNC signal or only When using the tunable-frequency NCO and 100 MHz FIR filter, on the first SYNC signal after the SPI control register is written. the output rate is equal to the sample clock rate. The response of A valid SYNC causes the FIR filter to restart at the programmed the high performance FIR filter is shown in Figure 43. The detailed pass-band response for this mode is shown in Figure 44. To place decimation phase value. Bit 4 and Bit 5 of Register 0x58 allow the part into this mode, set SPI Register 0x50 to 0xA0. When the FIR to be resynchronized on every SYNC signal or only on using the high performance FIR filter, the output level is −1.3 dBFS the first SYNC signal after the register is written. for a corresponding input level of −1.0 dBFS at the analog inputs. FILTER PERFORMANCE This is a result of the −0.3 dB pass-band attenuation of the FIR When using the fixed-frequency NCO and a 95 MHz FIR filter, filter in this mode and does not result in loss in the dynamic range the output rate is equal to the sample clock rate. The composite of the converter. response of this mode is shown in Figure 41. The detailed pass- band response for this mode is shown in Figure 42. To place the Rev. A | Page 24 of 40 AMPLITUDE (dBc) AMPLITUDE (dBc) 09635-144 09635-145 Data Sheet AD6649 0 OUTPUT NCO –10 The output of the 32-bit fine-tuning NCO is complex and –20 typically centered in frequency around dc. This complex output –30 is carried through the stages of either the 95 MHz or 100 MHz FIR –40 filter to provide proper antialiasing filtering. The final NCO –50 provides a means to move this complex output signal away from –60 dc so that a real output can be provided from the AD6649. The –70 output NCO translates the output from dc to a frequency equal –80 to the output frequency divided by 4 (f /4). This provides the user –90 S with an output signal centered at f /4 in frequency. –100 S –110 The AD6649 output NCOs within a single part or across –120 multiple parts can be synchronized using the external SYNC 0 30.72 61.44 92.16 122.88 FILTER RESPONSE (MHz) input. Bit 7 and Bit 6 of Register 0x58 allow the output NCO to be resynchronized on every SYNC signal or only on the first Figure 43. High Performance FIR Filter Pass-Band Response at 245.76 MSPS (Tunable-Frequency NCO, 100 MHz FIR Filter) SYNC signal after the register is written. 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1.0 0 15.36 30.72 46.08 61.44 FILTER RESPONSE (MHz) Figure 44. High Performance FIR Filter Pass-Band Response at 245.76 MSPS (Tunable-Frequency NCO, 100 MHz FIR Filter) Rev. A | Page 25 of 40 AMPLITUDE (dBc) AMPLITUDE (dBc) 09635-147 09635-146 AD6649 Data Sheet ADC OVERRANGE AND GAIN CONTROL In receiver applications, it is desirable to have a mechanism to an indicator that can be used to quickly insert an attenuator that reliably determine when the converter is about to be clipped. prevents ADC overdrive. The standard overflow indicator provides delayed information Fast Threshold Detection (FDA and FDB) on the state of the analog input that is of limited value in preventing The FD indicator is asserted if the input magnitude exceeds the clipping. Therefore, it is helpful to have a programmable threshold value programmed in the fast detect upper threshold register, below full scale that allows time to reduce the gain before the clip located in Register 0x47 and Register 0x48. The selected threshold occurs. In addition, because input signals can have significant register is compared with the signal magnitude at the output of slew rates, latency of this function is of concern. the ADC. The fast upper threshold detection has a latency of Using the SPI port, the user can provide a threshold above which 4 clock cycles. The upper threshold magnitude is defined by the the FD output is active. Bit 0 of SPI Register 0x45 allows the user to following equation: select the threshold level. As long as the signal is below the selected Upper Threshold Magnitude (dBFS) threshold, the FD output remains low. In this mode, the magnitude 13 = 20 log(Threshold Magnitude/2 ) of the data is considered in the calculation of the condition, but the sign of the data is not considered. The threshold detection The FD indicators are not cleared until the signal drops below responds identically to positive and negative signals outside the the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold desired range (magnitude). register, located at Register 0x49 and Register 0x4A. The fast ADC OVERRANGE (OR) detect lower threshold register is a 15-bit register that is The ADC overrange indicator is asserted when an overrange is compared with the signal magnitude at the output of the ADC. detected on the input of the ADC. The overrange condition is This comparison is subject to the ADC pipeline latency but is determined at the output of the ADC pipeline and, therefore, is accurate in terms of converter resolution. The lower threshold subject to a latency of 7 ADC clock cycles. An overrange at the magnitude is defined by the following equation: input is indicated by this bit 7 clock cycles after it occurs. Lower Threshold Magnitude (dBFS) 13 GAIN SWITCHING = 20 log(Threshold Magnitude/2 ) The AD6649 includes circuitry that is useful in applications The dwell time can be programmed from 1 to 65,535 sample either where large dynamic ranges exist or where gain ranging clock cycles by placing the desired value in the fast detect dwell amplifiers are employed. This circuitry allows digital thresholds time register, located in Register 0x4B and Register 0x4C. to be set such that an upper threshold and a lower threshold can The operation of the upper threshold and lower threshold be programmed. registers, along with the dwell time, is shown in Figure 45. One such use is to detect when an ADC is about to reach full scale with a particular input condition. The result is to provide UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LT LOWER THRESHOLD DWELL TIME TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LT FDA OR FDB Figure 45. Threshold Settings for FDA and FDB Signals Rev. A | Page 26 of 40 MIDSCALE 09635-148 Data Sheet AD6649 DC CORRECTION Because the dc offset of the ADC may be significantly larger DC Correction Readback than the signal being measured, a dc correction circuit is included The current dc correction value can be read back in Register 0x41 to null the dc offset before measuring the power. The dc correction and Register 0x42 for each channel. The dc correction value is a circuit can also be switched into the main signal path, but this 16-bit value that can span the entire input range of the ADC. may not be appropriate if the ADC is digitizing a time-varying DC Correction Freeze signal with significant dc content, such as GSM. Setting Bit 6 of Register 0x40 freezes the DC correction at its DC Correction Bandwidth current state and continues to use the last updated value as the The dc correction circuit is a high-pass filter with a program- dc correction value. Clearing this bit restarts dc correction and mable bandwidth (ranging between 0.29 Hz and 2.387 kHz at adds the currently calculated value to the data. 245.76 MSPS). The bandwidth is controlled by writing the 4-bit DC Correction Enable Bits dc correction bandwidth select register, located at Register 0x40, Setting Bit 1 of Register 0x40 enables dc correction for use in Bits[5:2]. The following equation can be used to compute the the output data signal path. bandwidth value for the dc correction circuit: f /k/14 CLK DC _ Corr _ BW= 2 × 2×π where: k is the 4-bit value programmed in Bits[5:2] of Register 0x40 (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). f is the AD6649 ADC sample rate in hertz. CLK Rev. A | Page 27 of 40 AD6649 Data Sheet CHANNEL/CHIP SYNCHRONIZATION The AD6649 has a SYNC input that allows the user flexible syn- The SYNC input is internally synchronized to the sample clock. chronization options for synchronizing the internal blocks. The However, to ensure that there is no timing uncertainty between SYNC feature is useful for guaranteeing synchronized operation multiple parts, the SYNC input signal should be synchronized across multiple ADCs. The input clock divider, NCO, FIR filters, to the input clock signal. The SYNC input should be driven and the output f /4 NCO can be synchronized using the SYNC using a single-ended CMOS type signal. S input. Each of these blocks can be enabled to synchronize on a If Bit 1 in Register 0x59 is used, the SYNC input can be set to single occurrence of the SYNC signal or on every occurrence by either level or edge sensitive mode. If the SYNC input is set to setting the appropriate bits in Register 0x58. edge sensitive mode, Bit 0 of Register 0x59 can be used to determine whether the rising or falling edge is used. The settings written to Register 0x59 apply only to the FIR filters and the NCOs. Rev. A | Page 28 of 40 Data Sheet AD6649 SERIAL PORT INTERFACE (SPI) The AD6649 serial port interface (SPI) allows the user to configure All data is composed of 8-bit words. The first bit of each individual the converter for specific functions or operations through a byte of serial data indicates whether a read or write command is structured register space provided inside the ADC. The SPI issued. This allows the serial data input/output (SDIO) pin to gives the user added flexibility and customization, depending on change direction from an input to an output. the application. Addresses are accessed via the serial port and In addition to word length, the instruction phase determines can be written to or read from via the port. Memory is organized whether the serial frame is a read or write operation, allowing into bytes that can be further divided into fields. These fields are the serial port to be used both to program the chip and to read documented in the Memory Map section. For detailed operational the contents of the on-chip memory. If the instruction is a readback information, see the AN-877 Application Note, Interfacing to operation, performing a readback causes the serial data input/ High Speed ADCs via SPI. output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. CONFIGURATION USING THE SPI Data can be sent in MSB first mode or in LSB first mode. MSB Three pins define the SPI of this ADC: the SCLK pin, the first is the default on power-up and can be changed via the SPI SDIO pin, and the CSB pin (see Table 13). The SCLK (serial port configuration register. For more information about this clock) pin is used to synchronize the read and write data presented and other features, see the AN-877 Application Note, Interfacing from/to the ADC. The SDIO (serial data input/output) pin is a to High Speed ADCs via SPI. dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) HARDWARE INTERFACE pin is an active low control that enables or disables the read and The pins described in Table 13 comprise the physical interface write cycles. between the user programming device and the serial port of the Table 13. Serial Port Interface Pins AD6649. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, Pin Function functioning as an input during write phases and as an output SCLK Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. during readback. SDIO Serial Data Input/Output. A dual-purpose pin that The SPI interface is flexible enough to be controlled by either typically serves as an input or an output, depending on FPGAs or microcontrollers. One method for SPI configuration the instruction being sent and the relative position in the is described in detail in the AN-812 Application Note, Micro- timing frame. controller-Based Serial Port Interface (SPI) Boot Circuit. CSB Chip Select Bar. An active low control that gates the read and write cycles. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the The falling edge of the CSB, in conjunction with the rising edge SCLK signal, the CSB signal, and the SDIO signal are typically of the SCLK, determines the start of the framing. An example of asynchronous to the ADC clock, noise from these signals can the serial timing and its definitions can be found in Figure 46 degrade converter performance. If the on-board SPI bus is used for and Table 5. other devices, it may be necessary to provide buffers between this bus and the AD6649 to prevent these signals from transi- Other modes involving the CSB are available. The CSB can be tioning at the converter inputs during critical sampling periods. held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. Rev. A | Page 29 of 40 AD6649 Data Sheet SPI ACCESSIBLE FEATURES Table 14 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD6649 part-specific features are described in the Memory Map Register Description section. Table 14. Features Accessible Using the SPI Feature Name Description Mode Allows the user to set either power-down mode or standby mode Clock Allows the user to access the DCS via the SPI Offset Allows the user to digitally adjust the converter offset Test I/O Allows the user to set test modes to have known data on output bits Output Mode Allows the user to set up outputs Output Phase Allows the user to set the output clock polarity Output Delay Allows the user to vary the DCO delay VREF Allows the user to set the reference voltage Digital Processing Allows the user to enable the NCOs, FIR filters, and synchronization features t HIGH t DS t t CLK H t t S DH t LOW CSB SCLK DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 SDIO DON’T CARE DON’T CARE Figure 46. Serial Port Interface Timing Diagram Rev. A | Page 30 of 40 09635-079 Data Sheet AD6649 MEMORY MAP Logic Levels READING THE MEMORY MAP REGISTER TABLE An explanation of logic level terminology follows: Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip • “Bit is set” is synonymous with “bit is set to Logic 1” or configuration registers (Address 0x00 to Address 0x02); the “writing Logic 1 for the bit.” channel index and transfer registers (Address 0x05 and • “Clear a bit” is synonymous with “bit is set to Logic 0” or Address 0xFF); the ADC functions registers, including setup, “writing Logic 0 for the bit.” control, and test (Address 0x08 to Address 0x3A); and the digital Transfer Register Map feature control registers (Address 0x40 to Address 0x5A). Address 0x08 to Address 0x20, Address 0x3A, Address 0x40 to The memory map register table (see Table 15) documents the Address 0x42, Address 0x45 to 0x4C, and Address 0x50 to default hexadecimal value for each hexadecimal address shown. Address 0x5A are shadowed. Writes to these addresses do The column with the heading Bit 7 (MSB) is the start of the not affect part operation until a transfer command is issued by default hexadecimal value given. For example, Address 0x14, writing 0x01 to Address 0xFF, setting the transfer bit. This allows the output mode register, has a hexadecimal default value of these registers to be updated internally and simultaneously when 0x05. This means that Bit 0 = 1 and the remaining bits are 0s. the transfer bit is set. The internal update takes place when the This setting is the default output format value, which is twos transfer bit is set, and then the bit autoclears. complement. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed Channel-Specific Registers ADCs via SPI. This document details the functions controlled Some channel setup functions, such as the signal monitor thresh- by Register 0x00 to Register 0x25. The remaining registers, from olds, can be programmed to a different value for each channel. Register 0x3A to Register 0x5A, are documented in the Memory In these cases, channel address locations are internally duplicated Map Register Description section. for each channel. These registers and bits are designated in Table 15 Open and Reserved Locations as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If All address and bit locations that are not included in Table 15 both bits are set, the subsequent write affects the registers of both are not currently supported for this device. Unused bits of a channels. In a read cycle, only Channel A or Channel B should valid address location should be written with 0s. Writing to these be set to read one of the two registers. If both bits are set during locations is required only when part of an address location is an SPI read cycle, the part returns the value for Channel A. open (for example, Address 0x18). If the entire address location Registers and bits designated as global in Table 15 affect the is open (for example, Address 0x13), this address location should entire part and the channel features for which independent not be written. settings are not allowed between channels. The settings in Default Values Register 0x05 do not affect the global registers and bits. After the AD6649 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 15. Rev. A | Page 31 of 40 AD6649 Data Sheet MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 15 are not currently supported for this device. Table 15. Memory Map Registers Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles configuration are 1 (global) mirrored so that LSB first mode or MSB first mode registers correctly, regardless of shift mode. 0x01 Chip ID 8-bit chip ID[7:0] 0xA1 Read only. (AD6649 = 0xA1) (global) (default) 0x02 Chip grade Open Open Speed grade ID Open Open Open Open Speed (global) grade ID 00 = 250 MSPS used to differentiate devices; read only. Channel Index and Transfer Registers 0x05 Channel index Open Open Open Open Open Open ADC B ADC A 0x03 Bits are set (global) (default) (default) to determine which device on the chip receives the next write command; applies to local registers only. 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchro- (global) nously transfers data from the master shift register to the slave. ADC Functions 0x08 Power modes Open Open External Open Open Open Internal power-down 0x00 Determines (local) power- mode (local) various down pin generic 00 = normal operation function modes of 01 = full power-down (local) chip 10 = standby operation. 0 = power- 11 = reserved down 1 = standby 0x09 Global clock Open Open Open Open Open Open Open Duty cycle 0x01 (global) stabilizer (default) 0x0B Clock divide Open Open Input clock divider phase adjust Clock divide ratio 0x00 Clock divide (global) values 000 = no delay 000 = divide by 1 other than 001 = 1 input clock cycle 001 = divide by 2 000 auto- 010 = 2 input clock cycles 010 = divide by 3 matically 011 = 3 input clock cycles 011 = divide by 4 cause the 100 = 4 input clock cycles 100 = divide by 5 101 = 5 input clock cycles 101 = divide by 6 duty cycle stabilizer 110 = 6 input clock cycles 110 = divide by 7 to become 111 = 7 input clock cycles 111 = divide by 8 active. Rev. A | Page 32 of 40 Data Sheet AD6649 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0D Test mode User test Open Reset PN Reset PN Output test mode 0x00 When this (local) mode long gen short gen register is 0000 = off (default) control set, 0001 = midscale short the test 0 = con- 0010 = positive FS data tinuous/ 0011 = negative FS is placed repeat 0100 = alternating checkerboard on the pattern 0101 = PN long sequence output pins 1 = single 0110 = PN short sequence in place of pattern, 0111 = one/zero word toggle normal then 0s 1000 = user test mode 1001 to 1110 = unused data. 1111 = ramp output 0x0E BIST enable Open Open Open Open Open Reset BIST Open BIST enable 0x00 (local) sequence 0x10 Offset adjust Open Open Offset adjust in LSBs from +31 to −32 0x00 (local) (twos complement format) 0x14 Output mode Open Open Open Output Open Output Output format 0x05 Configures enable bar the invert (local) 00 = offset binary (local) outputs 1 = normal 01 = twos complement and (default) (default) the format 0 = inverted 10 = gray code 11 = reserved (local) of the data. 0x15 Output adjust Open Open Open Open LVDS output drive current adjust 0x01 (global) 0000 = 3.72 mA output drive current 0001 = 3.5 mA output drive current (default) 0010 = 3.30 mA output drive current 0011 = 2.96 mA output drive current 0100 = 2.82 mA output drive current 0101 = 2.57 mA output drive current 0110 = 2.27 mA output drive current 0111 = 2.0 mA output drive current (reduced range) 1000 to 1111 = reserved 0x16 Clock phase Invert Open Open Open Open Open Open Open 0x00 control DCO clock (global) 0x17 DCO output Enable Open Open DCO clock delay 0x00 delay (global) DCO [delay = (3100 ps × register value/31 +100)] clock 00000 = 100 ps delay 00001 = 200 ps 00010 = 300 ps … 11110 = 3100 ps 11111 = 3200 ps 0x18 Input span Open Open Open Full-scale input voltage selection 0x00 Full-scale select input 01111 = 2.087 V p-p (global) adjustment … in 0.022 V 00001 = 1.772 V p-p steps. 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p … 10000 = 1.383 V p-p 0x19 User Test User Test Pattern 1[7:0] 0x00 Pattern 1 LSB (global) 0x1A User Test User Test Pattern 1[15:8] 0x00 Pattern 1 MSB (global) 0x1B User Test User Test Pattern 2[7:0] 0x00 Pattern 2 LSB (global) 0x1C User Test User Test Pattern 2[15:8] 0x00 Pattern 2 MSB (global) 0x1D User Test User Test Pattern 3[7:0] 0x00 Pattern 3 LSB (global) 0x1E User Test User Test Pattern 3[15:8] 0x00 Pattern 3 MSB (global) Rev. A | Page 33 of 40 AD6649 Data Sheet Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x1F User Test User Test Pattern 4[7:0] 0x00 Pattern 4 LSB (global) 0x20 User Test User Test Pattern 4[15:8] 0x00 Pattern 4 MSB (global) 0x24 BIST signature BIST signature[7:0] 0x00 Read only. LSB (local) 0x25 BIST signature BIST signature[15:8] 0x00 Read only. MSB (local) 0x3A Sync control Open Open Open Open Open Clock Clock Master sync 0x00 (global) divider divider buffer enable next sync sync only enable Digital Feature Control Registers 0x40 DC correction Open DC DC correction bandwidth select DC Open 0x00 control correction correction 0000 = 2387.32 Hz (local) freeze enable 0001 = 1193.66 Hz 0010 = 596.83 Hz 0011 = 298.42 Hz 0100 = 149.21 Hz 0101 = 74.60 Hz 0110 = 37.30 Hz 0111 = 18.65 Hz 1000 = 9.33 Hz 1001 = 4.66 Hz 1010 = 2.33 Hz 1011 = 1.17 Hz 1100 = 0.58 Hz 1101 = 0.29 Hz 1110 = reserved 1111 = reserved 0x41 DC Correction DC correction value[7:0] Read only. Value 0 (local) 0x42 DC Correction DC correction value[15:8] Read only. Value 1 (local) 0x45 Fast detect Open Open Open Open Force FD Force FD Reserved Enable fast 0x00 control (local) output output detect output enable value 0x47 Fast Detect Fast detect upper threshold[7:0] 0x00 Upper Threshold 0 (local) 0x48 Fast Detect Open Open Open Fast detect upper threshold[12:8] 0x00 Upper Threshold 1 (local) 0x49 Fast Detect Fast detect lower threshold[7:0] 0x00 Lower Threshold 0 (local) 0x4A Fast Detect Open Open Open Fast detect lower threshold[12:8] 0x00 Lower Threshold 1 (local) 0x4B Fast Detect Fast detect dwell time[7:0] 0x00 Dwell Time 0 (local) 0x4C Fast Detect Fast detect dwell time[15:8] 0x00 Dwell Time 1 (local) 0x50 Filter control 1 Reserved 1 FIR mode Output 9-bit Datapath gain 0xB0 (local) gain output 0 = high 00 = 0 dB mode perfor- 0 = 0 dB 01 = −6 dB enable mance 1 = −6 dB 10 = −12 dB 1 = low 11 = −18 dB latency Rev. A | Page 34 of 40 Data Sheet AD6649 Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x51 NCO control Reserved NCO32 to Spectral 1 Reserved NCO32 NCO32 1 0x51 (local) f /4 NCO reversal amplitude phase S sync dither dither enable enable enable 0x52 NCO NCO frequency value[31:24] 0x40 Frequency 3 (local) 0x53 NCO NCO frequency value[23:16] 0x00 Frequency 2 (local) 0x54 NCO NCO frequency value[15:8] 0x00 Frequency 1 (local) 0x55 NCO NCO frequency value[7:0] 0x00 Frequency 0 (local) 0x56 NCO Phase NCO phase value[15:8] 0x00 Offset 1 (local) 0x57 NCO Phase NCO phase value[7:0] 0x00 Offset 0 (local) 0x58 Sync control f /4 NCO f /4 NCO FIR next FIR Sync Reserved Reserved NCO32 NCO32 sync 0x00 S S next sync sync next sync (local) sync only Enable enable only enable only 0x59 NCO/FIR sync Open Open Open Open Open Open SYNC pin SYNC pin 0x00 pin control sensitivity edge (local) sensitivity 0 = sync on high level 0 = sync on 1 = sync on falling edge edge 1 = sync on rising edge 0x5A NCO Control 2 Open Open Open Open Open Open Open Low latency 0x01 (local) NCO select 1 The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00. Rev. A | Page 35 of 40 AD6649 Data Sheet MEMORY MAP REGISTER DESCRIPTION Bit 2—Force FD Output Value For more information on functions controlled in Register 0x00 The value written to Bit 2 is forced on the FD output pin when to Register 0x25, see the AN-877 Application Note, Interfacing Bit 3 is written high. to High Speed ADCs via SPI. Bit 1—Reserved Sync Control (Register 0x3A) Bit 0—Enable Fast Detect Output Bits[7:3]—Reserved Setting this bit high enables the output of the upper threshold Bit 2—Clock Divider Next Sync Only FD comparator to drive the FD output pin. If the master sync buffer enable bit (Address 0x3A, Bit 0) and Fast Detect Upper Threshold the clock divider sync enable bit (Address 0x3A, Bit 1) are high, (Register 0x47 and Register 0x48) Bit 2 allows the clock divider to sync to the first sync pulse that it Register 0x48, Bits[7:5]—Reserved receives and to ignore the rest. The clock divider sync enable bit Register 0x48, Bits[4:0]—Fast Detect Upper Threshold[12:8] (Address 0x3A, Bit 1) resets after it syncs. Register 0x47, Bits[7:0]—Fast Detect Upper Threshold[7:0] Bit 1—Clock Divider Sync Enable These registers provide an upper limit threshold. The 13-bit Bit 1 gates the sync pulse to the clock divider. The sync signal is value is compared with the output magnitude from the ADC enabled when Bit 1 is high and Bit 0 is high. This is continuous block. If the ADC magnitude exceeds this threshold value, the sync mode. FD output pin is set if Bit 0 in Register 0x45 is set. Bit 0—Master Sync Buffer Enable Fast Detect Lower Threshold Bit 0 must be set high to enable any of the sync functions. If (Register 0x49 and Register 0x4A) the sync capability is not used, this bit should remain low to Register 0x4A, Bits[7:5]—Reserved conserve power. Register 0x4A, Bits[4:0]—Fast Detect Lower Threshold[12:8] DC Correction Control (Register 0x40) Register 0x49, Bits[7:0]—Fast Detect Lower Threshold[7:0] Bit 7—Reserved These registers provide a lower limit threshold. The 13-bit value Bit 6—DC Correction Freeze is compared with the output magnitude from the ADC block. If When Bit 6 is set high, the dc correction is no longer updated to the ADC magnitude is less than this threshold value for the the signal monitor block, which holds the last dc value calculated. number of cycles programmed in the dwell time register, the FD output bit is cleared. Bits[5:2]—DC Correction Bandwidth Select Fast Detect Dwell Time Bits[5:2] set the averaging time of the signal monitor dc (Register 0x4B and Register 0x4C) correction function. This 4-bit word sets the bandwidth of the Register 0x4C, Bits[7:0]—Fast Detect Dwell Time[15:8] correction block, according to the following equation: Register 0x4B, Bits[7:0]—Fast Detect Dwell Time[7:0] f /k/14 CLK DC _ Corr _ BW= 2 × 2×π These register values set the minimum time in ADC sample clock cycles (after clock divider) that a signal needs to stay below where: the lower threshold limit before the FD output bits are cleared. k is the 4-bit value programmed in Bits[5:2] of Register 0x40 (values between 0 and 13 are valid for k; programming 14 or 15 Filter Control (Register 0x50) provides the same result as programming 13). Bit 7—Reserved (Reads Back as 1) f is the AD6649 ADC sample rate in hertz. CLK Bit 6—Reserved Bit 1—DC Correction Enable Bit 5—Reserved (Reads Back as 1) Setting this bit high causes the output of the dc measurement Bit 4—FIR Mode block to be summed with the data in the signal path to remove Setting this bit low enables the high performance FIR filter. the dc offset from the signal path. Setting this bit high enables the low latency FIR. Bit 0—Reserved Bit 3—Output Gain Fast Detect Control (Register 0x45) Setting this bit high sets the output gain to −6 dB. A 0 value on Bits[7:4]—Reserved this bit sets the gain at 0 dB. Bit 3—Force FD Output Enable Setting this bit high forces the FD output pin to the value written to Bit 2 of this register (Register 0x45). This enables the user to force a known value on the FD pin for debugging. Rev. A | Page 36 of 40 Data Sheet AD6649 NCO Phase Offset (Register 0x56 and Register 0x57) Bit 2—9-bit Output Mode Enable Register 0x56, Bits[7:0]—NCO Phase Value[15:8] If this bit is set, the NCOs and filters are bypassed and the part outputs nine bits of data. These nine bits are presented on the Register 0x57, Bits[7:0]—NCO Phase Value[7:0] nine MSBs of the output bus (that is, Bit D13 through Bit D5). The 16-bit value programmed into the NCO phase value register Bits[1:0]—Datapath Gain is loaded into the NCO block each time the NCO is started or when an NCO SYNC signal is received. This process allows the These bits set the datapath gain as follows: NCO to be started with a known nonzero phase. 00 = 0 dB gain Use the following equation to calculate the NCO phase offset value: 01 = −6 dB gain 16 NCO_PHASE = 2 × PHASE/360 10 = −12 dB gain where NCO_PHASE is a decimal number equal to the 16-bit binary 11 = −18 dB gain number to be programmed at Register 0x56 and Register 0x57, NCO Control (Register 0x51) and PHASE is the desired NCO phase in degrees. Bit 7—Reserved SYNC Control (Register 0x58) Bit 6—NCO32 to f /4 NCO Sync Enable S Bit 7—f /4 NCO Next Sync Only S This bit should be set high when NCO32 is set to f /4 using the If the master sync buffer enable bit (Register 0x3A, Bit 0) and S fixed-frequency NCO and the 95 MHz FIR filter. It should be the f /4 NCO sync enable bit (Register 0x58, Bit 6) are high, Bit 7 S disabled when using the tunable-frequency NCO and 100 MHz allows the f /4 NCO to synchronize following the first sync S FIR filter. pulse that it receives and ignore the rest. If Bit 7 is set, Bit 6 of Register 0x58 resets after this sync occurs. Bit 5—Spectral Reversal Bit 6—f /4 NCO Sync Enable This bit should be set high to reverse the output frequency S spectrum. Bit 6 gates the sync pulse to the f /4 NCO. When Bit 6 is set S high, the sync signal causes the f /4 NCO to synchronize. S Bit 4—Reserved (Reads Back as 1) This sync is active only when the master sync buffer enable bit Bit 3—Reserved (Register 0x3A, Bit 0) is high. This is continuous sync mode. Bit 2—NCO32 Amplitude Dither Enable Bit 5—FIR Next Sync Only When Bit 2 is set, amplitude dither in the NCO is enabled. If the master sync buffer enable bit (Register 0x3A, Bit 0) and the When Bit 2 is cleared, amplitude dither is disabled. FIR sync enable bit (Register 0x58, Bit 4) are high, Bit 5 allows Bit 1—NCO32 Phase Dither Enable the FIR to synchronize following the first sync pulse that it receives and to ignore the rest. If Bit 5 is set, Bit 4 of Register 0x3A resets When Bit 2 is set, phase dither in the NCO is enabled. When after this sync occurs. Bit 2 is cleared, phase dither is disabled. Bit 4—FIR Sync Enable Bit 0—Reserved (Reads Back as 1) Bit 4 gates the sync pulse to the FIR filter. When Bit 4 is set NCO Frequency (Register 0x52 to Register 0x55) high, the sync signal causes the half-band to resynchronize. Register 0x52, Bits[7:0]—NCO Frequency Value[31:24] This sync is active only when the master sync buffer enable bit Register 0x53, Bits[7:0]—NCO Frequency Value[23:16] (Register 0x3A, Bit 0) is high. This is continuous sync mode. Register 0x54, Bits[7:0]—NCO Frequency Value[15:8] Bits[3:2]—Reserved Register 0x55, Bits[7:0]—NCO Frequency Value[7:0] Bit 1—NCO32 Next Sync Only This 32-bit value is used to program the NCO tuning frequency. If the master sync buffer enable bit (Register 0x3A, Bit 0) and The frequency value to be programmed is given by the the NCO32 sync enable bit (Register 0x58, Bit 0) are high, Bit 1 following equation: allows the NCO32 to synchronize following the first sync pulse Mod( f , f ) that it receives and to ignore the rest. Bit 0 of Register 0x58 resets 32 CLK NCO_FREQ= 2 × after a sync occurs if Bit 1 is set. f CLK Bit 0—NCO32 Sync Enable where: NCO_FREQ is a 32-bit twos complement number representing Bit 0 gates the sync pulse to the 32-bit NCO. When this bit is set the NCO frequency register. high, the sync signal causes the NCO to resynchronize, starting f is the desired carrier frequency in hertz. at the NCO phase offset value. This sync is active only when the f is the AD6649 ADC clock rate in hertz. CLK master sync buffer enable bit (Register 0x3A, Bit 0) is high. This is continuous sync mode. Rev. A | Page 37 of 40 AD6649 Data Sheet NCO/FIR SYNC Pin Control (Register 0x59) NCO Control 2 (Register 0x5A) Bits[7:2]—Reserved Bits[7:1]—Reserved Bit 1—SYNC Pin Sensitivity Bit 0—Low Latency NCO Select If Bit 1 is set to a 0, the SYNC input responds to a level. If this If Bit 0 is set to a 1, the low latency NCO is selected. This bit bit is set low, the SYNC input responds to the edge (rising or should be selected for the fixed-frequency NCO, 95 MHz FIR falling) set in Bit 0 of Address 0x59. filter mode of operation. When this bit is set, the NCO value must be set to either 0x40000000 or 0xC0000000. Bit 0—SYNC Pin Edge Sensitivity If Bit 1 is set high, setting Bit 0 to a 0 causes the SYNC input to respond to a falling edge. If this bit is set, the SYNC input respond to a rising edge. Rev. A | Page 38 of 40 Data Sheet AD6649 APPLICATIONS INFORMATION VCM DESIGN GUIDELINES The VCM pin should be decoupled to ground with a 0.1 μF Before starting system level design and layout of the AD6649, capacitor, as shown in Figure 28. For optimal channel-to-channel it is recommended that the designer become familiar with these isolation, a 33 Ω resistor should be included between the AD6649 guidelines, which discuss the special circuit connections and VCM pin and the Channel A analog input network connection layout requirements needed for certain pins. and between the AD6649 VCM pin and the Channel B analog Power and Ground Recommendations input network connection. When connecting power to the AD6649, it is recommended SPI Port that two separate 1.8 V supplies be used: one supply should be The SPI port should not be active during periods when the full used for analog (AVDD), and a separate supply should be used dynamic performance of the converter is required. Because the for the digital outputs (DRVDD). The designer can employ SCLK, CSB, and SDIO signals are typically asynchronous to the several different decoupling capacitors to cover both high and ADC clock, noise from these signals can degrade converter low frequencies. These capacitors should be located close to the performance. If the on-board SPI bus is used for other devices, point of entry at the PC board level and close to the pins of the it may be necessary to provide buffers between this bus and the part with minimal trace length. AD6649 to keep these signals from transitioning at the converter A single PCB ground plane should be sufficient when using the inputs during critical sampling periods. AD6649. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD6649 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. See the evaluation board for a PCB layout example. For detailed information about packaging and PCB layout of chip scale packages, refer to the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). Rev. A | Page 39 of 40 AD6649 Data Sheet OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 6.35 8.75 BSC TOP VIEW EXPOSED PAD 6.20 SQ BSC SQ (BOTTOM VIEW) 6.05 0.50 33 16 0.40 32 17 0.30 0.25 MIN 7.50 REF 0.80 MAX 12° MAX 1.00 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 SEATING 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 47. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD6649BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD6649BCPZRL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD6649EBZ Evaluation Board with AD6649 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09635-0-9/11(A) Rev. A | Page 40 of 40 091707-C