ANALOG DEVICES AD6641

250 MHz Bandwidth DPD Observation Receiver AD6641 FEATURES GENERAL DESCRIPTION SNR = 65.8 dBFS at f up to 250 MHz at 500 MSPS The AD6641 is a 250 MHz bandwidth digital predistortion IN ENOB of 10.5 bits at f up to 250 MHz at 500 MSPS (−1.0 dBFS) IN (DPD) observation receiver that integrates a 12-bit 500 MSPS SFDR = 80 dBc at f up to 250 MHz at 500 MSPS (−1.0 dBFS) IN ADC, a 16k × 12 FIFO, and a multimode back end that allows Excellent linearity users to retrieve the data through a serial port (SPORT), the SPI DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS Integrated 16k × 12 FIFO port after being stored in the integrated FIFO memory. It is opti- FIFO readback options mized for outstanding dynamic performance and low power 12-bit parallel CMOS at 62.5 MHz consumption and is suitable for use in telecommunications 6-bit DDR LVDS interface applications such as a digital predistortion observation path SPORT at 62.5 MHz where wider bandwidths are desired. All necessary functions, SPI at 25 MHz including the sample-and-hold and voltage reference, are High speed synchronization capability included on the chip to provide a complete signal conversion 1 GHz full power analog bandwidth solution. Integrated input buffer The on-chip FIFO allows small snapshots of time to be captured On-chip reference, no external decoupling required via the ADC and read back at a lower rate. This reduces the Low power dissipation constraints of signal processing by transferring the captured 695 mW at 500 MSPS data at an arbitrary time and at a much lower sample rate. The Programmable input voltage range FIFO can be operated in several user-programmable modes. In 1.18 V to 1.6 V, 1.5 V nominal the single capture mode, the ADC data is captured when sig- 1.9 V analog and digital supply operation naled via the SPI port or the use of the external FILL± pins. In 1.9 V or 3.3 V SPI and SPORT operation the continuous capture mode, the data is loaded continuously Clock duty cycle stabilizer into the FIFO and the FILL± pins are used to stop this operation. Integrated data clock output with programmable clock and data alignment APPLICATIONS Wireless and wired broadband communications Communications test equipment Power amplifier linearization FUNCTIONAL BLOCK DIAGRAM FILL+ FILL– DUMP CLK+ CLOCK AND CONTROL CLK– PCLK+ PCLK– PARALLEL VIN+ PD[5:0]± IN DDR LVDS MODE AND FIFO OR PD[11:0] IN CMOS MODE ADC SPORT 16k × 12 VIN– SP_SCLK OUTPUTS SP_SDFS SP_SDO SPI CONTROL REFERENCE FULL AND DATA EMPTY VREF SCLK, SDIO, AND CSB Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09813-001 AD6641 TABLE OF CONTENTS Features .............................................................................................. 1  Thermal Resistance.................................................................... 10  Applications....................................................................................... 1  ESD Caution................................................................................ 10  General Description ......................................................................... 1  Pin Configurations and Function Descriptions ......................... 11  Functional Block Diagram .............................................................. 1  Typical Performance Characteristics ........................................... 15  Revision History ............................................................................... 2  Equivalent Circuits......................................................................... 18  Product Highlights ........................................................................... 3  SPI Register Map ............................................................................ 20  Specifications..................................................................................... 4  Theory of Operation ...................................................................... 23  DC Specifications ......................................................................... 4  FIFO Operation.......................................................................... 23  AC Specifications.......................................................................... 5  FIFO Output Interfaces ............................................................. 26  Digital Specifications ................................................................... 6  Configuration Using the SPI..................................................... 27  Switching Specifications .............................................................. 7  Outline Dimensions....................................................................... 28  SPI Timing Requirements ........................................................... 8  Ordering Guide .......................................................................... 28  Absolute Maximum Ratings.......................................................... 10  REVISION HISTORY 4/11—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD6641 The data stored in the FIFO can be read back based on several PRODUCT HIGHLIGHTS user-selectable output modes. The DUMP pin can be asserted 1. High Performance ADC Core. to output the FIFO data. The data stored in the FIFO can be Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input. accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit 2. Low Power. DDR LVDS interface. The maximum output throughput Consumes only 695 mW at 500 MSPS. supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR 3. Ease of Use. th LVDS mode and is internally limited to 1/8 of the maximum On-chip 16k FIFO allows the user to target the high perfor- input sample rate. This corresponds to the maximum output mance ADC to the time period of interest and reduce the data rate of 62.5 MHz at an input clock rate of 500 MSPS. constraints of processing the data by transferring it at an The ADC requires a 1.9 V analog voltage supply and a differen- arbitrary time and a lower sample rate. The on-chip refer- tial clock for full performance operation. Output format options ence and sample-and-hold provide flexibility in system include twos complement, offset binary format, or Gray code. A design. Use of a single 1.9 V supply simplifies system power data clock output is available for proper output data timing. Fabri- supply design. cated on an advanced SiGe BiCMOS process, the device is 4. Serial Port Control. available in a 56-lead LFCSP and is specified over the industrial Standard serial port interface supports configuration of the temperature range (−40°C to +85°C). This product is protected device and customization for the user’s needs. by a U.S. patent. 5. 1.9 V or 3.3 V SPI and Serial Data Port Operation. Rev. 0 | Page 3 of 28 AD6641 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.9 V, DRVDD = 1.9 V, T = −40°C, T = +85°C, f = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. MIN MAX IN Table 1. AD6641-500 1 Parameter Temp Min Typ Max Unit RESOLUTION 12 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full −2.6 0.0 +1.8 mV Gain Error Full −6.8 −2.3 +3.3 % FS Differential Nonlinearity (DNL) Full ±0.5 LSB Integral Nonlinearity (INL) Full ±0.6 LSB TEMPERATURE DRIFT Offset Error Full 18 μV/°C Gain Error Full 0.07 %/°C ANALOG INPUTS (VIN±) 2 Differential Input Voltage Range Full 1.18 1.5 1.6 V p-p Input Common-Mode Voltage Full 1.8 V Input Resistance (Differential) Full 1 kΩ Input Capacitance (Differential) 25°C 1.3 pF POWER SUPPLY AVDD Full 1.8 1.9 2.0 V DRVDD Full 1.8 1.9 2.0 V SPI_VDDIO Full 1.8 1.9 3.3 V Supply Currents 3 IAVDD Full 300 330 mA 3 IDRVDD Full 66 80 mA 3 Power Dissipation Full 695 779 mW Power-Down Dissipation Full 15 mW Standby Dissipation Full 72 mW Standby to Power-Up Time Full 10 μs 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the SPI Register Map section for additional details. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 30 MHz sine input at a rated sample rate. Rev. 0 | Page 4 of 28 AD6641 AC SPECIFICATIONS AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 2. AD6641-500 1, 2 Parameter Temp Min Typ Max Unit SNR fIN = 30 MHz 25°C 66.0 dBFS f = 125 MHz 25°C 65.9 dBFS IN Full 65.0 dBFS fIN = 250 MHz 25°C 65.8 dBFS fIN = 450 MHz 25°C 65.1 dBFS SINAD fIN = 30 MHz 25°C 66.0 dBFS fIN = 125 MHz 25°C 65.7 dBFS Full 63.8 dBFS f = 250 MHz 25°C 65.3 dBFS IN f = 450 MHz 25°C 64.6 dBFS IN EFFECTIVE NUMBER OF BITS (ENOB) f = 30 MHz 25°C 10.7 Bits IN f = 125 MHz 25°C 10.6 Bits IN f = 250 MHz 25°C 10.5 Bits IN fIN = 450 MHz 25°C 10.4 Bits SFDR fIN = 30 MHz 25°C 88 dBc fIN = 125 MHz 25°C 83 dBc Full 77 dBc f = 250 MHz 25°C 80 dBc IN f = 450 MHz 25°C 72 dBc IN WORST HARMONIC (SECOND OR THIRD) f = 30 MHz 25°C −92 dBc IN f = 125 MHz 25°C −77 dBc IN Full −84 dBc fIN = 250 MHz 25°C −80 dBc fIN = 450 MHz 25°C −72 dBc WORST OTHER HARMONIC (SFDR EXCLUDING SECOND AND THIRD) fIN = 30 MHz 25°C −90 dBc fIN = 125 MHz 25°C −90 dBc Full −77 dBc f = 250 MHz 25°C −85 dBc IN f = 450 MHz 25°C −78 dBc IN TWO-TONE IMD f = 119.8 MHz, f = 125.8 MHz (−7 dBFS, Each Tone) 25°C −82 dBc IN1 IN2 ANALOG INPUT BANDWIDTH 25°C 1 GHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. Rev. 0 | Page 5 of 28 AD6641 DIGITAL SPECIFICATIONS AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 3. AD6641-500 1 Parameter Temp Min Typ Max Unit CLOCK INPUTS (CLK±) Logic Compliance Full CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage High Level Input (VIH) Full 0.2 1.8 V p-p Low Level Input (VIL) Full −1.8 −0.2 V p-p High Level Input Current (IIH) Full −10 +10 μA Low Level Input Current (I) Full −10 +10 μA IL Input Resistance (Differential) Full 8 10 12 kΩ Input Capacitance Full 4 pF LOGIC INPUTS (SPI, SPORT) Logic Compliance Full CMOS Logic 1 Voltage Full 0.8 × SPI_VDDIO V Logic 0 Voltage Full 0.2 × SPI_VDDIO V Logic 1 Input Current (SDIO) Full 0 μA Logic 0 Input Current (SDIO) Full −60 μA Logic 1 Input Current (SCLK) Full 50 μA Logic 0 Input Current (SCLK) Full 0 μA Input Capacitance 25°C 4 pF LOGIC INPUTS (DUMP, CSB) Logic Compliance Full CMOS Logic 1 Voltage Full 0.8 × DRVDD V Logic 0 Voltage Full 0.2 × DRVDD V Logic 1 Input Current Full 0 μA Logic 0 Input Current Full −60 μA Input Capacitance 25°C 4 pF LOGIC INPUTS (FILL±) Logic Compliance Full CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage High Level Input (VIH) Full 0.2 1.8 V p-p Low Level Input (VIL) Full −1.8 −0.2 V p-p High Level Input Current (IIH) Full −10 +10 μA Low Level Input Current (I) Full −10 +10 μA IL Input Resistance (Differential) Full 8 10 12 kΩ Input Capacitance Full 4 pF 2 LOGIC OUTPUTS (FULL, EMPTY) Logic Compliance Full CMOS High Level Output Voltage Full DRVDD − 0.05 V Low Level Output Voltage Full DRGND + 0.05 V 2 LOGIC OUTPUTS (SPI, SPORT) Logic Compliance Full CMOS High Level Output Voltage Full SPI_VDDIO − 0.05 V Low Level Output Voltage Full DRGND + 0.05 V Rev. 0 | Page 6 of 28 AD6641 AD6641-500 1 Parameter Temp Min Typ Max Unit LOGIC OUTPUTS DDR LVDS Mode (PCLK±, PD[5:0]±, PDOR±) Logic Compliance Full LVDS V Differential Output Voltage Full 247 454 mV OD VOS Output Offset Voltage Full 1.125 1.375 V Parallel CMOS Mode (PCLK±, PD[11:0]) Logic Compliance Full CMOS High Level Output Voltage Full DRVDD − 0.05 V Low Level Output Voltage Full DRGND + 0.05 V Output Coding Twos complement, Gray code, or offset binary (default) 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 5 pF loading. SWITCHING SPECIFICATIONS AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. Table 4. AD6641-500 1 Parameter Temp Min Typ Max Unit OUTPUT DATA RATE Maximum Output Data Rate (Decimate by 8 at 500 MSPS Sample Rate, Parallel CMOS Full 62.5 MHz or DDR LVDS Mode Interface) Maximum Output Data Rate (Decimate by 8 at 500 MSPS Sample Rate, SPORT Mode) Full 62.5 MHz PULSE WIDTH/PERIOD (CLK±) CLK± Pulse Width High (t ) Full 1 ns CH CLK± Pulse Width Low (t ) Full 1 ns CL Rise Time (tR) (20% to 80%) 25°C 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 ns PULSE WIDTH/PERIOD (PCLK±, DDR LVDS MODE) PCLK± Pulse Width High (tPCLK_CH) Full 8 ns PCLK± Period (tPCLK) Full 16 ns Propagation Delay (tCPD, CLK± to PCLK±) Full ±0.1 ns Rise Time (t ) (20% to 80%) 25°C 0.2 ns R Fall Time (t ) (20% to 80%) 25°C 0.2 ns F Data to PCLK Skew (t ) Full 0.2 ns SKEW 2 SERIAL PORT OUTPUT TIMING SP_SDFS Propagation Delay (t) Full 3 ns DSDFS SP_SDO Propagation Delay (t) Full 3 ns DSDO SERIAL PORT INPUT TIMING SP_SDFS Setup Time (t) Full 2 ns SSF SP_SDFS Hold Time (tHSF) Full 2 ns FILL± INPUT TIMING FILL± Setup Time (t) Full 0.5 ns Sfill FILL± Hold Time (tHfill) Full 0.7 ns APERTURE DELAY (t) 25°C 0.85 ns A APERTURE UNCERTAINTY (JITTER, tJ) 25°C 80 fs rms 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 5 pF loading. Rev. 0 | Page 7 of 28 AD6641 SPI TIMING REQUIREMENTS Table 5. Parameter Description Limit Unit t Setup time between the data and the rising edge of SCLK 2 ns min DS tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min t Hold time between CSB and SCLK 2 ns min H t SCLK pulse width high 10 ns min HIGH t SCLK pulse width low 10 ns min LOW tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns min tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns min Timing Diagrams N– 1 t N+4 A N+5 N N+ 3 VIN± N+1 N+2 t t CH CL CLK+ CLK– Figure 2. Input Interface Timing CLK+ CLK– t CPD t PCLK t PCLK_CH PCLK+ PCLK– t SKEW PD[11:0] OUTPUT DATA BUS Figure 3. Parallel CMOS Mode Output Interface Timing SP_SCLK t DSDFS SP_SDFS Figure 4. SP_SDFS Propagation Delay Rev. 0 | Page 8 of 28 09813-004 09813-002 09813-003 AD6641 t DSDO SP_SCLK SP_SDO D11 D10 Figure 5. SP_SDO Propagation Delay SP_SCLK t t SSF HSF SP_SDFS Figure 6. Slave Mode SP_SDFS Setup/Hold Time CLK± t t Sfill Hfill FILL± Figure 7. FILL± Setup and Hold Times Rev. 0 | Page 9 of 28 09813-005 09813-007 09813-006 AD6641 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 6. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Electrical other conditions above those indicated in the operational AVDD to AGND −0.3 V to +2.0 V section of this specification is not implied. Exposure to absolute DRVDD to DRGND −0.3 V to +2.0 V maximum rating conditions for extended periods may affect AGND to DRGND −0.3 V to +0.3 V device reliability. AVDD to DRVDD −2.0 V to +2.0 V THERMAL RESISTANCE SPI_VDDIO to AVDD −2.0 V to +2.0 V SPI_VDDIO to DRVDD −2.0 V to +2.0 V The exposed pad must be soldered to the ground plane for PD[5:0]± to DRGND −0.3 V to DRVDD + 0.2 V the LFCSP package. Soldering the exposed pad to the PCB PCLK± to DRGND −0.3 V to DRVDD + 0.2 V increases the reliability of the solder joints, maximizing the PDOR± to DRGND −0.3 V to DRVDD + 0.2 V thermal capability of the package. FULL to DRGND −0.3 V to DRVDD + 0.2 V Table 7. CLK± to AGND −0.3 V to AVDD + 0.2 V Package Type θJA θJC Unit FILL± to AGND −0.3 V to DRVDD + 0.2 V 56-Lead LFCSP_VQ (CP-56-1) 23.7 1.7 °C/W DUMP to AGND −0.3 V to DRVDD + 0.2 V EMPTY to AGND −0.3 V to DRVDD + 0.2 V Typical θJA and θJC are specified for a 4-layer board in still air. VIN± to AGND −0.3 V to AVDD + 0.2 V Airflow increases heat dissipation, effectively reducing θJA. In VREF to AGND −0.3 V to AVDD + 0.2 V addition, metal in direct contact with the package leads from CML to AGND −0.3 V to AVDD + 0.2 V metal traces, through holes, ground, and power planes reduces CSB to DRGND −0.3 V to SPI_VDDIO + 0.3 V the θ . JA SP_SCLK, SP_SDFS to AGND −0.3 V to SPI_VDDIO + 0.3 V SDIO to DRGND −0.3 V to SPI_VDDIO + 0.3 V SP_SDO to DRGND −0.3 V to SPI_VDDIO + 0.3 V ESD CAUTION Environmental Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature 300°C (Soldering, 10 sec) Junction Temperature 150°C Rev. 0 | Page 10 of 28 AD6641 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PD0– 1 PIN 1 42 AVDD PD0+ 2 INDICATOR 41 AVDD PD1– 3 40 CML PD1+ 4 39 AVDD PD2– 5 38 AVDD PD2+ 6 37 AVDD AD6641 DRVDD 7 36 VIN– TOP VIEW DRGND 8 35 VIN+ (Not to Scale) PD3– 9 34 AVDD PD3+ 10 33 AVDD PD4– 11 32 AVDD PD4+ 12 31 VREF PD5– 13 30 AVDD PD5+ 14 29 SPI_VDDIO NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD IS THE ONLY ANALOG GROUND CONNECTION FOR THE CHIP. IT MUST BE CONNECTED TO PCB AGND. Figure 8. Pin Configuration for DDR LVDS Mode Table 8. DDR LVDS Mode Pin Function Descriptions Pin No. Mnemonic Description 0 EPAD Exposed Pad. The exposed pad is the only ground connection for the chip. The pad must be connected to PCB AGND. 1 PD0− PD0 Data Output (LSB)—Complement. 2 PD0+ PD0 Data Output (LSB)—True. 3 PD1− PD1 Data Output—Complement. 4 PD1+ PD1 Data Output—True. 5 PD2− PD2 Data Output—Complement. 6 PD2+ PD2 Data Output—True. 7, 24, 47 DRVDD 1.9 V Digital Output Supply. 8, 23, 48 DRGND Digital Output Ground. 9 PD3− PD3 Data Output—Complement. 10 PD3+ PD3 Data Output—True. 11 PD4− PD4 Data Output—Complement. 12 PD4+ PD4 Data Output—True. 13 PD5− PD5 Data Output (MSB)—Complement. 14 PD5+ PD5 Data Output (MSB)—True. 15 PDOR− Overrange Output—Complement. 16 PDOR+ Overrange Output—True. 17 SP_SDO SPORT Output. 18, 19, 20, 28, 54 DNC Do Not Connect. Do not connect to this pin. 21 SP_SDFS SPORT Frame Sync Input (Slave Mode)/Output (Master Mode). 22 SP_SCLK SPORT Clock Input (Slave Mode)/Output (Master Mode). 25 SDIO Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). 26 SCLK Serial Port Interface Clock (Serial Port Mode). 27 CSB Serial Port Chip Select (Active Low). 29 SPI_VDDIO 1.9 V or 3.3 V SPI I/O Supply. 30, 32, 33, 34, 37, 38, 39, AVDD 1.9 V Analog Supply. 41, 42, 43, 46 31 VREF Voltage Reference Input/Output. Nominally 0.75 V. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. Rev. 0 | Page 11 of 28 PDOR– PCLK+ PDOR+ PCLK– SP_SDO DNC DNC DUMP DNC EMPTY DNC FULL SP_SDFS FILL– SP_SCLK FILL+ DRGND DRGND DRVDD DRVDD SDIO AVDD SCLK CLK– CSB CLK+ DNC AVDD 09813-008 15 56 16 55 17 54 18 53 19 52 20 51 21 50 22 49 23 48 24 47 25 46 26 45 27 44 28 43 AD6641 Pin No. Mnemonic Description 40 CML Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+ and VIN−. 44 CLK+ Clock Input—True. 45 CLK− Clock Input—Complement. 49 FILL+ FIFO Fill Input (LVDS)—True. 50 FILL− FIFO Fill Input (LVDS)—Complement. 51 FULL FIFO Full Output Indicator. 52 EMPTY FIFO Empty Output Indicator. 53 DUMP FIFO Readback Input. 55 PCLK− Data Clock Output—Complement. 56 PCLK+ Data Clock Output—True. Rev. 0 | Page 12 of 28 AD6641 DNC 1 PIN 1 42 AVDD DNC 2 INDICATOR 41 AVDD PD0 3 40 CML PD1 4 39 AVDD PD2 5 38 AVDD PD3 6 37 AVDD AD6641 DRVDD 7 36 VIN– TOP VIEW DRGND 8 35 VIN+ (Not to Scale) PD4 9 34 AVDD PD5 33 10 AVDD PD6 32 11 AVDD PD7 31 VREF 12 PD8 13 30 AVDD PD9 14 29 SPI_VDDIO 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD IS THE ONLY ANALOG GROUND CONNECTION FOR THE CHIP. IT MUST BE CONNECTED TO PCB AGND. Figure 9. Pin Configuration for Parallel CMOS Mode Table 9. Parallel CMOS Mode Pin Function Descriptions Pin No. Mnemonic Description 0 EPAD Exposed Pad. The exposed pad is the only ground connection for the chip. The pad must be connected to PCB AGND. 1, 2, 18, 19, 20, 28, 54 DNC Do Not Connect. Do not connect to this pin. 3 PD0 PD0 Data Output. 4 PD1 PD1 Data Output. 5 PD2 PD2 Data Output. 6 PD3 PD3 Data Output. 7, 24, 47 DRVDD 1.9 V Digital Output Supply. 8, 23, 48 DRGND Digital Output Ground. 9 PD4 PD4 Data Output. 10 PD5 PD5 Data Output. 11 PD6 PD6 Data Output. 12 PD7 PD7 Data Output. 13 PD8 PD8 Data Output. 14 PD9 PD9 Data Output. 15 PD10 PD10 Data Output. 16 PD11 PD11 Data Output (MSB). 17 SP_SDO SPORT Output. 21 SP_SDFS SPORT Frame Sync Input (Slave Mode)/Output (Master Mode). 22 SP_SCLK SPORT Clock Input (Slave Mode)/Output (Master Mode). 25 SDIO Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). 26 SCLK Serial Port Interface Clock (Serial Port Mode). 27 CSB Serial Port Chip Select (Active Low). 29 SPI_VDDIO 1.9 V or 3.3 V SPI I/O Supply. 30, 32, 33, 34, 37, 38, 39, AVDD 1.9 V Analog Supply. 41, 42, 43, 46 31 VREF Voltage Reference Input/Output. Nominally 0.75 V. 35 VIN+ Analog Input—True. 36 VIN− Analog Input—Complement. 40 CML Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+ and VIN−. 44 CLK+ Clock Input—True. Rev. 0 | Page 13 of 28 PD10 PCLK+ PD11 PCLK– SP_SDO DNC DNC DUMP DNC EMPTY DNC FULL SP_SDFS FILL– SP_SCLK FILL+ DRGND DRGND DRVDD DRVDD SDIO AVDD SCLK CLK– CSB CLK+ DNC AVDD 09813-009 15 56 16 55 17 54 18 53 19 52 20 51 21 50 22 49 23 48 24 47 25 46 26 45 27 44 28 43 AD6641 Pin No. Mnemonic Description 45 CLK− Clock Input—Complement. 49 FILL+ FIFO Fill Input (LVDS)—True. 50 FILL− FIFO Fill Input (LVDS)—Complement. 51 FULL FIFO Full Output Indicator. 52 EMPTY FIFO Empty Output Indicator. 53 DUMP FIFO Readback Input. 55 PCLK− Data Clock Output—Complement. 56 PCLK+ Data Clock Output—True. Rev. 0 | Page 14 of 28 AD6641 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.9 V, DRVDD = 1.9 V, rated sample rate, TA = 25°C, 1.5 V p-p differential input, AIN = −1 dBFS, unless otherwise noted. 0 0 500MSPS 491.52MSPS 30.4MHz @ –1.0dBFS 368.0MHz @ –1.0dBFS SNR: 64.9dB SNR: 63.8dB –20 –20 ENOB: 10.7 BITS ENOB: 10.5 BITS SFDR: 87dBc SFDR: 77dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 20 40 60 80 100 120 140 160 180 200 220 240 0 20 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. 16k Point Single-Tone FFT; 500 MSPS, 30.4 MHz Figure 13. 16k Point Single-Tone FFT; 491.52 MSPS, 368.0 MHz 0 0 500MSPS 491.52MSPS 100.4MHz @ –1.0dBFS 450.1MHz @ –1.0dBFS SNR: 64.9dB SNR: 63.3dB –20 –20 ENOB: 10.6 BITS ENOB: 10.4 BITS SFDR: 86dBc SFDR: 76dBc –40 –40 –60 –60 –80 –80 –100 –100 –120 –120 0 20 40 60 80 100 120 140 160 180 200 220 240 0 20 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. 16k Point Single-Tone FFT; 500 MSPS, 100.4 MHz Figure 14. 16k Point Single-Tone FFT; 491.52 MSPS, 450.1 MHz 95 0 SFDR (dBc), –40°C 500MSPS 90 140.4MHz @ –1.0dBFS SFDR (dBc), +25°C SNR: 64.7dB –20 ENOB: 10.6 BITS 85 SFDR: 84dBc 80 –40 75 –60 SNR (dBFS), –40°C SFDR (dBc), +85°C 70 65 –80 60 SNR (dBFS), +85°C SNR (dBFS), +25°C –100 55 50 –120 0 100 200 300 400 500 0 20 40 60 80 100 120 140 160 180 200 220 240 ANALOG INPUT FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. 16k Point Single-Tone FFT; 500 MSPS, 140.4 MHz Figure 15. Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature; 500 MSPS Rev. 0 | Page 15 of 28 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) 09813-011 09813-012 09813-010 AMPLITUDE (dBFS) AMPLITUDE (dBFS) SNR/SFDR (MHz) 09813-015 09813-014 09813-013 AD6641 95 0.5 0.4 90 0.3 85 0.2 SFDR @ 30.3MHz, 1.8V 80 SFDR @ 30.3MHz, 1.9V 0.1 SFDR @ 100.3MHz, 1.8V 75 SFDR @ 100.3MHz, 1.9V 0 70 –0.1 65 –0.2 SNRFS @ 30.3MHz, 1.8V SNRFS @ 30.3MHz, 1.9V 60 –0.3 SNRFS @ 100.3MHz, 1.8V SNRFS @ 100.3MHz, 1.9V 55 –0.4 50 –0.5 250 300 350 400 450 500 550 –1 1023 2047 3071 4095 OUTPUT CODE Figure 16. SNR/SFDR vs. Sample Rate and Supply Figure 19. DNL; 500 MSPS 100 2.5 1.24 LSB rms 90 SFDR (dBFS) 2.0 80 SNR (dBFS) 70 60 1.5 50 SFDR (dBc) 40 1.0 SNRFS, 1.9V 30 SNR, 1.9V SFDR, 1.9V SFDRFS, 1.9V 20 0.5 SNRFS, 1.8V SNR (dB) SNR, 1.8V 10 SFDR, 1.8V SFDRFS, 1.8V 0 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 N– 3 N– 2 N– 1 N N +1 N +2 N+3 MORE BINS AMPLITUDE (dB) Figure 20. Grounded Input Histogram; 500 MSPS Figure 17. SNR/SFDR vs. Input Amplitude; 500 MSPS,140.3 MHz 1.0 491.52MSPS 0 f : 121.3MHz @ –7dBFS IN1 0.8 f : 124.7MHz @ –7dBFS IN2 SFDR: 85dBc –15 0.6 –30 0.4 0.2 –45 0 –60 –0.2 –75 –0.4 –90 –0.6 –105 –0.8 –120 –1.0 25 50 75 100 125 150 175 200 225 –1 1023 2047 3071 4095 OUTPUT CODE FREQUENCY (MHz) Figure 18. INL; 500 MSPS Figure 21. 16k Point Single-Tone FFT; 491.52 MSPS, fIN1 = 121.3 MHz, fIN2 = 124.7 MHz Rev. 0 | Page 16 of 28 SFDR (dBc) SNR (dBFS) SAMPLE RATE (MSPS) INL (LSB) SNR/SFDR (dB) SNR/SFDR (dB) 09813-117 09813-116 09813-018 DNL (LSB) AMPLITUDE (dBFS) NUMBER OF HITS (M) 09813-020 09813-021 09813-019 AD6641 120 90 IMD3 (dBFS) 85 100 SFDR (dBc) 80 SFDR (dBFS) 80 75 60 70 SNR (dBFS) 65 SFDR, 1.9V 40 SFDR (dBc) SFDRFS, 1.9V IMD3FS, 1.9V 60 SFDR, 1.8V 20 SFDRFS, 1.8V 55 IMD3FS, 1.8V 0 50 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 1.75 1.80 1.85 1.90 1.95 2.00 AMPLITUDE (dBFS) POWER SUPPLY (V) Figure 22. Two-Tone SFDR vs. Input Amplitude; Figure 24. SNR/SFDR vs. Power Supply 500 MSPS, 119.2 MHz, 122.5 MHz 400 800 120 IMD3 (dBFS) 350 700 100 TOTAL POWER 300 600 SFDR (dBFS) 80 I 250 AVDD 500 60 400 200 150 300 SFDR, 1.9V 40 SFDR (dBc) SFDRFS, 1.9V IMD3FS, 1.9V 100 200 SFDR, 1.8V 20 I DRVDD SFDRFS, 1.8V 50 100 IMD3FS, 1.8V 0 0 0 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 250 300 350 400 450 500 550 AMPLITUDE (dBFS) SAMPLE RATE (MSPS) Figure 23. Two-Tone SFDR vs. Input Amplitude; Figure 25. Current and Power vs. Sample Rate 500 MSPS, 139.3 MHz, 141.3 MHz Rev. 0 | Page 17 of 28 SFDR (dB) SFDR (dB) 09813-022 09813-023 CURRENT (mA) SNR/SFDR (dB) 09813-024 POWER (mW) 09813-025 AD6641 EQUIVALENT CIRCUITS V AVDD BOOST CML AVDD DC VIN+ DRVDD 500Ω A IN+ AVDD V+ V– SPI CONTROLLED 500Ω OUTPUT– OUTPUT+ V– V+ VIN– A IN– Figure 26. DC Equivalent Analog Input Circuit Figure 30. LVDS Outputs (PDOR±, PD[5:0]±, PCLK±) DRVDD DVDD VIN+ 350Ω SCLK 1.3pF 1kΩ 30kΩ VIN– Figure 27. AC Equivalent Analog Input Circuit Figure 31. Equivalent SCLK Input Circuit AVDD DRVDD AVDD AVDD DRVDD 0.9V CLK+ 15kΩ 15kΩ CLK– 30kΩ OR OR DRVDD FILL+ FILL– 350Ω CSB Figure 28. Equivalent CLK± and FILL± Input Circuit Figure 32. Equivalent CSB Input Circuit DRVDD DRVDD DRVDD 30kΩ 350Ω SDIO CTRL DRGND Figure 29. Equivalent PD[11:0], FULL, EMPTY, PCLK±, and Figure 33. Equivalent SDIO Circuit SP_SDO Output Circuit Rev. 0 | Page 18 of 28 09813-128 09813-017 09813-016 09813-127 09813-110 09813-130 09813-129 09813-131 AD6641 AVDD 20kΩ (00) DRVDD (01) VREF 350Ω (10) (11) 30kΩ SP_SDFS/ SP_SCLK NOT USED SPI CTRL VREF SELECT 00: INTERNAL VREF 01: IMORT VREF 10: EXPORT VREF CTRL 11: NOT USED MASTER/SLAVE Figure 34. Equivalent SP_SDFS and SP_SCLK Circuit Figure 35. Equivalent VREF Circuit Rev. 0 | Page 19 of 28 09813-132 09813-133 AD6641 SPI REGISTER MAP Table 10. Memory Map Register Default Default Addr. Bit 7 Bit 0 Value Notes/ (Hex) Parameter Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 CHIP_PORT_CONFIG 0 LSB Soft 1 1 Soft LSB first 0 0x18 The nibbles first reset reset should be mirrored by the user so that LSB or MSB first mode registers correctly, regardless of shift mode. 0x01 CHIP_ID 8-bit chip ID, Bits[7:0] = 0xA0 Read Default is only unique chip ID, different for each device. This is a read-only register. 1 1 1 1 0x02 CHIP_GRADE 0 0 Speed grade: X Read Child ID X XX XX 10 = 500 MSPS only used to differentiate graded devices. Transfer Register 0xFF DEVICE_UPDATE [7:1] = 0000000 SW 0x00 Synchro- transfer nously transfers data from the master shift register to the slave. ADC Functions 0x08 Modes 0 0 0 0 0 Internal power-down mode: 0x00 Determines 000 = normal (power-up, default) various 001 = full power-down generic 010 = standby modes of chip 011 = reserved operation. 0x0D TEST_IO (For user-defined Reset Reset Output test mode: 0x00 When set, the mode only, set PN23 PN9 test data is 0000 = off (default) Bits[3:0] = 1000) gen: gen: 1 = placed on the 0001 = midscale short 1 = on on output pins in 00 = Pattern 1 only 0010 = +FS short 0 = off 0 = off place of 0011 = −FS short 01 = toggle (default) (default) normal data. 0100 = checkerboard output Pattern 1/ 0101 = PN23 sequence Set pattern Pattern 2 0110 = PN9 values: 10 = toggle 0111 = one/zero word toggle Pattern 1: Pattern 1/0000 1000 = user defined Reg 0x19, 11 = toggle 1001 = unused Reg 0x1A Pattern 1/ 1010 = unused Pattern 2: Pattern 2/0000 1011 = unused Reg 0x1B 1100 = unused Reg 0x1C. (format determined by OUTPUT_MODE) 0x14 OUTPUT_MODE 0 0 0 Output 0 = Output Data format select: 0x08 disable: CMOS: invert: 00 = offset binary 0 = 1 = 1 = on (default) enable LVDS 0 = off 01 = twos (default) (default) (default) complement 1 = 10 = Gray code disable 11 = reserved Rev. 0 | Page 20 of 28 AD6641 Default Default Addr. Bit 7 Bit 0 Value Notes/ (Hex) Parameter Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x15 OUTPUT_ADJUST [7:4] = 0000 LVDS LVDS fine adjust: 0x00 course 001 = 3.50 mA adjust: 010 = 3.25 mA 0 = 011 = 3.00 mA 3.5 mA 100 = 2.75 mA (default) 101 = 2.50 mA 1 = 110 = 2.25 mA 2.0 mA 111 = 2.00 mA 0x16 OUTPUT_PHASE Output [6:0] = 0000000 0x03 clock polarity: 1 = inverted 0 = normal (default) 0x17 OUTPUT_DELAY 0 0 0 0 Output clock delay: 0 Shown as 0000 = 0 fractional 0001 = −1/10 value of 0010 = −2/10 sampling 0011 = −3/10 clock period 0100 = reserved that is 0101 = +5/10 subtracted or 0110 = +4/10 added to 0111 = +3/10 initial t , SKEW 1000 = +2/10 see Figure 3). 1001 = +1/10 0x18 Input range VREF select: 0 Input voltage range setting (V): 0 00 = internal VREF 11100 = 1.60 (20 kΩ pull-down) 11101 = 1.58 01 = import VREF 11110 = 1.55 (0.59 V to 0.80 V on 11111 = 1.52 VREF pin) 00000 = 1.50 10 = export V REF 00001 = 1.47 11= not used 00010 = 1.44 00011 = 1.42 00100 = 1.39 00101 = 1.36 00110 = 1.34 00111 = 1.31 01000 = 1.28 01001 = 1.26 01010 = 1.23 01011= 1.20 01100 = 1.18 0x19 USER_PATT1_LSB [7:0] 0 User Defined Pattern 1 LSB. 0x1A USER_PATT1_MSB [7:0] 0 User Defined Pattern 1 MSB. 0x1B USER_PATT2_LSB [7:0] 0 User Defined Pattern 2 LSB. 0x1C USER_PATT2_MSB [7:0] 0 User Defined Pattern 2 MSB. Digital Controls 0x101 Fill control register Reserved Fill Reserved LIFO FIFO fill mode: Reserved Standby 0 input mode 00 = single after fill pin 01 = continuous disable 1x = reserved 0x102 FIFO Config [7:4] = reserved Dump Fill reset Dump Fill 0 reset 0x104 Fill count [7:0] 0x7F Number of words to use for fill or dump. Rev. 0 | Page 21 of 28 AD6641 Default Default Addr. Bit 7 Bit 0 Value Notes/ (Hex) Parameter Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x105 Settle Count0 [7:0] 0 LSBs settling time given to ADC before initiating fill. 0x106 Settle Count1 [7:0] 0 MSBs settling time given to ADC before initiating fill. 0x107 Dump control [7:3] = reserved 0 = Readback mode: 0 Customer slave 00 = off drives 1 = 01 = parallel SP_SCLK, master 10 = SPORT SP_SDFS in 11 = reserved slave mode. 0x10A FIFO status [7:3] = reserved Over- Empty Full 0 range 0x10B FIFO Dump Data0 [7:0] = LSBs 0 LSBs readback data. 0x10C FIFO Dump Data1 [7:4] = reserved [3:0] = MSBs 0 MSBs upper four bits readback data. 0x10F Read Offset Data0 [7:0] = LSBs 0 LSBs offset to RAM, allowing subsegments of data cap- ture to be read. 0x110 Read Offset Data1 [7:6] = reserved [5:0] = MSBs 0 MSB’s offset. 0x111 PPORT control [7:5] = reserved Divide ratio = 2 × (bit word): 0x04 CMOS parallel 00100 = divide by 8 (default) port divide … rate. 01111 = divide by 30 1xxxx = divide by 32 0x112 SPORT control [7:5] = reserved Divide ratio= 2 × (bit word): 0x04 Serial port 00100 = divide by 8 (default) divide rate. … 01111 = divide by 30 1xxxx = divide by 32 0x13A FIFO test BIST [7:5] = reserved Sets the BIST mode for the FIFO: FIFO 0 BIST 1xxx = reserved enable 0111 = reserved 0110 = 12'hFFF (−1 LSB) 0101 = 12'h001 (+1 LSB) 0100 = PN data 0011 = checkerboard (12'hAAA, 12'h555, 12'hAAA, … ) 0010 = checkerboard (12'h555, 12'hAAA, 12'h555, … ) 0001 = decrementing ramp 0000 = incrementing ramp 1 X = don’t care. Rev. 0 | Page 22 of 28 AD6641 THEORY OF OPERATION The on-chip FIFO allows small snapshots of time to be captured allows the analog circuitry to stabilize before taking data. An via the ADC and read back at a lower rate. This reduces the intelligent trade-off between speed of acquisition and accuracy constraints of signal processing by transferring the captured can be made by using this register. data at an arbitrary time and at a much lower sample rate. The data can be read back through any of the three output inter- faces at a low data rate, which further saves power. If the SPI or FIFO OPERATION SPORT is used to read back the data, the interface can require The capture of the data can be signaled through writes to the as few as three pins. A full flag and an empty flag are provided SPI port by pulsing the FILL± pins. The transaction diagram to signal the state of the FIFO. The FIFO status register (0x10A) shown in Figure 36 illustrates the loading of the FIFO. in the SPI also allows this to be monitored via software. At Event 1, the FIFO is instructed to fill either by asserting the Single Capture Mode FILL± pins or via a write to the SPI bits. FILL± pin operation The FIFO can be placed into single capture mode by writing the can be delayed by a programmable fill hold-off counter so that FIFO fill mode bits in the fill control register (0x101[3:2]) to 00. the FIFO data can be surrounding a fill event. The FIFO then In the single capture mode, the user initiates a capture either by loads itself with data. The number of samples of data is driving the FILL± pins high or by initiating a fill command determined by the SPI fill count register (0x104). This is an 8- through the SPI port by writing the standby after fill bit bit register with values from 0 to 255. The number of samples (0x101[0]). This powers up the ADC (if needed) after a placed in the FIFO is determined by the following equation: programmable amount of time as determined by the SPI settle Number of Samples = (FILL_CNT + 1) × 64 count registers (0x105, 0x106). If Bit 0 of the 0x101 register in After the FIFO has begun filling at Event 2, the AD6641 asserts the SPI is set, the ADC returns to standby mode after the a full flag to indicate that the FIFO has finished capturing data capture is complete. and enters a wait state in which the device waits to receive the Fill Pin Timing dump instruction from the DUMP pin or the SPI. A fill of the FIFO can be initiated by asserting the differential After the data has been shifted (Event 4), the FIFO goes into the FILL± pins. When a pulse is detected on the FILL± pins, the idle state and waits for another fill command. During the idle FIFO is filled. state, the ADC can optionally be placed into standby mode to Dump Pin Timing save power. If the ADC powers down in the idle state, initiating a fill operation (Event 1) powers up the ADC. In this mode, the A readback of the FIFO can be initiated by asserting the DUMP ADC waits for settle count cycles (0x105, 0x106) before capturing pin. When a logic high is detected on the DUMP pin, the FIFO the data. Settle count is programmable from the SPI port and data is available through the chosen interface. 1 2 3 4 EVENTS IDLE STATE FILLING FIFO WITH DATA IDLE STATE STATE WAIT FOR DUMP (OPTIONAL) START SP_SCLK AND SP_SDFS SHIFT DATA Figure 36. On-Chip FIFO Transaction Timing Assuming Serial Port CLK+ CLK– FILL+, FILL– Figure 37. FIFO Fill Timing CLK+ CLK– DUMP Figure 38. FIFO DUMP Timing Rev. 0 | Page 23 of 28 09813-036 09813-035 09813-034 AD6641 SPORT Master Mode (Single Capture) Dump Signal (4)—Transition to High Details of the transaction diagram for serial master mode are The dump signal initiates reading data from the FIFO. Dump is shown in Figure 39 for single capture mode with the SDO enabled with a high level and should be initiated only after the output. Clock cycles are approximate because the fill and dump full signal goes high. The dump signal should be held high until signals can be driven asynchronously. In this example, SCLK is all data has been read out of the FIFO. derived from the master clock with a divide by 8 programmed SCLK Signal (5) from the SPI. The SCLK (serial clock) signal is configured as an output from Fill Pulse (1) the device when in the master mode of operation. SCLK begins The FIFO captures data after a fill signal (high level) is detected cycling five ADC clock cycles after the dump signal is sampled on the rising edge of the sampling clock. In synchronous opera- high and continues cycling up until one additional cycle after tion, a valid high level is accomplished by adhering to the setup the empty signal goes high. SCLK then remains low until the and hold times specified. For nonsynchronous control, the fill next dump operation. signal can be widened to accommodate two or more clock SDFS Signal (6) cycles to guarantee capture of a high level. Fill count (0x104) is The SDFS (serial data frame sync) signal is configured as an reset on the rising edge of the clock and is incremented on output from the device when in the master mode of operation. subsequent clock cycles only after the fill signal returns low. Frame synchronization begins 15 ADC clock cycles after the A new fill signal at any point during the capture resets the dump signal is sampled. counter and begins filling the FIFO. Dump Signal (7)—Transition to Low Empty Signal (2) A dump signal transition to low is applied after data has been After the FIFO state machine has begun loading data, the empty read out of the FIFO. signal goes low 24 clock cycles after the fill signal was last sampled high. Empty Signal (8)—Transition to High Full Signal (3) The empty signal transitions to high after data has been output from the FIFO based on the clock cycle count of (FILL_CNT + The full signal indicates when the FIFO has been filled and is 1) × 64. driven high when the number of samples specified has been captured in the FIFO, where The transition occurs 76 ADC clock cycles after the last LSB(s) of data have been output on the serial port. Number of Samples = (FILL_CNT + 1) × 64 The time at which the full signal goes high is based on (FILL_CNT + 1) × 64 + 13 clock cycles after the fill signal was last sampled high. 1 FILL 2 8 EMPTY 3 FULL 4 7 DUMP 5 SCLK 6 SDFS SDO Figure 39. SPORT Master Mode Transaction Diagram Rev. 0 | Page 24 of 28 09813-037 AD6641 Parallel Master Mode (Single Capture) Dump Signal (4)—Transition to High Details of the transaction diagram for parallel master mode are The dump signal initiates reading data from the FIFO. Dump is shown in Figure 40 with the PD[11:0] output word. Clock cycles enabled with a high level and should be initiated only after the are approximate because the fill and dump signals can be driven full signal goes high. The dump signal should be held high until asynchronously. In this example, PCLK± is derived from the all data has been read out of the FIFO. master clock with a divide by 8 programmed from the SPI. PCLK± Signal (5) Fill Pulse (1) The PCLK± (parallel clock) signal is configured as an output The FIFO captures data after a fill signal (high level) is detected from the device. PCLK± begins cycling 71 ADC clock cycles on the rising edge of the sampling clock. In synchronous opera- after the dump signal is sampled high. PCLK± goes low after tion, a valid high level is accomplished by adhering to the setup the last data is read out of the FIFO and remains low until the and hold times specified. For nonsynchronous control, the fill next dump operation. signal can be widened to accommodate two or more clock PD[11:0] Signal (6) cycles to guarantee capture of a high level. Fill count (0x104) The PD (parallel data) output provides 12 data bits (PD[11:0]) is reset on the rising edge of the clock and is incremented on th at a maximum rate of 1/8 of the sampling clock. Data begins subsequent clock cycles only after the fill signal returns low. A after two PCLK± cycles (assuming the dump signal has been new fill signal at any point during the capture resets the counter sampled). and begins filling the FIFO. Dump Signal (7)—Transition to Low Empty Signal (2) A dump signal transition to low is applied after data has been After the FIFO state machine has begun loading data, the read out of the FIFO. empty signal goes low 24 clock cycles after the fill signal was last sampled high. Empty Signal (8)—Transition to High Full Signal (3) The empty signal transitions to high after data has been output from the FIFO based on the clock cycle count of (FILL_CNT + The full signal indicates when the FIFO has been filled and is 1) × 64. The transition occurs nine clock cycles after the last driven high when the number of samples specified has been PCLK± rising edge. captured in the FIFO, where Continuous Capture Mode Number of Samples = (FILL_CNT + 1) × 64 The FIFO can be placed into continuous capture mode by writ- The time at which the full signal goes high is based on ing the FIFO fill mode bits in the fill control register (0x101[3:2]) (FILL_CNT + 1) × 64 + 13 clock cycles after the fill signal was to 01. In the continuous capture mode, data is loaded continu- last sampled high. ously into the FIFO and the FILL± pins pulsing high is used to stop the operation. This allows the history of the samples that preceded an event to be captured. 1 FILL 2 8 EMPTY 3 FULL 4 7 DUMP 5 PCLK+ PCLK– 6 PD[11:0] D16 D0 D8 Figure 40. Parallel Mode Transaction Diagram Rev. 0 | Page 25 of 28 09813-038 AD6641 at a 500 MSPS input sample rate. See Figure 3 for the parallel FIFO OUTPUT INTERFACES CMOS mode output interface timing diagram. The FIFO data is available through one of three interfaces. The LVDS Output Interface data can be output on the serial data port (SPORT), the SPI port, or a 12-bit CMOS interface. The data port chosen must be The AD6641 differential outputs conform to the ANSI-644 selected from the SPI port before the data is read from the FIFO. LVDS standard on default power-up. This can be changed to a Only one interface can be chosen at a time. The SPORT and SPI low power, reduced signal option similar to the IEEE 1596.3 interfaces are powered via the SPI_VDDIO pin and can support standard using the SPI. This LVDS standard can further reduce either 1.9 V or 3.3 V logic levels. the overall power dissipation of the device, which reduces the power by ~39 mW. The LVDS driver current is derived on chip SPORT Interface and sets the output current at each output equal to a nominal The SPORT consists of a clock (SP_SCLK) and frame sync 3.5 mA. A 100 Ω differential termination resistor placed at the (SP_SDFS) signal. The SP_SCLK and SP_SDFS signals are LVDS receiver inputs results in a nominal ±350 mV differential output from the AD6641 when the SPORT is configured as or 700 mV p-p swing at the receiver. a bus master and are input to the device when it is configured The AD6641 LVDS outputs facilitate interfacing with LVDS as a slave port. receivers in custom ASICs and FPGAs that have LVDS capability Serial Data Frame (Serial Bus Master) for superior switching performance in noisy environments. The serial data transfer is initiated with SP_SDFS. In master Single point-to-point net topologies are recommended with a mode, the internal serial controller initiates SP_SDFS after the 100 Ω termination resistor placed as close to the receiver as dump input goes high requesting the data. SP_SDFS is valid for possible. No far-end receiver termination and poor differential one complete clock cycle prior to the data shift. On the next trace routing may result in timing errors. It is recommended clock cycle, the AD6641 begins shifting out the data stream. that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal CMOS Output Interface lengths. The data stored in the FIFO can also be accessed via a 12-bit The data on the LVDS output port is interleaved in a MSB/LSB parallel CMOS interface. The maximum output throughput format. PCLK± is generated by dividing the ADC sample clock supported by the AD6641 is in the 12-bit CMOS mode and is th by the programmed decimation rate (8 to 32, even divides). The internally limited to 1/8 of the maximum input sample rate. maximum rate of PCLK± is limited to 62.5 MHz. Therefore, the output maximum output data rate is 62.5 MHz 0 4 8 12 16 20 24 28 SP_SCLK SP_SDFS SP_SDO D1 D2 D3 Figure 41. Data Output in Serial Bus Master Mode PCLK+ PCLK– PD[5:0]± X D0[5:0] D0[11:6] D8[5:0] D8[11:6] D16[5:0] D16[11:6] D24[5:0] D24[11:6] LSB/MSB LSB/MSB D0 SAMPLE D8 SAMPLE Figure 42. DDR LVDS Output MSB/LSB Interleaving with Decimate by 8 Rev. 0 | Page 26 of 28 09813-040 09813-039 AD6641 Table 11. Serial Port Interface Pins ANALOG INPUT AND VOLTAGE REFERENCE Pin Function The analog input to the AD6641 is a differential buffer. For SCLK Serial clock. Serial shift clock input. SCLK is used to best dynamic performance, match the source impedances synchronize serial interface reads and writes. driving VIN+ and VIN− such that common-mode settling SDIO Serial data input/output. Bidirectional pin that serves errors are symmetrical. The analog input is optimized to provide as an input or an output, depending on the instruction superior wideband performance and requires that the analog being sent and the relative position in the timing frame. inputs be driven differentially. SNR and SINAD performance CSB Chip select (active low). This control gates the read and degrades significantly if the analog input is driven with a single- write cycles. ended signal. The falling edge of the CSB pin, in conjunction with the rising A wideband transformer, such as Mini-Circuits® ADT1-1WT, edge of the SCLK pin, determines the start of the framing. An can provide the differential analog inputs for applications that example of the serial timing can be found in Figure 43 (for require a single-ended-to-differential conversion. Both analog symbol definitions, see Table 5). inputs are self-biased by an on-chip reference to a nominal 1.7 V. CSB can be held low indefinitely, which permanently enables An internal differential voltage reference creates positive and the device; this is called streaming. CSB can stall high between negative reference voltages that define the 1.5 V p-p fixed span bytes to allow additional external timing. When CSB is tied of the ADC core. This internal voltage reference can be adjusted high, SPI functions are placed in high impedance mode. by means of an SPI control. During an instruction phase, a 16-bit instruction is transmitted. VREF The first bit of the first byte in a serial data transfer frame indicates The AD6641 VREF pin (Pin 31) allows the user to monitor the whether a read command or a write command is issued. Data follows the instruction phase, and its length is determined by on-board voltage reference or provide an external reference the W0 and W1 bits. All data is composed of 8-bit words. (requires configuration through the SPI). The three optional settings are internal VREF (pin is connected to 20 kΩ to ground), The instruction phase determines whether the serial frame is a export VREF, and import VREF. Do not attach a bypass capacitor read or write operation, allowing the serial port to be used both to this pin. VREF is internally compensated and additional to program the chip and to read the contents of the on-chip loading may impact performance. memory. If the instruction is a read operation, the serial data input/output (SDIO) pin changes direction from an input to an CONFIGURATION USING THE SPI output at the appropriate point in the serial frame. Three pins define the SPI of the AD6641: SCLK, SDIO, and CSB Data can be sent in MSB first mode or in LSB first mode. MSB (see Table 11). SCLK (a serial clock) is used to synchronize the first is the default mode on power-up and can be changed via read and write data presented from and to the AD6641. SDIO the SPI port configuration register. For more information about (serial data input/output) is a bidirectional pin that allows data this and other features, see the AN-877 Application Note, to be sent to and read from the internal memory map registers. Interfacing to High Speed ADCs via SPI. CSB (chip select) is an active low control that enables or disables the read and write cycles. t t t t H DS HIGH CLK t t S DH t LOW CSB DON’T SCLK DON’T CARE CARE DON’T SDIO R/W W1 W0 A12 A11 A10 A9 A8A7 D5D4D3 D2 D1D0 DON’T CARE CARE Figure 43. Serial Port Interface Timing Diagram Rev. 0 | Page 27 of 28 09813 -073 AD6641 OUTLINE DIMENSIONS 0.30 8.00 0.23 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR 43 56 1 42 PIN 1 INDICATOR TOP 6.25 EXPOSED 7.75 VIEW PAD 6.10 SQ BSC SQ (BOTTOM VIEW) 5.95 0.50 0.40 29 14 28 15 0.30 0.25 MIN 6.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.85 THE EXPOSED PAD, REFER TO 0.05 MAX 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.50 BSC 0.08 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 Figure 44. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD6641BCPZ-500 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-1 AD6641BCPZRL7-500 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel CP-56-1 AD6641-500EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09813-0-4/11(0) Rev. 0 | Page 28 of 28 030509-A