ANALOG DEVICES AD5821

120 mA, Current Sinking, 2 ® 10-Bit, I C DAC AD5821 FEATURES INDUSTRIAL APPLICATIONS 120 mA current sink Heater controls Available in 3 × 3 array WLCSP package Fan controls 2 2-wire (I C-compatible) 1.8 V serial interface Cooler (Peltier) controls 10-bit resolution Solenoid controls Integrated current sense resistor Valve controls 2.7 V to 5.5 V power supply Linear actuator controls Guaranteed monotonic over all codes Light controls Power-down to 0.5 μA typical Current loop controls Internal reference Ultralow noise preamplifier GENERAL DESCRIPTION Power-down function The AD5821 is a single 10-bit digital-to-analog converter with Power-on reset 120 mA output current sink capability. It features an internal reference and operates from a single 2.7 V to 5.5 V supply. CONSUMER APPLICATIONS 2 The DAC is controlled via a 2-wire (I C-compatible) serial Lens autofocus interface that operates at clock rates up to 400 kHz. Image stabilization The AD5821 incorporates a power-on reset circuit that ensures Optical zoom that the DAC output powers up to 0 V and remains there until Shutters a valid write takes place. It has a power-down feature that reduces Iris/exposure the current consumption of the device to 1 μA maximum. Neutral density (ND) filters The AD5821 is designed for autofocus, image stabilization, and Lens covers optical zoom applications in camera phones, digital still cameras, Camera phones and camcorders. Digital still cameras Camera modules The AD5821 also has many industrial applications, such as Digital video cameras/camcorders controlling temperature, light, and movement, over the range of Camera-enabled devices −40°C to +85°C without derating. Security cameras 2 The I C address for the AD5821 is 0x18. Web/PC cameras FUNCTIONAL BLOCK DIAGRAM V XSHUTDOWN DGND DD REFERENCE POWER-ON V DD RESET SDA D1 10-BIT 2 I C SERIAL I CURRENT SINK SCL INTERFACE OUTPUT DAC R SENSE R 3.3Ω AD5821 DGND AGND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05950-001 AD5821 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Consumer Applications ................................................................... 1 Terminology.................................................................................... 10 Industrial Applications .................................................................... 1 Theory of Operation ...................................................................... 11 General Description ......................................................................... 1 Serial Interface ............................................................................ 11 2 Functional Block Diagram .............................................................. 1 I C Bus Operation ...................................................................... 11 Revision History ............................................................................... 2 Data Format ................................................................................ 11 Specifications..................................................................................... 3 Power Supply Bypassing and Grounding................................ 12 AC Specifications.......................................................................... 4 Applications Information .............................................................. 14 Timing Specifications .................................................................. 4 Outline Dimensions ....................................................................... 15 Absolute Maximum Ratings............................................................ 5 Ordering Guide .......................................................................... 15 Pin Configuration and Function Descriptions............................. 6 REVISION HISTORY 1/07—Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD5821 SPECIFICATIONS VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 B Version Parameter Min Typ Max Unit Test Conditions/Comments DC PERFORMANCE VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V with reduced performance Resolution 10 Bits 117 μA/LSB 2 Relative Accuracy ±1.5 ±4 LSB 2, 3 Differential Nonlinearity ±1 LSB Guaranteed monotonic over all codes 2, 4 Zero-Code Error 0 1 5 mA All 0s loaded to DAC 2 Offset Error @ Code 16 0.5 mA 2 Gain Error ±0.6 % of FSR @ 25°C 4, 5 Offset Error Drift 10 μA/°C 2, 5 Gain Error Drift ±0.2 ±0.5 LSB/°C OUTPUT CHARACTERISTICS 4 Minimum Sink Current 3 mA Maximum Sink Current 120 mA Output Current During XSHUTDOWN 80 nA XSHUTDOWN = 0 5 Output Compliance 0.6 VDD V Output voltage range over which maximum 120 mA sink current is available 5 Output Compliance 0.48 VDD V Output voltage range over which 90 mA sink current is available Power-Up Time 20 μs To 10% of FS, coming out of power-down mode; V = 5 V DD 5 LOGIC INPUTS (XSHUTDOWN) Input Current ±1 μA Input Low Voltage, V 0.54 V V = 2.7 V to 5.5 V INL DD Input High Voltage, VINH 1.3 V VDD = 2.7 V to 5.5 V Pin Capacitance 3 pF 5 LOGIC INPUTS (SCL, SDA) Input Low Voltage, VINL −0.3 +0.54 V VDD = 2.7 V to 3.6 V Input High Voltage, VINH 1.26 VDD + 0.3 V VDD = 2.7 V to 3.6 V Input Low Voltage, VINL −0.3 +0.54 V VDD = 3.6 V to 5.5 V Input High Voltage, V 1.4 V + 0.3 V V = 3.6 V to 5.5 V INH DD DD Input Leakage Current, I ±1 μA V = 0 V to V IN IN DD Input Hysteresis, V 0.05 V V HYST DD Digital Input Capacitance, CIN 6 pF 6 Glitch Rejection 50 ns Pulse width of spike suppressed POWER REQUIREMENTS VDD 2.7 5.5 V IDD (Normal Mode) IDD specification is valid for all DAC codes V = 2.7 V to 3.6 V 2.5 4 mA V = 1.8 V, V = GND, V = 3.6 V DD INH INL DD 7 I (Power-Down Mode) 0.5 μA V = 1.8 V, V = GND DD INH INL 1 Temperature range is as follows: B Version = −30°C to +85°C. 2 See the Terminology section. 3 Linearity is tested using a reduced code range: Code 32 to Code 1023. 4 To achieve near zero output current, use the power-down feature. 5 Guaranteed by design and characterization; not production tested. XSHUTDOWN is active low. SDA and SCL pull-up resistors are tied to 1.8 V. 6 Input filtering on both the SCL and the SDA inputs suppresses noise spikes that are less than 50 ns. 7 XSHUTDOWN is active low. Rev. 0 | Page 3 of 16 AD5821 AC SPECIFICATIONS VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD, unless otherwise noted. Table 2. 1, 2 B Version Parameter Min Typ Max Unit Test Conditions/Comments Output Current Settling Time 250 μs VDD = 3.6 V, RL = 25 Ω, LL = 680 μH, ¼ scale to ¾ scale change (0x100 to 0x300) Slew Rate 0.3 mA/μs Major Code Change Glitch Impulse 0.15 nA-s 1 LSB change around major carry 3 Digital Feedthrough 0.06 nA-s 1 Temperature range is as follows: B Version = −40°C to +85°C. 2 Guaranteed by design and characterization; not production tested. 3 See the Terminology section. TIMING SPECIFICATIONS V = 2.7 V to 3.6 V. All specifications T to T , unless otherwise noted. DD MIN MAX Table 3. B Version 1 Parameter Limit at TMIN, TMAX Unit Description f 400 kHz max SCL clock frequency SCL t 2.5 μs min SCL cycle time 1 t2 0.6 μs min tHIGH, SCL high time t3 1.3 μs min tLOW, SCL low time t4 0.6 μs min tHD, STA, start/repeated start condition hold time t 100 ns min t , data setup time 5 SU, DAT 2 t 0.9 μs max t , data hold time 6 HD, DAT 0 μs min t7 0.6 μs min tSU, STA, setup time for repeated start t8 0.6 μs min tSU, STO, stop condition setup time t 1.3 μs min t , bus free time between a stop condition and a start condition 9 BUF t 300 ns max t rise time of both SCL and SDA when receiving 10 R, 0 ns min May be CMOS driven t11 250 ns max tF, fall time of SDA when receiving 300 ns max tF, fall time of both SCL and SDA when transmitting 3 20 + 0.1 CB ns min C 400 pF max Capacitive load for each bus line B 1 Guaranteed by design and characterization; not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VINH MIN of the SCL signal) to bridge the undefined region of the SCL falling edge. 3 CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD. Timing Diagram SDA t t t 3 4 9 t t 10 11 SCL t t t t t t 2 t 7 1 8 4 6 5 START REPEATED STOP CONDITION START CONDITION CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram Rev. 0 | Page 4 of 16 05950-002 AD5821 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to AGND –0.3 V to +5.5 V DD other conditions above those indicated in the operational V to DGND –0.3 V to V + 0.3 V DD DD section of this specification is not implied. Exposure to absolute AGND to DGND –0.3 V to +0.3 V maximum rating conditions for extended periods may affect SCL, SDA to DGND –0.3 V to VDD + 0.3 V device reliability. XSHUTDOWN to DGND –0.3 V to VDD + 0.3 V I to AGND –0.3 V to V + 0.3 V SINK DD Operating Temperature Range ESD CAUTION Industrial (B Version) −30°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ MAX) 150°C WLFCSP Power Dissipation (TJ MAX − TA)/θJA 1 θ Thermal Impedance JA Mounted on 4-Layer Board 95°C/W Lead Temperature, Soldering 2 Maximum Peak Reflow Temperature 260°C (±5°C) 1 To achieve the optimum θJA, it is recommended that the AD5821 be soldered on a 4-layer board. 2 As per JEDEC J-STD-020C. Rev. 0 | Page 5 of 16 AD5821 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3 2 1 A B C VIEW FROM BALL SIDE Figure 3. 9-Ball WLCSP Pin Configuration Table 5. 9-Ball WLCSP Pin Function Description Ball Number Mnemonic Description A1 ISINK Output Current Sink. A2 NC No Connection. A3 XSHUTDOWN Power-Down. Asynchronous power-down signal, active low. B1 AGND Analog Ground Pin. B2 DGND Digital Ground Pin. 2 B3 SDA I C Interface Signal. C1 DGND Digital Ground Pin. C2 V Digital Supply Voltage. DD 2 C3 SCL I C Interface Signal. 1515µm NC XSHUTDOWN I SINK 1 8 AGND DGND 7 2 1690µm SDA V 3 DD 6 SCL DGND 4 5 Figure 4. Metallization Photo Dimensions shown in microns (μm) Rev. 0 | Page 6 of 16 05950-021 05950-030 AD5821 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 VERT = 50μs/DIV INL V = 3.8V DD TEMP = 25°C 1.5 1.0 0.5 3 0 HORIZ = 468μA/DIV –0.5 CH3 M50.0μs CODE Figure 5. Typical INL vs. Code Plot Figure 8. Settling Time for a 4-LSB Step (VDD = 3.6 V) 0.6 DNL V = 3.8V DD VERT = 2μA/DIV 4.8μA p-p TEMP = 25°C 0.5 0.4 0.3 0.2 1 0.1 0 –0.1 –0.2 HORIZ = 2s/DIV –0.3 CH1 M2.0s CODE Figure 6. Typical DNL vs. Code Plot Figure 9. 0.1 Hz to 10 Hz Noise Plot (VDD = 3.6 V) 0.14 92.0 I @ +25°C OUT 91.5 0.12 I @ –40°C OUT 91.0 0.10 90.5 I @ +85°C OUT 0.08 90.0 0.06 89.5 0.04 89.0 0.02 88.5 88.0 0 –6 –6 –6 –6 –6 –6 –6 53.5 100.0 150.0 200.0 250.0 300.0 333.1 TIME CODE Figure 7. ¼ to ¾ Scale Settling Time (VDD = 3.6 V) Figure 10. Sink Current vs. Code vs. Temperature (VDD = 3.6 V) Rev. 0 | Page 7 of 16 OUTPUT CURRENT (mA) DNL (LSB) INL (LSB) 0 0 56 56 112 112 168 168 224 224 280 280 336 336 392 392 448 448 504 504 560 560 616 616 672 672 728 728 784 784 840 840 896 896 952 952 1008 1008 1023 1023 05034-006 05034-005 05034-004 I (A) OUT 0 56 112 168 224 280 336 392 448 504 560 616 672 728 784 840 896 952 1008 05034-008 05034-007 1023 05034-009 AD5821 2000 0.45 V = 3.6V DD 1800 0.40 1600 0.35 1400 0.30 V = 4.5V DD 1200 V = 3.8V DD 0.25 1000 0.20 800 0.15 600 0.10 400 0.05 200 0 0 –40 –30 –20 –10 0 15 25 35 45 55 65 75 85 10 100 1k 10k 100k FREQUENCY TEMPERATURE (°C) Figure 11. AC Power Supply Rejection (VDD = 3.6 V) Figure 14. Zero-Code Error vs. Supply Voltage vs. Temperature 1.5 3.5 V = 4.5V DD 3.0 1.0 POSITIVE INL (V = 3.8V) POSITIVE INL (V = 4.5V) DD DD 2.5 0.5 2.0 V = 3.8V DD 0 1.5 POSITIVE INL (V = 3.6V) DD 1.0 –0.5 0.5 NEGATIVE INL (V = 3.6V) DD –1.0 NEGATIVE INL (V = 3.8V) DD 0 –1.5 –0.5 V = 3.6V DD NEGATIVE INL (V = 4.5V) DD –1.0 –2.0 –40–30–20–100 15 2535 455565 75 85 –40 –30 –20 –10 0 15 25 35 45 55 65 75 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Full-Scale Error vs. Temperature vs. Supply Voltage Figure 12. INL vs. Temperature vs. Supply Voltage 1.4 1.0 V = 5.5V 1.3 DD 0.8 V = 4.5V DD 1.2 0.6 POSITIVE DNL (V = 3.6V) V = 3.6V DD DD 1.1 0.4 POSITIVE DNL (V = 4.5V) DD V = 2.7V DD 1.0 0.2 0.9 0 POSITIVE DNL (V = 3.8V) = 3.8V) NEGATIVE DNL (V DD DD 0.8 –0.2 0.7 –0.4 0.6 –0.6 NEGATIVE DNL (V = 4.5V) DD NEGATIVE DNL (V = 3.6V) DD 0.5 –0.8 0.4 –1.0 –50 –30 –10 10 30 50 70 90 –40–30–20–100 15 2535 455565 75 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. SCL and SDA Logic High Level (VINH) vs. Figure 13. DNL vs. Temperature vs. Supply Voltage Supply Voltage and Temperature Rev. 0 | Page 8 of 16 μA/V DNL (LSB) INL (LSB) 05034-010 05034-012 05034-011 VOLTAGE (V) FULL-SCALE ERROR (mA) ZERO-CODE ERROR (mA) 05950-024 05950-014 05950-013 AD5821 1.4 1.4 1.3 1.3 1.2 1.2 1.1 1.1 V = 5.5V DD 1.0 1.0 V = 4.5V DD 0.9 0.9 V = 5.5V DD V = 4.5V DD 0.8 0.8 V = 3.6V DD 0.7 0.7 V = 3.6V DD V = 2.7V DD V = 2.7V DD 0.6 0.6 0.5 0.5 0.4 0.4 –50 –30 –10 10 30 50 70 90 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. SCL and SDA Logic Low Level (VINL) vs. Figure 19. DNL vs. XSHUTDOWN Logic Low Level (VINL) vs. Supply Voltage and Temperature Supply Voltage and Temperature 1.4 V = 5.5V DD 1.3 V = 4.5V DD 1.2 V = 3.6V DD 1.1 V = 2.7V DD 1.0 0.9 0.8 0.7 0.6 0.5 0.4 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) Figure 18. XSHUTDOWN Logic High Level (V ) vs. INH Supply Voltage and Temperature Rev. 0 | Page 9 of 16 VOLTAGE (V) VOLTAGE (V) 05950-025 05950-026 VOLTAGE (V) 05950-027 AD5821 TERMINOLOGY Relative Accuracy Digital-to-Analog Glitch Impulse For the DAC, relative accuracy or integral nonlinearity is a This is the impulse injected into the analog output when the measurement of the maximum deviation, in LSB, from a input code in the DAC register changes state. It is normally straight line passing through the endpoints of the DAC transfer specified as the area of the glitch in nanoamperes per second function. A typical INL vs. code plot is shown in Figure 5. (nA-s) and is measured when the digital input code is changed by 1 LSB at the major carry transition. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured Digital Feedthrough change and the ideal 1 LSB change between any two adjacent Digital feedthrough is a measurement of the impulse injected codes. A specified differential nonlinearity of ±1 LSB maximum into the analog output of the DAC from the digital inputs of the ensures monotonicity. This DAC is guaranteed monotonic by DAC, but it is measured when the DAC output is not updated. design. A typical DNL vs. code plot is shown in Figure 6. It is specified in nanoamperes per second (nA-s) and measured with a full-scale code change on the data bus, that is, from all 0s Zero-Code Error to all 1s and vice versa. Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output Offset Error is 0 mA. The zero-code error is always positive in the AD5821 Offset error is a measurement of the difference between I SINK because the output of the DAC cannot go below 0 mA. This is (actual) and IOUT (ideal) in the linear region of the transfer due to a combination of the offset errors in the DAC and output function, expressed in milliamperes (mA). Offset error is amplifier. Zero-code error is expressed in milliamperes (mA). measured on the AD5821 with Code 16 loaded into the DAC register. Gain Error Gain error is a measurement of the span error of the DAC. It is Offset Error Drift the deviation in slope of the DAC transfer characteristic from Offset error drift is a measurement of the change in offset error the ideal, expressed as a percent of the full-scale range. with a change in temperature. It is expressed in microvolts per degree Celsius (μV/°C). Gain Error Drift Gain error drift is a measurement of the change in gain error with changes in temperature. It is expressed in LSB/°C. Rev. 0 | Page 10 of 16 AD5821 THEORY OF OPERATION The AD5821 is a fully integrated, 10-bit digital-to-analog When the bus is idle, SCL and SDA are both high. The master converter (DAC) with 120 mA output current sink capability. device initiates a serial bus operation by generating a start It is intended for driving voice coil actuators in applications condition, which is defined as a high-to-low transition on the such as lens autofocus, image stabilization, and optical zoom. SDA low while SCL is high. The slave device connected to the The circuit diagram is shown in Figure 20. A 10-bit current bus responds to the start condition and shifts in the next eight output DAC coupled with Resistor R generates the voltage that data bits under control of the serial clock. These eight data bits drives the noninverting input of the operational amplifier. This W consist of a 7-bit address, plus a read/write (R/ ) bit that is 0 if voltage also appears across the R resistor and generates the SENSE data is to be written to a device, and 1 if data is to be read from a 2 sink current required to drive the voice coil. device. Each slave device on an I C bus must have a unique address. The address of the AD5821 is 0001100; however, 0001101, Resistor R and Resistor RSENSE are interleaved and matched. 0001110, and 0001111 address the part because the last two bits Therefore, the temperature coefficient and any nonlinearities are unused/don’t cares (see Figure 22 and Figure 23). Because the over temperature are matched, and the output drift over tempera- W address plus the R/ bit always equals eight bits of data, the write ture is minimized. Diode D1 is an output protection diode. address of the AD5821 is 00011000 (0x18) and the read address V XSHUTDOWN DD DGND is 00011001 (0x19) (see Figure 22 and Figure 23). REFERENCE At the end of the address data, after the R/W bit, the slave POWER-ON V DD device that recognizes its own address responds by generating RESET an acknowledge (ACK) condition. This is defined as the slave D1 SDA 10-BIT 2 I C SERIAL device pulling SDA low while SCL is low before the ninth clock I CURRENT SINK SCL INTERFACE OUTPUT DAC pulse and keeping it low during the ninth clock pulse. Upon receiving ACK, the master device can clock data into the AD5821 R SENSE R in a write operation, or it can clock it out in a read operation. 3.3Ω AD5821 Data must change either during the low period of the clock (because SDA transitions during the high period define a start DGND AGND condition, as described previously), or during a stop condition, Figure 20. Block Diagram Showing Connection to Voice Coil as described in the Data Format section. 2 SERIAL INTERFACE I C data is divided into blocks of eight bits, and the slave generates 2 an ACK at the end of each block. Because the AD5821 requires The AD5821 is controlled using the industry-standard I C 10 bits of data, two data-words must be written to it when a 2-wire serial protocol. Data can be written to or read from the write operation occurs, or read from it when a read operation DAC at data rates of up to 400 kHz. After a read operation, the occurs. At the end of a read or write operation, the AD5821 contents of the input register are reset to all 0s. acknowledges the second data byte. The master generates a stop 2 I C BUS OPERATION condition, defined as a low-to-high transition on SDA while SCL 2 An I C bus operates with one or more master devices that is high, to end the transaction. generate the serial clock (SCL) and read and write data on the DATA FORMAT serial data line (SDA) to and from slave devices such as the 2 Data is written to the AD5821 high byte first, MSB first, and is AD5821. All devices on an I C bus have their SDA pin connected shifted into the 16-bit input register. After all data is shifted in, to the SDA line and their SCL pin connected to the SCL line of 2 data from the input register is transferred to the DAC register. the master device. I C devices can only pull the bus lines low; pulling high is achieved by pull-up resistors, R . The value of R P P Because the DAC requires only 10 bits of data, not all bits of the depends on the data rate, bus capacitance, and the maximum load input register data are used. The MSB is reserved for an active- 2 current that the I C device can sink (3 mA for a standard device). high, software-controlled, power-down function. Bit 14 is unused; 1.8V Bit 13 to Bit 4 correspond to the DAC data bits, Bit 9 to Bit 0. Bit 3 to Bit 0 are unused. R R P P During a read operation, data is read in the same bit order. SDA SCL 2 2 2 I C MASTER I C SLAVE I C SLAVE AD5821 DEVICE DEVICE DEVICE 2 Figure 21. Typical I C Bus Rev. 0 | Page 11 of 16 05950-001 05950-016 AD5821 1191 9 SCL 00 01 1 1 1 R/W SDA PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X START BY ACK BY ACK BY ACK BY STOP BY MASTER AD5821 AD5821 AD5821 MASTER FRAME 1 FRAME 2 FRAME 3 SERIAL BUS MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE Figure 22. Write Operation 1191 9 SCL 00 01 1 1 1R/W PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X SDA START BY ACK BY ACK BY ACK BY STOP BY MASTER AD5821 AD5821 AD5821 MASTER FRAME 1 FRAME 2 FRAME 3 SERIAL BUS MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE Figure 23. Read Operation 1 Table 6. Data Format Serial Data-Words High Byte Low Byte Serial Data Bits SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Input Register R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Function XSHUTDOWN X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 1 XSHUTDOWN = soft power-down; X = unused/don’t care; and D9 to D0 = DAC data. V BATTERY POWER SUPPLY BYPASSING AND GROUNDING L VOICE C COIL When accuracy is important in an application, it is beneficial to V COIL consider power supply and ground return layout on the PCB. R C V DD The PCB for the AD5821 should have separate analog and digital TRACE power supply sections. Where shared AGND and DGND is AD5821 R T DGND RESISTANCE necessary, the connection of grounds should be made at only I SINK one point, as close as possible to the AD5821. Q1 Special attention should be paid to the layout of the AGND return SDA path and, and it should be tracked between the voice coil motor V DROP SCL R R SENSE and I to minimize any series resistance. Figure 24 shows the SINK XSHUTDOWN output current sink of the AD5821 and illustrates the importance of reducing the effective series impedance of AGND and the track AGND DGND resistance between the motor and I . The voice coil is modeled SINK R G as Inductor LC and Resistor RC. The current through the voice coil GROUND RETURN is effectively a dc current that results in a voltage drop, VC, when L G the AD5821 is sinking current. The effect of any series inductance is minimal. Figure 24. Effect of PCB Trace Resistance and Inductance Rev. 0 | Page 12 of 16 05950-019 05950-018 05950-017 AD5821 When sinking the maximum current of 120 mA, the maximum Using another example, if voltage drop allowed across R is 400 mV, and the minimum SENSE V = 3.6 V BATTERY drain to source voltage of Q1 is 200 mV. This means that the R = 0.5 Ω G AD5821 output has a compliance voltage of 600 mV. If VDROP RT = 0.5 Ω falls below 600 mV, the output transistor, Q1, can no longer ISINK = 90 mA operate properly and ISINK may not be maintained as a constant. VDROP = 480 mV (the compliance voltage specification at 90 mA) When sinking 90 mA, the maximum voltage drop allowed Then the largest value of resistance of the voice coil, RC, is across R is 300 mV, and the minimum drain to source SENSE V −[V + (I ×R )+ (I ×R )] voltage of Q1 is 180 mV. This means that the AD5821 output BAT DROP SINK T SINK G R = = C has a compliance voltage of 480 mV. If V falls below 480 mV, I DROP SINK the output transistor, Q1, can no longer operate properly and 3.6 V− [480 mV+ 2× (90 mA× 0.5 Ω)] ISINK may not be maintained as a constant. As ISINK decreases, the =33.66Ω voltage required across the transistor, Q1, also decreases and, 90 mA therefore, lower supplies can be used with the voice coil motor. For this reason, it is important to minimize any series impedance As the current increases to 120 mA through the voice coil, on both the ground return path and interconnect between the V increases. V decreases and eventually approaches the C DROP AD5821 and the motor. It is also important to note that for minimum specified compliance voltage of 600 mV (or 480 mV, lower values of I , the compliance voltage of the output stage SINK if I = 90 mA). The ground return path is modeled by the SINK also decreases. This decrease allows the user to either use voice components RG and LG. The track resistance between the voice coil motors with high resistance values or decrease the power coil and the AD5821 is modeled as RT. The inductive effects of supply voltage on the voice coil motor. The compliance voltage LG influence RSENSE and RC equally, and because the current is decreases as the ISINK current decreases. maintained as a constant, it is not as critical as the purely resistive The power supply of the AD5821, or the regulator used to supply component of the ground return path. When the maximum sink the AD5821, should be decoupled. Best practice power supply current is flowing through the motor, the resistive elements, R and T decoupling recommends that the power supply be decoupled R , may have an impact on the voltage headroom of Q1 and G with a 10 μF capacitor. Ideally, this 10 μF capacitor should be of could, in turn, limit the maximum value of R because of C a tantalum bead type. However, if the power supply or regulator voltage compliance. supply is well regulated and clean, such decoupling may not be For example, if required. The AD5821 should be decoupled locally with a 0.1 μF ceramic capacitor, and this 0.1 μF capacitor should be located as VBATTERY = 3.6 V close as possible to the VDD pin. The 0.1 μF capacitor should be RG = 0.5 Ω ceramic with a low effective series resistance and effective series R = 0.5 Ω T inductance. The 0.1 μF capacitor provides a low impedance path I = 120 mA SINK to ground for high transient currents. V = 600 mV (the compliance voltage) DROP The power supply line should have as large a trace as possible to Then the largest value of resistance of the voice coil, R , is C provide a low impedance path and reduce glitch effects on the V −[V + (I ×R )+ (I ×R )] BAT DROP SINK T SINK G supply line. Clocks and other fast switching digital signals should R = = C I SINK be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When 3.6 V−[600 mV+ 2×(120 mA× 0.5 Ω)] traces cross on opposite sides of the board, they should run at = 24 Ω right angles to each other to reduce feedthrough effects through 120 mA the board. The best technique is to use a multilayer board with ground and power planes, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Rev. 0 | Page 13 of 16 AD5821 APPLICATIONS INFORMATION The AD5821 is designed to drive both spring-preloaded and 0.5 nonspring linear motors used in applications such as lens auto- focus, image stabilization, or optical zoom. The operation principle 0.4 of the spring-preloaded motor is that the lens position is controlled by the balancing of a voice coil and spring. Figure 25 shows the 0.3 transfer curve of a typical spring-preloaded linear motor for autofocus. The key points of this transfer function are displace- 0.2 START ment or stroke, which is the actual distance the lens moves in CURRENT millimeters (mm) and the current through the motor, measured 0.1 in milliamps (mA). A start current is associated with spring-preloaded linear 10 20 30 40 50 60 70 80 90 100 110 120 motors, which is a threshold current that must be exceeded for SINK CURRENT (mA) any displacement in the lens to occur. The start current is usually Figure 25. Spring-Preloaded Voice Coil Stroke vs. Sink Current 20 mA or greater; the rated stroke or displacement is usually 0.25 mm to 0.4 mm; and the slope of the transfer curve is approximately 10 μm/mA or less. The AD5821 is designed to sink up to 120 mA, which is more than adequate for available commercial linear motors or voice coils. Another factor that makes the AD5821 the ideal solution for these applications is the monotonicity of the device, ensuring that lens positioning is repeatable for the application of a given digital word. Figure 26 shows a typical application circuit for the AD5821. V DD V CC 0.1µF 6 2 V DD POWER-ON VOICE REFERENCE RESET 1 COIL XSHUTDOWN R R P P D1 SDA 10-BIT 3 2 I C SERIAL I 8 SINK CURRENT INTERFACE SCL OUTPUT DAC 4 2 2 I C MASTER I C SLAVE R R SENSE DEVICE DEVICE AD5821 5 7 V DD V CC + + 10µF 0.1µF 10µF Figure 26. Typical Application Circuit Rev. 0 | Page 14 of 16 STROKE (mm) 05950-028 05950-029 AD5821 OUTLINE DIMENSIONS 0.65 0.59 1.575 0.53 1.515 SEATING 1.455 3 2 1 PLANE A 0.36 BALL 1 0.32 IDENTIFIER 1.750 0.28 1.690 B 1.630 C 0.50 BSC BALL PITCH TOP VIEW BOTTOM VIEW 0.28 (BALL SIDE DOWN) (BALL SIDE UP) 0.24 0.20 Figure 27. 9-Ball Wafer Level Chip Scale Package [WLCSP] (CB-9-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding 1 AD5821BCBZ-REEL7 −40°C to +85°C 9-Ball Wafer Level Chip Scale Package (WLCSP) CB-9-1 D82 1 AD5821BCBZ-REEL −40°C to +85°C 9-Ball Wafer Level Chip Scale Package (WLCSP) CB-9-1 D82 AD5821-WAFER −40°C to +85°C Bare Die Wafer AD5821D-WAFER −40°C to +85°C Bare Die Wafer on Film 1 EVAL-AD5821EBZ Evaluation Board 1 Z = Pb-free part. Rev. 0 | Page 15 of 16 110405-0 AD5821 NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05950-0-1/07(0) TTTT Rev. 0 | Page 16 of 16