ANALOG DEVICES AD5790

System Ready, 20-Bit, ±2LSB INL, Voltage Output DAC Data Sheet AD5790 FEATURES FUNCTIONAL BLOCK DIAGRAM V V V CC DD REFP Single 20-bit voltage output DAC, ±2 LSB INL 8 nV/√Hz output noise spectral density 6.8kΩ 6.8kΩ 0.1 LSB long-term linearity error stability A1 R IOV CC FB R1 R FB ±0.018 ppm/°C gain error temperature coefficient INV SDIN INPUT 20 20 2.5 μs output voltage settling time SHIFT DAC 20-BIT SCLK V OUT REGISTER DAC REG 3.5 nV-sec midscale glitch impulse AND SYNC CONTROL Integrated precision reference buffers LOGIC SDO Operating temperature range: −40°C to +125°C 6kΩ LDAC 4 mm × 5 mm LFCSP package CLR POWER-ON-RESET Wide power supply range of up to ±16.5 V AND CLEAR LOGIC RESET AD5790 35 MHz Schmitt-triggered digital interface DGND V AGND V 1.8 V compatible digital interface SS REFN Figure 1. APPLICATIONS Table 1. Related Devices Part No. Description Medical instrumentation AD5791 20-bit, 1 LSB accurate DAC Test and measurement AD5780 18-bit, ±1 LSB INL, voltage output DAC , Industrial control buffered reference inputs Scientific and aerospace instrumentation AD5781 18-bit, ±1 LSB INL, voltage Output DAC , Data acquisition systems unbuffered reference inputs Digital gain and offset adjustment AD5760 16-bit, ±0.5 LSB INL, voltage Output DAC Power supply control AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC GENERAL DESCRIPTION 1 The AD5790 is a single 20-bit, unbuffered voltage-output DAC PRODUCT HIGHLIGHTS that operates from a bipolar supply of up to 33 V. The AD5790 1. 20-bit resolution. accepts a positive reference input in the range of 5 V to VDD − 2. Wide power supply range of up to ±16.5 V. 2.5 V and a negative reference input in the range of V + 2.5 V SS 3. −40°C to +125°C operating temperature range. to 0 V. The AD5790 offers a relative accuracy specification of 4. Low 8 nV/√Hz noise. ±2 LSB maximum range, and operation is guaranteed mono- 5. Low ±0.018 ppm/°C gain error temperature coefficient. tonic with a −1 LSB to +3 LSB DNL specification. COMPANION PRODUCTS The part uses a versatile 3-wire serial interface that operates at Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1 clock rates of up to 35 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards. External Reference: ADR445 Reference buffers are also provided on chip. The part incorpo- DC-to-DC Design Tool: ADIsimPower™ rates a power-on reset circuit that ensures the DAC output Additional companion products on the AD5790 product page powers up to 0 V in a known output impedance state and remains in this state until a valid write to the device takes place. The part provides a disable feature that places the output in a defined load state. The part provides an output clamp feature that places the output in a defined load state. 1 Protected by U.S. Patent No. 7,884,747. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 10239-001 AD5790 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  DAC Architecture....................................................................... 19  Applications....................................................................................... 1  Serial Interface ............................................................................ 19  Functional Block Diagram .............................................................. 1  Standalone Operation................................................................ 20  General Description ......................................................................... 1  Hardware Control Pins.............................................................. 20  Product Highlights ........................................................................... 1  On-Chip Registers...................................................................... 21  Companion Products ....................................................................... 1  AD5790 Features ............................................................................ 24  Revision History ............................................................................... 2  Power-On to 0 V......................................................................... 24  Specifications..................................................................................... 3  Configuring the AD5790 .......................................................... 24  Timing Characteristics ................................................................ 5  DAC Output State ...................................................................... 24  Absolute Maximum Ratings............................................................ 8  Output Amplifier Configuration.............................................. 24  ESD Caution.................................................................................. 8  Applications Information .............................................................. 26  Pin Configuration and Function Descriptions............................. 9  Typical Operating Circuit ......................................................... 26  Typical Performance Characteristics ........................................... 10  Evaluation Board........................................................................ 27  Terminology .................................................................................... 18  Outline Dimensions....................................................................... 28  Theory of Operation ...................................................................... 19  Ordering Guide .......................................................................... 28  REVISION HISTORY 2/12—Rev. A to Rev. B Deleted Linearity Compensation Section ................................... 24 12/11—Rev. 0 to Rev. A Changes to Table 1............................................................................ 1 Changes to Table 2............................................................................ 4 Changes to Figure 48...................................................................... 17 Changes to DAC Register Section................................................ 21 Changes to Table 11........................................................................ 22 Updated Outline Dimensions ....................................................... 28 11/11—Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet AD5790 SPECIFICATIONS VDD = 12.5 V to 16.5 V, VSS = −16.5 V to −12.5 V, VREFP = 10 V, VREFN = −10 V, VCC = 2.7 V to +5.5 V, IOVCC = 1.71 V to 5.5 V, RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted. Table 2. 1 B Version Parameter Min Typ Max Unit Test Conditions/Comments 2 STATIC PERFORMANCE Resolution 20 Bits Integral Nonlinearity Error (Relative −2 ±1.2 +2 LSB V = +10 V, V = −10 V, T = 0°C to 105°C REFP REFN A Accuracy) −3 ±1.2 +3 LSB VREFP = +10 V, VREFN = −10 V, TA =−40°C to +105°C −4 ±1.2 +4 LSB V = ±10 V, +10 V, and +5 V REFx Differential Nonlinearity Error −1 +2 LSB VREFP = +10 V, VREFN = −10 V, TA = 0°C to 105°C −1 +3 LSB V = ±10 V, +10 V, and +5 V REFx 3 Long-Term Linearity Error Stability 0.1 LSB After 750 hours at T = 135°C A Full-Scale Error −12 ±3.8 +12 LSB VREFP = +10 V, VREFN = −10 V −22 ±2.7 +22 LSB V = 10 V, V = 0 V REFP REFN −40 ±1.8 +40 LSB VREFP = 5 V, VREFN = 0 V −9 ±3.8 +9 LSB VREFP = +10 V, VREFN = −10 V, TA = 0°C to 105°C −12 ±2.7 +12 LSB V = 10 V, V = 0 V, T = 0°C to 105°C REFP REFN A −22 ±1.8 +22 LSB VREFP = 5 V, VREFN = 0 V, TA = 0°C to 105°C Full-Scale Error Temperature Coefficient ±0.026 ppm/°C V = +10 V, V = −10 V REFP REFN Zero-Scale Error −19 ±1.3 +19 LSB VREFP = +10 V, VREFN = −10 V −40 ±0.7 +40 LSB VREFP = 10 V, VREFN = 0 V −82 ±0.9 +82 LSB V = 5 V, V = 0 V REFP REFN −8 ±1.3 +8 LSB VREFP = +10 V, VREFN = −10 V, TA = 0°C to 105°C −13 ±0.7 +13 LSB V = 10 V, V = 0 V, T = 0°C to 105°C REFP REFN A −22 ±0.9 +22 LSB V = 5 V, V = 0 V, T = 0°C to 105°C REFP REFN A Zero-Scale Error Temperature Coefficient ±0.025 ppm/°C VREFP = +10 V, VREFN = −10 V Gain Error −19 ±2.3 +19 ppm FSR V = +10 V, V = −10 V REFP REFN −35 ±1.9 +35 ppm FSR VREFP = 10 V, VREFN = 0 V −68 ±0.9 +68 ppm FSR VREFP = 5 V, VREFN = 0 V −9 ±2.3 +9 ppm FSR V = +10 V, V = −10 V, T = 0°C to 105°C REFP REFN A −15 ±2.9 +15 ppm FSR VREFP = 10 V, VREFN = 0 V, TA = 0°C to 105°C −22 ±0.9 +22 ppm FSR V = 5 V, V = 0 V, T = 0°C to 105°C REFP REFN A Gain Error Temperature Coefficient ±0.018 ppm/°C VREFP = +10 V, VREFN = −10 V R1, RFB Matching 0.015 % OUTPUT CHARACTERISTICS Output Voltage Range V V V REFN REFP Output Voltage Settling Time 2.5 μs 10 V step to 0.02%, using the ADA4898-1 buffer in unity-gain mode 4 3.5 μs 500 code step to ±1 LSB Output Noise Spectral Density 8 nV/√Hz At 1 kHz, DAC code = midscale 8 nV/√Hz At 10 kHz, DAC code = midscale Output Voltage Noise 1.1 μV p-p DAC code = midscale, 0.1 Hz to 10 Hz bandwidth 4 Midscale Glitch Impulse 14 nV-sec VREFP = +10 V, VREFN = −10 V 3.5 nV-sec VREFP = 10 V, VREFN = 0 V 4 nV-sec V = 5 V, V = 0 V REFP REFN 4 MSB Segment Glitch Impulse 14 nV-sec V = +10 V, V = −10 V, see Figure 43 REFP REFN 3.5 nV-sec VREFP = 10 V, VREFN = 0 V, see Figure 44 4 nV-sec VREFP = 5 V, VREFN = 0 V, see Figure 45 Rev. B | Page 3 of 28 AD5790 Data Sheet 1 B Version Parameter Min Typ Max Unit Test Conditions/Comments Output Enabled Glitch Impulse 57 nV-sec On removal of output ground clamp Digital Feedthrough 0.27 nV-sec DC Output Impedance (Normal Mode) 3.4 kΩ DC Output Impedance (Output 6 kΩ Clamped to Ground) REFERENCE INPUTS VREFP Input Range 5 VDD − 2.5 V V Input Range V + 2.5 0 V REFN SS Input Bias Current −20 −0.63 +20 nA −4 −0.63 +4 T = 0°C to 105°C A Input Capacitance 1 pF V , V REFP REFN LOGIC INPUTS 5 Input Current −1 +1 μA Input Low Voltage, V 0.3 × IOV V IOV = 1.71 V to 5.5 V IL CC CC Input High Voltage, VIH 0.7 × IOVCC V IOVCC = 1.71 V to 5.5 V Pin Capacitance 5 pF LOGIC OUTPUT (SDO) Output Low Voltage, V 0.4 V IOV = 1.71 V to 5.5 V, sinking 1 mA OL CC Output High Voltage, VOH IOVCC − 0.5 V IOVCC = 1.71 V to 5.5 V, sourcing 1 mA High Impedance Leakage Current ±1 μA High Impedance Output Capacitance 3 pF POWER REQUIREMENTS All digital inputs at DGND or IOV CC VDD 7.5 VSS + 33 V VSS VDD − 33 −2.5 V V 2.7 5.5 V CC IOVCC 1.71 5.5 V IOVCC ≤ VCC I 10.3 14 mA DD ISS −10 −14 mA ICC 600 900 μA IOI 52 140 μA SDO disabled CC DC Power Supply Rejection Ratio ±7.5 μV/V ∆VDD ± 10%, VSS = −15 V ±1.5 μV/V ∆V ± 10%, V = 15 V SS DD AC Power Supply Rejection Ratio 90 dB ∆V ± 200 mV, 50 Hz/60 Hz, V = −15 V DD SS 90 dB ∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V 1 Temperature range: −40°C to +125°C, typical conditions: T = +25°C, V = +15 V, V = −15 V, V = +10 V, V = −10 V. A DD SS REFP REFN 2 Performance characterized with the AD8675ARZ output buffer. 3 Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified. 4 The AD5790 is configured in unity-gain mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead capacitance, and so forth). 5 Current flowing in an individual logic pin. Rev. B | Page 4 of 28 Data Sheet AD5790 TIMING CHARACTERISTICS VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. 1 Limit Parameter Unit Test Conditions/Comments IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.5 V 2 t 40 28 ns min SCLK cycle time 1 92 60 ns min SCLK cycle time (readback and daisy-chain modes) t2 15 10 ns min SCLK high time t3 9 5 ns min SCLK low time t4 5 5 ns min SYNC to SCLK falling edge setup time t 2 2 ns min SCLK falling edge to SYNC rising edge hold time 5 t 48 40 ns min Minimum SYNC high time 6 t7 8 6 ns min SYNC rising edge to next SCLK falling edge ignore t8 9 7 ns min Data setup time t9 12 7 ns min Data hold time t 13 10 ns min LDAC falling edge to SYNC falling edge 10 t 20 16 ns min SYNC rising edge to LDAC falling edge 11 t 14 11 ns min pulse width low 12 LDAC t13 130 130 ns typ LDAC falling edge to output response time t14 130 130 ns typ SYNC rising edge to output response time (LDAC tied low) t15 50 50 ns min CLR pulse width low t 140 140 ns typ CLR pulse activation time 16 t 0 0 ns min SYNC falling edge to first SCLK rising edge 17 t18 65 60 ns max SYNC rising edge to SDO tristate (CL = 50 pF) t19 62 45 ns max SCLK rising edge to SDO valid (CL = 50 pF) t20 0 0 ns min SYNC rising edge to SCLK rising edge ignore t 35 35 ns typ RESET pulse width low 21 t 150 150 ns typ RESET pulse activation time 22 1 All input signals are specified with t = t = 1 ns/V (10% to 90% of IOV ) and timed from a voltage level of (V + V )/2. R F CC IL IH 2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes. Rev. B | Page 5 of 28 AD5790 Data Sheet t t 1 7 SCLK 1 2 24 t t t 6 3 2 t t 4 5 SYNC t 9 t 8 SDIN DB23 DB0 t t 12 10 t 11 LDAC t V 13 OUT t V 14 OUT t 15 CLR t 16 V OUT t 21 RESET t 22 V OUT Figure 2. Write Mode Timing Diagram t 20 t t 1 t 17 7 SCLK 12 2 4 1 2 24 t t t 3 2 6 t t 5 17 t t 4 5 SYNC t 9 t 8 SDIN DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION t 18 REGISTER TO BE READ t 19 SDO DB23 DB0 REGISTER CONTENTS CLOCKED OUT Figure 3. Readback Mode Timing Diagram Rev. B | Page 6 of 28 10239-002 10239-003 Data Sheet AD5790 t t 20 t 1 17 SCLK 12 24 25 26 48 t t t 3 2 6 t 5 t 4 SYNC t 9 t 8 SDIN DB23 DB0 DB23 DB0 INPUT WORDFORDACN– 1 INPUT WORD FOR DAC N t t 18 19 SDO DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N UNDEFINED Figure 4. Daisy-Chain Mode Timing Diagram Rev. B | Page 7 of 28 10239-004 AD5790 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to AGND −0.3 V to +34 V DD other conditions above those indicated in the operational VSS to AGND −34 V to +0.3 V section of this specification is not implied. Exposure to absolute VDD to VSS −0.3 V to +34 V maximum rating conditions for extended periods may affect VCC to DGND −0.3 V to +7 V device reliability. IOV to DGND −0.3 V to V + 3 V or +7 V CC CC (whichever is less) This device is a high performance integrated circuit with an Digital Inputs to DGND −0.3 V to IOVCC + 0.3 V or ESD rating of <1.6 kV, and it is ESD sensitive. Proper +7 V (whichever is less) precautions must be taken for handling and assembly. VOUT to AGND −0.3 V to VDD + 0.3 V VREFP to AGND −0.3 V to VDD + 0.3 V V to AGND V − 0.3 V to + 0.3 V REFN SS ESD CAUTION DGND to AGND −0.3 V to +0.3 V Operating Temperature Range, TA Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature, 150°C T max J Power Dissipation (T max − T )/θ J A JA LFCSP Package θJA Thermal Impedance 31.0°C/W Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 1.6 kV Rev. B | Page 8 of 28 Data Sheet AD5790 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 19 AGND OUT V V 2 18 REFP SS V V DD 3 17 SS AD5790 V RESET 4 16 REFN TOP VIEW V 5 (Not to Scale) 15 DGND DD CLR 6 14 SYNC LDAC 7 13 SCLK NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. NEGATIVE ANALOG SUPPLY CONNECTION (V ). SS A VOLTAGE IN THE RANGE OF –16.5 V TO –2.5 V CAN BE CONNECTED. V SHOULD BE DECOUPLED SS TO AGND. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE VSS PINS. IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT Analog Output Voltage. 2 VREFP Positive Reference Voltage Input. A voltage in the range of 5 V to VDD − 2.5 V can be connected. 3, 5 V Positive Analog Supply Connection. A voltage in the range of 7.5 V to 16.5 V can be connected. V must be DD DD decoupled to AGND. 4 RESET Active Low Reset. Asserting this pin returns the AD5790 to its power-on status. 6 CLR Active Low Input. Asserting this pin sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. 7 LDAC Active Low Load DAC Logic Input. This is used to update the DAC register and, consequently, the analog output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The LDAC pin should not be left unconnected. 8 VCC Digital Supply. Voltage range is from 2.7 V to 5.5 V. VCC should be decoupled to DGND. 9 IOV Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. Voltage range is CC from 1.71 V to 5.5 V 10, 21, 22, 23 DNC Do Not Connect. Do not connect to these pins. 11 SDO Serial Data Output. 12 SDIN Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 35 MHz. 14 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The DAC is updated on the rising edge of SYNC. 15 DGND Ground Reference Pin for Digital Circuitry. 16 VREFN Negative Reference Voltage Input. 17, 18 V Negative Analog Supply Connection. A voltage in the range of −16.5 V to −2.5 V can be connected. V must be SS SS decoupled to AGND. 19 AGND Ground Reference Pin for Analog Circuitry. 20 R FB Feedback Connection for External Amplifier. See the AD5790 Features section for further details. 24 INV Inverting Input Connection for External Amplifier. See the AD5790 Features section for further details. EPAD VSS Negative Analog Supply Connection (VSS). A voltage in the range of −16.5 V to −2.5 V can be connected. VSS must be decoupled to AGND. The paddle can be left electrically unconnected provided that a supply connection is made at the VSS pins. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. B | Page 9 of 28 INV V CC IOV DNC CC DNC DNC SDO DNC SDIN R FB 10239-005 8 24 9 23 10 22 11 21 12 20 AD5790 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AD8675 OUTPUT BUFFER 2.0 AD8675 OUTPUT BUFFER 1.25 T = 25°C A T = 25°C A 1.5 0.75 1.0 0.5 0.25 0 –0.5 –0.25 –1.0 –0.75 –1.5 V = +10V –2.0 REFP –1.25 V = +5V V = –10V REFN REFP V = 0V V = +15V DD REFN –2.5 V = +15V V = –15V SS DD V = –15V –1.75 SS 0 200000 400000 600000 800000 1000000 1200000 –3.0 0 200000 400000 600000 800000 1000000 1200000 DAC CODE DAC CODE Figure 6. Integral Nonlinearity Error vs. DAC Code, ±10 V Span Figure 9. Integral Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain Mode 2.5 2.0 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER T = 25°C A T = 25°C A 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 V = +10V REFP V = +10V REFP V = 0V –1.0 REFN V = –10V –1.5 REFN V = +15V DD V = +15V DD V = –15V SS V = –15V SS –2.0 –1.5 0 200000 400000 600000 800000 1000000 1200000 0 200000 400000 600000 800000 1000000 1200000 DAC CODE DAC CODE Figure 10. Differential Nonlinearity Error vs. DAC Code, ±10 V Span Figure 7. Integral Nonlinearity Error vs. DAC Code, 10 V Span 2.0 2.0 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER T = 25°C T = 25°C A A 1.5 1.5 1.0 1.0 0.5 0 0.5 –0.5 0 –1.0 –0.5 –1.5 –2.0 V = +10V REFP V = +5V REFP –1.0 V = 0V REFN V = 0V REFN –2.5 V = +15V DD V = +15V DD V = –15V SS V = –15V SS –1.5 –3.0 0 200000 400000 600000 800000 1000000 1200000 0 200000 400000 600000 800000 1000000 1200000 DAC CODE DAC CODE Figure 11. Differential Nonlinearity Error vs. DAC Code, 10 V Span Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span Rev. B | Page 10 of 28 INL (LSB) INL (LSB) INL (LSB) 10239-008 10239-006 10239-007 DNL (LSB) INL (LSB) DNL (LSB) 10239-009 10239-011 10239-010 Data Sheet AD5790 3.0 ±10V SPAN MAX DNL ±10V SPAN MIN DNL AD8675 OUTPUT BUFFER 1.6 V = +5V REFP +10V SPAN MAX DNL +10V SPAN MIN DNL T = 25°C V = 0V A REFN +5V SPAN MAX DNL +5V SPAN MIN DNL 2.5 V = +15V DD 1.4 V = –15V SS 2.0 1.2 1.0 1.5 0.8 1.0 0.6 V = +15V DD V = –15V 0.5 SS AD8675 OUTPUT BUFFER 0.4 0 0.2 –0.5 0 –0.2 –1.0 –40 –20 0 20 40 60 80 100 0 200000 400000 600000 800000 1000000 1200000 TEMPERATURE (°C) DAC CODE Figure 15. Differential Nonlinearity Error vs. Temperature Figure 12. Differential Nonlinearity Error vs. DAC Code, 5 V Span 1.5 2.5 AD8675 OUTPUT BUFFER V = +5V REFP T = 25°C A V = 0V REFN INL MAX V = +15V DD 2.0 1.0 V = –15V SS 1.5 0.5 1.0 T = 25°C A V = +10V 0 REFP V = –10V REFN AD8675 OUTPUT BUFFER 0.5 –0.5 0 –1.0 INL MIN –0.5 –1.5 –1.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 0 200000 400000 600000 800000 1000000 1200000 V /|V | (V) DD SS DAC CODE Figure 16. Integral Nonlinearity Error vs. Supply Voltage, ±10 V Span Figure 13. Differential Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain Mode 1.8 2.5 ±10V SPAN MAX INL ±10V SPAN MIN INL INL MAX +10V SPAN MAX INL +10V SPAN MIN INL 1.3 2.0 +5V SPAN MAX INL +5V SPAN MIN INL 0.8 1.5 0.3 T = 25°C 1.0 A V = 5V REFP V = 0V REFN –0.2 0.5 AD8675 OUTPUT BUFFER V = +15V DD V = –15V SS –0.7 0 AD8675 OUTPUT BUFFER –1.2 –0.5 INL MIN –1.7 –1.0 –2.2 –1.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 –40 –20 0 20406080 100 V /|V | (V) TEMPERATURE (°C) DD SS Figure 17. Integral Nonlinearity Error vs. Supply Voltage, 5 V Span Figure 14. Integral Nonlinearity Error vs. Temperature Rev. B | Page 11 of 28 DNL (LSB) DNL (LSB) INL ERROR (LSB) 10239-014 10239-013 10239-012 INL ERROR (LSB) INL ERROR (LSB) DNL ERROR (LSB) 10239-015 10239-016 10239-017 AD5790 Data Sheet 1.4 11 T = 25°C A V = 5V REFP DNL MAX 1.2 9 V = 0V REFN AD8675 OUTPUT BUFFER 1.0 7 0.8 T = 25°C A 5 V = +10V REFP V = –10V REFN 0.6 AD8675 OUTPUT BUFFER 3 0.4 1 0.2 –1 DNL MIN 0 –3 –0.2 –5 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V /|V | (V) DD SS V /|V | (V) DD SS Figure 18. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span Figure 21. Zero-Scale Error vs. Supply Voltage, 5 V Span 1.4 –0.2 T = 25°C DNL MAX A V = +10V REFP –0.4 1.2 V = –10V REFN AD8675 OUTPUT BUFFER –0.6 1.0 –0.8 0.8 –1.0 T = 25°C A 0.6 V = 5V REFP V = 0V REFN –1.2 AD8675 OUTPUT BUFFER 0.4 –1.4 0.2 –1.6 DNL MIN 0 –1.8 –0.2 –2.0 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 V /|V | (V) DD SS V /|V | (V) DD SS Figure 19. Differential Nonlinearity Error vs. Supply Voltage, 5 V Span Figure 22. Midscale Error vs. Supply Voltage, ±10 V Span 10 T = 25°C A T = 25°C A V = +10V REFP V = 5V 1.0 V = –10V REFP 8 REFN V = 0V REFN AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER 6 0.5 4 0 2 0 –0.5 –2 –1.0 –4 –6 –1.5 –8 –2.0 –10 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V /|V | (V) DD SS V /|V | (V) DD SS Figure 20. Zero-Scale Error vs. Supply Voltage, ±10 V Span Figure 23. Midscale Error vs. Supply Voltage, 5 V Span Rev. B | Page 12 of 28 ZERO-SCALE ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 10239-020 10239-019 10239-018 MIDSCALE ERROR (LSB) MIDSCALE ERROR (LSB) ZERO-SCALE ERROR (LSB) 10239-023 10239-022 10239-021 Data Sheet AD5790 2.0 6.0 T = 25°C A V = +10V REFP 1.8 5.8 V = –10V REFN AD8675 OUTPUT BUFFER 1.6 5.6 1.4 5.4 1.2 5.2 1.0 5.0 0.8 4.8 0.6 4.6 0.4 4.4 T = 25°C A V = 5V REFP 0.2 4.2 V = 0V REFN AD8675 OUTPUT BUFFER 0 4.0 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 V /|V | (V) V /|V | (V) DD SS DD SS Figure 27. Gain Error vs. Supply Voltage, 5 V Span Figure 24. Full-Scale Error vs. Supply Voltage, ±10 V Span 1.25 8 T = 25°C A V = 5V REFP INL MAX 6 V = 0V REFN 0.75 AD8675 OUTPUT BUFFER 4 2 0.25 T = 25°C A V = +15V DD 0 V = –15V SS AD8675 OUTPUT BUFFER –0.25 –2 –4 –0.75 –6 INL MIN –8 –1.25 –10 –12 –1.75 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 5.05.5 6.06.57.07.58.0 8.59.09.5 10.0 V /|V | (V) V /|V | (V) DD SS REFP REFN Figure 25. Full-Scale Error vs. Supply Voltage, 5 V Span Figure 28. Integral Nonlinearity Error vs. Reference Voltage 1.5 1.15 T = 25°C A V = +10V REFP INL MAX V = –10V REFN 0.95 AD8675 OUTPUT BUFFER 1.0 0.75 0.5 T = 25°C 0.55 A V = +15V DD V = –15V SS AD8675 OUTPUT BUFFER 0.35 0 0.15 INL MIN –0.5 –0.05 –0.25 –1.0 5.0 5.56.06.57.07.58.08.59.09.5 10.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 V /|V | (V) REFP REFN V /|V | (V) DD SS Figure 26. Gain Error vs. Supply Voltage, ±10 V Span Figure 29. Differential Nonlinearity Error vs. Reference Voltage Rev. B | Page 13 of 28 GAIN ERROR (LSB) FULL-SCALE ERROR (LSB) FULL-SCALE ERROR (LSB) 10239-024 10239-026 10239-025 INL ERROR (LSB) DNL ERROR (LSB) GAIN ERROR (LSB) 10239-029 10239-027 10239-028 AD5790 Data Sheet –4.0 T = 25°C A T = 25°C –0.1 A V = +15V DD V = +15V DD V = –15V SS V = –15V SS –4.5 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER –0.3 –5.0 –0.5 –5.5 –0.7 –6.0 –0.9 –1.1 –6.5 –1.3 –7.0 –1.5 –7.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 V /|V | (V) REFP REFN V /|V | (V) REFP REFN Figure 30. Zero-Scale Error vs. Reference Voltage Figure 33. Gain Error vs. Reference Voltage –1.0 7.0 T = 25°C A V = +15V DD V = +15V V = –15V REFP SS V = –15V REFN 6.5 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER –1.5 6.0 5.5 –2.0 5.0 –2.5 4.5 4.0 –3.0 ±10V SPAN 3.5 +10V SPAN +5V SPAN –3.5 3.0 5.05.56.06.57.07.5 8.0 8.59.09.5 10.0 –40 –20 0 20 40 60 80 100 V /|V | (V) TEMPERATURE (°C) REFP REFN Figure 31. Midscale Error vs. Reference Voltage Figure 34. Full-Scale Error vs. Temperature 6.5 3 T = 25°C V = +15V ±10V SPAN A DD V = +15V V = –15V +10V SPAN DD SS V = –15V AD8675 OUTPUT BUFFER +5V SPAN SS 2 6.0 AD8675 OUTPUT BUFFER 1 5.5 0 5.0 –1 –2 4.5 –3 4.0 –4 3.5 –5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 –40 –20 0 204060 80 100 V /|V | (V) REFP REFN TEMPERATURE (°C) Figure 32. Full-Scale Error vs. Reference Voltage Figure 35. Midscale Error vs. Temperature Rev. B | Page 14 of 28 FULL-SCALE ERROR (LSB) MIDSCALE ERROR (LSB) ZERO-SCALE ERROR (LSB) 10239-030 10239-032 10239-031 GAIN ERROR (LSB) MIDSCALE ERROR (LSB) FULL-SCALE ERROR (LSB) 10239-034 10239-035 10239-033 Data Sheet AD5790 0.010 5 V = +15V ±10V SPAN DD V = –15V +10V SPAN SS 0.008 +5V SPAN 3 AD8675 OUTPUT BUFFER I DD 0.006 1 0.004 –1 0.002 –3 0 –0.002 –5 –0.004 –7 –0.006 I SS –9 –0.008 –11 –0.010 –40 –20 0 20 40 60 80 100 –20 –15 –10 –5 0 5 10 15 20 V /V (V) TEMPERATURE (°C) DD SS Figure 36. Zero-Scale Error vs. Temperature Figure 39. Power Supply Currents vs. Power Supply Voltages 0 6 V = +15V ±10V SPAN DD V = –15V +10V SPAN SS +5V SPAN –2 AD8675 OUTPUT BUFFER 4 –4 2 –6 0 –8 –2 –4 –10 –6 –12 –8 –14 –10 –16 –1 01 2345 –40 –20 0 20406080 100 TIME (µs) TEMPERATURE (°C) Figure 37. Gain Error vs. Temperature Figure 40. Rising Full-Scale Voltage Step 6 900 IOV = 5V, LOGIC VOLTAGE CC T = 25°C A INCREASING 800 4 IOV = 5V, LOGIC VOLTAGE CC DECREASING 700 IOV = 3V, LOGIC VOLTAGE CC 2 INCREASING IOV = 3V, LOGIC VOLTAGE 600 CC 0 DECREASING 500 –2 400 –4 300 –6 200 –8 100 –10 0 –1 0 12345 01 2 345 6 TIME (µs) LOGIC INPUT VOLTAGE (V) Figure 38. IOI vs. Logic Input Voltage Figure 41. Falling Full-Scale Voltage Step CC Rev. B | Page 15 of 28 IOI (µA) GAIN ERROR (LSB) ZERO-SCALE ERROR (LSB) CC 10239-037 10239-036 10239-038 I /I (mA) DD SS V (V) V (V) OUT OUT 10239-041 10239-040 10239-039 AD5790 Data Sheet 10 6 V = 5V NEGATIVE REFP V = 0V POSITIVE REFN 9 UNITY GAIN MODE ADA4898-1 5 8 RC LOW-PASS FILTER 7 4 6 5 3 4 2 3 V = +10V 2 REFP V = –10V 1 REFN RC LOW-PASS FILTER 1 UNITY GAIN MODE ADA4898-1 0 0 –1 012 345 TIME (µs) CODE Figure 42. 500 Code Step Settling Time Figure 45. 6 MSB Segment Glitch Energy for 5 V VREF 25 55 ±10V SPAN V = +10V NEGATIVE V = +10V REFP REFP +10V SPAN V = –10V POSITIVE REFN V = –10V REFN +5V SPAN 45 UNITY GAIN MODE RC LOW-PASS FILTER ADA4898-1 UNITY GAIN MODE 20 RC LOW-PASS FILTER ADA4898-1 NEGATIVE CODE POSITIVE CODE 35 CHANGE CHANGE 25 15 15 10 5 –5 5 –15 –25 0 10 12 3 TIME (µs) CODE Figure 43. 6 MSB Segment Glitch Energy for ±10 V VREF Figure 46. Midscale Peak-to-Peak Glitch for ±10 V 800 4.0 V = 10V T = 25°C REFP A MIDSCALE CODE LOADED V = 0V REFN V = +15V DD OUTPUT UNBUFFERED UNITY GAIN MODE 3.5 V = –15V 600 SS AD8676 REFERENCE BUFFERS ADA4898-1 V = +10V REFP RC LOW-PASS FILTER V = –10V REFN 3.0 400 NEGATIVE POSITIVE 2.5 200 2.0 0 1.5 –200 1.0 –400 0.5 –600 0 0 1 23 4 567 8 9 10 TIME (Seconds) CODE Figure 44. 6 MSB Segment Glitch Energy for 10 V VREF Figure 47. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth Rev. B | Page 16 of 28 OUTPUT GLITCH (nV-sec) OUTPUT GLITCH (nV-sec) V (mV) OUT 16384 16384 49152 65536 81920 114688 114688 147456 163840 180224 212992 212992 245760 262144 278528 311296 311296 344064 360448 376832 409600 409600 442368 458752 475136 507904 507904 540672 557056 573440 606208 606208 638976 655360 671744 704512 704512 737280 753664 770048 802816 802816 835584 851968 868352 901120 901120 933888 950272 966656 999424 999424 1032192 10239-042 10239-044 10239-043 OUTPUT VOLTAGE (nV) OUTPUT GLITCH (mV) OUTPUT GLITCH (nV-sec) 16384 65536 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 10239-045 10239-047 10239-047 Data Sheet AD5790 200 100 V = +15V V = +15V DD DD V = –15V V = –15V SS 180 SS V = +10V V = +10V REFP REFP V = –10V V = –10V REFN REFN 160 UNITY GAIN ADA4898-1 140 120 100 10 80 60 40 20 0 1 –20 0.1 1 10 100 1k 10k 01 23456 FREQUENCY (Hz) TIME (µs) Figure 48. Noise Spectral Density vs. Frequency Figure 49. Glitch Impulse on Removal of Output Clamp Rev. B | Page 17 of 28 NSD (nV/√Hz) 10239-056 OUTPUT VOLTAGE (mV) 10239-048 AD5790 Data Sheet TERMINOLOGY Output Voltage Settling Time Relative Accuracy Output voltage settling time is the amount of time it takes for Relative accuracy, or integral nonlinearity (INL), is a measure of the output voltage to settle to a specified level for a specified the maximum deviation, in LSB, from a straight line passing change in voltage. For fast settling applications, a high speed through the endpoints of the DAC transfer function. A typical buffer amplifier is required to buffer the load from the 3.4 kΩ INL error vs. code plot is shown in Figure 6. output impedance of the AD5790, in which case, it is the Differential Nonlinearity (DNL) amplifier that determines the settling time. Differential nonlinearity is the difference between the measured Digital-to-Analog Glitch Impulse change and the ideal 1 LSB change between any two adjacent Digital-to-analog glitch impulse is the impulse injected into the codes. A specified differential nonlinearity of ±1 LSB maximum analog output when the input code in the DAC register changes ensures monotonicity. This DAC is guaranteed monotonic. A state. It is specified as the area of the glitch in nV-s and is typical DNL error vs. code plot is shown in Figure 10. measured when the digital input code is changed by 1 LSB at Long-Term Linearity Error Stability the major carry transition. See Figure 49. Linearity error long-term stability is a measure of the stability of Output Enabled Glitch Impulse the linearity of the DAC over a long period of time. It is speci- Output enabled glitch impulse is the impulse injected into the fied in LSB for a time period of 500 hours and 1000 hours at an analog output when the clamp to ground on the DAC output is elevated ambient temperature. removed. It is specified as the area of the glitch in nV-sec (see Zero-Scale Error Figure 49). Zero-scale error is a measure of the output error when zero-scale Digital Feedthrough code (0x00000) is loaded to the DAC register. Ideally, the output Digital feedthrough is a measure of the impulse injected into voltage should be VREFN. Zero-scale error is expressed in LSBs. the analog output of the DAC from the digital inputs of the Zero-Scale Error Temperature Coefficient DAC but is measured when the DAC output is not updated. It is Zero-scale error temperature coefficient is a measure of the specified in nV-sec and measured with a full-scale code change change in zero-scale error with a change in temperature. It is on the data bus, that is, from all 0s to all 1s, and vice versa. expressed in ppm FSR/°C. Total Harmonic Distortion (THD) Full-Scale Error Total harmonic distortion is the ratio of the rms sum of the Full-scale error is a measure of the output error when full-scale harmonics of the DAC output to the fundamental value. Only code (0x3FFFF) is loaded to the DAC register. Ideally, the the second to fifth harmonics are included. output voltage should be V − 1 LSB. Full-scale error is REFP DC Power Supply Rejection Ratio expressed in LSBs. DC power supply rejection ratio is a measure of the rejection of Full-Scale Error Temperature Coefficient the output voltage to dc changes in the power supplies applied Full-scale error temperature coefficient is a measure of the to the DAC. It is measured for a given dc change in power change in full-scale error with a change in temperature. It is supply voltage and is expressed in μV/V. expressed in ppm FSR/°C. AC Power Supply Rejection Ratio (AC PSRR) Gain Error AC power supply rejection ratio is a measure of the rejection of Gain error is a measure of the span error of the DAC. It is the the output voltage to ac changes in the power supplies applied deviation in slope of the DAC transfer characteristic from the to the DAC. It is measured for a given amplitude and frequency ideal, expressed in ppm of the full-scale range. change in power supply voltage and is expressed in decibels. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with a change in temperature. It is expressed in ppm FSR/°C. Midscale Error Midscale error is a measure of the output error when midscale code (0x20000) is loaded to the DAC register. Ideally, the output voltage should be (V − V )/2 + V . Midscale error is REFP REFN REFN expressed in LSBs. Rev. B | Page 18 of 28 Data Sheet AD5790 THEORY OF OPERATION RR R The AD5790 is a high accuracy, fast settling, single, 20-bit, V OUT .......... serial input, voltage-output DAC. It operates from a VDD supply ..................... 2R 2R 2R 2R 2R 2R ..................... ......... voltage of 7 V to 16.5 V and a VSS supply of −16.5 V to -2.5 V. S0 S1 S13 E62 E61 E0 Data is written to the AD5790 in a 24-bit word format via a 3-wire V REFP serial interface. The AD5790 incorporates a power-on reset V REFN circuit that ensures the DAC output powers up to 0 V with the V pin clamped to AGND through a ~6 kΩ internal resistor. OUT 14-BIT R-2R LADDER SIX MSBs DECODED INTO 63 EQUAL SEGMENTS DAC ARCHITECTURE Figure 50. DAC Ladder Structure The architecture of the AD5790 consists of two matched DAC SERIAL INTERFACE sections. A simplified circuit diagram is shown in Figure 50. The AD5790 has a 3-wire serial interface ( , SCLK, and SYNC The six MSBs of the 20-bit data-word are decoded to drive 63 switches, E0 to E62. Each of these switches connects one of SDIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards, as well as most DSPs (see Figure 2 for a 63 matched resistors to either the buffered VREFP or buffered timing diagram). VREFN voltage. The remaining 14 bits of the data-word drive Switches S0 to S13 of a 14-bit voltage mode R-2R ladder Input Shift Register network. The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK, which can operate at up to 35 MHz. The input register consists of a R/W bit, three address bits and 20 data bits as shown in Table 6. The timing diagram for this operation is shown in Figure 2. Table 6. Input Shift Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 to DB0 R/W Register address Register data Table 7. Decoding the Input Shift Register R/W Register Address Description 1 X 0 0 0 No operation (NOP). Used in readback operations. 0 0 0 1 Write to the DAC register. 0 0 1 0 Write to the control register. 0 0 1 1 Write to the clearcode register. 0 1 0 0 Write to the software control register. 1 0 0 1 Read from the DAC register. 1 0 1 0 Read from the control register. 1 0 1 1 Read from the clearcode register. 1 X is don’t care. Rev. B | Page 19 of 28 10239-050 AD5790 Data Sheet STANDALONE OPERATION AD5790* CONTROLLER The serial interface works with both a continuous and noncon- DATA OUT SDIN tinuous serial clock. A continuous SCLK source can be used SERIAL CLOCK SCLK SYNC only if is held low for the correct number of clock cycles. CONTROL OUT SYNC In gated clock mode, a burst clock containing the exact number DATA IN SYNC SDO of clock cycles must be used, and must be taken high after the final clock to latch the data. The first falling edge of SDIN SYNC starts the write cycle. Exactly 24 falling clock edges must AD5790* be applied to SCLK before SYNC is brought high again. If th SYNC is brought high before the 24 falling SCLK edge, the SCLK data written is invalid. If more than 24 falling SCLK edges are SYNC SYNC applied before is brought high, the input data is also invalid. SDO SYNC The input shift register is updated on the rising edge of . SYNC For another serial transfer to take place, must be brought SDIN low again. After the end of the serial data transfer, data is AD5790* automatically transferred from the input shift register to the addressed register. When the write cycle is complete, the output SCLK LDAC SYNC can be updated by taking low while is high. SYNC Daisy-Chain Operation SDO For systems that contain several devices, the SDO pin can be used to daisy chain several devices together. Daisy-chain mode *ADDITIONAL PINS OMITTED FOR CLARITY. can be useful in system diagnostics and in reducing the number Figure 51. Daisy-Chain Block Diagram of serial interface lines. The first falling edge of SYNC starts the Readback write cycle. SCLK is continuously applied to the input shift The contents of all the on-chip registers can be read back via SYNC register when is low. If more than 24 clock pulses are the SDO pin. Table 7 outlines how the registers are decoded. applied, the data ripples out of the shift register and appears on After a register has been addressed for a read, the next 24 clock the SDO line. This data is clocked out on the rising edge of cycles clock the data out on the SDO pin. The clocks must be SCLK and is valid on the falling edge. By connecting the SDO applied while SYNC is low. When SYNC is returned high, the of the first device to the SDIN input of the next device in the SDO pin is placed in tristate. For a read of a single register, the chain, a multidevice interface is constructed. Each device in the NOP function can be used to clock out the data. Alternatively, system requires 24 clock pulses. Therefore, the total number of if more than one register is to be read, the data of the first clock cycles must equal 24 × N, where N is the total number of register to be addressed can be clocked out at the same time AD5790 devices in the chain. When the serial transfer to all the second register to be read is being addressed. The SDO pin SYNC devices is complete, is taken high. This latches the input must be enabled to complete a readback operation. The SDO data in each device in the daisy chain and prevents any further pin is enabled by default. data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock. HARDWARE CONTROL PINS A continuous SCLK source can be used only if SYNC is held LDAC Load DAC Function ( ) low for the correct number of clock cycles. In gated clock mode, After data has been transferred into the input register of the a burst clock containing the exact number of clock cycles must DAC, there are two ways to update the DAC register and DAC SYNC be used, and must be taken high after the final clock to output. Depending on the status of both SYNC and LDAC, one latch the data. of two update modes is selected: synchronous DAC update or In any one daisy-chain sequence, do not mix writes to the DAC asynchronous DAC update. register with writes to any of the other registers. All writes to the Synchronous DAC Update daisy-chained parts must be either writes to the DAC registers LDAC In this mode, is held low while data is being clocked into or writes to the control, clearcode, or software control register. the input shift register. The DAC output is updated on the rising SYNC edge of . Rev. B | Page 20 of 28 10239-051 Data Sheet AD5790 CLR Asynchronous DAC Update output cannot be updated with a new value while the pin is low. A clear operation can also be performed by setting the CLR In this mode, LDAC is held high while data is being clocked bit in the software control register (see Table 13). into the input shift register. The DAC output is asynchronously LDAC SYNC updated by taking low after has been taken high. ON-CHIP REGISTERS LDAC The update now occurs on the falling edge of . DAC Register Reset Function (RESET) Table 9 outlines how data is written to and read from the DAC register. The AD5790 can be reset to its power-on state by two means: RESET pin or by using the software reset The following equation describes the ideal transfer function of either by asserting the the DAC: RESET control function (see Table 13). If the pin is not used, hardwire it to IOV . CC (V −V )×D REFP REFN V = +V OUT REFN 20 Asynchronous Clear Function (CLR) 2 The CLR pin is an active low clear that allows the output to where: be cleared to a user defined value. The 20-bit clear code value VREFN is the negative voltage applied at the VREFN input pin. is programmed to the clearcode register (see Table 12). It is V is the positive voltage applied at the V input pin. REFP REFP CLR D is the 20-bit code programmed to the DAC. necessary to maintain low for a minimum amount of time CLR to complete the operation (see Figure 2).When the signal LDAC is returned high the output remains at the clear value (if is high) until a new value is loaded to the DAC register. The Table 8. Hardware Control Pins Truth Table LDAC CLR RESET Function 1 1 X XX 0 The AD5790 is in reset mode. The device cannot be programmed. 1 1 X XX The AD5790 is returned to its power-on state. All registers are set to their default values. 0 0 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 0 1 1 The output is set according to the DAC register value. 1 0 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 1 1 The output is set according to the DAC register value. 0 1 The output remains at the clearcode register value. 1 1 The output remains set according to the DAC register value. 0 1 The output remains at the clearcode register value. 1 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 0 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 1 1 The output remains at the clearcode register value. 0 1 The output is set according to the DAC register value. 1 X is don’t care. Table 9. DAC Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB0 R/W Register address DAC register data R/W 0 0 1 20 bits of data Rev. B | Page 21 of 28 AD5790 Data Sheet Clearcode Register Control Register The clearcode register sets the value to which the DAC output is The control register controls the mode of operation of the set when the CLR pin or CLR bit in the software control register AD5790. is asserted. The output value depends on the DAC coding that is being used, either binary or twos complement. The default register value is 0. Table 10. Control Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W Register address Control register data R/ R/W 0 1 0 Reserved Reserved 0000 SDODIS BIN/2sC DACTRI OPGND RBUF Reserved Table 11. Control Register Functions Bit Name Description Reserved These bits are reserved and should be programmed to zero. RBUF Output amplifier configuration control. 0: the internal amplifier, A1, is powered up and Resistors R and R1 are connected in series, as shown in Figure 54. This FB allows an external amplifier to be connected in a gain of two configuration. See the AD5790 Features section for further details. 1: (default) the internal amplifier, A1, is powered down and Resistors RFB and R1 are connected in parallel, as shown in Figure 53, so that the resistance between the RFB and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the RFB and INV pins to be used for input bias current compensation for an external unity-gain amplifier. See the AD5790 Features section for further details. OPGND Output ground clamp control. 0: the DAC output clamp to ground is removed and the DAC is placed in normal mode. 1: (default) the DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode. Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated. Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit. DACTRI DAC tristate control. 0: the DAC is in normal operating mode. 1: (default) DAC is in tristate mode. BIN/2sC DAC register coding selection. 0: (default) the DAC register uses twos complement coding. 1: the DAC register uses offset binary coding. SDODIS SDO pin enable/disable control. 0: (default) the SDO pin is enabled. 1: the SDO pin is disabled (tristate). R/W Read/write select bit. 0: AD5790 is addressed for a write operation. 1: AD5790 is addressed for a read operation. Table 12. Clearcode Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB0 R/W Register address Clearcode register data R/W 0 1 1 20 bits of data Rev. B | Page 22 of 28 Data Sheet AD5790 Software Control Register This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low. Table 13. Software Control Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB3 DB2 DB1 DB0 R/W Register address Software control register data 1 2 0 1 0 0 Reserved Reset CLR LDAC 1 LDAC The CLR function has no effect when the pin is low. 2 The LDAC function has no effect when the CLR pin is low. Table 14. Software Control Register Functions Bit Name Description LDAC Setting this bit to 1 updates the DAC register and consequently the DAC output. CLR Setting this bit to 1 sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. Reset Setting this bit to 1 returns the AD5790 to its power-on state. Rev. B | Page 23 of 28 AD5790 Data Sheet AD5790 FEATURES A second unity-gain configuration for the output amplifier is POWER-ON TO 0 V one that removes an offset from the input bias currents of the The AD5790 contains a power-on reset circuit that, as well as amplifier. It does this by inserting a resistance in the feedback resetting all registers to their default values, controls the output path of the amplifier that is equal to the output resistance of the voltage during power-up. Upon power-on, the DAC is placed in DAC. The DAC output resistance is 3.4 kΩ. By connecting R1 tristate (its reference inputs are disconnected), and its output is and R in parallel, a resistance equal to the DAC resistance is FB clamped to AGND through a ~6 kΩ resistor. The DAC remains available on chip. Because the resistors are all on one piece of in this state until programmed otherwise via the control register. silicon, they are temperature coefficient matched. To enable this This is a useful feature in applications where it is important to mode of operation the RBUF bit of the control register must be know the state of the DAC output while it is in the process of set to Logic 1. Figure 53 shows how the output amplifier is powering up. connected to the AD5790. In this configuration, the output CONFIGURING THE AD5790 amplifier is in unity gain and the output spans from VREFN to V . This unity-gain configuration allows a capacitor to be placed REFP After power-on, the AD5790 must be configured to put it into in the amplifier feedback path to improve dynamic performance. normal operating mode before programming the output. To do V REFP this, the control register must be programmed. The DAC is removed from tristate by clearing the DACTRI bit, and the R FB output clamp is removed by clearing the OPGND bit. At this R1 R FB 10pF point, the output goes to VREFN, unless an alternative value is 6.8kΩ 6.8kΩ INV first programmed to the DAC register. V OUT V OUT 20-BIT DAC DAC OUTPUT STATE AD8675 ADA4898-1 The DAC output can be placed in one of three states, controlled ADA4004-1 by the DACTRI and OPGND bits of the control register, as AD5790 shown in Table 15. V = 0V REFN Figure 53. Output Amplifier in Unity Gain with Amplifier Input Bias Current Table 15. Output State Truth Table Compensation DACTRI OPGND Output State 0 0 Normal operating mode 0 1 Output is clamped via ~6 kΩ to AGND 1 0 Output is in tristate 1 1 Output is clamped via ~6 kΩ to AGND OUTPUT AMPLIFIER CONFIGURATION There are a number of different ways that an output amplifier can be connected to the AD5790, depending on the voltage references applied and the desired output voltage span. Unity-Gain Configuration Figure 52 shows an output amplifier configured for unity gain. In this configuration, the output spans from VREFN to VREFP. V REFP 6.8kΩ 6.8kΩ R FB A1 AD8675 R1 R FB ADA4898-1 INV ADA4004-1 V OUT 20-BIT DAC V OUT AD5790 V REFN Figure 52. Output Amplifier in Unity-Gain Configuration Rev. B | Page 24 of 28 10239-052 10239-053 Data Sheet AD5790 V REFP Gain of Two Configuration (×2 Gain Mode) Figure 54 shows an output amplifier configured for a gain of 6.8kΩ 6.8kΩ R FB A1 two. The gain is set by the internal matched 6.8 kΩ resistors, R1 R 10pF FB INV which are exactly twice the DAC resistance, having the effect of V removing an offset from the input bias current of the external V OUT OUT 20-BIT DAC amplifier. In this configuration, the output spans from 2 × AD8675 V − V to V . This configuration is used to generate a ADA4898-1 REFN REFP REFP ADA4004-1 bipolar output span from a single ended reference input with AD5790 V = 0 V. For this mode of operation, the RBUF bit of the REFN V REFN control register must be cleared to Logic 0. Figure 54. Output Amplifier in Gain of Two Configuration Rev. B | Page 25 of 28 10239-054 AD5790 Data Sheet APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Figure 55. Typical Operating Circuit Rev. B | Page 26 of 28 10239-055 Data Sheet AD5790 Figure 55 shows a typical operating circuit for the AD5790 The evaluation board interfaces to the USB port of a PC. Soft- using an AD8675 as an output buffer. Because the output ware is available with the evaluation board to allow the user to impedance of the AD5790 is 3.4 kΩ, an output buffer is easily program the AD5790. The software runs on any PC that required for driving low resistive, high capacitive loads. has Microsoft® Windows® XP (SP2), or Vista (32-bit or 64-bit), or Windows 7 installed. The AD5790 user guide, UG-342, is EVALUATION BOARD available, which gives full details on the operation of the An evaluation board is available for the AD5790 to aid evaluation board. designers in evaluating the high performance of the part with minimum effort. The AD5790 evaluation kit includes a populated and tested AD5790 printed circuit board (PCB). Rev. B | Page 27 of 28 AD5790 Data Sheet OUTLINE DIMENSIONS 2.75 2.65 4.00 BSC 2.50 PIN 1 PIN 1 INDICATOR INDICATOR 20 24 (Chamfer 0.225) 19 1 0.50 5.00 BSC 3.75 BSC EXPOSED PAD 3.65 3.50 13 7 12 8 0.50 TOP VIEW BOTTOM VIEW 0.40 1.00 0.30 0.90 0.05 MAX FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS 0.30 0.08 SECTION OF THIS DATA SHEET. SEATING 0.20 REF 0.25 PLANE 0.20 Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 5 mm Body, Very Thin Quad (CP-24-5) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range INL Package Description Package Option AD5790BCPZ −40°C to +125°C ±4 LSB 24-Lead LFCSP_VQ CP-24-5 AD5790BCPZ-RL7 −40°C to +125°C ±4 LSB 24-Lead LFCSP_VQ CP-24-5 EVAL-AD5790SDZ Evaluation Board 1 Z = RoHS Compliant Part. ©2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10239-0-2/12(B) Rev. B | Page 28 of 28 122409-B