ANALOG DEVICES AD5780

System Ready, 18-Bit ±1 LSB INL, Voltage Output DAC Data Sheet AD5780 FEATURES FUNCTIONAL BLOCK DIAGRAM V V V CC DD REFP True 18-bit voltage output DAC, ±1 LSB INL R 8 nV/√Hz output noise spectral density R1 FB 6.8kΩ 6.8kΩ AD5780 0.025 LSB long-term linearity error stability A1 R IOV CC FB ±0.018 ppm/°C gain error temperature coefficient INV SDIN INPUT 18 18 2.5 μs output voltage settling time SHIFT DAC 18-BIT SCLK V OUT REGISTER DAC REG 3.5 nV-sec midscale glitch impulse AND SYNC CONTROL Integrated precision reference buffers LOGIC SDO Operating temperature range: −40°C to +125°C 6kΩ LDAC 4 mm × 5 mm LFCSP package CLR POWER-ON RESET Wide power supply range of up to ±16.5 V AND CLEAR LOGIC RESET 35 MHz Schmitt triggered digital interface DGND V AGND V 1.8 V-compatible digital interface SS REFN Figure 1. APPLICATIONS Table 1. Related Devices Medical instrumentation Part No. Description Test and measurement AD5790 20-bit, 2 LSB accurate DAC Industrial control AD5791 20-bit, 1 ppm accurate DAC Scientific and aerospace instrumentation AD5781 18-bit, 0.5 LSB accurate DAC Data acquisition systems AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC Digital gain and offset adjustment Power supply control AD5760 16-bit, 0.5 LSB accurate DAC GENERAL DESCRIPTION 1 The AD5780 is a true 18-bit, unbuffered voltage output DAC PRODUCT HIGHLIGHTS that operates from a bipolar supply of up to 33 V. The AD5780 1. True 18-bit accuracy. accepts a positive reference input range of 5 V to VDD − 2.5 V 2. Wide power supply range of up to ±16.5 V. and a negative reference input range of VSS + 2.5 V to 0 V. Both 3. −40°C to +125°C operating temperature range. reference inputs are buffered on chip and external buffers are 4. Low 8 nV/√Hz noise. not required. The AD5780 offers a relative accuracy specifica- 5. Low ±0.018 ppm/°C gain error temperature coefficient. tion of ±1 LSB maximum range, and operation is guaranteed monotonic with a ±1 LSB DNL maximum range specification. COMPANION PRODUCTS Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1 The part uses a versatile 3-wire serial interface that operates at clock rates of up to 35 MHz and is compatible with standard External Reference: ADR445 SPI, QSPI™, MICROWIRE™, and DSP interface standards. The DC-to-DC Design Tool: ADIsimPower™ part incorporates a power-on reset circuit that ensures that the Additional companion products on the AD5780 product page DAC output powers up to 0 V in a known output impedance state and remains in this state until a valid write to the device takes place. The part provides an output clamp feature that places the output in a defined load state. 1 Protected by U.S. Patent No. 7,884,747 and 8,089,380. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09649-001 AD5780 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  DAC Architecture....................................................................... 19  Applications....................................................................................... 1  Serial Interface ............................................................................ 19  Functional Block Diagram .............................................................. 1  Hardware Control Pins.............................................................. 20  General Description ......................................................................... 1  On-Chip Registers...................................................................... 21  Product Highlights ........................................................................... 1  AD5780 Features ............................................................................ 24  Companion Products ....................................................................... 1  Power-On to 0 V......................................................................... 24  Revision History ............................................................................... 2  Configuring the AD5780 .......................................................... 24  Specifications..................................................................................... 3  DAC Output State ...................................................................... 24  Timing Characteristics ................................................................ 5  Output Amplifier Configuration.............................................. 24  Absolute Maximum Ratings............................................................ 8  Applications Information .............................................................. 26  ESD Caution.................................................................................. 8  Typical Operating Circuit ......................................................... 26  Pin Configuration and Function Descriptions............................. 9  Evaluation Board........................................................................ 27  Typical Performance Characteristics ........................................... 10  Outline Dimensions....................................................................... 28  Terminology .................................................................................... 18  Ordering Guide .......................................................................... 28  Theory of Operation ...................................................................... 19  REVISION HISTORY 3/12—Rev. B to Rev. C Changes to Data Sheet Title and added Patent 8,089,380 ........... 1 2/12—Rev. A to Rev. B Deleted Linearity Compensation Section ................................... 24 12/11—Rev. 0 to Rev. A Edits to Table 2.................................................................................. 3 Changes to Figure 48...................................................................... 17 Changes to DAC Register Section................................................ 21 Changes to Table 10 and Table 11 ................................................ 22 11/11—Revision 0: Initial Version Rev. C | Page 2 of 28 Data Sheet AD5780 SPECIFICATIONS VDD = 12.5 V to 16.5 V, VSS = −16.5 V to −12.5 V, VREFP = 10 V, VREFN = −10 V, VCC = 2.7 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted. Table 2. 1 A, B Versions Parameter Min Typ Max Unit Test Conditions/Comments 2 STATIC PERFORMANCE Resolution 18 Bits Integral Nonlinearity Error (Relative −0.85 +0.85 LSB B grade, VREFP = +10 V, VREFN = −10 V, Accuracy) T = 25°C A −1 +1 LSB B grade, VREFx = ±10 V, +10 V, and +5 V −2 +2 LSB A grade, V = ±10 V, +10 V, and +5 V REFx Differential Nonlinearity Error −0.25 +0.75 LSB B grade, V = ±10 V, +10 V, and +5 V REFx −1 +1 LSB A grade, VREFx = ±10 V, +10 V, and +5 V 3 Long-Term Linearity Error Stability 0.025 LSB After 750 hours at T = 135°C A Full-Scale Error −3 ±0.95 +3 LSB VREFP = +10 V, VREFN = −10 V −5.5 ±0.675 +0.5 LSB V = 10 V, V = 0 V REFP REFN −10 ±0.45 +10 LSB V = 5 V, V = 0 V REFP REFN Full-Scale Error Temperature Coefficient ±0.026 ppm/°C VREFP = +10 V, VREFN = −10 V Zero-Scale Error −4.8 ±0.325 +4.8 LSB V = +10 V, V = −10 V REFP REFN −10 ±0.175 +10 LSB VREFP = 10 V, VREFN = 0 V −20.5 ±0.225 +20.5 LSB VREFP = 5 V, VREFN = 0 V Zero-Scale Error Temperature ±0.025 ppm/°C V = +10 V, V = −10 V REFP REFN Coefficient Gain Error −19 ±2.3 +19 ppm FSR V = +10 V, V = −10 V REFP REFN −35 ±1.9 +35 ppm FSR VREFP = 10 V, VREFN = 0 V −68 ±0.9 +68 ppm FSR VREFP = 5 V, VREFN = 0 V Gain Error Temperature Coefficient ±0.018 ppm/°C V = +10 V, V = −10 V REFP REFN R1, RFB Matching 0.015 % OUTPUT CHARACTERISTICS Output Voltage Range V V V REFN REFP Output Voltage Settling Time 2.5 μs 10 V step to 0.02%, using the ADA4898-1 buffer in unity-gain mode 4 3.5 μs 500 code step to ±1 LSB Output Noise Spectral Density 8 nV/√Hz At 1 kHz, DAC code = midscale 8 nV/√Hz At 10 kHz, DAC code = midscale Output Voltage Noise 1.1 μV p-p DAC code = midscale, 0.1 Hz to 10 Hz bandwidth 4 Midscale Glitch Impulse 14 nV-sec VREFP = +10 V, VREFN = −10 V 3.5 nV-sec V = 10 V, V = 0 V REFP REFN 4 nV-sec V = 5 V, V = 0 V REFP REFN 4 MSB Segment Glitch Impulse 14 nV-sec VREFP = +10 V, VREFN = −10 V, see Figure 43 3.5 nV-sec V = 10 V, V = 0 V, see Figure 44 REFP REFN 4 nV-sec V = 5 V, V = 0 V, see Figure 45 REFP REFN Output Enabled Glitch Impulse 57 nV-sec On removal of output ground clamp Digital Feedthrough 0.27 nV-sec DC Output Impedance (Normal Mode) 3.4 kΩ DC Output Impedance (Output 6 kΩ Clamped to Ground) Rev. C | Page 3 of 28 AD5780 Data Sheet 1 A, B Versions Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUTS V Input Range 5 V − 2.5 V REFP DD V Input Range V + 2.5 0 V REFN SS Input Bias Current −20 −0.63 +20 nA T = 0°C to 105°C −4 −0.63 +4 A Input Capacitance 1 pF VREFP, VREFN LOGIC INPUTS 5 Input Current −1 +1 μA Input Low Voltage, VIL 0.3 × IOVCC V IOVCC = 1.71 V to 5.5 V Input High Voltage, VIH 0.7 × IOVCC V IOVCC = 1.71 V to 5.5 V Pin Capacitance 5 pF LOGIC OUTPUT (SDO) Output Low Voltage, V 0.4 V IOV = 1.71 V to 5.5 V, sinking 1 mA OL CC Output High Voltage, V IOV − 0.5 V IOV = 1.71 V to 5.5 V, sourcing 1 mA OH CC CC High Impedance Leakage Current ±1 μA High Impedance Output Capacitance 3 pF POWER REQUIREMENTS All digital inputs at DGND or IOV CC V 7.5 V + 33 V DD SS VSS VDD − 33 −2.5 V VCC 2.7 5.5 V IOVCC 1.71 5.5 V IOVCC ≤ VCC I 10.3 14 mA DD I −10 −14 mA SS ICC 600 900 μA IOICC 52 140 μA SDO disabled DC Power Supply Rejection Ratio ±7.5 μV/V ∆VDD ± 10%, VSS = −15 V ±1.5 μV/V ∆V ± 10%, V = 15 V SS DD AC Power Supply Rejection Ratio 90 dB ∆V ± 200 mV, 50 Hz/60 Hz, V = −15 V DD SS 90 dB ∆V ± 200 mV, 50 Hz/60 Hz, V = 15 V SS DD 1 Temperature range: −40°C to +125°C, typical conditions: T = 25°C, V = +15 V, V = −15 V, V = +10 V, V = −10 V. A DD SS REFP REFN 2 Performance characterized with the AD8675ARZ output buffer. 3 Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified. 4 The AD5780 is configured in the unity-gain mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead capacitance, and so forth). 5 Current flowing in an individual logic pin. Rev. C | Page 4 of 28 Data Sheet AD5780 TIMING CHARACTERISTICS VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. 1 Limit Parameter IOV = 1.71 V to 3.3 V IOV = 3.3 V to 5.5 V Unit Test Conditions/Comments CC CC 2 t1 40 28 ns min SCLK cycle time 92 60 ns min SCLK cycle time (readback and daisy-chain modes) t 15 10 ns min SCLK high time 2 t 9 5 ns min SCLK low time 3 t4 5 5 ns min SYNC to SCLK falling edge setup time t5 2 2 ns min SCLK falling edge to SYNC rising edge hold time t6 48 40 ns min Minimum SYNC high time t 8 6 ns min SYNC rising edge to next SCLK falling edge ignore 7 t 9 7 ns min Data setup time 8 t 12 7 ns min Data hold time 9 t10 13 10 ns min LDAC falling edge to SYNC falling edge t11 20 16 ns min SYNC rising edge to LDAC falling edge t12 14 11 ns min LDAC pulse width low t 130 130 ns typ LDAC falling edge to output response time 13 t 130 130 ns typ SYNC rising edge to output response time (LDAC tied low) 14 t 50 50 ns min 15 CLR pulse width low t16 140 140 ns typ CLR pulse activation time t17 0 0 ns min SYNC falling edge to first SCLK rising edge t 65 60 ns max SYNC rising edge to SDO tristate (C = 50 pF) 18 L t 62 45 ns max SCLK rising edge to SDO valid (C = 50 pF) 19 L t 0 0 ns min SYNC rising edge to SCLK rising edge ignore 20 t21 35 35 ns typ RESET pulse width low t22 150 150 ns typ RESET pulse activation time 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes. Rev. C | Page 5 of 28 AD5780 Data Sheet t t 1 7 SCLK 1 2 24 t t t 6 3 2 t t 4 5 SYNC t 9 t 8 SDIN DB23 DB0 t t 12 10 t 11 LDAC t V 13 OUT t V 14 OUT t 15 CLR t 16 V OUT t 21 RESET t 22 V OUT Figure 2. Write Mode Timing Diagram t 20 t t t 1 17 7 SCLK 12 2 4 1 2 24 t t t 3 2 6 t t 17 5 t t 4 5 SYNC t 9 t 8 SDIN DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION t 18 REGISTER TO BE READ t 19 SDO DB23 DB0 REGISTER CONTENTS CLOCKED OUT Figure 3. Readback Mode Timing Diagram Rev. C | Page 6 of 28 09649-002 09649-003 Data Sheet AD5780 t t 20 t 1 17 SCLK 12 24 25 26 48 t t t 3 2 6 t 5 t 4 SYNC t 9 t 8 SDIN DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N – 1 INPUT WORD FOR DAC N t 18 t 19 DB23 DB0 DB23 DB0 SDO UNDEFINED INPUT WORD FOR DAC N Figure 4. Daisy-Chain Mode Timing Diagram Rev. C | Page 7 of 28 09649-004 AD5780 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to Stresses above those listed under Absolute Maximum Ratings 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 4. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to AGND −0.3 V to +34 V DD maximum rating conditions for extended periods may affect VSS to AGND −34 V to +0.3 V device reliability. VDD to VSS −0.3 V to +34 V This device is a high performance integrated circuit with an VCC to DGND −0.3 V to +7 V ESD rating of 1.6 kV, and it is ESD sensitive. Proper precautions IOV to DGND −0.3 V to V + 3 V or +7 V CC CC (whichever is less) must be taken for handling and assembly. Digital Inputs to DGND + 0.3 V or −0.3 V to IOVCC +7 V (whichever is less) ESD CAUTION VOUT to AGND −0.3 V to VDD + 0.3 V VREFP to AGND −0.3 V to VDD + 0.3 V V to AGND V − 0.3 V to +0.3 V REFN SS DGND to AGND −0.3 V to +0.3 V Operating Temperature Range, TA Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature, 150°C T max J Power Dissipation (T max − T )/θ J A JA LFCSP Package θJA Thermal Impedance 31.0°C/W Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 1.6 kV Rev. C | Page 8 of 28 Data Sheet AD5780 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 19 AGND OUT V 2 18 V SS REFP 3 17 V V DD AD5780 SS V 4 TOP VIEW 16 RESET REFN (Not to Scale) V 5 15 DGND DD CLR 6 14 SYNC 7 13 SCLK LDAC NOTES TO THIS PIN. 1. DNC = DO NOT CONNECT. DO NOT CONNECT SUPPLY CONNECTION (V 2. NEGATIVE ANALOG ). SS A VOLTAGE IN THE RANGE OF –16.5 V TO –2.5 V CAN BE CONNECTED. V SHOULD BE DECOUPLED SS TO AGND. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY PINS. IT IS CONNECTION IS MADE AT THE VSS ENDED THAT THE PADDLE BE THERMALLY RECOMM CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT Analog Output Voltage. 2 V Positive Reference Voltage Input. A voltage in the range of 5 V to V − 2.5 V can be connected to this pin. REFP DD 3, 5 VDD Positive Analog Supply Connection. A voltage in the range of 7.5 V to 16.5 V can be connected to this pin. VDD must be decoupled to AGND. 4 RESET Active Low Reset. Asserting this pin returns the AD5780 to its power-on status. 6 CLR Active Low Input. Asserting this pin sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. 7 LDAC Active Low Load DAC Logic Input. This pin is used to update the DAC register and, consequently, the analog output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. Do not leave the LDAC pin unconnected. 8 VCC Digital Supply. Voltage range is from 2.7 V to 5.5 V. VCC should be decoupled to DGND. 9 IOVCC Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. Voltage range is from 1.71 V to 5.5 V. 10, 21, DNC Do Not Connect. Do not connect to these pins. 22, 23 11 SDO Serial Data Output. 12 SDIN Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 35 MHz. 14 SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The DAC SYNC is updated on the rising edge of . 15 DGND Ground Reference Pin for Digital Circuitry. 16 VREFN Negative Reference Voltage Input. 17, 18 V Negative Analog Supply Connection. A voltage in the range of −16.5 V to −2.5 V can be connected to this pin. SS VSS must be decoupled to AGND. 19 AGND Ground Reference Pin for Analog Circuitry. 20 R Feedback Connection for External Amplifier. See the AD5780 Features section for further details. FB 24 INV Inverting Input Connection for External Amplifier. See the AD5780 Features section for further details. EPAD V Negative Analog Supply Connection (V ). A voltage in the range of −16.5 V to −2.5 V can be connected to this pin. V SS SS SS must be decoupled to AGND. The paddle can be left electrically unconnected provided that a supply connection is made at the VSS pins. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. C | Page 9 of 28 09649-005 V 8 24 INV CC IOV 9 23 DNC CC DNC 10 22 DNC SDO 11 21 DNC SDIN 12 20 R FB AD5780 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.4 0.4 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER T = 25°C T = 25°C A 0.3 A 0.3 0.2 0.2 0.1 0 0.1 –0.1 0 –0.2 –0.1 –0.3 –0.4 –0.2 –0.5 V = +10V V = +5V REFP REFP V = –10V V = 0V –0.3 REFN REFN –0.6 V = +15V V = +15V DD DD V = –15V V = –15V SS SS –0.7 –0.4 0 50000 100000 150000 200000 250000 300000 0 50000 100000 150000 200000 250000 300000 DAC CODE DAC CODE Figure 6. Integral Nonlinearity Error vs. DAC Code, ±10 V Span Figure 9. Integral Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain Mode 0.6 0.5 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER T = 25°C T = 25°C A A 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 V = +10V V = +10V REFP REFP V = –10V V = 0V REFN REFN –0.3 –0.3 V = +15V V = +15V DD DD V = –15V V = –15V SS SS –0.4 –0.4 0 50000 100000 150000 200000 250000 300000 0 50000 100000 150000 200000 250000 300000 DAC CODE DAC CODE Figure 7. Integral Nonlinearity Error vs. DAC Code, 10 V Span Figure 10. Differential Nonlinearity Error vs. DAC Code, ±10 V Span 0.8 0.7 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER T = 25°C T = 25°C A A 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.2 –0.1 –0.4 –0.3 –0.6 V = +5V REFP V = +10V REFP –0.5 V = 0V REFN –0.8 V = 0V REFN V = +15V DD V = +15V DD V = –15V SS V = –15V SS –1.0 –0.7 0 50000 100000 150000 200000 250000 300000 0 50000 100000 150000 200000 250000 300000 DAC CODE DAC CODE Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span Figure 11. Differential Nonlinearity Error vs. DAC Code, 10 V Span Rev. C | Page 10 of 28 INL (LSB) INL (LSB) INL (LSB) 09649-008 09649-007 09649-006 DNL (LSB) INL (LSB) DNL (LSB) 09649-010 09649-009 09649-011 Data Sheet AD5780 0.5 0.40 ±10V SPAN MAX DNL ±10V SPAN MIN DNL +10V SPAN MAX DNL +10V SPAN MIN DNL 0.4 0.35 +5V SPAN MAX DNL +5V SPAN MIN DNL 0.3 0.30 0.2 0.25 0.1 0.20 V = +15V DD 0.15 0 V = –15V SS AD8675 OUTPUT BUFFER 0.10 –0.1 0.05 –0.2 V = +5V REFP V = 0V REFN 0 –0.3 AD8675 OUTPUT BUFFER V = +15V DD T = 25°C V = –15V A SS –0.05 –0.4 –40 –20 0 20 40 60 80 100 0 50000 100000 150000 200000 250000 300000 DAC CODE TEMPERATURE (°C) Figure 15. Differential Nonlinearity Error vs. Temperature Figure 12. Differential Nonlinearity Error vs. DAC Code, 5 V Span 0.6 0.4 V = +5V AD8675 OUTPUT BUFFER REFP V = 0V T = 25°C A REFN V = +15V 0.5 0.3 DD INL MAX V = –15V SS 0.4 0.2 0.3 0.1 T = 25°C A V = +10V REFP 0.2 0 V = –10V REFN AD8675 OUTPUTBUFFER 0.1 –0.1 0 –0.2 INL MIN –0.1 –0.3 –0.4 –0.2 0 50000 100000 150000 200000 250000 300000 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 DAC CODE V /|V | (V) DD SS Figure 13. Differential Nonlinearity Error vs. DAC Code, 5 V Span, Figure 16. Integral Nonlinearity Error vs. Supply Voltage, ±10 V Span ×2 Gain Mode ±10V SPAN MAX INL ±10V SPAN MIN INL 0.7 +10V SPAN MAX INL +10V SPAN MIN INL 0.4 INL MAX +5V SPAN MAX INL +5V SPAN MIN INL 0.5 0.2 0.3 T = 25°C A 0 V = 5V REFP V = 0V REFN 0.1 AD8675 OUTPUTBUFFER –0.2 –0.1 INL MIN –0.4 –0.3 V = +15V DD V = –15V SS AD8675 OUTPUT BUFFER –0.6 –0.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 –40 –20 0 20 40 60 80 100 V /|V | (V) DD SS TEMPERATURE (°C) Figure 14. Integral Nonlinearity Error vs. Temperature Figure 17. Integral Nonlinearity Error vs. Supply Voltage, 5 V Span Rev. C | Page 11 of 28 DNL (LSB) DNL (LSB) INL ERROR (LSB) 09649-014 09649-012 09649-013 DNL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 09649-016 09649-017 09649-015 AD5780 Data Sheet 0.35 4 T = 25°C A V = 5V DNL MAX REFP 0.30 V = 0V REFN 3 AD8675 OUTPUT BUFFER 0.25 2 0.20 T = 25°C A V = +10V REFP V = –10V REFN 0.15 1 AD8675 OUTPUT BUFFER 0.10 0 0.05 DNL MIN –1 0 –0.05 –2 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V /|V | (V) V /|V | (V) DD SS DD SS Figure 18. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span Figure 21. Zero-Scale Error vs. Supply Voltage, 5 V Span 0.35 0 T = 25°C A DNL MAX V = +10V REFP 0.30 V = –10V REFN –0.1 AD8675 OUTPUT BUFFER 0.25 –0.2 0.20 T = 25°C A V = 5V REFP V = 0V REFN –0.3 0.15 AD8675 OUTPUT BUFFER 0.10 –0.4 0.05 –0.5 DNL MIN 0 –0.6 –0.05 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V /|V | (V) V /|V | (V) DD SS DD SS Figure 19. Differential Nonlinearity Error vs. Supply Voltage, 5 V Span Figure 22. Midscale Error vs. Supply Voltage, ±10 V Span 0.5 2.0 T = 25°C A V = +10V 0.4 REFP 1.5 V = –10V REFN AD8675 OUTPUT BUFFER 0.3 1.0 0.2 0.5 0.1 0 0 –0.1 –0.5 –0.2 –1.0 –0.3 T = 25°C A –1.5 V = 5V REFP –0.4 V = 0V REFN AD8675 OUTPUT BUFFER –0.5 –2.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V /|V | (V) V /|V | (V) DD SS DD SS Figure 20. Zero-Scale Error vs. Supply Voltage, ±10 V Span Figure 23. Midscale Error vs. Supply Voltage, 5 V Span Rev. C | Page 12 of 28 ZERO-SCALE ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 09649-020 09649-019 09649-018 MIDSCALE ERROR (LSB) MIDSCALE ERROR (LSB) ZERO-SCALE ERROR (LSB) 09649-023 09649-022 09649-021 Data Sheet AD5780 0.50 1.50 T = 25°C A 0.45 V = +10V 1.45 REFP V = –10V REFN AD8675 OUTPUT BUFFER 1.40 0.40 0.35 1.35 1.30 0.30 0.25 1.25 0.20 1.20 1.15 0.15 0.10 1.10 T = 25°C A V = 5V REFP 1.05 0.05 V = 0V REFN AD8675 OUTPUT BUFFER 0 1.00 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V /|V | (V) V /|V | (V) DD SS DD SS Figure 24. Full-Scale Error vs. Supply Voltage, ±10 V Span Figure 27. Gain Error vs. Supply Voltage, 5 V Span 1.5 0.3 T = 25°C A INL MAX V = 5V REFP 1.0 V = 0V REFN 0.2 AD8675 OUTPUT BUFFER 0.5 0.1 0 0 –0.5 T = 25°C A V = +15V DD V = –15V SS –1.0 –0.1 AD8675 OUTPUT BUFFER –1.5 –0.2 –2.0 INL MIN –0.3 –2.5 –3.0 –0.4 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 5.05.56.06.57.07.58.08.5 9.09.5 10.0 V /|V | (V) V /|V | (V) DD SS REFP REFN Figure 25. Full-Scale Error vs. Supply Voltage, 5 V Span Figure 28. Integral Nonlinearity Error vs. Reference Voltage 0.35 0.30 T = 25°C A INL MAX V = +10V REFP V = –10V 0.25 REFN 0.25 AD8675 OUTPUT BUFFER 0.20 0.15 0.15 T = 25°C A V = +15V 0.05 DD V = –15V SS 0.10 AD8675 OUTPUT BUFFER –0.05 0.05 INL MIN –0.15 0 –0.25 –0.05 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 5.05.56.06.57.07.58.08.59.09.5 10.0 V /|V | (V) V /|V | (V) REFP REFN DD SS Figure 26. Gain Error vs. Supply Voltage, ±10 V Span Figure 29. Differential Nonlinearity Error vs. Reference Voltage Rev. C | Page 13 of 28 GAIN ERROR (LSB) FULL-SCALE ERROR (LSB) FULL-SCALE ERROR (LSB) 09649-025 09649-024 09649-026 DNL ERROR (LSB) INL ERROR (LSB) GAIN ERROR (LSB) 09649-027 09649-029 09649-028 AD5780 Data Sheet –1.0 0 T = 25°C T = 25°C A A V = +15V V = +15V DD –1.1 DD –0.05 V = –15V V = –15V SS SS AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER –1.2 –0.10 –1.3 –0.15 –1.4 –1.5 –0.20 –1.6 –0.25 –1.7 –0.30 –1.8 –0.35 –1.9 –2.0 –0.40 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 V /|V | (V) V /|V | (V) REFP REFN REFP REFN Figure 30. Zero-Scale Error vs. Reference Voltage Figure 33. Gain Error vs. Reference Voltage –0.2 1.8 ±10V SPAN T = 25°C A +10V SPAN V = +15V DD –0.3 +5V SPAN V = –15V SS 1.6 AD8675 OUTPUT BUFFER –0.4 1.4 –0.5 –0.6 1.2 –0.7 1.0 –0.8 0.8 –0.9 V = +15V DD V = –15V SS AD8675 OUTPUT BUFFER –1.0 0.6 5.05.56.06.57.07.58.08.59.09.5 10.0 –40 –20 0 20406080 100 V /|V | (V) TEMPERATURE (°C) REFP REFN Figure 34. Full-Scale Error vs. Temperature Figure 31. Midscale Error vs. Reference Voltage 0.6 1.7 T = 25°C ±10V SPAN A +10V SPAN V = +15V DD 0.4 +5V SPAN V = –15V SS AD8675 OUTPUT BUFFER 0.2 1.5 0 1.3 –0.2 –0.4 1.1 –0.6 –0.8 0.9 V = +15V DD –1.0 V = –15V SS AD8675 OUTPUT BUFFER 0.7 –1.2 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 –40 –20 0 2040 6080 100 V /|V | (V) REFP REFN TEMPERATURE (°C) Figure 35. Midscale Error vs. Temperature Figure 32. Full-Scale Error vs. Reference Voltage Rev. C | Page 14 of 28 MIDSCALE ERROR (LSB) ZERO-SCALE ERROR (LSB) FULL-SCALE ERROR (LSB) 09649-032 09649-031 09649-030 GAIN ERROR (LSB) MIDSCALE ERROR (LSB) FULL-SCALE ERROR (LSB) 09649-035 09649-034 09649-033 Data Sheet AD5780 1.0 0.010 ±10V SPAN +10V SPAN 0.008 +5V SPAN 0.5 I DD 0.006 0 0.004 –0.5 0.002 –1.0 0 –0.002 –1.5 –0.004 –2.0 –0.006 I SS –2.5 V = +15V DD –0.008 V = –15V SS AD8675 OUTPUT BUFFER –3.0 –0.010 –40 –20 0 20 40 60 80 100 –20 –15 –10 –5 0 5 10 15 20 V /V (V) TEMPERATURE (°C) DD SS Figure 36. Zero-Scale Error vs. Temperature Figure 39. Power Supply Currents vs. Power Supply Voltages 0 6 ±10V SPAN +10V SPAN –0.5 +5V SPAN 4 2 –1.0 0 –1.5 V = +15V DD –2 V = –15V –2.0 SS V = +10V REFP V = –10V REFN –4 –2.5 ADA4808-1 BUFFERED LOAD = 10MΩ || 20pF –6 –3.0 –8 –3.5 V = +15V DD V = –15V SS AD8675 OUTPUT BUFFER –10 –4.0 –1 0 1 2 345 –40 –200 20406080 100 TIME (µs) TEMPERATURE (°C) Figure 37. Gain Error vs. Temperature Figure 40. Rising Full-Scale Voltage Step 6 900 IOV = 5V, LOGIC VOLTAGE V = +15V CC T = 25°C DD A INCREASING V = –15V SS 800 4 V = +10V IOV = 5V, LOGIC VOLTAGE CC REFP V = –10V DECREASING REFN ADA4808-1 BUFFERED 700 IOV = 3V, LOGIC VOLTAGE CC 2 LOAD = 10MΩ || 20pF INCREASING IOV = 3V, LOGIC VOLTAGE 600 CC 0 DECREASING 500 –2 400 –4 300 –6 200 –8 100 –10 0 –1 0 1 2 345 01 23 4 5 6 LOGIC INPUT VOLTAGE (V) TIME (µs) Figure 41. Falling Full-Scale Voltage Step Figure 38. IOICC vs. Logic Input Voltage Rev. C | Page 15 of 28 ZERO-SCALE ERROR (LSB) GAIN ERROR (LSB) IOI (µA) CC 09649-038 09649-037 09649-036 I /I (mA) DD SS V (V) V (V) OUT OUT 09649-041 09649-040 09649-039 AD5780 Data Sheet 6 10 V = 5V REFP NEGATIVE V = 0V REFN POSITIVE 9 UNITY-GAIN MODE ADA4898-1 OUTPUT BUFFER 5 RC LOW-PASS FILTER 8 7 4 6 3 5 4 2 3 V = +10V REFP 2 V = –10V 1 REFN RC LOW-PASS FILTER 1 UNITY-GAIN MODE ADA4898-1 OUTPUT BUFFER 0 0 –1 012 34 5 TIME (µs) CODE Figure 42. 500 Code Step Settling Time Figure 45. 6 MSB Segment Glitch Energy for 5 V VREF 25 55 NEGATIVE V = +10V ±10V SPAN REFP POSITIVE V = –10V +10V SPAN REFN 45 +5V SPAN UNITY-GAIN MODE ADA4898-1 OUTPUT BUFFER 20 RC LOW-PASS FILTER POSITIVE NEGATIVE 35 CODE CHANGE CODE CHANGE 25 15 15 10 5 –5 5 –15 0 –25 –1 0 1 23 TIME (µs) CODE Figure 43. 6 MSB Segment Glitch Energy for ±10 V VREF Figure 46. Midscale Peak-to-Peak Glitch for ±10 V 4.0 800 V = 10V NEGATIVE T = 25°C MIDSCALE CODE LOADED REFP A V = 0V POSITIVE REFN V = +15V OUTPUT UNBUFFERED DD UNITY-GAIN MODE 3.5 V = –15V 600 SS ADA4898-1 V = +10V OUTPUT BUFFER REFP RC LOW-PASS FILTER V = –10V REFN 3.0 400 2.5 200 2.0 0 1.5 –200 1.0 –400 0.5 0 –600 0 1 23 4 5 67 8 9 10 TIME (Seconds) CODE Figure 44. 6 MSB Segment Glitch Energy for 10 V V REF Figure 47. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth Rev. C | Page 16 of 28 OUTPUT GLITCH (nV-s) V (mV) OUTPUT GLITCH (nV-s) OUT 16384 16384 65536 49152 81920 114688 114688 163840 147456 180224 212992 212992 262144 245760 278528 311296 311296 360448 344064 376832 409600 409600 442368 458752 475136 507904 507904 540672 557056 573440 606208 606208 638976 655360 671744 704512 704512 737280 753664 770048 802816 802816 835584 851968 868352 901120 901120 933888 950272 966656 999424 999424 1032192 09649-044 09649-043 09649-042 OUTPUT GLITCH (mV) OUTPUT VOLTAGE (nV) OUTPUT GLITCH (nV-s) 16384 65536 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 09649-047 09649-045 09649-046 Data Sheet AD5780 100 200 V = +15V V = +15V DD DD V = –15V = –15V SS V 180 SS V = +10V REFP V = +10V REFP V = –10V REFN V = –10V REFN 160 UNITY GAIN ADA4898-1 140 120 100 10 80 60 40 20 0 1 –20 0.1 1 10 100 1k 10k 0123 456 TIME (µs) FREQUENCY (Hz) Figure 49. Glitch Impulse on Removal of Output Clamp Figure 48. Noise Spectral Density vs. Frequency Rev. C | Page 17 of 28 NSD (nV/√Hz) 09649-055 OUTPUT VOLTAGE (mV) 09649-048 AD5780 Data Sheet TERMINOLOGY Relative Accuracy Output Voltage Settling Time Relative accuracy, or integral nonlinearity (INL), is a measure of Output voltage settling time is the amount of time it takes for the maximum deviation, in LSB, from a straight line passing the output voltage to settle to a specified level for a specified through the endpoints of the DAC transfer function. A typical change in voltage. For fast settling applications, a high speed INL error vs. code plot is shown in Figure 6. buffer amplifier is required to buffer the load from the 3.4 kΩ output impedance of the AD5780, in which case, it is the Differential Nonlinearity (DNL) amplifier that determines the settling time. Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent Digital-to-Analog Glitch Impulse codes. A specified differential nonlinearity of ±1 LSB maximum Digital-to-analog glitch impulse is the impulse injected into the ensures monotonicity. This DAC is guaranteed monotonic. A analog output when the input code in the DAC register changes typical DNL error vs. code plot is shown in Figure 10. state. It is specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at Linearity Error Long-Term Stability the major carry transition (see Figure 49). Linearity error long-term stability is a measure of the stability of the linearity of the DAC over a long period of time. It is speci- Output Enabled Glitch Impulse fied in LSB for a time period of 500 hours and 1000 hours at an Output enabled glitch impulse is the impulse injected into the elevated ambient temperature. analog output when the clamp to ground on the DAC output is removed. It is specified as the area of the glitch in nV-sec (see Zero-Scale Error Figure 49). Zero-scale error is a measure of the output error when zero-scale code (0x00000) is loaded to the DAC register. Ideally, the output Digital Feedthrough voltage should be VREFN. Zero-scale error is expressed in LSBs. Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the Zero-Scale Error Temperature Coefficient DAC but is measured when the DAC output is not updated. It is Zero-scale error temperature coefficient is a measure of the specified in nV-sec and measured with a full-scale code change change in zero-scale error with a change in temperature. It is on the data bus, that is, from all 0s to all 1s, and vice versa. expressed in ppm FSR/°C. Total Harmonic Distortion (THD) Full-Scale Error Total harmonic distortion is the ratio of the rms sum of the Full-scale error is a measure of the output error when full-scale harmonics of the DAC output to the fundamental value. Only code (0x3FFFF) is loaded to the DAC register. Ideally, the the second to fifth harmonics are included. output voltage should be V − 1 LSB. Full-scale error is REFP expressed in LSBs. DC Power Supply Rejection Ratio DC power supply rejection ratio is a measure of the rejection of Full-Scale Error Temperature Coefficient the output voltage to dc changes in the power supplies applied Full-scale error temperature coefficient is a measure of the to the DAC. It is measured for a given dc change in power change in full-scale error with a change in temperature. It is supply voltage and is expressed in μV/V. expressed in ppm FSR/°C. AC Power Supply Rejection Ratio (AC PSRR) Gain Error AC power supply rejection ratio is a measure of the rejection of Gain error is a measure of the span error of the DAC. It is the the output voltage to ac changes in the power supplies applied deviation in slope of the DAC transfer characteristic from the to the DAC. It is measured for a given amplitude and frequency ideal, expressed in ppm of the full-scale range. change in power supply voltage and is expressed in decibels. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with a change in temperature. It is expressed in ppm FSR/°C. Midscale Error Midscale error is a measure of the output error when midscale code (0x20000) is loaded to the DAC register. Ideally, the output voltage should be (V – V )/2 + V . Midscale error is REFP REFN REFN expressed in LSBs. Rev. C | Page 18 of 28 Data Sheet AD5780 THEORY OF OPERATION RR R The AD5780 is a high accuracy, fast settling, single, 18-bit, V OUT ... ... serial input, voltage output DAC. It operates from a VDD supply 2R 2R 2R 2R 2R 2R 2R ... ... voltage of 7.5 V to 16.5 V and a VSS supply of −16.5 V to −2.5 V. S0 S1 S11 E62 E61 E0 V REFP Data is written to the AD5780 in a 24-bit word format via a 3-wire serial interface. The AD5780 incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V with the V REFN V pin clamped to AGND through a ~6 kΩ internal resistor. OUT 12-BIT R-2R LADDER SIX MSBs DECODED INTO 63 EQUAL SEGMENTS DAC ARCHITECTURE Figure 50. DAC Ladder Structure Serial Interface The architecture of the AD5780 consists of two matched DAC SERIAL INTERFACE sections. A simplified circuit diagram is shown in Figure 50. The AD5780 has a 3-wire serial interface ( , SCLK, and SYNC The six MSBs of the 18-bit data-word are decoded to drive SDIN) that is compatible with SPI, QSPI, and MICROWIRE 63 switches, E0 to E62. Each of these switches connects one interface standards, as well as most DSPs (see Figure 2 for a of 63 matched resistors to either the buffered VREFP or buffered timing diagram). VREFN voltage. The remaining 12 bits of the data-word drive the S0 to S11 switches of a 12-bit voltage mode R-2R ladder Input Shift Register network. The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK, which can operate at up to 35 MHz. The W input register consists of a R/ bit, three address bits, and 20 data bits as shown in Table 6. The timing diagram for this operation is shown in Figure 2. Table 6. Input Shift Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 to DB0 R/W Register address Register data Table 7. Decoding the Input Shift Register R/W Register Address Description 1 X 0 0 0 No operation (NOP). Used in readback operations. 0 0 0 1 Write to the DAC register. 0 0 1 0 Write to the control register. 0 0 1 1 Write to the clearcode register. 0 1 0 0 Write to the software control register. 1 0 0 1 Read from the DAC register. 1 0 1 0 Read from the control register. 1 0 1 1 Read from the clearcode register. 1 X is don’t care. Rev. C | Page 19 of 28 09649-049 AD5780 Data Sheet Standalone Operation AD5780* CONTROLLER The serial interface works with both a continuous and noncon- DATA OUT SDIN tinuous serial clock. A continuous SCLK source can be used SERIAL CLOCK SCLK SYNC only if is held low for the correct number of clock cycles. CONTROL OUT SYNC In gated clock mode, a burst clock containing the exact number DATA IN SYNC SDO of clock cycles must be used, and must be taken high after the final clock to latch the data. The first falling edge of SYNC SDIN starts the write cycle. Exactly 24 falling clock edges must be AD5780* applied to SCLK before SYNC is brought high again. If SYNC is th brought high before the 24 falling SCLK edge, the data written SCLK is invalid. If more than 24 falling SCLK edges are applied before SYNC SYNC is brought high, the input data is also invalid. SYNC The input shift register is updated on the rising edge of . SDO SYNC For another serial transfer to take place, must be brought low again. After the end of the serial data transfer, data is SDIN automatically transferred from the input shift register to the AD5780* addressed register. When the write cycle is complete, the output LDAC SYNC can be updated by taking low while is high. SCLK SYNC Daisy-Chain Operation For systems that contain several devices, the SDO pin can be SDO used to daisy-chain several devices together. Daisy-chain mode can be useful in system diagnostics and in reducing the number *ADDITIONAL PINS OMITTED FOR CLARITY. of serial interface lines. The first falling edge of SYNC starts the Figure 51. Daisy-Chain Block Diagram write cycle. SCLK is continuously applied to the input shift register Readback SYNC when is low. If more than 24 clock pulses are applied, the The contents of all the on-chip registers can be read back via data ripples out of the shift register and appears on the SDO the SDO pin. Table 7 outlines how the registers are decoded. line. This data is clocked out on the rising edge of SCLK and After a register has been addressed for a read, the next 24 clock is valid on the falling edge. By connecting the SDO of the first cycles clock the data out on the SDO pin. The clocks must be device to the SDIN input of the next device in the chain, a applied while SYNC is low. When SYNC is returned high, the multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock SDO pin is placed in tristate. For a read of a single register, the cycles must equal 24 × N, where N is the total number of NOP function can be used to clock out the data. Alternatively, AD5780 devices in the chain. When the serial transfer to all if more than one register is to be read, the data of the first SYNC register to be addressed can be clocked out at the same time devices is complete, is taken high. This latches the input that the second register to be read is being addressed. The SDO data in each device in the daisy chain and prevents any further pin must be enabled to complete a readback operation. The data from being clocked into the input shift register. The serial SDO pin is enabled by default. clock can be a continuous or a gated clock. A continuous SCLK source can be used only if SYNC is held HARDWARE CONTROL PINS low for the correct number of clock cycles. In gated clock mode, LDAC Load DAC Function ( ) a burst clock containing the exact number of clock cycles must After data has been transferred into the input register of the SYNC be used, and must be taken high after the final clock to DAC, there are two ways to update the DAC register and DAC latch the data. output. Depending on the status of both SYNC and LDAC, one In any one daisy-chain sequence, do not mix writes to the DAC of two update modes is selected: synchronous DAC update or register with writes to any of the other registers. All writes to the asynchronous DAC update. daisy-chained parts must be either writes to the DAC registers Synchronous DAC Update or writes to the control, clearcode, or software control register. LDAC In this mode, is held low while data is being clocked into the input shift register. The DAC output is updated on the rising SYNC edge of . Rev. C | Page 20 of 28 09649-050 Data Sheet AD5780 is high) until a new value is loaded to the DAC register. The Asynchronous DAC Update CLR output cannot be updated with a new value while the pin is In this mode, LDAC is held high while data is being clocked low. A clear operation can also be performed by setting the CLR into the input shift register. The DAC output is asynchronously bit in the software control register (see Table 13). LDAC SYNC updated by taking low after has been taken high. LDAC ON-CHIP REGISTERS The update now occurs on the falling edge of . DAC Register Reset Function (RESET) Table 9 outlines how data is written to and read from the DAC The AD5780 can be reset to its power-on state by two means: register. RESET pin or by using the reset function either by asserting the The following equation describes the ideal transfer function of RESET in the software control register (see Table 13). If the pin the DAC: is not used, hardwire it to IOV . CC (V −V )×D Asynchronous Clear Function (CLR) REFP REFN V = +V OUT REFN 18 2 The CLR pin is an active low clear that allows the output to be where: cleared to a user defined value. The 18-bit clearcode value is V is the negative voltage applied at the V input pin. REFN REFN programmed to the clearcode register (see Table 12). It is V is the positive voltage applied at the V input pin. REFP REFP CLR necessary to maintain low for a minimum amount of time D is the 18-bit code programmed to the DAC. CLR to complete the operation (see Figure 2). When the signal LDAC is returned high, the output remains at the clear value (if Table 8. Hardware Control Pins Truth Table LDAC CLR RESET Function 1 1 X XX 0 The AD5780 is in reset mode. The device cannot be programmed. 1 1 X XX The AD5780 is returned to its power-on state. All registers are set to their default values. 0 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly. 0 1 1 The output is set according to the DAC register value. 1 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly. 1 1 The output is set according to the DAC register value. 0 1 The output remains at the clearcode register value. 1 1 The output remains set according to the DAC register value. 0 1 The output remains at the clearcode register value. 1 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 0 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 1 1 The output remains at the clearcode register value. 0 1 The output is set according to the DAC register value. 1 X is don’t care. Table 9. DAC Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 R/W Register address DAC register data 1 1 0 0 1 18 bits of data X XX R/W 1 X is don’t care. Rev. C | Page 21 of 28 AD5780 Data Sheet Control Register is asserted. The output value depends on the DAC coding that is being used, either binary or twos complement. The default The control register controls the mode of operation of the register value is 0. AD5780. Clearcode Register The clearcode register sets the value to which the DAC output is set when the pin or CLR bit in the software control register CLR Table 10. Control Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R/W Register address Control register data W 0 1 0 Reserved Reserved 0000 SDODIS BIN/2sC DACTRI OPGND RBUF Reserved R/ Table 11. Control Register Functions Bit Name Description Reserved These bits are reserved and should be programmed to zero. RBUF Output amplifier configuration control. 0: the internal amplifier, A1, is powered up and Resistors RFB and R1 are connected in series as shown in Figure 54. This allows an external amplifier to be connected in a gain of two configuration. See the AD5780 Features section for further details. 1: (default) the internal amplifier, A1, is powered down and Resistors R and R1 are connected in parallel, as shown in Figure 53, FB so that the resistance between the RFB and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the RFB and INV pins to be used for input bias current compensation for an external unity-gain amplifier. See the AD5780 Features section for further details. OPGND Output ground clamp control. 0: the DAC output clamp to ground is removed, and the DAC is placed in normal mode. 1: (default) the DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode. Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated. Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit DACTRI DAC tristate control. 0: the DAC is in normal operating mode. 1: (default) the DAC is in tristate mode. BIN/2sC DAC register coding selection. 0: (default) the DAC register uses twos complement coding. 1: the DAC register uses offset binary coding. SDODIS SDO pin enable/disable control. 0: (default) the SDO pin is enabled. 1: the SDO pin is disabled (tristate). R/W Read/write select bit. 0: AD5780 is addressed for a write operation. 1: AD5780 is addressed for a read operation. Table 12. Clearcode Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 R/W Register address Clearcode register data 1 1 R/W 0 1 1 18 bits of data X XX 1 X is don’t care. Rev. C | Page 22 of 28 Data Sheet AD5780 Software Control Register This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low. Table 13. Software Control Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB3 DB2 DB1 DB0 R/W Register address Software control register data 1 2 0 1 0 0 Reserved Reset CLR LDAC 1 LDAC The CLR function has no effect when the pin is low. 2 The LDAC function has no effect when the CLR pin is low. Table 14. Software Control Register Functions Bit Name Description LDAC Setting this bit to 1 updates the DAC register and consequently the DAC output. CLR Setting this bit to 1 sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. Reset Setting this bit to 1 returns the AD5780 to its power-on state. Rev. C | Page 23 of 28 AD5780 Data Sheet AD5780 FEATURES Unity-Gain Configuration POWER-ON TO 0 V Figure 52 shows an output amplifier configured for unity gain. The AD5780 contains a power-on reset circuit that, as well as In this configuration, the output spans from VREFN to VREFP. resetting all registers to their default values, controls the output voltage during power-up. Upon power-on, the DAC is placed in V REFP tristate (its reference inputs are disconnected), and its output is clamped to AGND through a ~6 kΩ resistor. The DAC remains R R1 FB R FB A1 in this state until programmed otherwise via the control register. AD8675, 6.8kΩ 6.8kΩ ADA4898-1, This is a useful feature in applications where it is important to INV ADA4004-1 know the state of the DAC output while it is in the process of 18-BIT DAC V V OUT powering up. OUT CONFIGURING THE AD5780 AD5780 After power-on, the AD5780 must be configured to put it into V REFN normal operating mode before programming the output. To Figure 52. Output Amplifier in Unity-Gain Configuration do this, the control register must be programmed. The DAC is removed from tristate by clearing the DACTRI bit, and the A second unity-gain configuration for the output amplifier is output clamp is removed by clearing the OPGND bit. At this one that removes an offset from the input bias currents of the point, the output goes to VREFN unless an alternative value is first amplifier. It does this by inserting a resistance in the feedback programmed to the DAC register. path of the amplifier that is equal to the output resistance of the DAC. The DAC output resistance is 3.4 kΩ. By connecting R1 DAC OUTPUT STATE and RFB in parallel, a resistance equal to the DAC resistance is The DAC output can be placed in one of three states, controlled available on chip. Because the resistors are all on one piece of by the DACTRI and OPGND bits of the control register, as silicon, they are temperature coefficient matched. To enable this shown in Table 15. mode of operation, the RBUF bit of the control register must be set to Logic 1. Figure 53 shows how the output amplifier is Table 15. Output State Truth Table connected to the AD5780. In this configuration, the output DACTRI OPGND Output State amplifier is in unity gain and the output spans from VREFN to 0 0 Normal operating mode. VREFP. This unity-gain configuration allows a capacitor to be 0 1 Output is clamped via ~6 kΩ to AGND. placed in the amplifier feedback path to improve dynamic 1 0 Output is in tristate. performance. 1 1 Output is clamped via ~6 kΩ to AGND. V REFP OUTPUT AMPLIFIER CONFIGURATION R FB There are a number of different ways that an output amplifier R1 R FB 10pF 6.8kΩ can be connected to the AD5780, depending on the voltage 6.8kΩ INV V OUT references applied and the desired output voltage span. 18-BIT DAC V OUT AD8675, ADA4898-1, ADA4004-1 AD5780 V = 0V REFN Figure 53. Output Amplifier in Unity Gain with Amplifier Input Bias Current Compensation Rev. C | Page 24 of 28 09649-049 09649-051 Data Sheet AD5780 V REFP Gain of Two Configuration (×2 Gain Mode) Figure 54 shows an output amplifier configured for a gain of R R1 FB R FB two. The gain is set by the internal matched 6.8 kΩ resistors, A1 10pF 6.8kΩ 6.8kΩ which are exactly twice the DAC resistance, having the effect V of removing an offset from the input bias current of the external INV OUT 18-BIT amplifier. In this configuration, the output spans from 2 × V − REFN DAC V OUT AD8675, V to V . This configuration is used to generate a bipolar REFP REFP ADA4898-1, ADA4004-1 output span from a single-ended reference input, with V = REFN AD5780 0 V. For this mode of operation, the RBUF bit of the control V REFN register must be cleared to Logic 0. Figure 54. Output Amplifier in Gain-of-Two Configuration Rev. C | Page 25 of 28 09649-050 AD5780 Data Sheet APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Figure 55. Typical Operating Circuit Rev. C | Page 26 of 28 09649-054 Data Sheet AD5780 Figure 55 shows a typical operating circuit for the AD5780 populated and tested AD5780 printed circuit board (PCB). The using an AD8675 as an output buffer. Because the output evaluation board interfaces to the USB port of a PC. Software is impedance of the AD5780 is 3.4 kΩ, an output buffer is available with the evaluation board to allow the user to easily required for driving low resistive, high capacitive loads. program the AD5780. The software runs on any PC that has Microsoft® Windows® XP (SP2), Vista (32-bit or 64-bit), or EVALUATION BOARD Windows 7 installed. The AD5780 user guide, UG-256, is An evaluation board is available for the AD5780 to aid available, which gives full details on the operation of the designers in evaluating the high performance of the part evaluation board. with minimum effort. The AD5780 evaluation kit includes a Rev. C | Page 27 of 28 AD5780 Data Sheet OUTLINE DIMENSIONS 2.75 2.65 4.00 BSC 2.50 PIN 1 PIN 1 INDICATOR INDICATOR 20 24 (Chamfer 0.225) 19 1 0.50 5.00 BSC 3.75 BSC EXPOSED PAD 3.65 3.50 7 13 12 8 0.50 TOP VIEW BOTTOM VIEW 0.40 1.00 0.30 0.90 0.05 MAX FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS 0.30 0.08 SECTION OF THIS DATA SHEET. SEATING 0.20 REF 0.25 PLANE 0.20 Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 5 mm Body, Very Thin Quad (CP-24-5) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range INL Package Description Package Option AD5780ACPZ −40°C to +125°C ±2 LSB 24-Lead LFCSP_VQ CP-24-5 AD5780ACPZ-REEL7 −40°C to +125°C ±2 LSB 24-Lead LFCSP_VQ CP-24-5 AD5780BCPZ −40°C to +125°C ±1 LSB 24-Lead LFCSP_VQ CP-24-5 AD5780BCPZ-REEL7 −40°C to +125°C ±1 LSB 24-Lead LFCSP_VQ CP-24-5 EVAL-AD5780SDZ Evaluation Board 1 Z = RoHS Compliant Part. ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09649-0-3/12(C) Rev. C | Page 28 of 28 122409-B