ANALOG DEVICES AD5760

Ultra Stable, 16-Bit ±0.5 LSB INL, Voltage Output DAC Data Sheet AD5760 FEATURES FUNCTIONAL BLOCK DIAGRAM V V V CC DD REFP True 16-bit voltage output DAC, ±0.5 LSB INL 8 nV/√Hz output noise spectral density 6.8kΩ 6.8kΩ 0.00625 LSB long-term linearity error stability A1 IOV R FB CC R1 R FB ±0.018 ppm/°C gain error temperature coefficient INV SDIN INPUT 2.5 μs output voltage settling time 16 16 SHIFT 16-BIT DAC SCLK V OUT REGISTER DAC REG 3.5 nV-sec midscale glitch impulse AND SYNC CONTROL Integrated precision reference buffers LOGIC SDO Operating temperature range: −40°C to +125°C 6kΩ LDAC 4 mm × 5 mm LFCSP package CLR POWER-ON RESET Wide power supply range of up to ±16.5 V AND CLEAR LOGIC RESET AD5760 35 MHz Schmitt triggered digital interface 1.8 V-compatible digital interface DGND V AGND V SS REFN Figure 1. APPLICATIONS Medical instrumentation Test and measurement Table 1. Related Devices Industrial control Part No. Description Scientific and aerospace instrumentation AD5790 20-bit, 2 LSB accurate DAC Data acquisition systems AD5791 20-bit, 1 LSB accurate DAC Digital gain and offset adjustment AD5780 18-bit, 1 LSB accurate DAC Power supply control AD5781 18-bit, 0.5 LSB INL AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC GENERAL DESCRIPTION 1 The AD5760 is a true 16-bit, unbuffered voltage output DAC PRODUCT HIGHLIGHTS that operates from a bipolar supply of up to 33 V. The AD5760 1. True 16-bit accuracy. accepts a positive reference input range of 5 V to V − 2.5 V DD 2. Wide power supply range of up to ±16.5 V. and a negative reference input range of V + 2.5 V to 0 V. The SS 3. −40°C to +125°C operating temperature range. AD5760 offers a relative accuracy specification of ±0.5 LSB 4. Low 8 nV/√Hz noise. maximum range, and operation is guaranteed monotonic with a 5. Low ±0.018 ppm/°C gain error temperature coefficient. ±0.5 LSB DNL maximum range specification. COMPANION PRODUCTS The part uses a versatile 3-wire serial interface that operates at Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1 clock rates of up to 35 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards. The External Reference: ADR445 part incorporates a power-on reset circuit that ensures that the DC-to-DC Design Tool: ADIsimPower™ DAC output powers up to 0 V in a known output impedance Additional companion products on the AD5780 product page state and remains in this state until a valid write to the device takes place. The part provides an output clamp feature that places the output in a defined load state. 1 Protected by U.S. Patent No. 7,884,747. Other patents pending. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09650-001 AD5760 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  DAC Architecture....................................................................... 20  Applications....................................................................................... 1  Serial Interface ............................................................................ 20  Functional Block Diagram .............................................................. 1  Hardware Control Pins.............................................................. 21  General Description ......................................................................... 1  On-Chip Registers...................................................................... 22  Product Highlights ........................................................................... 1  AD5760 Features ............................................................................ 25  Companion Products ....................................................................... 1  Power-On to 0 V......................................................................... 25  Revision History ............................................................................... 2  Configuring the AD5760 .......................................................... 25  Specifications..................................................................................... 3  DAC Output State ...................................................................... 25  Timing Characteristics ................................................................ 5  Output Amplifier Configuration.............................................. 25  Absolute Maximum Ratings............................................................ 8  Applications Information .............................................................. 27  ESD Caution.................................................................................. 8  Typical Operating Circuit ......................................................... 27  Pin Configuration and Function Descriptions............................. 9  Evaluation Board........................................................................ 28  Typical Performance Characteristics ........................................... 11  Outline Dimensions....................................................................... 29  Terminology .................................................................................... 19  Ordering Guide .......................................................................... 29  Theory of Operation ...................................................................... 20  REVISION HISTORY 2/12—Rev. A to Rev. B Deleted Linearity Compensation Section ..................................... 3 12/11—Rev. 0 to Rev. A Changes to Table 2............................................................................ 3 Changes to Figure 48...................................................................... 18 Changes to DAC Register Section................................................ 22 Changes to Table 10 and Table 11 ................................................ 23 11/11—Revision 0: Initial Version Rev. B | Page 2 of 32 Data Sheet AD5760 SPECIFICATIONS VDD = +12.5 V to +16.5 V, VSS = −16.5 V to −12.5 V, VREFP = +10 V, VREFN = −10 V, VCC = 2.7 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted. Table 2. 1 A, B Versions Parameter Min Typ Max Unit Test Conditions/Comments 2 STATIC PERFORMANCE Resolution 16 Bits Integral Nonlinearity Error (Relative −0.5 +0.5 LSB B grade, V = ±10 V, +10 V and +5 V REFx Accuracy) −2 +2 LSB A grade, V = ±10 V, +10 V and +5 V REFx Differential Nonlinearity Error −0.5 +0.5 LSB B grade, VREFx = ±10 V, +10 V and +5 V −1 +1 LSB A grade, VREFx = ±10 V, +10 V and +5 V 3 Long-Term Linearity Error Stability 0.00625 LSB After 750 hours at TA = 135°C Full-Scale Error −0.75 ±0.2 +0.75 LSB V = +10 V, V = −10 V REFP REFN −1.4 ±0.17 +1.4 LSB V = 10 V, V = 0 V REFP REFN −2.5 ±0.1 +2.5 LSB V = 5 V, V = 0 V REFP REFN Full-Scale Error Temperature ±0.026 ppm/°C VREFP = +10 V, VREFN = −10 V Coefficient Zero-Scale Error −1.2 ±0.0812 +1.2 LSB V = +10 V, V = −10 V REFP REFN −2.5 ±0.044 +2.5 LSB V = 10 V, V = 0 V REFP REFN −5.2 ±0.056 +5.2 LSB V = 5 V, V = 0 V REFP REFN Zero-Scale Error Temperature ±0.025 ppm/°C VREFP = +10 V, VREFN = −10 V Coefficient Gain Error −19 ±2.3 +19 ppm FSR VREFP = +10 V, VREFN = −10 V −35 ±1.9 +35 ppm FSR V = 10 V, V = 0 V REFP REFN −68 ±0.9 +68 ppm FSR V = 5 V, V = 0 V REFP REFN Gain Error Temperature Coefficient ±0.018 ppm/°C V = +10 V, V = −10 V REFP REFN R1, RFB Matching 0.015 % OUTPUT CHARACTERISTICS Output Voltage Range V V V REFN REFP Output Voltage Settling Time 2.5 μs 10 V step to 0.02%, using the ADA4898-1 buffer in unity-gain mode 4 3.5 μs 125 code step to ±1 LSB Output Noise Spectral Density 8 nV/√Hz At 1 kHz, DAC code = midscale 8 nV/√Hz At 10 kHz, DAC code = midscale Output Voltage Noise 1.1 μV p-p DAC code = midscale, 0.1 Hz to 10 Hz bandwidth 4 Midscale Glitch Impulse 14 nV-sec VREFP = +10 V, VREFN = −10 V 3.5 nV-sec V = 10 V, V = 0 V REFP REFN 4 nV-sec V = 5 V, V = 0 V REFP REFN 4 MSB Segment Glitch Impulse 14 nV-sec V = +10 V, V = −10 V, see Figure 43 REFP REFN 3.5 nV-sec VREFP = 10 V, VREFN = 0 V, see Figure 44 4 nV-sec VREFP = 5 V, VREFN = 0 V, see Figure 45 Output Enabled Glitch Impulse 57 nV-sec On removal of output ground clamp Digital Feedthrough 0.27 nV-sec DC Output Impedance (Normal 3.4 kΩ Mode) DC Output Impedance (Output 6 kΩ Clamped to Ground) Rev. B | Page 3 of 32 AD5760 Data Sheet 1 A, B Versions Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUTS V Input Range 5 V − 2.5 V REFP DD V Input Range V + 2.5 0 V REFN SS Input Bias Current −20 −0.63 +20 nA −4 −0.63 +4 TA = 0°C to 105°C Input Capacitance 1 pF VREFP, VREFN LOGIC INPUTS 5 Input Current −1 +1 μA Input Low Voltage, VIL 0.3 × IOVCC V IOVCC = 1.71 V to 5.5 V Input High Voltage, VIH 0.7 × IOVCC V IOVCC = 1.71 V to 5.5 V Pin Capacitance 5 pF LOGIC OUTPUT (SDO) Output Low Voltage, V 0.4 V IOV = 1.71 V to 5.5 V, sinking 1 mA OL CC Output High Voltage, V IOV − 0.5 V IOV = 1.71 V to 5.5 V, sourcing 1 mA OH CC CC High Impedance Leakage Current ±1 μA High Impedance Output 3 pF Capacitance POWER REQUIREMENTS All digital inputs at DGND or IOV CC VDD 7.5 VSS + 33 V VSS VDD − 33 −2.5 V VCC 2.7 5.5 V IOV 1.71 5.5 V IOV ≤ V CC CC CC I 10.3 14 mA DD I −10 −14 mA SS ICC 600 900 μA IOICC 52 140 μA SDO disabled DC Power Supply Rejection Ratio ±7.5 μV/V ∆V ± 10%, V = −15 V DD SS ±1.5 μV/V ∆V ± 10%, V = 15 V SS DD AC Power Supply Rejection Ratio 90 dB ∆V ± 200 mV, 50 Hz/60 Hz, V = −15 V DD SS 90 dB ∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V 1 Temperature range: −40°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V. 2 Performance characterized with the AD8675ARZ output buffer. 3 Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified. 4 The AD5760 is configured in unity-gain mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead capacitance, and so forth). 5 Current flowing in an individual logic pin. Rev. B | Page 4 of 32 Data Sheet AD5760 TIMING CHARACTERISTICS VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. 1 Limit Parameter IOV = 1.71 V to 3.3 V IOV = 3.3 V to 5.5 V Unit Test Conditions/Comments CC CC 2 t1 40 28 ns min SCLK cycle time 92 60 ns min SCLK cycle time (readback and daisy-chain modes) t 15 10 ns min SCLK high time 2 t 9 5 ns min SCLK low time 3 t4 5 5 ns min SYNC to SCLK falling edge setup time t5 2 2 ns min SCLK falling edge to SYNC rising edge hold time t6 48 40 ns min Minimum SYNC high time t 8 6 ns min SYNC rising edge to next SCLK falling edge ignore 7 t 9 7 ns min Data setup time 8 t 12 7 ns min Data hold time 9 t10 13 10 ns min LDAC falling edge to SYNC falling edge t11 20 16 ns min SYNC rising edge to LDAC falling edge t12 14 11 ns min LDAC pulse width low t 130 130 ns typ LDAC falling edge to output response time 13 t 130 130 ns typ SYNC rising edge to output response time (LDAC tied low) 14 t 50 50 ns min 15 CLR pulse width low t16 140 140 ns typ CLR pulse activation time t17 0 0 ns min SYNC falling edge to first SCLK rising edge t 65 60 ns max SYNC rising edge to SDO tristate (C = 50 pF) 18 L t 62 45 ns max SCLK rising edge to SDO valid (C = 50 pF) 19 L t 0 0 ns min SYNC rising edge to SCLK rising edge ignore 20 t21 35 35 ns typ RESET pulse width low t22 150 150 ns typ RESET pulse activation time 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes. Rev. B | Page 5 of 32 AD5760 Data Sheet t t 1 7 SCLK 1 2 24 t t t 6 3 2 t t 4 5 SYNC t 9 t 8 SDIN DB23 DB0 t t 12 10 t 11 LDAC t V 13 OUT t V 14 OUT t 15 CLR t 16 V OUT t 21 RESET t 22 V OUT Figure 2. Write Mode Timing Diagram t 20 t t 1 t 17 7 SCLK 12 2 4 1 2 24 t t t 3 2 6 t t 17 5 t t 4 5 SYNC t 9 t 8 SDIN DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION t 18 REGISTER TO BE READ t 19 SDO DB23 DB0 REGISTER CONTENTS CLOCKED OUT Figure 3. Readback Mode Timing Diagram Rev. B | Page 6 of 32 09650-002 09650-003 Data Sheet AD5760 t t 20 t 1 17 SCLK 12 24 25 26 48 t t t 3 2 6 t 5 t 4 SYNC t 9 t 8 SDIN DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N – 1 INPUT WORD FOR DAC N t t 18 19 SDO DB23 DB0 DB23 DB0 UNDEFINED INPUT WORD FOR DAC N Figure 4. Daisy-Chain Mode Timing Diagram Rev. B | Page 7 of 32 09650-004 AD5760 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to Stresses above those listed under Absolute Maximum Ratings 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 4. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to AGND −0.3 V to +34 V DD maximum rating conditions for extended periods may affect VSS to AGND −34 V to +0.3 V device reliability. VDD to VSS −0.3 V to +34 V This device is a high performance integrated circuit with an VCC to DGND −0.3 V to +7 V ESD rating of 1.6 kV, and it is ESD sensitive. Proper precautions IOV to DGND −0.3 V to V + 3 V or +7 V CC CC (whichever is less) must be taken for handling and assembly. Digital Inputs to DGND + 0.3 V or −0.3 V to IOVCC +7 V (whichever is less) ESD CAUTION VOUT to AGND −0.3 V to VDD + 0.3 V VREFP to AGND −0.3 V to VDD + 0.3 V V to AGND V − 0.3 V to +0.3 V REFN SS DGND to AGND −0.3 V to +0.3 V Operating Temperature Range, TA Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature, 150°C T max J Power Dissipation (T max − T )/θ J A JA LFCSP Package θJA Thermal Impedance 31.0°C/W Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 1.6 kV Rev. B | Page 8 of 32 Data Sheet AD5760 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 19 AGND OUT V V 2 18 REFP SS V V DD 3 17 SS AD5760 V RESET 4 16 REFN TOP VIEW V DD 5 (Not to Scale) 15 DGND CLR 6 14 SYNC LDAC 7 13 SCLK NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. NEGATIVE ANALOG SUPPLY CONNECTION (V ). SS A VOLTAGE IN THE RANGE OF –16.5 V TO –2.5 V CAN BE CONNECTED. V SHOULD BE DECOUPLED SS TO AGND. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE V PINS. IT IS SS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT Analog Output Voltage. 2 VREFP Positive Reference Voltage Input. A voltage in the range of 5 V to VDD − 2.5 V can be connected to this pin. 3, 5 VDD Positive Analog Supply Connection. A voltage in the range of 7.5 V to 16.5 V can be connected to this pin. V must be decoupled to AGND. DD 4 RESET Active Low Reset. Asserting this pin returns the AD5760 to its power-on status. 6 CLR Active Low Input. Asserting this pin sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. 7 LDAC Active Low Load DAC Logic Input. This pin is used to update the DAC register and, consequently, the analog output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. Do not leave the LDAC pin unconnected. 8 VCC Digital Supply. Voltage range is from 2.7 V to 5.5 V. VCC should be decoupled to DGND. 9 IOVCC Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. Voltage range is from 1.71 V to 5.5 V. 10, 21, 22, 23 DNC Do Not Connect. Do not connect to these pins. 11 SDO Serial Data Output. 12 SDIN Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 35 MHz. 14 SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The DAC is updated on the rising edge of SYNC. 15 DGND Ground Reference Pin for Digital Circuitry. 16 V Negative Reference Voltage Input. REFN 17, 18 V Negative Analog Supply Connection. A voltage in the range of −16.5 V to −2.5 V can be connected to this SS pin. VSS must be decoupled to AGND. 19 AGND Ground Reference Pin for Analog Circuitry. Rev. B | Page 9 of 32 V INV CC IOV DNC CC DNC DNC SDO DNC SDIN R FB 09650-005 8 24 9 23 10 22 11 21 12 20 AD5760 Data Sheet Pin No. Mnemonic Description 20 RFB Feedback Connection for External Amplifier. See the AD5760 Features section for further details. 24 INV Inverting Input Connection for External Amplifier. See the AD5760 Features section for further details. EPAD VSS Negative Analog Supply Connection (VSS). A voltage in the range of −16.5 V to −2.5 V can be connected to this pin. V must be decoupled to AGND. The paddle can be left electrically unconnected provided that a SS supply connection is made at the V pins. It is recommended that the paddle be thermally connected to a SS copper plane for enhanced thermal performance. Rev. B | Page 10 of 32 Data Sheet AD5760 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.10 V = +5V V = +10V REFP REFP V = 0V V = –10V REFN 0.08 REFN V = +15V V = +15V DD DD V = –15V V = –15V 0.05 SS SS 0.06 0.04 0 0.02 0 –0.05 –0.02 –0.10 –0.04 –0.06 –0.15 –0.08 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER T = 25°C A T = 25°C A –0.10 –0.20 0 10000 20000 30000 40000 50000 60000 70000 0 10000 20000 30000 40000 50000 60000 70000 DAC CODE DAC CODE Figure 6. Integral Nonlinearity Error vs. DAC Code, ±10 V Span Figure 9. Integral Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain Mode 0.15 0.10 V = +10V REFP V = +10V REFP V = 0V REFN V = –10V REFN 0.08 V = +15V DD V = +15V DD V = –15V SS V = –15V SS 0.10 0.06 0.04 0.05 0.02 0 0 –0.02 –0.04 –0.05 –0.06 –0.08 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER T = 25°C T = 25°C A A –0.10 –0.10 0 10000 20000 30000 40000 50000 60000 70000 0 10000 20000 30000 40000 50000 60000 70000 DAC CODE DAC CODE Figure 7. Integral Nonlinearity Error vs. DAC Code, 10 V Span Figure 10. Differential Nonlinearity Error vs. DAC Code, ±10 V Span 0.10 0.20 V = +5V REFP V = +10V REFP V = 0V REFN V = 0V REFN V = +15V DD V = +15V DD V = –15V 0.05 0.15 V = –15V SS SS 0 0.10 –0.05 0.05 –0.10 0 –0.15 –0.05 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER T = 25°C T = 25°C A A –0.20 –0.10 0 10000 20000 30000 40000 50000 60000 70000 0 10000 20000 30000 40000 50000 60000 70000 DAC CODE DAC CODE Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span Figure 11. Differential Nonlinearity Error vs. DAC Code, 10 V Span Rev. B | Page 11 of 32 INL (LSB) INL (LSB) INL (LSB) 09650-008 09650-007 09650-006 DNL (LSB) INL (LSB) DNL (LSB) 09650-010 09650-011 09650-009 AD5760 Data Sheet 0.10 0.09 V = +15V V = +5V REFP DD V = –15V V = 0V REFN SS 0.08 V = +15V AD8675 OUTPUT BUFFER DD V = –15V SS 0.06 0.07 0.04 0.02 0.05 0 ±10V SPAN MAX INL ±10V SPAN MIN INL +10V SPAN MAX INL +10V SPAN MIN INL –0.02 0.03 +5V SPAN MAX INL +5V SPAN MIN INL –0.04 –0.06 0.01 –0.08 AD8675 OUTPUT BUFFER T = 25°C A –0.01 –0.10 –40 –20 0 20406080 100 0 10000 20000 30000 40000 50000 60000 70000 TEMPERATURE (°C) DAC CODE Figure 15. Differential Nonlinearity Error vs. Temperature Figure 12. Differential Nonlinearity Error vs. DAC Code, 5 V Span 0.08 AD8675 OUTPUT BUFFER 0.09 INL MAX T = 25°C A 0.06 0.07 0.04 0.05 0.02 T = 25°C 0 A 0.03 V = +10V REFP V = –10V REFN –0.02 AD8675 OUTPUT BUFFER 0.01 –0.04 –0.01 –0.06 V = +5V REFP INL MIN –0.03 V = 0V REFN V = +15V –0.08 DD V = –15V SS –0.05 –0.1.0 0 10000 20000 30000 40000 50000 60000 70000 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 DAC CODE V /|V | (V) DD SS Figure 13. Differential Nonlinearity Error vs. DAC Code, 5 V Span, Figure 16. Integral Nonlinearity Error vs. Supply Voltage, ±10 V Span ×2 Gain Mode 0.20 0.15 V = +15V DD V = –15V SS AD8675 OUTPUT BUFFER 0.15 0.10 INL MAX 0.10 0.05 0.05 T = 25°C A V = 5V ±10V SPAN MAX INL ±10V SPAN MIN INL 0 REFP V = 0V +10V SPAN MAX INL +10V SPAN MIN INL REFN 0 AD8675 OUTPUT BUFFER +5V SPAN MAX INL +5V SPAN MIN INL –0.05 –0.05 INL MIN –0.10 –0.10 –0.15 –0.15 –40 –20 0 20 40 60 80 100 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 TEMPERATURE (°C) V /|V | (V) DD SS Figure 14. Integral Nonlinearity Error vs. Temperature Figure 17. Integral Nonlinearity Error vs. Supply Voltage, 5 V Span Rev. B | Page 12 of 32 DNL (LSB) DNL (LSB) INL ERROR (LSB) 09650-015 09650-013 09650-012 INL ERROR (LSB) INL ERROR (LSB) DNL ERROR (LSB) 09650-014 09650-017 09650-016 Data Sheet AD5760 0.8 0.09 T = 25°C A V = 5V 0.08 REFP DNL MAX V = 0V REFN 0.6 AD8675 OUTPUT BUFFER 0.07 0.06 0.4 0.05 T = 25°C A V = +10V REFP V = –10V REFN 0.2 0.04 AD8675 OUTPUT BUFFER 0.03 0 0.02 0.01 –0.2 DNL MIN 0 –0.4 –0.01 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 V /|V | (V) V /|V | (V) DD SS DD SS Figure 18. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span Figure 21. Zero-Scale Error vs. Supply Voltage, 5 V Span 0.09 –0.02 –0.03 0.08 DNL MAX –0.04 0.07 –0.05 0.06 –0.06 0.05 T = 25°C A V = 5V REFP –0.07 0.04 V = 0V REFN AD8675 OUTPUT BUFFER –0.08 0.03 –0.09 0.02 –0.10 0.01 T = 25°C A V = +10V REFP –0.11 0 DNL MIN V = –10V REFN AD8675 OUTPUT BUFFER –0.12 –0.01 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V /|V | (V) DD SS V /|V | (V) DD SS Figure 19. Differential Nonlinearity Error vs. Supply Voltage, 5 V Span Figure 22. Midscale Error vs. Supply Voltage, ±10 V Span 0.15 0.5 T = 25°C A V = +10V REFP 0.4 V = –10V REFN AD8675 OUTPUT BUFFER 0.3 0.10 0.2 0.05 0.1 0 0 –0.1 –0.2 –0.05 –0.3 T = 25°C A V = 5V REFP –0.4 V = 0V REFN AD8675 OUTPUT BUFFER –0.10 –0.5 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V /|V | (V) V /|V | (V) DD SS DD SS Figure 20. Zero-Scale Error vs. Supply Voltage, ±10 V Span Figure 23. Midscale Error vs. Supply Voltage, 5 V Span Rev. B | Page 13 of 32 ZERO-SCALE ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 09650-019 09650-020 09650-018 MIDSCALE ERROR (LSB) MIDSCALE ERROR (LSB) ZERO-SCALE ERROR (LSB) 09650-023 09650-022 09650-021 AD5760 Data Sheet 0.14 0.38 T = 25°C A T = 25°C A V = +10V REFP V = 5V REFP V = –10V V = 0V 0.12 REFN REFN 0.36 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER 0.10 0.34 0.08 0.32 0.06 0.30 0.04 0.28 0.02 0 0.26 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 V /|V | (V) DD SS V /|V | (V) DD SS Figure 24. Full-Scale Error vs. Supply Voltage, ±10 V Span Figure 27. Gain Error vs. Supply Voltage, 5 V Span 0.5 0.08 T = 25°C A INL MAX V = 5V REFP 0.06 V = 0V 0.3 REFN AD8675 OUTPUT BUFFER 0.04 0.1 0.02 T = 25°C A –0.1 V = +15V DD 0 V = –15V SS AD8675 OUTPUT BUFFER –0.02 –0.3 –0.04 –0.5 –0.06 INL MIN –0.7 –0.08 –0.9 –0.10 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 V /|V | (V) DD SS V /|V | (V) REFP REFN Figure 25. Full-Scale Error vs. Supply Voltage, 5 V Span Figure 28. Integral Nonlinearity Error vs. Reference Voltage 0.10 0.08 T = 25°C A V = +10V REFP V = –10V 0.08 REFN INL MAX AD8675 OUTPUT BUFFER 0.06 0.06 T = 25°C A 0.04 0.04 V = +15V DD V = –15V SS AD8675 OUTPUT BUFFER 0.02 0.02 0 –0.02 INL MIN 0 –0.04 –0.06 –0.02 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 V /|V | (V) DD SS V /|V | (V) REFP REFN Figure 26. Gain Error vs. Supply Voltage, ±10 V Span Figure 29. Differential Nonlinearity Error vs. Reference Voltage Rev. B | Page 14 of 32 GAIN ERROR (LSB) FULL-SCALE ERROR (LSB) FULL-SCALE ERROR (LSB) 09650-026 09650-025 09650-024 DNL ERROR (LSB) INL ERROR (LSB) GAIN ERROR (LSB) 09650-029 09650-028 09650-027 Data Sheet AD5760 –0.25 –0.02 T = 25°C A V = +15V DD –0.03 V = –15V SS AD8675 OUTPUT BUFFER –0.30 –0.04 –0.05 –0.35 –0.06 –0.40 –0.07 –0.08 –0.45 T = 25°C A V = +15V –0.09 DD V = –15V SS AD8675 OUTPUT BUFFER –0.10 –0.50 5.05.5 6.06.57.0 7.58.08.5 9.09.5 10.0 5.05.5 6.06.57.0 7.58.08.59.0 9.5 10.0 V /|V | (V) V /|V | (V) REFP REFN REFP REFN Figure 30. Zero-Scale Error vs. Reference Voltage Figure 33. Gain Error vs. Reference Voltage 0.50 –0.05 T = 25°C ±10V SPAN A V = +15V +10V SPAN –0.07 DD V = –15V +5V SPAN SS 0.45 AD8675 OUTPUT BUFFER –0.09 0.40 –0.11 –0.13 0.35 –0.15 0.30 –0.17 –0.19 0.25 –0.21 0.20 V = +15V DD –0.23 V = –15V SS AD8675 OUTPUT BUFFER 0.15 –0.25 –40 –20 0 20 40 60 80 100 5.05.56.06.57.07.58.08.5 9.09.5 10.0 V /|V | (V) TEMPERATURE (°C) REFP REFN Figure 34. Full-Scale Error vs. Temperature Figure 31. Midscale Error vs. Reference Voltage 0.15 0.40 ±10V SPAN T = 25°C A +10V SPAN V = +15V DD 0.38 0.10 +5V SPAN V = –15V SS AD8675 OUTPUT BUFFER 0.36 0.05 0.34 0 0.32 –0.05 0.3 –0.10 0.28 –0.15 0.26 –0.20 0.24 V = +15V DD –0.25 0.22 V = –15V SS AD8675 OUTPUT BUFFER –0.30 0.20 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 –40 –20 0 20 40 60 80 100 V /|V | (V) TEMPERATURE (°C) REFP REFN Figure 35. Midscale Error vs. Temperature Figure 32. Full-Scale Error vs. Reference Voltage Rev. B | Page 15 of 32 MIDSCALE ERROR (LSB) FULL-SCALE ERROR (LSB) ZERO-SCALE ERROR (LSB) 09650-032 09650-030 09650-031 GAIN ERROR (LSB) MIDSCALE ERROR (LSB) FULL-SCALE ERROR (LSB) 09650-034 09650-035 09650-033 AD5760 Data Sheet 0.4 0.010 ±10V SPAN +10V SPAN 0.008 +5V SPAN I DD 0.2 0.006 0.004 0 0.002 –0.2 0 –0.002 –0.4 –0.004 –0.006 –0.6 I SS V = +15V DD –0.008 V = –15V SS AD8675 OUTPUT BUFFER –0.8 –0.010 –40 –20 0 20 40 60 80 100 –20 –15 –10 –5 0 5 10 15 20 V /V (V) TEMPERATURE (°C) DD SS Figure 36. Zero-Scale Error vs. Temperature Figure 39. Power Supply Currents vs. Power Supply Voltages 0 6 ±10V SPAN +10V SPAN –0.1 +5V SPAN 4 –0.2 2 –0.3 0 –0.4 V = +15V DD V = –15V SS V = +10V REFP –0.5 –2 V = –10V REFN ADA4808-1 BUFFERED –0.6 LOAD = 10MΩ || 20pF –4 –0.7 –6 –0.8 V = +15V DD –8 –0.9 V = –15V SS AD8675 OUTPUT BUFFER –1.0 –10 –40 –20 0 20 40 60 80 100 –1 012345 TEMPERATURE (°C) TIME (µs) Figure 40. Rising Full-Scale Voltage Step Figure 37. Gain Error vs. Temperature 6 900 IOV = 5V, LOGIC VOLTAGE V = +15V CC T = 25°C DD A INCREASING V = –15V SS 800 4 V = +10V IOV = 5V, LOGIC VOLTAGE REFP CC V = –10V REFN DECREASING ADA4808-1 BUFFERED 700 IOV = 3V, LOGIC VOLTAGE CC 2 LOAD = 10MΩ || 20pF INCREASING IOV = 3V, LOGIC VOLTAGE 600 CC 0 DECREASING 500 –2 400 –4 300 –6 200 –8 100 –10 0 01 23 4 5 6 –1 01234 5 LOGIC INPUT VOLTAGE (V) TIME (µs) Figure 41. Falling Full-Scale Voltage Step Figure 38. IOICC vs. Logic Input Voltage Rev. B | Page 16 of 32 ZERO-SCALE ERROR (LSB) IOI (µA) GAIN ERROR (LSB) CC 09650-037 09650-038 09650-036 I /I (mA) DD SS V (V) V (V) OUT OUT 09650-041 09650-040 09650-039 Data Sheet AD5760 6 10 V = 5V NEGATIVE REFP V = 0V POSITIVE REFN 9 UNITY-GAIN MODE 5 ADA4898-1 8 RC LOW-PASS FILTER 7 4 6 3 5 4 2 3 V = +10V 2 REFP 1 V = –10V REFN RC LOW-PASS FILTER 1 UNITY-GAIN MODE ADA4898-1 0 0 –1 0123 45 TIME (µs) CODE Figure 42. 500 Code Step Settling Time Figure 45. 6 MSB Segment Glitch Energy for 5 V V REF 25 55 V = +10V NEGATIVE REFP ±10V REF V = –10V POSITIVE 10V REF REFN UNITY-GAIN MODE 45 5V REF ADA4898-1 20 RC LOW PASS FILTER POSITIVE NEGATIVE CODE CHANGE 35 CODE CHANGE 25 15 15 10 5 –5 5 –15 0 –25 –1 012 3 TIME (µs) CODE Figure 43. 6 MSB Segment Glitch Energy for ±10 V VREF Figure 46. Midscale Peak-to-Peak Glitch for ±10 V 4.0 800 V = 10V T = 25°C NEGATIVE MIDSCALE CODE LOADED REFP A V = 0V POSITIVE V = +15V REFN OUTPUT UNBUFFERED DD 3.5 UNITY-GAIN MODE V = –15V AD8676 REFERENCE BUFFERS 600 SS ADA4898-1 V = +10V REFP RC LOW-PASS FILTER V = –10V REFN 3.0 400 2.5 200 2.0 0 1.5 –200 1.0 –400 0.5 0 –600 0 1 23 4 567 8 9 10 TIME (Seconds) CODE Figure 44. 6 MSB Segment Glitch Energy for 10 V V Figure 47. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth REF Rev. B | Page 17 of 32 V (mV) OUTPUT GLITCH (nV-s) OUT OUTPUT GLITCH (nV-s) 16384 16384 49152 81920 65536 114688 114688 147456 180224 163840 212992 212992 245760 278528 262144 311296 311296 344064 376832 360448 409600 409600 442368 475136 458752 507904 507904 540672 573440 557056 606208 606208 638976 671744 655360 704512 704512 737280 770048 753664 802816 802816 835584 868352 851968 901120 901120 933888 966656 950272 999424 999424 1032192 09650-045 09650-044 09650-042 OUTPUT GLITCH (V) OUTPUT VOLTAGE (nV) OUTPUT GLITCH (nV-s) 16384 65536 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 09650-046 09650-047 09650-048 AD5760 Data Sheet 100 0.20 V = +15V V = +15V DD DD V = –15V V = –15V SS SS 0.18 V = +10V V = +10V REFP REFP V = –10V V = –10V REFN REFN 0.16 UNITY GAIN ADA4898-1 0.14 0.12 0.10 10 0.08 0.06 0.04 0.02 0 1 –0.02 0.1 1 10 100 1k 10k 0 123 45 6 TIME (µs) FREQUENCY (Hz) Figure 48. Noise Spectral Density vs. Frequency Figure 49. Glitch Impulse on Removal of Output Clamp Rev. B | Page 18 of 32 NSD (nV/√Hz) 09650-056 OUTPUT VOLTAGE (V) 09650-049 Data Sheet AD5760 TERMINOLOGY Relative Accuracy Output Voltage Settling Time Relative accuracy, or integral nonlinearity (INL), is a measure of Output voltage settling time is the amount of time it takes for the maximum deviation, in LSB, from a straight line passing the output voltage to settle to a specified level for a specified through the endpoints of the DAC transfer function. A typical change in voltage. For fast settling applications, a high speed INL error vs. code plot is shown in Figure 6. buffer amplifier is required to buffer the load from the 3.4 kΩ output impedance of the AD5760, in which case, it is the Differential Nonlinearity (DNL) amplifier that determines the settling time. Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent Digital-to-Analog Glitch Impulse codes. A specified differential nonlinearity of ±1 LSB maximum Digital-to-analog glitch impulse is the impulse injected into the ensures monotonicity. This DAC is guaranteed monotonic. A analog output when the input code in the DAC register changes typical DNL error vs. code plot is shown in Figure 10. state. It is specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at Linearity Error Long-Term Stability the major carry transition (see Figure 49). Linearity error long-term stability is a measure of the stability of the linearity of the DAC over a long period of time. It is specified Output Enabled Glitch Impulse in LSB for a time period of 500 hours and 1000 hours at an Output enabled glitch impulse is the impulse injected into the elevated ambient temperature. analog output when the clamp to ground on the DAC output is removed. It is specified as the area of the glitch in nV-sec (see Zero-Scale Error Figure 49). Zero-scale error is a measure of the output error when zero-scale code (0x00000) is loaded to the DAC register. Ideally, the output Digital Feedthrough voltage should be VREFN. Zero-scale error is expressed in LSBs. Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the Zero-Scale Error Temperature Coefficient DAC but is measured when the DAC output is not updated. It is Zero-scale error temperature coefficient is a measure of the specified in nV-sec and measured with a full-scale code change change in zero-scale error with a change in temperature. It is on the data bus, that is, from all 0s to all 1s, and vice versa. expressed in ppm FSR/°C. Total Harmonic Distortion (THD) Full-Scale Error Total harmonic distortion is the ratio of the rms sum of the Full-scale error is a measure of the output error when full-scale harmonics of the DAC output to the fundamental value. Only code (0x3FFFF) is loaded to the DAC register. Ideally, the the second to fifth harmonics are included. output voltage should be V − 1 LSB. Full-scale error is REFP expressed in LSBs. DC Power Supply Rejection Ratio. DC power supply rejection ratio is a measure of the rejection of Full-Scale Error Temperature Coefficient the output voltage to dc changes in the power supplies applied Full-scale error temperature coefficient is a measure of the to the DAC. It is measured for a given dc change in power change in full-scale error with a change in temperature. It is supply voltage and is expressed in μV/V. expressed in ppm FSR/°C. AC Power Supply Rejection Ratio (AC PSRR) Gain Error AC power supply rejection ratio is a measure of the rejection of Gain error is a measure of the span error of the DAC. It is the the output voltage to ac changes in the power supplies applied deviation in slope of the DAC transfer characteristic from the to the DAC. It is measured for a given amplitude and frequency ideal, expressed in ppm of the full-scale range. change in power supply voltage and is expressed in decibels. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with a change in temperature. It is expressed in ppm FSR/°C. Midscale Error Midscale error is a measure of the output error when midscale code (0x20000) is loaded to the DAC register. Ideally, the output voltage should be (V – V )/2 +V . Midscale error is REFP REFN REFN expressed in LSBs. Rev. B | Page 19 of 32 AD5760 Data Sheet THEORY OF OPERATION RR R The AD5760 is a high accuracy, fast settling, single, 16-bit, V OUT ... ... serial input, voltage output DAC. It operates from a VDD supply 2R 2R 2R 2R 2R 2R 2R ... ... voltage of 7.5 V to 16.5 V and a VSS supply of −16.5 V to −2.5 V. S0 S1 S9 E62 E61 E0 V REFP Data is written to the AD5760 in a 24-bit word format via a 3-wire serial interface. The AD5760 incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V with the V REFN V pin clamped to AGND through a ~6 kΩ internal resistor. OUT 10-BIT R-2R LADDER SIX MSBs DECODED INTO 63 EQUAL SEGMENTS DAC ARCHITECTURE Figure 50. DAC Ladder Structure Serial Interface The architecture of the AD5760 consists of two matched DAC SERIAL INTERFACE sections. A simplified circuit diagram is shown in Figure 50. The AD5760 has a 3-wire serial interface ( , SCLK, and SYNC The six MSBs of the 16-bit data-word are decoded to drive SDIN) that is compatible with SPI, QSPI, and MICROWIRE 63 switches, E0 to E62. Each of these switches connects one of interface standards, as well as most DSPs (see Figure 2 for a 63 matched resistors to either the buffered VREFP or buffered timing diagram). VREFN voltage. The remaining 10 bits of the data-word drive the S0 to S9 switches of a 10-bit voltage mode R-2R ladder network. Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK, which can operate at up to 35 MHz. The input register consists of a R/W bit, three address bits, and 20 data bits as shown in Table 6. The timing diagram for this operation is shown in Figure 2. Table 6. Input Shift Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 to DB0 R/W Register address Register data Table 7. Decoding the Input Shift Register R/W Register Address Description 1 X 0 0 0 No operation (NOP). Used in readback operations. 0 0 0 1 Write to the DAC register. 0 0 1 0 Write to the control register. 0 0 1 1 Write to the clearcode register. 0 1 0 0 Write to the software control register. 1 0 0 1 Read from the DAC register. 1 0 1 0 Read from the control register. 1 0 1 1 Read from the clearcode register. 1 X is don’t care. Rev. B | Page 20 of 32 09650-050 Data Sheet AD5760 Standalone Operation AD5760* CONTROLLER The serial interface works with both a continuous and noncon- DATA OUT SDIN tinuous serial clock. A continuous SCLK source can be used SERIAL CLOCK SCLK SYNC only if is held low for the correct number of clock cycles. CONTROL OUT SYNC In gated clock mode, a burst clock containing the exact number DATA IN SYNC SDO of clock cycles must be used, and must be taken high after the final clock to latch the data. The first falling edge of SYNC SDIN starts the write cycle. Exactly 24 falling clock edges must be applied AD5760* to SCLK before SYNC is brought high again. If SYNC is brought th high before the 24 falling SCLK edge, the data written is invalid. SCLK SYNC If more than 24 falling SCLK edges are applied before is SYNC brought high, the input data is also invalid. SYNC The input shift register is updated on the rising edge of . SDO SYNC For another serial transfer to take place, must be brought low again. After the end of the serial data transfer, data is SDIN automatically transferred from the input shift register to the AD5760* addressed register. When the write cycle is complete, the output LDAC SYNC can be updated by taking low while is high. SCLK SYNC Daisy-Chain Operation For systems that contain several devices, the SDO pin can be SDO used to daisy chain several devices together. Daisy-chain mode can be useful in system diagnostics and in reducing the number *ADDITIONAL PINS OMITTED FOR CLARITY. of serial interface lines. The first falling edge of SYNC starts Figure 51. Daisy-Chain Block Diagram the write cycle. SCLK is continuously applied to the input shift Readback SYNC register when is low. If more than 24 clock pulses are The contents of all the on-chip registers can be read back via applied, the data ripples out of the shift register and appears on the SDO pin. Table 7 outlines how the registers are decoded. the SDO line. This data is clocked out on the rising edge of After a register has been addressed for a read, the next 24 clock SCLK and is valid on the falling edge. By connecting the SDO cycles clock the data out on the SDO pin. The clocks must be of the first device to the SDIN input of the next device in the applied while SYNC is low. When SYNC is returned high, the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of SDO pin is placed in tristate. For a read of a single register, the clock cycles must equal 24 × N, where N is the total number of NOP function can be used to clock out the data. Alternatively, AD5760 devices in the chain. When the serial transfer to all if more than one register is to be read, the data of the first SYNC register to be addressed can be clocked out at the same time devices is complete, is taken high. This latches the input that the second register to be read is being addressed. The SDO data in each device in the daisy chain and prevents any further pin must be enabled to complete a readback operation. The data from being clocked into the input shift register. The serial SDO pin is enabled by default. clock can be a continuous or a gated clock. A continuous SCLK source can be used only if SYNC is held HARDWARE CONTROL PINS low for the correct number of clock cycles. In gated clock mode, LDAC Load DAC Function ( ) a burst clock containing the exact number of clock cycles must After data has been transferred into the input register of the SYNC be used, and must be taken high after the final clock to DAC, there are two ways to update the DAC register and DAC latch the data. output. Depending on the status of both SYNC and LDAC, one In any one daisy-chain sequence, do not mix writes to the DAC of two update modes is selected: synchronous DAC update or register with writes to any of the other registers. All writes to the asynchronous DAC update. daisy-chained parts must be either writes to the DAC registers Synchronous DAC Update or writes to the control, clearcode, or software control register. LDAC In this mode, is held low while data is being clocked into the input shift register. The DAC output is updated on the rising SYNC edge of . Rev. B | Page 21 of 32 09650-051 AD5760 Data Sheet is high) until a new value is loaded to the DAC register. The Asynchronous DAC Update CLR output cannot be updated with a new value while the pin is In this mode, LDAC is held high while data is being clocked low. A clear operation can also be performed by setting the CLR into the input shift register. The DAC output is asynchronously bit in the software control register (see Table 13). LDAC SYNC updated by taking low after has been taken high. LDAC ON-CHIP REGISTERS The update now occurs on the falling edge of . DAC Register Reset Function (RESET) Table 9 outlines how data is written to and read from the DAC The AD5760 can be reset to its power-on state by two means: register. RESET pin or by using the reset function either by asserting the The following equation describes the ideal transfer function of RESET in the software control register (see Table 13). If the pin the DAC: is not used, hardwire it to IOV . CC (V −V )×D Asynchronous Clear Function ( ) CLR REFP REFN V = +V OUT REFN 16 2 CLR The pin is an active low clear that allows the output to be where: cleared to a user defined value. The 16-bit clearcode value is V is the negative voltage applied at the V input pin. REFN REFN programmed to the clearcode register (see Table 12). It is VREFP is the positive voltage applied at the VREFP input pin. necessary to maintain CLR low for a minimum amount of time D is the 16-bit code programmed to the DAC. to complete the operation (see Figure 2). When the CLR signal is returned high, the output remains at the clear value (if LDAC Table 8. Hardware Control Pins Truth Table LDAC CLR RESET Function 1 1 X XX 0 The AD5760 is in reset mode. The device cannot be programmed. 1 1 X XX The AD5760 is returned to its power-on state. All registers are set to their default values. 0 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly. 0 1 1 The output is set according to the DAC register value. 1 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly. 1 1 The output is set according to the DAC register value. 0 1 The output remains at the clearcode register value. 1 1 The output remains set according to the DAC register value. 0 1 The output remains at the clearcode register value. 1 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 0 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 1 1 The output remains at the clearcode register value. 0 1 The output is set according to the DAC register value. 1 X is don’t care. Table 9. DAC Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB4 DB3 DB2 DB1 DB0 R/W Register address DAC register data 1 1 1 1 R/W 0 0 1 16 bits of data X X X X 1 X is don’t care. Rev. B | Page 22 of 32 Data Sheet AD5760 Control Register is asserted. The output value depends on the DAC coding that is being used, either binary or twos complement. The default The control register controls the mode of operation of the register value is 0. AD5760. Clearcode Register The clearcode register sets the value to which the DAC output is set when the pin or CLR bit in the software control register CLR Table 10. Control Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Register address Control register data R/W 0 1 0 Reserved Reserved 0000 SDODIS BIN/2sC DACTRI OPGND RBUF Reserved R/W Table 11. Control Register Functions Bit Name Description Reserved These bits are reserved and should be programmed to zero. RBUF Output amplifier configuration control. 0: the internal amplifier, A1, is powered up and Resistors R and R1 are connected in series, as shown in Figure 54. This allows FB   an external amplifier to be connected in a gain of two configuration. See the AD5760 Features section for further details. 1: (default) the internal amplifier, A1, is powered down and Resistors RFB and R1 are connected in parallel, as shown in Figure 53, so that the resistance between the RFB and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the RFB   and INV pins to be used for input bias current compensation for an external unity-gain amplifier. See the AD5760 Features section for further details. OPGND Output ground clamp control. 0: the DAC output clamp to ground is removed, and the DAC is placed in normal mode.   1: (default) the DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode.   Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated. Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit. DACTRI DAC tristate control. 0: the DAC is in normal operating mode.   1: (default) the DAC is in tristate mode.   BIN/2sC DAC register coding selection. 0: (default) the DAC register uses twos complement coding.   1: the DAC register uses offset binary coding.   SDODIS SDO pin enable/disable control. 0: (default) the SDO pin is enabled.   1: the SDO pin is disabled (tristate).   R/W Read/write select bit. 0: AD5760 is addressed for a write operation. 1: AD5760 is addressed for a read operation. Table 12. Clearcode Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB4 DB3 DB2 DB1 DB0 R/W Register address Clearcode register data 1 1 1 1 R/W 0 1 1 16 bits of data X XX XX XX 1 X is don’t care. Rev. B | Page 23 of 32 AD5760 Data Sheet Software Control Register This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low. Table 13. Software Control Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB3 DB2 DB1 DB0 R/W Register address Software control register data 1 2 0 1 0 0 Reserved Reset CLR LDAC 1 The CLR function has no effect when the LDAC pin is low. 2 CLR The LDAC function has no effect when the pin is low. Table 14. Software Control Register Functions Bit Name Description LDAC Setting this bit to 1 updates the DAC register and, consequently, the DAC output. CLR Setting this bit to 1 sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. Reset Setting this bit to 1 returns the AD5760 to its power-on state. Rev. B | Page 24 of 32 Data Sheet AD5760 AD5760 FEATURES A second unity-gain configuration for the output amplifier is POWER-ON TO 0 V one that removes an offset from the input bias currents of the The AD5760 contains a power-on reset circuit that, as well as amplifier. It does this by inserting a resistance in the feedback resetting all registers to their default values, controls the output path of the amplifier that is equal to the output resistance of the voltage during power-up. Upon power-on, the DAC is placed in DAC. The DAC output resistance is 3.4 kΩ. By connecting R1 tristate (its reference inputs are disconnected), and its output is and R in parallel, a resistance equal to the DAC resistance is FB clamped to AGND through a ~6 kΩ resistor. The DAC remains available on chip. Because the resistors are all on one piece of in this state until programmed otherwise via the control register. silicon, they are temperature coefficient matched. To enable this This is a useful feature in applications where it is important to mode of operation, the RBUF bit of the control register must be know the state of the DAC output while it is in the process of set to Logic 1. Figure 53 shows how the output amplifier is powering up. connected to the AD5760. In this configuration, the output CONFIGURING THE AD5760 amplifier is in unity gain, and the output spans from VREFN to V . This unity-gain configuration allows a capacitor to be After power-on, the AD5760 must be configured to put it into REFP placed in the amplifier feedback path to improve dynamic normal operating mode before programming the output. To performance. do this, the control register must be programmed. The DAC is removed from tristate by clearing the DACTRI bit, and the V REFP output clamp is removed by clearing the OPGND bit. At this point, the output goes to VREFN unless an alternative value is R FB R1 R FB 10pF first programmed to the DAC register. 6.8kΩ 6.8kΩ INV V DAC OUTPUT STATE OUT V OUT 16-BIT DAC The DAC output can be placed in one of three states, controlled AD8675 ADA4898-1 by the DACTRI and OPGND bits of the control register, as ADA4004-1 shown in Table 15. AD5760 V = 0V REFN Table 15. Output State Truth Table Figure 53. Output Amplifier in Unity-Gain with Amplifier Input Bias Current DACTRI OPGND Output State Compensation 0 0 Normal operating mode. 0 1 Output is clamped via ~6 kΩ to AGND. 1 0 Output is in tristate. 1 1 Output is clamped via ~6 kΩ to AGND. OUTPUT AMPLIFIER CONFIGURATION There are a number of different ways that an output amplifier can be connected to the AD5760, depending on the voltage references applied and the desired output voltage span. Unity-Gain Configuration Figure 52 shows an output amplifier configured for unity gain. In this configuration, the output spans from VREFN to VREFP. V REFP 6.8kΩ 6.8kΩ R FB A1 R1 R AD8675 FB INV ADA4898-1 ADA4004-1 V OUT 16-BIT DAC V OUT AD5760 V REFN Figure 52. Output Amplifier in Unity-Gain Configuration Rev. B | Page 25 of 32 09650-052 09650-053 AD5760 Data Sheet V REFP Gain of Two Configuration (×2 Gain Mode) Figure 54 shows an output amplifier configured for a gain of 6.8kΩ 6.8kΩ R FB A1 two. The gain is set by the internal matched 6.8 kΩ resistors, R1 R 10pF FB INV which are exactly twice the DAC resistance, having the effect V OUT V of removing an offset from the input bias current of the external OUT 16-BIT DAC amplifier. In this configuration, the output spans from 2 × VREFN − AD8675 ADA4898-1 VREFP to VREFP. This configuration is used to generate a bipolar ADA4004-1 output span from a single-ended reference input, with V = REFN AD5760 0 V. For this mode of operation, the RBUF bit of the control V REFN register must be cleared to Logic 0. Figure 54. Output Amplifier in Gain of Two Configuration Rev. B | Page 26 of 32 09650-054 Data Sheet AD5760 APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Figure 55. Typical Operating Circuit Rev. B | Page 27 of 32 09650-055 AD5760 Data Sheet Figure 55 shows a typical operating circuit for the AD5760 to aid designers in evaluating the high performance of the part using an AD8675 as an output buffer. Because the output with minimum effort. The evaluation kit includes a populated impedance of the AD5760 is 3.4 kΩ, an output buffer is and tested AD5780 printed circuit board (PCB). The evaluation required for driving low resistive, high capacitive loads. board interfaces to the USB port of a PC. Software is available with the evaluation board to allow the user to easily program EVALUATION BOARD the AD5780. The software runs on any PC that has Microsoft® Refer to the evaluation board available for the AD5780 or Windows® XP (SP2), Vista (32-bit or 64-bit), or Windows 7 AD5790 to evaluate a 18-bit version or 20-bit version of the installed. The UG-256 is available, which gives full details on AD5760. An evaluation board is available for the AD5780 the operation of the evaluation board Rev. B | Page 28 of 32 Data Sheet AD5760 OUTLINE DIMENSIONS 2.75 2.65 4.00 BSC 2.50 PIN 1 PIN 1 INDICATOR INDICATOR 20 24 (Chamfer 0.225) 19 1 0.50 5.00 BSC 3.75 BSC EXPOSED PAD 3.65 3.50 13 7 12 8 0.50 TOP VIEW BOTTOM VIEW 0.40 1.00 0.30 0.90 0.05 MAX FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS 0.30 0.08 SECTION OF THIS DATA SHEET. SEATING 0.20 REF 0.25 PLANE 0.20 Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 5 mm, Very Thin Quad (CP-24-5) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range INL Package Description Package Option AD5760BCPZ −40°C to +125°C ±0.5 LSB 24-Lead LFCSP_VQ CP-24-5 AD5760BCPZ-REEL7 −40°C to +125°C ±0.5 LSB 24-Lead LFCSP_VQ CP-24-5 AD5760ACPZ −40°C to +125°C ±2 LSB 24-Lead LFCSP_VQ CP-24-5 AD5760ACPZ-REEL7 −40°C to +125°C ±2 LSB 24-Lead LFCSP_VQ CP-24-5 1 Z = RoHS Compliant Part. Rev. B | Page 29 of 32 122409-B AD5760 Data Sheet NOTES Rev. B | Page 30 of 32 Data Sheet AD5760 NOTES Rev. B | Page 31 of 32 AD5760 Data Sheet NOTES ©2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09650-0-2/12(B) Rev. B | Page 32 of 32