ANALOG DEVICES AD5748

Industrial Current/Voltage Output Driver with Programmable Ranges AD5748 The output current range is programmable across two current FEATURES ranges: 4 mA to 21 mA and 0 mA to 21 mA. Current output ranges: 4 mA to 21 mA, 0 mA to 21 mA ±0.15% FSR total unadjusted error (TUE) Voltage output is provided from a separate pin that can be ±5 ppm/°C FSR typical output drift configured to provide 0 V to 5 V, 0 V to 10.5 V, or ±10.5 V Voltage output ranges: 0 V to 5 V, 0 V to 10.5 V, ±10.5 V output range. ±0.05% FSR total unadjusted error (TUE) Analog outputs are short-circuit and open-circuit protected and ±3 ppm/°C FSR output drift can drive capacitive loads of 2 μF and inductive loads of 0.1 H. Flexible serial digital interface The device is specified to operate with a power supply range from On-chip output fault detection ±12 V to ±24 V. Output loop compliance is 0 V to AVDD − 2.75 V. PEC error checking Asynchronous CLEAR function The flexible serial interface is SPI- and MICROWIRE-compatible Flexible power-up condition to 0 V or tristate and can be operated in 3-wire mode to minimize the digital Power supply range isolation required in isolated applications. The interface also AV : +12 V (± 10%) to +24 V (± 10%) DD features an optional PEC error checking feature using CRC-8 AV : −12 V (± 10%) to −24 V (± 10%) SS error checking, useful in industrial environments where data Output loop compliance to AV − 2.75 V DD communication corruption can occur. Temperature range: −40°C to +105°C The device also includes a power-on-reset function, ensuring 32-lead, 5 mm × 5 mm LFCSP package that the device powers up in a known state (0 V or tristate), and a asynchronous CLEAR pin that sets the outputs to zero APPLICATIONS scale/midscale voltage output or the low end of the selected Process control current range. Actuator control PLCs An HW SELECT pin is used to configure the part for hardware or software mode on power-up. GENERAL DESCRIPTION Note that the plots in the Typical Performance Characteristics The AD5748 is a single-channel, low cost, precision, voltage/ section of this data sheet contain information on the standard current output driver with hardware or software programmable ranges, as released in the AD5750/AD5750-1 data sheet. Although output ranges. The software ranges are configured via an SPI-/ the overranges have been tested, new plots were not generated MICROWIRE™-compatible serial interface. The AD5748 targets and substitution data was used for plotting purposes. applications in PLC and industrial process control. The analog input to the AD5748 is provided from a low voltage, single-supply, Table 1. Related Device digital-to-analog converter (DAC) and is internally conditioned Part Number Description to provide the desired output current/voltage range. The analog AD5422 Single-channel, 16-bit, serial input current input range is 0 V to 4.096 V. source and voltage output DAC Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AD5748 TABLE OF CONTENTS Features .............................................................................................. 1  Reset Function ............................................................................ 25  Applications ....................................................................................... 1 OUTEN ........................................................................................ 25  General Description ......................................................................... 1  Software Control ........................................................................ 25  Revision History ............................................................................... 2  Hardware Control ...................................................................... 27  Functional Block Diagram .............................................................. 3  Transfer Function ....................................................................... 27  Specif ica t ions ..................................................................................... 4  Detailed Description of Features .................................................. 28  Timing Characteristics ................................................................ 7  Output Fault Alert—Software Mode ....................................... 28  Absolute Maximum Ratings ............................................................ 9  Output Fault Alert—Hardware Mode ..................................... 28  ESD Caution .................................................................................. 9  Voltage Output Short-Circuit Protection ................................ 28  Pin Configuration and Function Descriptions ........................... 10  Asynchronous Clear (CLEAR) ................................................. 28  Typical Performance Characteristics ........................................... 12  Current Setting Resistor ............................................................ 29  Voltage Output ............................................................................ 12  Packet Error Checking ............................................................... 29  Current Output ........................................................................... 16  Applications Information .............................................................. 30  Terminology .................................................................................... 21  Transient Voltage Protection .................................................... 30  Theory of Operation ...................................................................... 22  Thermal Considerations ............................................................ 30  Software Mode ............................................................................ 22  Layout Guidelines....................................................................... 30  Current Output Architecture .................................................... 24  Galvanically Isolated Interface ................................................. 31  Driving Inductive Loads ............................................................ 24  Microprocessor Interfacing ....................................................... 31  Power-On State of the AD5748 ................................................ 24  Outline Dimensions ....................................................................... 32  Default Registers at Power-On ................................................. 25  Ordering Guide .......................................................................... 32  REVISION HISTORY 5/10—Rev. 0 to Rev. A Changes to Table 2, Power Requirements ..................................... 6 3/10—Revision 0: Initial Version Rev. A | Page 2 of 32 AD5748 FUNCTIONAL BLOCK DIAGRAM DVCC GND AVDD GND COMP1 COMP2 CLEAR AD5748 CLRSEL VSENSE+ SCLK/OUTEN* INPUT SHIFT REGISTER SDIN/R0* VOUT RANGE VOUT AND SCALING SYNC/RSET* CONTROL LOGIC VOUT SDO/VFAULT* SHORT FAULT HW SELECT STATUS VSENSE– REGISTER AVDD VIN R2 R3 VREF REXT1 RESET REXT2 IOUT IOUT RANGE SCALING R SET OVERTEMP FAULT/TEMP* VOUT SHORT FAULT IOUT OPEN FAULT NC/IFAULT* IOUT POWER- OPEN FAULT ON RESET PEC ERROR AD2/R1* AD1/R2* AD0/R3* AVSS *DENOTES SHARED PIN. SOFTWARE MODE DENOTED BY REGULAR TEXT, HARDWARE MODE DENOTED BYITALIC TEXT. FOR EXAMPLE, FOR FAULT/TEMP PIN, IN SOFTWARE MODE, THIS PIN TAKES ON FAULT FUNCTION. IN HARDWARE MODE, THIS PIN TAKES ONTEMP FUNCTION. Figure 1. Rev. A | Page 3 of 32 08922-001 AD5748 SPECIFICATIONS AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter Min Typ Max Unit Test Conditions/Comments INPUT VOLTAGE RANGE Output unloaded V 0 to 4.096 V IN Input Leakage Current −1 +1 μA REFERENCE INPUT Reference Input Voltage 4.096 V External reference needs to be exactly as stated; otherwise, accuracy errors show up as error in output Input Leakage Current −1 +1 μA VOLTAGE OUTPUT, V OUT Output Voltage Ranges 0 5 V 0 10.5 V AVDD must have minimum 1.3 V headroom −10.5 +10.5 V AVDD/AVSS must have minimum 1.3 V headroom Accuracy 2 Total Unadjusted Error (TUE) −0.3 +0.3 % FSR −0.1 ±0.05 +0.1 % FSR T = 25°C A Relative Accuracy (INL) −0.02 ±0.005 +0.02 % FSR Bipolar Zero Error (Offset at −10 +10 mV ±10.5 V range Midscale) −8 ±0.5 +8 mV TA = 25°C, ±10.5 V range 3 Bipolar Zero Error TC ±1.5 ppm FSR/°C ±10.5 V range Zero-Scale Error −10 +10 mV ±10.5 V range −8 ±0.5 +8 mV TA = 25°C, ±10.5 V range 3 ±1 ppm FSR/°C ±10.5 V range Zero-Scale Error TC Zero-Scale/Offset Error −5 +5 mV 0 V to 10.5 V range −4 ±0.5 +4 mV TA = 25°C, 0 V to 10.5 V range −3 +3 mV 0 V to 5 V range −2.2 ±0.3 +2.2 mV T = 25°C, 0 V to 5 V range A 3 Offset Error TC ±2 ppm FSR/°C Gain Error −0.05 +0.05 % FSR All ranges −0.04 ±0.015 +0.04 % FSR TA = 25°C 3 ±0.5 ppm FSR/°C Gain Error TC Full-Scale Error −0.05 +0.05 % FSR All ranges −0.04 ±0.015 +0.04 % FSR TA = 25°C 3 Full-Scale Error TC ±1.5 ppm FSR/°C 3 VOLTAGE OUTPUT CHARACTERISTICS Headroom 1.3 V Output unloaded Short-Circuit Current 15 mA Load 1 kΩ Capacitive Load Stability T = 25°C A RLOAD = ∞ 1 nF RLOAD = 2 kΩ 1 nF R = ∞ 2 μF External compensation capacitor required; LOAD see the Driving Inductive Loads section DC Output Impedance 0.12 Ω 0 V to 5 V range, ¼ to ¾ Step 7 μs Specified with 2 kΩ || 220 pF, ±0.05% 0 V to 5 V range, 40 mV Input Step 4.5 μs Specified with 2 kΩ || 220 pF, ±0.05% Slew Rate 2 V/μs Specified with 2 kΩ || 220 pF Output Noise 2.5 μV rms 0.1 Hz to 10 Hz bandwidth 45.5 μV rms 100 kHz bandwidth Rev. A | Page 4 of 32 AD5748 1 Parameter Min Typ Max Unit Test Conditions/Comments Output Noise Spectral Density 165 nV/√Hz Measured at 10 kHz; specified with 2 kΩ || 220 pF AC PSRR −65 dB 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage DC PSRR 10 μV/V Outputs unloaded CURRENT OUTPUT, I OUT Output Current Ranges 0 21 mA 4 21 mA 4 Accuracy, Internal R SET 2 Total Unadjusted Error (TUE) −0.5 +0.5 % FSR −0.3 ±0.15 +0.3 % FSR TA = 25°C Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR 4 mA to 21 mA, 0 mA to 21 mA Offset Error −16 +16 μA 4 mA to 21 mA, 0 mA to 21 mA −10 +5 +10 μA TA = 25°C 3 ±3 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA Offset Error TC Gain Error −0.2 +0.2 % FSR 4 mA to 21 mA, 0 mA to 21 mA −0.03 ±0.006 +0.03 % FSR T = 25°C A 3 Gain TC ±8 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA Full-Scale Error −0.2 +0.2 % FSR 4 mA to 21 mA, 0 mA to 21 mA −0.125 ±0.02 +0.125 % FSR TA = 25°C 3 Full-Scale TC ±4 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA 4 Accuracy, External R SET 2 Total Unadjusted Error (TUE) −0.3 +0.3 % FSR −0.1 ±0.02 +0.1 % FSR T = 25°C A Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR 4 mA to 21 mA, 0 mA to 21 mA Offset Error −14 +14 μA 4 mA to 21 mA, 0 mA to 21 mA −11 +5 +11 μA TA = 25°C 3 Offset Error TC ±2 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA Gain Error −0.08 +0.08 % FSR 4 mA to 21 mA, 0 mA to 21 mA −0.07 ±0.02 +0.07 % FSR T = 25°C A Gain TC ±1 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA Full-Scale Error −0.1 +0.1 % FSR 4 mA to 21 mA, 0 mA to 21 mA −0.07 ±0.02 +0.07 % FSR T = 25°C A 3 Full-Scale TC ±2 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA 3 CURRENT OUTPUT CHARACTERISTICS Current Loop Compliance Voltage 0 AVDD − 2.75 V Resistive Load See comments Chosen so that compliance is not exceeded Inductive Load See comments Needs appropriate capacitor at higher inductance values; see the Driving Inductive Loads section Settling Time 4 mA to 21 mA, Full-Scale Step 8.5 μs 250 Ω load 120 μA Step, 4 mA to 21 mA Range 1.2 μs 250 Ω load DC PSRR 1 μA/V Output Impedance 130 MΩ DIGITAL INPUT JEDEC compliant Input High Voltage, VIH 2 V Input Low Voltage, V 0.8 V IL Input Current −1 +1 μA Per pin Pin Capacitance 5 pF Per pin 3 DIGITAL OUTPUTS FAULT, IFAULT, TEMP, VFAULT Output Low Voltage, V 0.4 V 10 kΩ pull-up resistor to DVCC OL Output Low Voltage, VOL 0.6 V At 2.5 mA Output High Voltage, VOH 3.6 V 10 kΩ pull-up resistor to DVCC Rev. A | Page 5 of 32 AD5748 1 Parameter Min Typ Max Unit Test Conditions/Comments SDO Output Low Voltage, V 0.5 0.5 V Sinking 200 μA OL Output High Voltage, VOH DVCC − 0.5 DVCC − 0.5 V Sourcing 200 μA High Impedance Output 3 pF Capacitance High Impedance Leakage Current −1 +1 μA POWER REQUIREMENTS Positive Analog Supply, AV 12 24 V ±10% DD Negative Analog Supply, AVSS −12 −24 V ±10% Digital Power Supply, DV CC Input Voltage 2.7 5.5 V AIDD 4.4 5.6 mA Output unloaded, output disabled, R3, R2, R1, R0 = 0, 1, 0, 1 5.2 6.2 mA Current output enabled 5.2 6.2 mA Voltage output enabled AISS 2.0 2.5 mA Output unloaded, output disabled, R3, R2, R1, R0 = 0, 1, 0, 1 2.5 3 mA Current output enabled 2.5 3 mA Voltage output enabled DI 0.3 1 mA V = DVCC, V = GND CC IH IL Power Dissipation 108 mW AVDD/AVSS = ±24 V, outputs unloaded 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Specification includes gain and offset errors over temperature, and drift after 1000 hours, T = 125°C. A 3 Guaranteed by characterization, but not production tested. 4 See the Current Setting Resistor section. Rev. A | Page 6 of 32 AD5748 TIMING CHARACTERISTICS AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ, CL = 200 pF, IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX, unless otherwise noted. Table 3. 1, 2 Parameter Limit at TMIN, TMAX Unit Description t1 20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time t 5 ns min SYNC falling edge to SCLK falling edge setup time 4 th th t 10 ns min 16 SCLK falling edge to SYNC rising edge (on 24 SCLK falling edge if using PEC) 5 t 5 ns min 6 Minimum SYNC high time (write mode) t7 5 ns min Data setup time t8 5 ns min Data hold time t , t 1.5 μs max CLEAR pulse low/high activation time 9 10 t 5 ns min Minimum SYNC high time (read mode) 11 t 40 ns max SCLK rising edge to SDO valid (SDO C = 15 pF) 12 L t13 10 ns min RESET pulse low time 1 Guaranteed by characterization, but not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. Rev. A | Page 7 of 32 AD5748 Timing Diagrams t 1 SCLK 12 16 t t 3 2 t 6 t t 4 5 SYNC t 8 t 7 SDIN D15 D0 CLEAR t 10 t 9 VOUT RESET t 13 Figure 2. Write Mode Timing Diagram 12 16 SCLK SYNC t 11 A2 A1 A0 R = 1 0 X X X X X X X X X X X SDIN t 12 PEC OVER IOUT VOUT X X X X X R3 R2 R1 R0 CLRSEL OUTEN RSET SDO ERROR TEMP FAULT FAULT Figure 3. Readback Mode Timing Diagram Rev. A | Page 8 of 32 08922-003 08922-002 AD5748 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any AVDD to GND −0.3 V to +30 V other conditions above those indicated in the operational AVSS to GND +0.3 V to −28 V section of this specification is not implied. Exposure to absolute AVDD to AVSS −0.3 V to +58 V maximum rating conditions for extended periods may affect DVCC to GND −0.3 V to +7 V device reliability. VSENSE+ to GND AVSS to AVDD VSENSE− to GND ±5.0 V ESD CAUTION Digital Inputs to GND + 0.3 V or 7 V −0.3 V to DVCC (whichever is less) Digital Outputs to GND −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) VREF to GND −0.3 V to +7 V VIN to GND −0.3 V to +7 V VOUT, IOUT to GND AVSS to AVDD Operating Temperature Range, −40°C to +105°C Industrial Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 125°C J 32-Lead LFCSP Package θJA Thermal Impedance 28°C/W Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 3 kV Rev. A | Page 9 of 32 AD5748 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR SDO/VFAULT 1 24 VSENSE+ CLRSEL 2 23 VOUT CLEAR 3 22 VSENSE– AD5748 DVCC 4 21 AVSS GND 5 TOP VIEW 20 COMP1 (Not to Scale) SYNC/RSET 6 19 COMP2 SCLK/OUTEN 7 18 IOUT SDIN/R0 8 17 AVDD NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE IS TIED TO AVSS. Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 SDO/VFAULT Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin is a CMOS output. Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected to a pull-up resistor. 2 CLRSEL In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In software mode, this pin is implemented as a logic OR with the internal CLRSEL bit. 3 CLEAR Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code of the range selected (user-selectable). CLEAR is a logic OR with the internal clear bit. In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage channel, which can be active 0 V or tristate. See the Asynchronous Clear (CLEAR) section for more details. 4 DVCC Digital Power Supply. 5 GND Ground Connection. 6 SYNC/RSET Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data into the AD5748, also updating the output. Resistor Select (RSET). In hardware mode, this pin chooses whether the internal or the external current sense resistor is used. If RSET = 0, the external sense resistor is chosen. If RSET = 1, the internal sense resistor is chosen. 7 SCLK/OUTEN Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of SCLK. This pin operates at clock speeds of up to 50 MHz. Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin. 8 SDIN/R0 Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK. Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output current/voltage range setting on the part. 9 AD2/R1 Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD1 and AD0, allows up to eight devices to be addressed on one bus. Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output current/voltage range setting on the part. 10 AD1/R2 Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD2 and AD0 allows up to eight devices to be addressed on one bus. Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output current/voltage range setting on the part. Rev. A | Page 10 of 32 08922-004 32 NC/IFAULT AD2/R1 9 AD1/R2 10 31 FAULT/TEMP AD0/R3 11 30 RESET REXT2 12 29 HW SELECT REXT1 13 28 NC VREF 14 27 NC VIN 15 26 NC GND 16 25 NC AD5748 Pin No. Mnemonic Description 11 AD0/R3 Device Addressing Bit (AD0). In software mode, this pin, in conjunction with AD1 and AD2, allows up to eight devices to be addressed on one bus. Range Decode Bit (R3). In hardware mode, this pin, in conjunction with, R0, R1, and R2, selects the output current/voltage range setting on the part. 12, 13 REXT2, REXT1 A 15 kΩ external current setting resistor can be connected between the REXT1 and REXT2 pins to improve the IOUT temperature drift performance. 14 VREF Buffered Reference Input. 15 VIN Buffered Analog Input (0 V to 4.096 V). 16 GND Ground Connection. 17 AVDD Positive Analog Supply Pin. 18 IOUT Current Output Pin. 19, 20 COMP2, Optional Compensation Capacitor Connections for the Voltage Output Buffer. These are used to drive higher COMP1 capacitive loads on the output. These pins also reduce overshoot on the output. Care should be taken when choosing the value of the capacitor connected between the COMP1 and COMP2 pins because it has a direct influence on the settling time of the output. See the Driving Large Capacitive Loads section for further details. 21 AVSS Negative Analog Supply Pin. 22 VSENSE− Sense Connection for the Negative Voltage Output Load Connection. This pin must stay within ±3.0 V of ground for correct operation. 23 VOUT Buffered Analog Output Voltage. 24 VSENSE+ Sense Connection for the Positive Voltage Output Load Connection. 25, 26, NC No Connect. Can be tied to GND. 27, 28 29 HW SELECT This pin is used to configure the part to hardware or software mode. HW SELECT = 0 selects software control. HW SELECT = 1 selects hardware control. 30 RESET Resets the part to its power-on state. 31 FAULT/TEMP Fault Alert (FAULT). In software mode, this pin acts as a general fault alert pin. It is asserted low when an open circuit, short circuit, overtemperature error, or PEC interface error is detected. This pin is an open-drain output and must be connected to a pull-up resistor. Overtemperature Fault (TEMP). In hardware mode, this pin acts as an overtemperature fault pin. It is asserted low when an overtemperature error is detected. This pin is an open-drain output and must be connected to a pull-up resistor. 32 NC/IFAULT No Connect (NC). In software mode, this pin is a no connect. Instead, tie this pin to GND. Open-Circuit Fault Alert (IFAULT). In hardware mode, this pin acts as an open-circuit fault alert pin. It is asserted low when an open-circuit error is detected. This pin is an open-drain output and must be connected to a pull- up resistor. 33 (EPAD) Exposed The exposed paddle is tied to AVSS. paddle Rev. A | Page 11 of 32 AD5748 TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUT 0.0020 0.10 AV = +24V DD AV = –24V SS 0.0015 0.08 0.0010 0.06 0.0005 0.04 0 0.02 –0.0005 0 –0.0010 –0.02 –0.0015 –0.04 +5V POSITIVE TUE, NO LOAD +10V POSITIVE TUE, NO LOAD –0.0020 –0.06 ±10V POSITIVE TUE, NO LOAD +5V +5V NEGATIVE TUE, NO LOAD –0.0025 –0.08 +10V +10V NEGATIVE TUE, NO LOAD ±10V ±10V NEGATIVE TUE, NO LOAD –0.0030 –0.10 04 0.585 1.170 1.755 2.341 2.926 3.511.096 –40 25 105 V (V) TEMPERATURE (°C) IN Figure 8. Total Unadjusted Error vs. Temperature Figure 5. Integral Nonlinearity Error vs. V IN 0.03 0.005 AV = +24V +5V LINEARITY, NO LOAD DD AV = –24V +10V LINEARITY, NO LOAD SS 0.004 0.02 ±10V LINEARITY, NO LOAD 0.003 0.01 0.002 0.001 0 0 –0.01 –0.001 –0.002 –0.02 –0.003 +5V RANGE, FULL-SCALE ERROR –0.03 +10V RANGE, FULL-SCALE ERROR –0.004 ±10V RANGE, FULL-SCALE ERROR –0.04 –0.005 –40 25 105 –40 25 105 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. Full-Scale Error vs. Temperature Figure 6. Integral Nonlinearity Error vs. Temperature 2.5 0.006 AV = +24V DD AV = +24V DD AV = –24V SS AV = –24V 2.0 SS 0.004 1.5 0.002 1.0 ±10V ZERO ERROR 0 0.5 0 –0.002 –0.5 –0.004 +5V –1.0 +10V –0.006 ±10V –1.5 –0.008 –2.0 –2.5 –0.010 –40 25 105 0 0.585 1.170 1.755 2.341 2.926 3.511 4.096 TEMPERATURE (°C) V (V) IN Figure 10. Bipolar Zero Error vs. Temperature Figure 7. Total Unadjusted Error vs. V IN Rev. A | Page 12 of 32 INL (%FSR) TUE (%FSR) INL (%FSR) 08922-007 08922-006 08922-005 BIPOLAR ZERO ERROR (mV) FULL-SCALE ERROR (%FSR) TUE (%FSR) 08922-010 08922-009 08922-008 AD5748 0.020 0.10 AV = +24V +5V POSITIVE TUE, NO LOAD DD AV = –24V +10V POSITIVE TUE, NO LOAD SS 0.08 0.015 ±10V POSITIVE TUE, NO LOAD +5V NEGATIVE TUE, NO LOAD 0.06 0.010 +10V NEGATIVE TUE, NO LOAD 0.04 ±10V NEGATIVE TUE, NO LOAD 0.005 0.02 0 0 –0.005 –0.02 –0.010 –0.04 –0.015 –0.06 +5V GAIN, NO LOAD –0.020 –0.08 +10V GAIN, NO LOAD ±10V GAIN, NO LOAD –0.025 –0.10 +11.2/–10.8 ±15.0 ±24.0 ±26.4 –40 25 105 TEMPERATURE (°C) SUPPLY VOLTAGES (AV /AV ) DD SS Figure 11. Gain Error vs. Temperature Figure 14. Total Unadjusted Error vs. Supply Voltages 2.5 1.2 AV = +24V DD AV = –24V 2.0 SS OUTPUT UNLOADED 1.0 1.5 1.0 0.8 0.5 ±10V AV HEADROOM, LOAD OFF DD 0 0.6 –0.5 –1.0 0.4 –1.5 –2.0 0.2 +5V RANGE +10V RANGE –2.5 ±10V RANGE –3.0 0 –40 25 105 –40 25 105 TEMPERATURE (°C) TEMPERATURE (°C) Figure 12. Zero-Scale Error (Offset Error) vs. Temperature Figure 15. AV Headroom, ±10 V Range, Output Set to 10 V, Load Off DD 0.003 0.05 +5V LINEARITY, NO LOAD +5V RANGE +10V LINEARITY, NO LOAD ±10V RANGE 0.04 ±10V LINEARITY, NO LOAD 0.002 0.03 0.02 0.001 0.01 0 0 –0.01 –0.001 –0.02 –0.03 –0.002 –0.04 –0.003 –0.05 +11.2/–10.8 ±15.0 ±24.0 ±26.4 –15–13–11 –9–7–5–3–1 1 3 5 7 9 11 13 15 SUPPLY VOLTAGES (AV /AV ) DD SS SOURCE/SINK CURRENT (mA) Figure 13. Integral Nonlinearity Error vs. Supply Voltage Figure 16. Source and Sink Capability of Output Amplifier Rev. A | Page 13 of 32 INL (%FSR) ZERO-SCALE ERROR (mV) GAIN ERROR (%FSR) 08922-013 08922-012 08922-011 OUTPUT VOLTAGE DELTA (V) HEADROOM (V) TUE (%FSR) 08922-016 08922-015 08922-014 AD5748 12 10 1 8 6 4 2 2 0 B CH1 5.00V CH2 20.0mV M1.0µs A CH1 3.00V W –8 –3 2 7 12 17 22 27 TIME (µs) Figure 17. Full-Scale Positive Step Figure 20. VOUT Enable Glitch, Load = 2 kΩ || 1 nF 12 10 8 6 4 2 5µV/DIV 1s/DIV 0 –8 –3 2 7 12 17 22 27 TIME (µs) Figure 18. Full-Scale Negative Step Figure 21. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) 40 35 30 25 20 15 10 5 0 100µV/DIV 1s/DIV –5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 TIME (ms) Figure 22. Peak-to-Peak Noise (100 kHz Bandwidth) Figure 19. V vs. Time on Power-Up, Load = 2 kΩ || 200 pF OUT Rev. A | Page 14 of 32 V (mV) OUT VOLTAGE (V) VOLTAGE (V) 08922-018 08922-017 08922-019 08922-022 08922-021 08922-020 AD5748 4.0 1.0 3.5 0.8 3.0 AV DD 0.6 2.5 2.0 0.4 1.5 0.2 1.0 V OUT 0 0.5 0 –0.2 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 TIME (ms) Figure 23. AVDD and VOUT vs. Time on Power-Up Rev. A | Page 15 of 32 AV (V) DD V (V) OUT 08922-023 AD5748 CURRENT OUTPUT 0.004 0.010 +4mA TO +20mA +4mA TO +20mA INTERNAL R LINEARITY SET 0mA TO +20mA 0.008 0mA TO +20mA INTERNAL R LINEARITY SET 0.002 0.006 0 0.004 0.002 –0.002 0 –0.004 –0.002 –0.004 –0.006 –0.006 –0.008 –0.008 AV = +24V DD AV = –24V SS –0.010 –0.010 +11.2/–10.8 ±15.0 ±24.0 ±26.4 0 0.585 1.170 1.755 2.341 2.926 3.511 4.096 V (V) SUPPLY VOLTAGES (AV /AV ) IN DD SS Figure 24. Integral Nonlinearity Error vs. VIN, External RSET Resistor Figure 27. Integral Nonlinearity Error Current Mode, Internal RSET Sense Resistor 0.004 0.010 +4mA TO +20mA AV = +24V DD 0mA TO +20mA AV = –24V SS 0.008 0.002 0.006 0 0.004 –0.002 0.002 –0.004 0 –0.006 –0.002 –0.008 –0.004 –0.010 –0.006 AV = +24V DD +4mA TO +20mA AV = –24V 0mA TO +20mA SS –0.012 –0.008 0 0.585 1.170 1.755 2.341 2.926 3.511 4.096 0 0.585 1.170 1.755 2.341 2.926 3.511 4.096 V (V) V (V) IN IN Figure 25. Integral Nonlinearity Error vs. V , Internal R Resistor Figure 28. Total Unadjusted Error vs. V , External R Resistor IN SET IN SET 0.010 0.015 +4mA TO +20mA EXTERNAL R LINEARITY +4mA TO +20mA AV = +24V SET DD 0mA TO +20mA AV = –24V 0mA TO +20mA EXTERNAL R LINEARITY SS 0.008 SET 0.010 0.006 0.004 0.005 0.002 0 0 –0.002 –0.005 –0.004 –0.006 –0.010 –0.008 –0.010 –0.015 +11.2/–10.8 ±15.0 ±24.0 ±26.4 0 0.585 1.170 1.755 2.341 2.926 3.511 4.096 V (V) SUPPLY VOLTAGES (AV /AV ) DD SS IN Figure 26. Integral Nonlinearity Error, Current Mode, Figure 29. Total Unadjusted Error vs. VIN, Internal RSET Resistor External R Sense Resistor SET Rev. A | Page 16 of 32 INL (%FSR) INL (%FSR) INL (%FSR) 08922-026 08922-025 08922-024 TUE (%FSR) TUE (%FSR) INL (%FSR) 08922-029 08922-028 08922-027 AD5748 0.10 0.010 +4mA TO +20mA EXTERNAL R POSITIVE TUE +4mA TO +20mA EXTERNAL R LINEARITY SET SET 0mA TO +20mA EXTERNAL R LINEARITY 0mA TO +20mA EXTERNAL R POSITIVE TUE 0.08 0.008 SET SET +4mA TO +20mA EXTERNAL R NEGATIVE TUE SET 0.06 0.006 0mA TO +20mA EXTERNAL R NEGATIVE TUE SET 0.04 0.004 0.02 0.002 0 0 –0.02 –0.002 –0.04 –0.004 –0.06 –0.006 –0.08 –0.008 AV = +24V DD AV = –24V SS –0.10 –0.010 +11.2/–10.8 ±15.0 ±24.0 ±26.4 –40 25 105 SUPPLY VOLTAGES (AV /AV ) TEMPERATURE (°C) DD SS Figure 30. Total Unadjusted Error Current Mode, External R Sense Resistor Figure 33. INL vs. Temperature, External R Sense Resistor SET SET 0.10 0.10 +4mA TO +20mA INTERNAL R POSITIVE TUE SET +4mA TO +20mA INTERNAL R POSITIVE TUE SET 0mA TO +20mA INTERNAL R POSITIVE TUE 0.08 SET 0mA TO +20mA INTERNAL R POSITIVE TUE SET 0.08 +4mA TO +20mA INTERNAL R NEGATIVE TUE SET +4mA TO +20mA INTERNAL R NEGATIVE TUE SET 0mA TO +20mA INTERNAL R NEGATIVE TUE SET 0.06 0mA TO +20mA INTERNAL R NEGATIVE TUE SET 0.06 0.04 0.04 0.02 0.02 0 0 –0.02 –0.02 –0.04 –0.04 –0.06 –0.06 –0.08 –0.08 –0.10 –0.10 +11.2/–10.8 ±15.0 ±24.0 ±26.4 –40 25 105 SUPPLY VOLTAGES (AV /AV ) DD SS TEMPERATURE (°C) Figure 31. Total Unadjusted Error Current Mode, Internal RSET Sense Resistor Figure 34. Total Unadjusted Error vs. Temperature, Internal RSET Sense Resistor 0.010 0.10 +4mA TO +20mA EXTERNAL R POSITIVE TUE +4mA TO +20mA INTERNAL R LINEARITY SET SET 0mA TO +20mA EXTERNAL R POSITIVE TUE 0mA TO +20mA INTERNAL R LINEARITY 0.008 SET 0.08 SET +4mA TO +20mA EXTERNAL R NEGATIVE TUE SET 0mA TO +20mA EXTERNAL R NEGATIVE TUE 0.06 SET 0.006 0.04 0.004 0.002 0.02 0 0 –0.02 –0.002 –0.004 –0.04 –0.006 –0.06 –0.08 –0.008 AV = +24V DD AV = –24V SS –0.10 –0.010 –40 25 105 –40 25 105 TEMPERATURE (°C) TEMPERATURE (°C) Figure 32. INL vs. Temperature, Internal R Sense Resistor Figure 35. Total Unadjusted Error vs. Temperature, External RSET Sense Resistor SET Rev. A | Page 17 of 32 INL (%FSR) TUE (%FSR) TUE (%FSR) 08922-032 08922-031 08922-030 TUE (%FSR) INL (%FSR) TUE (%FSR) 08922-035 08922-034 08922-033 AD5748 6 0.04 +4mA TO +20mA EXTERNAL R +4mA TO +20mA INTERNAL R SET SET 0mA TO +20mA EXTERNAL R 0mA TO +20mA INTERNAL R SET SET 0.03 4 0.02 0.01 2 0 0 –0.01 –0.02 –2 –0.03 –0.04 –4 AV = +24V –0.05 DD AV = +24V DD AV = –24V SS AV = –24V SS –6 –0.06 –40 25 105 –40 25 105 TEMPERATURE (°C) TEMPERATURE (°C) Figure 36. Zero-Scale Error vs. Temperature, External RSET Sense Resistor Figure 39. Full-Scale Error vs. Temperature, Internal RSET Sense Resistor 25 0.020 +4mA TO +20mA INTERNAL R +4mA TO +20mA EXTERNAL R SET SET 0mA TO +20mA EXTERNAL R 0mA TO +20mA INTERNAL R SET SET 20 0.015 15 0.010 AV = +24V DD 10 AV = –24V SS 0.005 5 0 0 –5 –0.005 –10 –0.010 –15 ±20mA INTERNAL R AV = +24V SET DD ±24mA INTERNAL R AV = –24V SET SS –20 –0.015 –40 25 105 –40 25 105 TEMPERATURE (°C) TEMPERATURE (°C) Figure 37. Zero-Scale Error vs. Temperature, Internal R Sense Resistor Figure 40. Gain Error vs. Temperature, External R Sense Resistor SET SET 0.04 0.08 +4mA TO +20mA INTERNAL R +4mA TO +20mA EXTERNAL R SET SET 0mA TO +20mA INTERNAL R 0mA TO +20mA EXTERNAL R SET SET 0.06 0.03 0.04 0.02 0.02 0.01 0 0 –0.02 –0.01 –0.04 –0.02 –0.06 –0.03 AV = +24V –0.08 DD AV = +24V DD AV = –24V SS AV = –24V SS –0.04 –0.10 –40 25 105 –40 25 105 TEMPERATURE (°C) TEMPERATURE (°C) Figure 38. Full-Scale Error vs. Temperature, External R Sense Resistor Figure 41. Gain Error vs. Temperature, Internal RSET Sense Resistor SET Rev. A | Page 18 of 32 FULL-SCALE ERROR (%FSR) ZERO-SCALE ERROR (µA) ZERO-SCALE ERROR (µA) 08922-040 08922-037 08922-036 GAIN ERROR (%FSR) GAIN ERROR (%FSR) FULL-SCALE ERROR (%FSR) 08922-043 08922-042 08922-041 AD5748 1.4 0.025 1.2 AV COMPLIANCE DD 0.020 1.0 0.015 0.8 0.6 0.010 0.4 0.005 0.2 0 0 –40 25 105 –12 –6 1 8 14 21 28 34 41 48 54 61 68 TEMPERATURE (°C) TIME (µs) Figure 42. Output Compliance vs. Temperature Figure 45. 4 mA to 20 mA Output Current Step Tested When IOUT = 10.8 mA 12 0.000010 3000 0.000008 10 2500 0.000006 8 0.000004 2000 0.000002 6 DV = 5V CC I OUT 0 1500 4 –0.000002 –0.000004 1000 2 –0.000006 0 500 V –0.000008 DD DV = 3V CC –2 –0.000010 0 –10 –8 –6 –4 –2 0246 8 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TIME (ms) LOGIC LEVEL (V) Figure 46. DI vs. Logic Input Voltage Figure 43. Output Current vs. Time on Power-Up CC 0 –2 –4 –6 –8 –10 –12 –14 –16 –18 –2 –1 0 12 345 67 8 TIME (µs) Figure 44. Output Current vs. Time on Output Enable Rev. A | Page 19 of 32 V (V) DD COMPLIANCE (V) I (V) OUT 08922-046 08922-044 I (A) OUT 08922-045 DI (µA) CURRENT (A) CC 08922-048 08922-047 AD5748 6 6 5 5 AI AI DD DD 4 4 3 3 2 2 1 1 0 0 –1 –1 –2 –2 AI AI SS SS –3 –3 ±10.8 ±15.0 ±24.0 ±26.4 ±10.8 ±15.0 ±24.0 ±26.4 AV /AV (V) AV /AV (V) DD SS DD SS Figure 47. AI /AI vs. AV /AV , V = 0 V Figure 48. AI /AI vs. AV /AV , I = 0 mA DD SS DD SS OUT DD SS DD SS OUT Rev. A | Page 20 of 32 AI /AI (mA) DD SS 08922-049 AI /AI (mA) DD SS 08922-050 AD5748 TERMINOLOGY Zero-Scale Error Total Unadjusted Error (TUE) TUE is a measure of the output error taking all the various Zero-scale error is the deviation of the actual zero-scale analog errors into account: INL error, offset error, gain error, and output from the ideal zero-scale output. Zero-scale error is output drift over supplies, temperature, and time. TUE is expressed in millivolts (mV). expressed as a percentage of full-scale range (% FSR). Zero-Scale TC Relative Accuracy or Integral Nonlinearity (INL) Zero-scale TC is a measure of the change in zero-scale error INL is a measure of the maximum deviation, in % FSR, from a with a change in temperature. Zero-scale error TC is expressed straight line passing through the endpoints of the output driver in ppm FSR/°C. transfer function. A typical INL vs. input voltage plot can be Offset Error seen in Figure 5. Offset error is a measurement of the difference between VOUT Bipolar Zero Error (actual) and VOUT (ideal) expressed in millivolts (mV) in the Bipolar zero error is the deviation of the actual vs. ideal half- linear region of the transfer function. It can be negative or scale output of 0 V/0 mA with a bipolar range selected. A plot positive. of bipolar zero error vs. temperature can be seen in Figure 10. Output Voltage Settling Time Bipolar Zero TC Output voltage settling time is the amount of time it takes for Bipolar zero TC is a measure of the change in the bipolar the output to settle to a specified level for a half-scale input change. zero error with a change in temperature. It is expressed in Slew Rate ppm FSR/°C. The slew rate of a device is a limitation in the rate of change Full-Scale Error of the output voltage. The output slewing speed is usually Full-scale error is the deviation of the actual full-scale analog limited by the slew rate of the amplifier used at its output. output from the ideal full-scale output. Full-scale error is Slew rate is measured from 10% to 90% of the output signal expressed as a percentage of full-scale range (% FSR). and is expressed in V/μs. Full-Scale TC Current Loop Voltage Compliance Full-scale TC is a measure of the change in the full-scale error Current loop voltage compliance is the maximum voltage at with a change in temperature. It is expressed in ppm FSR/°C. the IOUT pin for which the output current is equal to the programmed value. Gain Error Gain error is a measure of the span error of the output. It is the Power-On Glitch Energy deviation in slope of the output transfer characteristic from the Power-on glitch energy is the impulse injected into the analog ideal expressed in % FSR. A plot of gain error vs. temperature output when the AD5748 is powered on. It is specified as the can be seen in Figure 11. area of the glitch in nV-sec. Gain Error TC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output is affected by changes in the Gain error TC is a measure of the change in gain error with changes in temperature. Gain error TC is expressed power supply voltage. in ppm FSR/°C. Rev. A | Page 21 of 32 AD5748 THEORY OF OPERATION The AD5748 is a single-channel, precision, voltage/current Figure 49 and Figure 50 show a typical configuration of the output driver with hardware or software programmable AD5748 in software mode and in hardware mode, respectively, output ranges. The software ranges are configured via an SPI-/ in an output module system. The HW SELECT pin selects MICROWIRE-compatible serial interface. The analog input whether the part is configured in software or hardware mode. to the AD5748 is provided from a low voltage, single-supply, The analog input to the AD5748 is provided from a low voltage, digital-to-analog converter and is internally conditioned to single-supply, digital-to-analog converter (DAC) such as the provide the desired output current/voltage range. The analog AD506x or AD566x, which provides an output range of 0 V input range is 0 V to 4.096 V. to 4.096 V. The supply and reference for the DAC, as well as the reference for the AD5748, can be supplied from a reference The output current range is programmable across two current such as the ADR392. The AD5748 can operate from supplies ranges: 4 mA to 21 mA and 0 mA to 21 mA. up to ±26.4 V. The voltage output is provided from a separate pin that can SOFTWARE MODE be configured to provide 0 V to 5 V, 0 V to 10.5 V, or ±10.5 V output ranges. The current and voltage outputs are available on In current mode, software-selectable output ranges include 0 mA separate pins. Only one output can be enabled at one time. The to 21 mA, and 4 mA to 21 mA. output range is selected by programming the R3 to R0 bits in In voltage mode, software-selectable output ranges include 0 V the control register (see Table 6 and Table 7). to 5 V, 0 V to 10.5 V, and ±10.5 V. VDD AGND VSS ADP1720 AVDD GND AVSS AD5748 VSENSE+ ADR392 VREF VSENSE– VDD REFIN VOUT SCLK VOUT RANGE 0V TO +5V, SCALE SDI/DIN VIN 0V TO +10.5V, AD506x MCU SDO ±10.5V AD566x IOUT SYNC1 RANGE IOUT SCALE 4mA TO 21mA, 0mA TO 21mA SCLK VOUT SHORT FAULT SDIN IOUT OPEN FAULT SERIAL OVERTEMP FAULT SDO INTERFACE PEC ERROR SYNC STATUS REGISTER HW SELECT FAULT Figure 49. Typical System Configuration in Software Mode (Pull-Up Resistors Not Shown for Open-Drain Outputs) Rev. A | Page 22 of 32 08922-051 AD5748 VDD AGND VSS ADP1720 AVDD GND AVSS AD5748 VSENSE+ VREF ADR3192 VSENSE– VDD REFIN VOUT SCLK VOUT RANGE 0V TO +5V, SCALE SDI/DIN 0V TO +10.5V, VIN AD506x SDO ±10.5V AD566x MCU SYNC1 IOUT RANGE IOUT SCALE 4mA TO +21mA, DVCC HW SELECT 0mA TO +21mA OUTEN R3 R2 OUTPUT RANGE SELECT PINS R1 TEMP VFAULT IFAULT R0 Figure 50. Typical System Configuration in Hardware Mode Using Internal DAC Reference (Pull-Up Resistors Not Shown for Open-Drain Outputs) Table 5. Suggested Parts for Use with AD5748 DAC Reference Power Accuracy Description 1 AD5660 Internal ADP1720 12-bit INL Mid end system, single channel, internal reference AD5664R Internal N/A N/A Mid end system, quad channel, internal reference AD5668 Internal N/A N/A Mid end system, octal channel, internal reference AD5060 ADR434 ADP1720 16-bit INL High end system, single channel, external reference AD5064 ADR434 N/A N/A High end system, quad channel, external reference 2 2 AD5662 ADR392 ADR392 12-bit INL Mid end system, single channel, external reference 2 AD5664 ADR392 N/A N/A Mid end system, quad channel, external reference 1 ADP1720 input range up to 28 V. 2 ADR392 input range up to 15 V. Rev. A | Page 23 of 32 08922-052 AD5748 CURRENT OUTPUT ARCHITECTURE Driving Large Capacitive Loads The voltage input from the analog input VIN pin (0 V to 4.096 V) The voltage output amplifier is capable of driving capacitive loads is either converted to a current (see Figure 51), which is then of up to 1 μF with the addition of a nonpolarized compensation mirrored to the supply rail so that the application simply sees capacitor between the COMP1 and COMP2 pins. a current source output with respect to an internal reference Without the compensation capacitor, up to 20 nF capacitive loads voltage, or buffered and scaled to output a software-selectable can be driven. Care should be taken to choose an appropriate unipolar or bipolar voltage range (see Figure 52). The reference value for the CCOMP capacitor. This capacitor, while allowing the is used to provide internal offsets for range and gain scaling. AD5748 to drive higher capacitive loads and reduce overshoot, The selectable output range is programmable through the increases the settling time of the part and, therefore, affects the digital interface. bandwidth of the system. Considered values of this capacitor AVDD should be in the range 100 pF to 4 nF depending on the trade- off required between settling time, overshoot, and bandwidth. RANGEDECODE R2 R3 FROM INTERFACE POWER-ON STATE OF THE AD5748 T2 A2 On power-up, the AD5748 senses whether hardware or T1 VIN IOUT A1 RANGE IOUT software mode is loaded and sets the power-up conditions SCALING VREF accordingly. RSET In software SPI mode, the power-up state of the output is depen- dent on the state of the CLEAR pin. If the CLEAR pin is pulled Figure 51. Current Output Configuration high, then the part powers up, driving an active 0 V on the RANGE DECODE FROM INTERFACE output. If the CLEAR pin is pulled low, then the part powers up VSENSE+ with the voltage output channel in tristate mode. In both cases, the VIN (0V TO 4.096V) VOUT RANGE current output channel powers up in a tristate condition (0 mA). VOUT SCALING VREF This allows the voltage and current outputs to be connected VOUT SHORT FAULT together if desired. VSENSE– To put the part into normal operation, the user must set the Figure 52. Voltage Output OUTEN bit in the control register to enable the output and, in the same write, set the output range configuration using the R3 DRIVING INDUCTIVE LOADS to R0 range bits. If the CLEAR pin is still high (active) during When driving inductive or poorly defined loads, connect a 0.01 μF this write, the part automatically clears to its normal clear state capacitor between IOUT and GND. This ensures stability with as defined by the programmed range and by the CLRSEL pin or loads beyond 50 mH. There is no maximum capacitance limit. CLRSEL bit (see the Asynchronous Clear (CLEAR) section for The capacitive component of the load may cause slower settling. more details). The CLEAR pin must be taken low to operate the Voltage Output Amplifier part in normal mode. The voltage output amplifier is capable of generating both The CLEAR pin is typically driven directly from a microcontroller. unipolar and bipolar output voltages. It is capable of driving a In cases where the power supply for the AD5748 supply may be load of 1 kΩ in parallel with 1.2 μF (with an external compensa- independent of the microcontroller power supply, the user can tion capacitor on the COMP1 and COMP2 pins). The source connect a weak pull-up resistor to DVCC or a pull-down resistor and sink capabilities of the output amplifier can be seen in to ground to ensure that the correct power-up condition is Figure 16. The slew rate is 2 V/μs. achieved independent of the microcontroller. A 10 kΩ pull- up/pull-down resistor on the CLEAR pin should be sufficient Internal to the device, there is a 2.5 MΩ resistor connected for most applications. between the VOUT and VSENSE+ pins and similarly between the VSENSE− pin and the internal device ground. Should a If hardware mode is selected, the part powers up to the condi- fault condition occur, these resistors act to protect the AD5748 tions defined by the R3 to R0 range bits and the status of the by ensuring that the amplifier loop is closed so that the part OUTEN or CLEAR pin. It is recommended to keep the output does not enter into an open-loop condition. disabled when powering up the part in hardware mode. The VSENSE− pin can work in a common-mode range of ±3 V with respect to the remote load ground point. The current and voltage are output on separate pins and cannot be output simultaneously. This allows the user to tie both the current and voltage output pins together and configure the end system as a single-channel output. Rev. A | Page 24 of 32 08922-054 08922-059 AD5748 disabled, both the current and voltage channels go into tristate. DEFAULT REGISTERS AT POWER-ON The user must set the OUTEN bit to enable the output and The AD5748 power-on reset circuit ensures that all registers are simultaneously set the output range configuration. loaded with zero code. In hardware mode, the output can be enabled or disabled using In software SPI mode, the part powers up with all outputs dis- the OUTEN pin. When the output is disabled, both the current abled (OUTEN bit = 0). The user must set the OUTEN bit in and voltage channels both go into tristate. The user must write the control register to enable the output and, in the same write, to the OUTEN pin to enable the output. It is recommended set the output range configuration using the R3 to R0 bits. that the output be disabled when changing the ranges. If hardware mode is selected, the part powers up to the SOFTWARE CONTROL conditions defined by the R3 to R0 bits and the status of the OUTEN pin. It is recommended to keep the output disabled Software control is enabled by connecting the HW SELECT pin when powering up the part in hardware mode. to ground. In software mode, the AD5748 is controlled over a versatile 3-wire serial interface that operates at clock rates of up RESET FUNCTION to 50 MHz. It is compatible with SPI, QSPI™, MICROWIRE, In software mode, the part can be reset using the RESET pin and DSP standards. (active low) or the reset bit (reset = 1). A reset disables both the Input Shift Register current and voltage outputs to their power-on condition. The The input shift register is 16 bits wide. Data is loaded into the user must write to the OUTEN bit to enable the output and, in device MSB first as a 16-bit word under the control of a serial RESET the same write, set the output range configuration. The clock input, SCLK. Data is clocked in on the falling edge of pin is a level-sensitive input; the part stays in reset mode as long SCLK. The input shift register consists of 16 control bits, as RESET as the pin is low. The reset bit clears to 0 following a shown in Table 6. The timing diagram for this write operation reset command to the control register. is shown in Figure 2. The first three bits of the input shift register In hardware mode, there is no reset. If using the part in hardware are used to set the hardware address of the AD5748 device on mode, the RESET pin should be tied high. the printed circuit board (PCB). Up to eight devices can be addressed per board. OUTEN Bit D11, Bit D1, and Bit D0 must always be set to 0 during any In software mode, the output can be enabled or disabled using write sequence. the OUTEN bit in the control register. When the output is Table 6. Input Shift Register Contents for a Write Operation—Control Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 R/W 0 R3 R2 R1 R0 CLRSEL OUTEN Clear RSET Reset 0 0 Table 7. Input Shift Register Descriptions Bit Description A2, A1, A0 Used in association with the AD2, AD1, and AD0 external pins to determine which part is being addressed by the system controller A2 A1 A0 Function 0 0 0 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 0 0 0 1 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 1 0 1 0 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 0 0 1 1 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 1 1 0 0 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 0 1 0 1 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 1 1 1 0 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 0 1 1 1 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 1 R/W Indicates a read from or a write to the addressed register Rev. A | Page 25 of 32 AD5748 Bit Description R3, R2, R1, R0 Selects output configuration in conjunction with RSET RSET R3 R2 R1 R0 Output Configuration 0 0 0 0 0 4 mA to 21 mA (external 15 kΩ current sense resistor) 0 0 0 0 1 0 mA to 21 mA (external 15 kΩ current sense resistor) 0 0 0 1 0 N/A 0 0 0 1 1 N/A 0 0 1 0 0 N/A 0 0 1 0 1 0 V to 5 V 0 0 1 1 0 N/A 0 0 1 1 1 N/A 0 1 0 0 0 N/A 0 1 0 0 1 N/A 0 1 0 1 0 0 V to 10.5 V 0 1 0 1 1 N/A 0 1 1 0 0 ±10.5 V 0 1 1 0 1 N/A 0 1 1 1 0 N/A 0 1 1 1 1 N/A 1 0 0 0 0 4 mA to 21 mA (internal current sense resistor) 1 0 0 0 1 0 mA to 21 mA (internal current sense resistor) 1 0 0 1 0 N/A 1 0 0 1 1 N/A 1 0 1 0 0 N/A 1 0 1 0 1 0 V to 5 V 1 0 1 1 0 N/A 1 0 1 1 1 N/A 1 1 0 0 0 N/A 1 1 0 0 1 N/A 1 1 0 1 0 0 V to 10.5 V 1 1 0 1 1 N/A 1 1 1 0 0 ±10.5 V 1 1 1 0 1 N/A 1 1 1 1 0 N/A 1 1 1 1 1 N/A CLRSEL Sets clear mode to zero scale or midscale. See the Asynchronous Clear (CLEAR) section CLRSEL Function 0 Clear to 0 V 1 Clear to midscale in unipolar mode; clear to zero scale in bipolar mode OUTEN Output enable bit. This bit must be set to 1 to enable the outputs Clear Software clear bit, active high RSET Select internal/external current sense resistor RSET Function 1 Select internal current sense resistor; used with the R3 to R0 bits to select range 0 Select external current sense resistor; used with the R3 to R0 bits to select range Reset Resets the part to its power-on state Rev. A | Page 26 of 32 AD5748 Readback Operation In hardware mode, there is no status register. The fault condi- tions (open circuit, short circuit, and overtemperature) are Readback mode is activated by selecting the correct device address available on Pin IFAULT, Pin VFAULT, and Pin TEMP. If any (A2, A1, A0) and then setting the R/W bit to 1. By default, the one of these fault conditions is set, then a low is asserted on the SDO pin is disabled. After having addressed the AD5748 for a specific fault pin. IFAULT, VFAULT, and TEMP are open-drain W to 1 enables the SDO pin and SDO read operation, setting R/ outputs and, therefore, can be connected together to allow the th data is clocked out on the 5 rising edge of SCLK. After the data user to generate one interrupt to the system controller to commu- SYNC has been clocked out on SDO, a rising edge on disables nicate a fault. If hardwired in this way, it is not possible to (tristate) the SDO pin again. Status register data (see Table 8) isolate which fault occurred in the system. and control register data are both available during the same TRANSFER FUNCTION read cycle. The AD5748 consists of an internal signal conditioning block The status bits comprise four read-only bits. They are used to that maps the analog input voltage to a programmed output notify the user of specific fault conditions that occur, such as range. The available analog input range is 0 V to 4.096 V. an open circuit or short circuit on the output, overtemperature error, or an interface error. If any of these fault conditions occurs, For all ranges, both current and voltage, the AD5748 imple- a hardware FAULT is also asserted low, which can be used as a ments a straight linear mapping function. 0 V maps to the hardware interrupt to the controller. lower end of the selected range; 4.096 V maps to the upper end of the selected range. See the Detailed Description of Features section for a full explanation of fault conditions. HARDWARE CONTROL Hardware control is enabled by connecting the HW SELECT pin to DVCC. In this mode, the R3, R2, R1, and R0 pins in conjunction with the RSET pin are used to configure the output range, as per Table 7. Table 8. Input Shift Register Contents for a Read Operation—Status Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1 0 R3 R2 R1 R0 CLRSEL OUTEN RSET PEC error OVER TEMP IOUT fault VOUT fault Table 9. Status Bit Options Bit Description PEC Error This bit is set if there is an interface error detected by CRC-8 error checking. See the Detailed Description of Features section. VOUT Fault This bit is set if there is a short circuit on the VOUT pin. IOUT Fault This bit is set is there is an open circuit on the IOUT pin. OVER TEMP This bit is set if the AD5748 core temperature exceeds approximately 150°C. Rev. A | Page 27 of 32 AD5748 DETAILED DESCRIPTION OF FEATURES output stage has less than approximately 1 V of remaining OUTPUT FAULT ALERT—SOFTWARE MODE drive capability. Thus, the fault output activates slightly In software mode, the AD5748 is equipped with one FAULT before the compliance limit is reached. Because the compari- pin; this is an open-drain output allowing several AD5748 son is made within the feedback loop of the output amplifier, devices to be connected together to one pull-up resistor for the output accuracy is maintained by its open-loop gain, global fault detection. In software mode, the FAULT pin is and an output error does not occur before the fault output forced active low by any one of the following fault scenarios: becomes active. If this fault is detected, the IFAULT pin is forced low. • The voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power • A short is detected on the voltage output pin (VOUT). supply voltage. The internal circuitry that develops the The short-circuit current is limited to 15 mA. If this fault fault output avoids using a comparator with window limits is detected, the VFAULT pin is forced low. because this requires an actual output error before the fault • If the core temperature of the AD5748 exceeds approx- output becomes active. Instead, the signal is generated when imately 150°C. If this fault is detected, the TEMP pin is the internal amplifier in the output stage has less than forced low. approximately 1 V of remaining drive capability. Thus, VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION the fault output activates slightly before the compliance limit is reached. Because the comparison is made within Under normal operation, the voltage output sinks and sources the feedback loop of the output amplifier, the output up to 12 mA and maintains the specified operation. The maxi- accuracy is maintained by its open-loop gain, and an output mum current that the voltage output delivers is 15 mA; this is error does not occur before the fault output becomes active. the short-circuit current. • A short is detected on the voltage output pin (VOUT). The ASYNCHRONOUS CLEAR (CLEAR) short-circuit current is limited to 15 mA. CLEAR is an active high clear that allows the voltage output • An interface error is detected due to a packet error to be cleared to either zero-scale code or midscale code and is checking (PEC) failure. See the Packet Error Checking user-selectable via the CLRSEL pin or the CLRSEL bit of the section. input shift register, as described in Table 7. (The clear select • If the core temperature of the AD5748 exceeds feature is a logical OR function of the CLRSEL pin and the approximately 150°C. CLRSEL bit.) The current loop output clears to the bottom of its programmed range. When the CLEAR signal is returned OUTPUT FAULT ALERT—HARDWARE MODE low, the output returns to its programmed value or a new value In hardware mode, the AD5748 is equipped with three fault if programmed. A clear operation can also be performed via the pins: VFAULT, IFAULT, and TEMP. These are open-drain clear command in the control register. outputs allowing several AD5748 devices to be connected together to one pull-up resistor for global fault detection. In Table 10. CLRSEL Options hardware control mode, these fault pins are forced active by Output Clear Value any one of the following fault scenarios: Unipolar Output CLRSEL Voltage Range Unipolar Current Output Range • Open-circuit detect. The voltage at IOUT attempts to rise 0 0 V Zero scale; for example: above the compliance range, due to an open-loop circuit 4 mA on the 4 mA to 21 mA range or insufficient power supply voltage. The internal circuitry 0 mA on the 0 mA to 21 mA range that develops the fault output avoids using a comparator 1 Midscale Midscale; for example: with window limits because this requires an actual output 12.5 mA on the 4 mA to 21 mA range 10.5 mA on the 0 mA to 21 mA range error before the fault output becomes active. Instead, the signal is generated when the internal amplifier in the Rev. A | Page 28 of 32 AD5748 CURRENT SETTING RESISTOR PACKET ERROR CHECKING Referring to Figure 1, RSET is an internal sense resistor as part of To verify that data has been received correctly in noisy environ- the voltage-to-current conversion circuitry. The nominal value ments, the AD5748 offers the option of error checking based on of the internal current sense resistor is 15 kΩ. To allow for over- an 8-bit (CRC-8) cyclic redundancy check. The device controlling range capability in current mode, the user can also select the the AD5748 should generate an 8-bit frame check sequence internal current sense resistor to be 14.7 kΩ, giving a nominal using the following polynomial: 2% overrange capability. This feature is available in the 0 mA C(x) = x + x + x + 1 8 2 1 to 21 mA and 4 mA to 21 mA current ranges. This is added to the end of the data-word, and 24 data bits are The stability of the output current value over temperature is sent to the AD5748 before taking SYNC high. If the AD5748 dependent on the stability of the value of RSET. As a method of receives a 24-bit data frame, it performs the error check when improving the stability of the output current over temperature, SYNC goes high. If the check is valid, then the data is written an external low drift resistor can be connected to the REXT1 to the selected register. If the error check fails, the FAULT pin and REXT2 pins of the AD5748, which can be used instead of goes low and Bit D3 of the status register is set. After reading the internal resistor. The external resistor is selected via the this register, this error flag is cleared automatically and the input shift register. If the external resistor option is not used, FAULT pin goes high again. the REXT1 and REXT2 pins should be left floating. UPDATE ON SYNC HIGH SYNC SCLK D15 D0 (MSB) (LSB) 16-BIT DATA SDIN 16-BIT DATA TRANSER—NO ERROR CHECKING UPDATE AFTER SYNC HIGH ONLY IF ERROR CHECK PASSED SYNC SCLK D23 D8 (MSB) (LSB) D7 D0 SDIN 16-BIT DATA 8-BIT FCS FAULT GOES LOW IF FAULT ERROR CHECK FAILS 16-BIT DATA TRANSER WITH ERROR CHECKING Figure 53. PEC Error Checking Timing Rev. A | Page 29 of 32 08922-055 AD5748 APPLICATIONS INFORMATION LAYOUT GUIDELINES TRANSIENT VOLTAGE PROTECTION In any circuit where accuracy is important, careful consideration The AD5748 contains ESD protection diodes that prevent damage of the power supply and ground return layout helps to ensure from normal handling. The industrial control environment can, the rated performance. The PCB on which the AD5748 is however, subject I/O circuits to much higher transients. To protect mounted should be designed so that the AD5748 lies on the the AD5748 from excessively high voltage transients, external analog plane. power diodes and a surge current limiting resistor may be required, as shown in Figure 54. The constraint on the resistor The AD5748 should have ample supply bypassing of 10 μF value is that, during normal operation, the output level at IOUT in parallel with 0.1 μF on each supply located as close to the must remain within its voltage compliance limit of AV − 2.75 V, DD package as possible, ideally right up against the device. The and the two protection diodes and resistor must have appropri- 10 μF capacitors are the tantalum bead type. The 0.1 μF capaci- ate power ratings. Further protection can be added with transient tor should have low effective series resistance (ESR) and low voltage suppressors if needed. effective series inductance (ESI) such as the common ceramic AVDD types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. AVDD In systems where there are many devices on one board, it is often AD5748 R P IOUT useful to provide some heat sinking capability to allow the power R LOAD to dissipate easily. AD5748 AVSS Figure 54. Output Transient Voltage Protection THERMAL CONSIDERATIONS It is important to understand the effects of power dissipation on the package and on junction temperature. The internal junction temperature should not exceed 125°C. The AD5748 is packaged AVSS PLANE in a 32-lead LFCSP 5, 5 mm × 5 mm package. The thermal impedance, θJA, is 28°C/W. It is important that the devices are BOARD not operated under conditions that cause the junction tempera- ture to exceed its junction temperature. Figure 55. Paddle Connection to Board Worst-case conditions occur when the AD5748 is operated from The AD5748 has an exposed paddle beneath the device. This the maximum AV (26.4 V) while driving the maximum DD paddle is connected to the AVSS supply for the part. For opti- current (24 mA) directly to ground. The quiescent current of the mum performance, special considerations should be used to AD5748 should also be taken into account, nominally ~4 mA. design the motherboard and to mount the package. For enhanced The following calculations estimate maximum power dissipation thermal, electrical, and board level performance, the exposed under these worst-case conditions, and determine maximum paddle on the bottom of the package is soldered to the correspond- ambient temperature based on the power dissipation: ing thermal land paddle on the PCB. Thermal vias are designed Power Dissipation = 26.4 V × 28 mA = 0.7392 W into the PCB land paddle area to further improve heat dissipation. Temp Increase = 28°C × 0.7392 W = 20.7°C The AVSS plane on the device can be increased (as shown in Figure 55) to provide a natural heat sinking effect. Maximum Ambient Temp = 125°C − 20.7°C = 104.3°C These figures assume that proper layout and grounding techniques are followed to minimize power dissipation, as outlined in the Layout Guidelines section. Rev. A | Page 30 of 32 08922-056 08922-057 AD5748 GALVANICALLY ISOLATED INTERFACE MICROPROCESSOR INTERFACING In many process control applications, it is necessary to provide Microprocessor interfacing to the AD5748 is via a serial bus an isolation barrier between the controller and the unit being that uses a protocol compatible with microcontrollers and DSP controlled to protect and isolate the controlling circuitry from processors. The communications channel is a 3-wire (minimum) any hazardous common-mode voltages that may occur. The SYNC interface consisting of a clock signal, a data signal, and a iCoupler® family of products from Analog Devices, Inc., provides signal. The AD5748 requires a 16-bit data-word with data valid voltage isolation in excess of 5.0 kV. The serial loading structure on the falling edge of SCLK. of the AD5748 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 56 shows a 4-channel isolated interface using an ADuM1400. For further information, visit www.analog.com/icouplers. 1 CONTROLLER ADuM1400 V V OA IA TO SERIAL SCLK CLOCK OUT V V IB OB TO SERIAL SDIN DATA OUT V V OC IC TO SYNC OUT SYNC V V OD ID TO CONTROL OUT CLEAR 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 56. Isolated Interface Rev. A | Page 31 of 32 ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE 08922-058 AD5748 OUTLINE DIMENSIONS 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 BSC TOP EXPOSED 3.25 4.75 VIEW BSC SQ PAD 3.10 SQ (BOTTOM VIEW) 2.95 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 1.00 0.02 NOM THE PIN CONFIGURATION AND 0.85 0.30 FUNCTION DESCRIPTIONS COPLANARITY 0.20 REF SECTION OF THIS DATA SHEET. 0.80 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Analog Input External Temperature Package 1 Model TUE Accuracy Range Reference Range Package Description Option AD5748ACPZ ±0.3% V , ±0.5% I 0 V to 4.096 V 4.096 V −40°C to +105°C 32-Lead LFCSP_VQ CP-32-2 OUT OUT AD5748ACPZ-RL7 ±0.3% V , ±0.5% I 0 V to 4.096 V 4.096 V −40°C to +105°C 32-Lead LFCSP_VQ CP-32-2 OUT OUT 1 Z = RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08922-0-5/10(A) Rev. A | Page 32 of 32 011708-A