ANALOG DEVICES AD5732

Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs AD5722/AD5732/AD5752 FEATURES GENERAL DESCRIPTION Complete, dual, 12-/14-/16-bit digital-to-analog converter (DAC) The AD5722/AD5732/AD5752 are dual, 12-/14-/16-bit, serial Operates from single/dual supplies input, voltage output, digital-to-analog converters. They operate Software programmable output range from single-supply voltages from +4.5 V up to +16.5 V or dual- +5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V supply voltages from ±4.5 V up to ±16.5 V. Nominal full-scale INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum output range is software-selectable from +5 V, +10 V, +10.8 V, Total unadjusted error (TUE): 0.1% FSR maximum ±5 V, ±10 V, or ±10.8 V. Integrated output amplifiers, reference Settling time: 10 μs typical buffers, and proprietary power-up/power-down control circuitry Integrated reference buffers are also provided. Output control during power-up/brownout The parts offer guaranteed monotonicity, integral nonlinearity Simultaneous updating via LDAC (INL) of ±16 LSB maximum, low noise, and 10 μs typical Asynchronous CLR to zero scale or midscale settling time. DSP-/microcontroller-compatible serial interface The AD5722/AD5732/AD5752 use a serial interface that 24-lead TSSOP operates at clock rates up to 30 MHz and are compatible with Operating temperature range: −40°C to +85°C 1 DSP and microcontroller interface standards. Double buffering iCMOS process technology allows the simultaneous updating of all DACs. The input coding APPLICATIONS is user-selectable twos complement or offset binary for a bipolar Industrial automation 2sComp output (depending on the state of Pin BIN/ ), and Closed-loop servo control, process control straight binary for a unipolar output. The asynchronous clear Automotive test and measurement function clears all DAC registers to a user-selectable zero-scale Programmable logic controllers or midscale output. The parts are available in a 24-lead TSSOP and offer guaranteed specifications over the −40°C to +85°C industrial temperature range. The AD5722/AD5732/AD5752 are pin compatible with the AD5724/AD5734/AD5754, which are complete, quad, 12-/14-/ 16-bit, serial input, unipolar/bipolar voltage output DACs. FUNCTIONAL BLOCK DIAGRAM AV AV SS DD REFIN DV CC AD5722/AD5732/AD5752 REFERENCE BUFFERS CLR BIN/2sCOMP 12/14/16 12/14/16 INPUT DAC DAC A SDIN V A REGISTER A REGISTER A OUT INPUT SHIFT REGISTER SCLK AND CONTROL 12/14/16 SYNC INPUT DAC LOGIC DAC B REGISTER B REGISTER B V B OUT SDO GND LDAC DAC_GND (2) SIG_GND (2) Figure 1. 1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS® is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, as well as increased ac and dc performance. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06467-001 AD5722/AD5732/AD5752 TABLE OF CONTENTS Features .............................................................................................. 1 Transfer Function....................................................................... 20 Applications....................................................................................... 1 Input Shift Register .................................................................... 24 General Description ......................................................................... 1 DAC Register .............................................................................. 25 Functional Block Diagram .............................................................. 1 Output Range Select Register ................................................... 25 Revision History ............................................................................... 2 Control Register ......................................................................... 26 Specifications..................................................................................... 3 Power Control Register ............................................................. 26 AC Performance Characteristics ................................................ 5 Design Features............................................................................... 27 Timing Characteristics ................................................................ 5 Analog Output Control ............................................................. 27 Timing Diagrams.......................................................................... 6 Power-Down Mode.................................................................... 27 Absolute Maximum Ratings............................................................ 8 Overcurrent Protection ............................................................. 27 ESD Caution.................................................................................. 8 Thermal Shutdown .................................................................... 27 Pin Configuration and Function Descriptions............................. 9 Applications Information .............................................................. 28 Typical Performance Characteristics ........................................... 10 +5 V/±5 V Operation ................................................................ 28 Terminology .................................................................................... 16 Layout Guidelines....................................................................... 28 Theory of Operation ...................................................................... 18 Galvanically Isolated Interface ................................................. 28 Architecture................................................................................. 18 Voltage Reference Selection ...................................................... 28 Serial Interface ............................................................................ 18 Microprocessor Interfacing....................................................... 29 Load DAC (LDAC)..................................................................... 20 Outline Dimensions....................................................................... 30 Ordering Guide .......................................................................... 30 Asynchronous Clear (CLR)....................................................... 20 Configuring the AD5722/AD5732/AD5752 .......................... 20 REVISION HISTORY 7/11—Rev. C to Rev. D Changes to Table 3: t7, t8, t10 Limits......................................................5 3/11—Rev. B to Rev. C Changes to Configuring the AD5722/AD5732/AD5752 Section..20 8/10—Rev. A to Rev. B Changes to Table 27........................................................................ 26 5/10—Rev. 0 to Rev. A Changes to Junction Temperature, T max Parameter, Table 4 .. 8 J Changes to Exposed Paddle Description, Table 5........................ 9 Changes to Ordering Guide .......................................................... 30 10/08—Revision 0: Initial Version Rev. D | Page 2 of 32 AD5722/AD5732/AD5752 SPECIFICATIONS 1 1 AVDD = 4.5 V to 16.5 V; AVSS = −4.5 V to −16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ; CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution AD5752 16 Bits AD5732 14 Bits AD5722 12 Bits Total Unadjusted Error (TUE) B Version −0.1 +0.1 % FSR A Version −0.3 +0.3 % FSR 2 Integral Nonlinearity (INL) AD5752 A, B Versions −16 +16 LSB AD5732 A Version −4 +4 LSB AD5722 A Version −1 +1 LSB Differential Nonlinearity (DNL) −1 +1 LSB All models, all versions, guaranteed monotonic Bipolar Zero Error −6 +6 mV TA = 25°C, error at other temperatures obtained using bipolar zero TC 3 Bipolar Zero TC ±4 ppm FSR/°C Zero-Scale Error −6 +6 mV T = 25°C, error at other temperatures obtained using A zero-scale TC 3 Zero-Scale TC ±4 ppm FSR/°C Offset Error −6 +6 mV TA = 25°C, error at other temperatures obtained using zero-scale TC Offset Error TC ±4 ppm FSR/°C Gain Error −0.025 +0.025 % FSR ±10 V range, T = 25°C, error at other temperatures A obtained using gain TC 3 Gain Error −0.065 0 +10 V and +5 V ranges, TA = 25°C, error at other temperatures obtained using gain TC 3 Gain Error 0 +0.08 ±5 V range, T = 25°C, error at other temperatures A obtained using gain TC 3 Gain TC ±4 ppm FSR/°C 3 DC Crosstalk 120 μV 3 REFERENCE INPUT Reference Input Voltage 2.5 V ±1% for specified performance DC Input Impedance 1 5 MΩ Input Current −2 ±0.5 +2 μA Reference Range 2 3 V 3 OUTPUT CHARACTERISTICS Output Voltage Range −10.8 +10.8 V AVDD/AVSS = ±11.7 V min, REFIN = +2.5 V −12 +12 V AVDD/AVSS = ±12.9 V min, REFIN = +3 V Headroom Required 0.5 0.9 V Output Voltage TC ±4 ppm FSR/°C Output Voltage Drift vs. Time ±50 ppm FSR Drift after 1000 hours of lifetest @ 125°C Short-Circuit Current 20 mA Load 2 kΩ For specified performance Capacitive Load Stability 4000 pF DC Output Impedance 0.5 Ω Rev. D | Page 3 of 32 AD5722/AD5732/AD5752 Parameter Min Typ Max Unit Test Conditions/Comments 3 DIGITAL INPUTS DVCC = 2.7 V to 5.5 V, JEDEC compliant Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current ±1 μA Per pin Pin Capacitance 5 pF Per pin 3 DIGITAL OUTPUTS (SDO) Output Low Voltage, V 0.4 V DV = 5 V ± 10%, sinking 200 μA OL CC Output High Voltage, V DV − 1 V DV = 5 V ± 10%, sourcing 200 μA OH CC CC Output Low Voltage, VOL 0.4 V DVCC = 2.7 V to 3.6 V, sinking 200 μA Output High Voltage, VOH DVCC − 0.5 V DVCC = 2.7 V to 3.6 V, sourcing 200 μA High Impedance Leakage −1 +1 μA Current High Impedance Output 5 pF Capacitance POWER REQUIREMENTS AV 4.5 16.5 V DD AV −4.5 −16.5 V SS DVCC 2.7 5.5 V 3 Power Supply Sensitivity ∆VOUT/∆ΑVDD −65 dB AI 3.25 mA/channel Outputs unloaded DD 2.4 mA/channel AV = 0 V, outputs unloaded SS AI 2.5 mA/channel Outputs unloaded SS DICC 0.5 3 μA VIH = DVCC, VIL = GND Power Dissipation 190 mW ±16.5 V operation, outputs unloaded 79 mW 16.5 V operation, AV = 0 V, outputs unloaded SS Power-Down Currents AI 40 μA DD AISS 40 μA DICC 300 nA 1 For specified performance, the maximum headroom requirement is 0.9 V. 2 INL is the relative accuracy. It is measured from Code 512, Code 128, and Code 32 for the AD5752, the AD5732, and the AD5722, respectively. 3 Guaranteed by characterization; not production tested. Rev. D | Page 4 of 32 AD5722/AD5732/AD5752 AC PERFORMANCE CHARACTERISTICS 1 AVDD = 4.5 V to 16.5 V; AVSS = −4.5 V to −16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ; CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 2 Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 10 12 μs 20 V step to ±0.03% FSR 7.5 8.5 μs 10 V step to ±0.03% FSR 5 μs 512 LSB step settling (16-bit resolution) Slew Rate 3.5 V/μs Digital-to-Analog Glitch Energy 13 nV-sec Glitch Impulse Peak Amplitude 35 mV Digital Crosstalk 10 nV-sec DAC-to-DAC Crosstalk 10 nV-sec Digital Feedthrough 0.6 nV-sec Output Noise 0.1 Hz to 10 Hz Bandwidth 15 μV p-p 0x8000 DAC code 100 kHz Bandwidth 80 μV rms Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code 1 For specified performance, the maximum headroom requirement is 0.9 V. 2 Guaranteed by design and characterization; not production tested. TIMING CHARACTERISTICS AVDD = 4.5 V to 16.5 V; AVSS = −4.5 V to −16.5 V, or AVSS = 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ; CLOAD = 200 pF; all specifications tMIN to tMAX, unless otherwise noted. Table 3. 1, 2, 3 Parameter Limit at tMIN, tMAX Unit Description t 33 ns min SCLK cycle time 1 t2 13 ns min SCLK high time t3 13 ns min SCLK low time t 13 ns min SYNC falling edge to SCLK falling edge setup time 4 t 13 ns min SCLK falling edge to SYNC rising edge 5 t 100 ns min high time (write mode) 6 Minimum SYNC t7 7 ns min Data setup time t8 2 ns min Data hold time t9 20 ns min LDAC falling edge to SYNC falling edge t 130 ns min SYNC rising edge to LDAC falling edge 10 t 20 ns min LDAC pulse width low 11 t 10 μs max DAC output settling time 12 t13 20 ns min CLR pulse width low t14 2.5 μs max CLR pulse activation time 4 t15 13 ns min SYNC rising edge to SCLK falling edge 4 5 t 40 ns max SCLK rising edge to SDO valid (C = 15 pF) 16 L SDO t 200 ns min Minimum SYNC high time (readback/daisy-chain mode) 17 1 Guaranteed by characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 Daisy-chain and readback mode. 5 C = capacitive load on SDO output. L SDO Rev. D | Page 5 of 32 AD5722/AD5732/AD5752 TIMING DIAGRAMS t 1 SCLK 1 2 24 t t t 6 3 2 t t 5 4 SYNC t 8 t 7 SDIN DB23 DB0 t 11 t 9 t 10 LDAC t 12 V x OUT t 12 V x OUT t 13 CLR t 14 V x OUT Figure 2. Serial Interface Timing Diagram t 1 SCLK 24 48 t t t t 3 2 5 17 t 15 t 4 SYNC t 8 t 7 D32B D0B D32B D0B SDIN INPUT WORD FOR DAC N INPUT WORD FOR DAC N – 1 t 16 DB23 DB0 SDO t UNDEFINED INPUT WORD FOR DAC N 10 t 11 LDAC Figure 3. Daisy-Chain Timing Diagram Rev. D | Page 6 of 32 06467-002 06467-003 AD5722/AD5732/AD5752 SCLK 1 1 24 24 t 17 SYNC DB23 DB0 DB23 DB0 SDIN INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ DB23 DB0 DB23 DB0 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 4. Readback Timing Diagram Rev. D | Page 7 of 32 06467-004 AD5722/AD5732/AD5752 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any AV to GND −0.3 V to +17 V DD other conditions above those indicated in the operational AVSS to GND +0.3 V to −17 V section of this specification is not implied. Exposure to absolute DVCC to GND −0.3 V to +7 V maximum rating conditions for extended periods may affect Digital Inputs to GND −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) device reliability. Digital Outputs to GND −0.3 V to DV + 0.3 V or 7 V CC (whichever is less) ESD CAUTION REFIN to GND −0.3 V to +5 V VOUTA or VOUTB to GND AVSS to AVDD DAC_GND to GND −0.3 V to +0.3 V SIG_GND to GND −0.3 V to +0.3 V Operating Temperature Range, T A Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature, TJ max 150°C 24-Lead TSSOP Package θ Thermal Impedance 42°C/W JA θ Thermal Impedance 9°C/W JC Power Dissipation (TJ max − TA)/ θJA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 3.5 kV Rev. D | Page 8 of 32 AD5722/AD5732/AD5752 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AV 1 24 AV DD SS NC 2 23 V B OUT AD5722/ V A 3 22 NC OUT AD5732/ 4 21 SIG_GND NC AD5752 5 20 SIG_GND BIN/2sCOMP TOP VIEW NC 6 19 DAC_GND (Not to Scale) 7 18 DAC_GND SYNC SCLK 8 17 REFIN SDIN 9 16 SDO LDAC 10 15 GND DV CLR 11 14 CC NC 12 13 NC NOTES 1. NC = NO CONNECT 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 AVSS Negative Analog Supply. Voltage ranges from −4.5 V to −16.5 V. This pin can be connected to 0 V if output ranges are unipolar. 2, 4, 6, 12, NC Do not connect to these pins. 13, 22 3 VOUTA Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. 5 BIN/2sCOMP Determines the DAC coding for a bipolar output range. This pin should be hardwired to either DVCC or GND. When hardwired to DV , input coding is offset binary. When hardwired to GND, input coding is twos CC complement. (For unipolar output ranges, coding is always straight binary.) 7 Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is SYNC transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC. 8 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10 LDAC Load DAC, Logic Input. This is used to update the DAC registers and, consequently, the analog outputs. When this pin is tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin should not be left unconnected. 11 CLR Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user-selectable). 14 DV Digital Supply. Voltage ranges from 2.7 V to 5.5 V. CC 15 GND Ground Reference. 16 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. 17 REFIN External Reference Voltage Input. Reference input range is 2 V to 3 V. REFIN = 2.5 V for specified performance. 18, 19 DAC_GND Ground Reference for the Two Digital-to-Analog Converters (DACs). 20, 21 SIG_GND Ground Reference for the Two Output Amplifiers. 23 VOUTB Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. 24 AVDD Positive Analog Supply. Voltage ranges from 4.5 V to 16.5 V. Exposed This exposed paddle should be connected to the potential of the AV pin, or alternatively, it can be left electrically SS Paddle unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. D | Page 9 of 32 06467-005 AD5722/AD5732/AD5752 TYPICAL PERFORMANCE CHARACTERISTICS 6 0.6 AV /AV = +12V/0V, RANGE = +10V DD SS AV /AV = ±12V, RANGE = ±10V DD SS AV /AV = ±6.5V, RANGE = ±5V DD SS 4 0.4 AV /AV = +6.5V/0V, RANGE = +5V DD SS 2 0.2 0 0 –2 –0.2 –4 –0.4 AV /AV = +12V/0V, RANGE = +10V DD SS –6 –0.6 AV /AV = ±12V, RANGE = ±10V DD SS AV /AV = ±6.5V, RANGE = ±5V DD SS AV /AV = +6.5V/0V, RANGE = +5V DD SS –8 –0.8 0 10,000 20,000 30,000 40,000 50,000 60,000 0 10,000 20,000 30,000 40,000 50,000 60,000 CODE CODE Figure 6. AD5752 Integral Nonlinearity Error vs. Code Figure 9. AD5752 Differential Nonlinearity Error vs. Code 1.5 0.15 AV /AV = +12V/0V, RANGE = +10V DD SS AV /AV = ±12V, RANGE = ±10V DD SS AV /AV = ±6.5V, RANGE = ±5V DD SS 1.0 0.10 AV /AV = +6.5V/0V, RANGE = +5V DD SS 0.5 0.05 0 0 –0.5 –0.05 –1.0 –0.10 AV /AV = +12V/0V, RANGE = +10V DD SS –1.5 –0.15 AV /AV = ±12V, RANGE = ±10V DD SS AV /AV = ±6.5V, RANGE = ±5V DD SS AV /AV = +6.5V/0V, RANGE = +5V DD SS –2.0 –0.20 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 CODE CODE Figure 7. AD5732 Integral Nonlinearity Error vs. Code Figure 10. AD5732 Differential Nonlinearity Error vs. Code 0.3 0.04 AV /AV = +12V/0V, RANGE = +10V AV /AV = +12V/0V, RANGE = +10V DD SS DD SS AV /AV = ±12V, RANGE = ±10V AV /AV = ±12V, RANGE = ±10V DD SS DD SS AV /AV = ±6.5V, RANGE = ±5V 0.03 AV /AV = ±6.5V, RANGE = ±5V 0.2 DD SS DD SS AV /AV = +6.5V/0V, RANGE = +5V AV /AV = +6.5V/0V, RANGE = +5V DD SS DD SS 0.02 0.1 0.01 0 0 –0.1 –0.01 –0.2 –0.02 –0.3 –0.03 –0.4 –0.04 –0.5 –0.05 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 8. AD5722 Integral Nonlinearity Error vs. Code Figure 11. AD5722 Differential Nonlinearity Error vs. Code Rev. D | Page 10 of 32 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 06467-013 06467-015 06467-014 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 06467-016 06467-017 06467-018 AD5722/AD5732/AD5752 8 10 8 6 6 4 4 MAX INL ±10V MAX INL ±5V 2 2 MIN INL ±10V BIPOLAR 5V MIN MIN INL ±5V UNIPOLAR 5V MIN MAX INL +10V 0 0 BIPOLAR 5V MAX MIN INL +10V UNIPOLAR 5V MAX MAX INL +5V –2 MIN INL +5V –2 –4 –4 –6 –6 –8 –8 –10 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.513.514.515.516.5 –40 –20 0 20 40 60 80 TEMPERATURE (°C) SUPPLY VOLTAGE (V) Figure 12. AD5752 Integral Nonlinearity Error vs. Temperature Figure 15. AD5752 Integral Nonlinearity Error vs. Supply Voltage 0.1 1.0 BIPOLAR 10V MIN UNIPOLAR 10V MIN 0.8 BIPOLAR 10V MAX 0 UNIPOLAR 10V MAX 0.6 –0.1 MAX DNL ±10V 0.4 MAX DNL ±5V MIN DNL ±10V 0.2 MIN DNL ±5V –0.2 MAX DNL +10V MIN DNL +10V 0 MAX DNL +5V –0.3 MIN DNL +5V –0.2 –0.4 –0.4 –0.6 –0.5 –0.8 –0.6 –1.0 –40 –20 0 20 40 60 80 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 TEMPERATURE (°C) SUPPLY VOLTAGE (V) Figure 13. AD5752 Differential Nonlinearity Error vs. Temperature Figure 16. AD5752 Differential Nonlinearity Error vs. Supply Voltage 10 1.0 BIPOLAR 5V MIN UNIPOLAR 5V MIN 8 0.8 BIPOLAR 5V MAX UNIPOLAR 5V MAX 6 0.6 0.4 4 2 0.2 BIPOLAR 10V MIN UNIPOLAR 10V MIN 0 0 BIPOLAR 10V MAX UNIPOLAR 10V MAX –2 –0.2 –4 –0.4 –6 –0.6 –8 –0.8 –10 –1.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 14. AD5752 Integral Nonlinearity Error vs. Supply Voltage Figure 17. AD5752 Differential Nonlinearity Error vs. Supply Voltage Rev. D | Page 11 of 32 INL ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 06467-045 06467-044 06467-034 DNL ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 06467-033 06467-032 06467-035 AD5722/AD5732/AD5752 0.02 6.0 5.5 0.01 5.0 BIPOLAR 10V MIN 0 UNIPOLAR 10V MIN 4.5 BIPOLAR 10V MAX UNIPOLAR 10V MAX –0.01 4.0 3.5 –0.02 3.0 –0.03 2.5 –0.04 2.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 4.5 6.5 8.5 10.5 12.5 14.5 16.5 SUPPLY VOLTAGE (V) AV (V) DD Figure 18. AD5752 Total Unadjusted Error vs. Supply Voltage Figure 21. Supply Current vs. Supply Voltage (Single Supply) 0.04 4 +10V 0.03 3 0.02 2 0.01 BIPOLAR 5V MIN UNIPOLAR 5V MIN BIPOLAR 5V MAX 1 0 UNIPOLAR 5V MAX ±10V –0.01 0 –0.02 –1 –0.03 –2 –0.04 ±5V –0.05 –3 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 –40 –20 0 20 40 60 80 SUPPLY VOLTAGE (V) TEMPERATURE (°C) Figure 19. AD5752 Total Unadjusted Error vs. Supply Voltage Figure 22. Zero-Scale Error vs. Temperature 5 0.8 4 0.6 AI (mA) DD 3 0.4 ±5V RANGE 2 0.2 1 0 ±10V RANGE 0 –0.2 –1 –0.4 –2 AI (mA) –0.6 DD –3 –0.8 –4 –1.0 4.5 6.5 8.5 10.5 12.5 14.5 16.5 –40 –20 0 20 40 60 80 TEMPERATURE (°C) AV /AV (V) DD SS Figure 20. Supply Current vs. Supply Voltage (Dual Supply) Figure 23. Bipolar Zero Error vs. Temperature Rev. D | Page 12 of 32 TUE (%) TUE (%) AI /AI (mA) DD SS 06467-038 06467-037 06467-036 AI (mA) BIPOLAR ZERO ERROR (mV) DD ZERO-SCALE ERROR (mV) 06467-047 06467-046 06467-042 AD5722/AD5732/AD5752 0.06 15 ±5V 0.04 10 0.02 5 0 0 ±10V –0.02 –5 +10V –0.04 –10 –0.06 –15 –3 –1 13579 11 –40 –20 0 20 406080 TEMPERATURE (°C) TIME (µs) Figure 24. Gain Error vs. Temperature Figure 27. Full-Scale Settling Time, ±10 V Range 1000 7 900 5 800 700 3 600 1 500 400 –1 DV = 5V CC 300 –3 200 100 DV = 3V –5 CC 0 –100 –7 0123456 –3 –1 13579 11 V (V) TIME (µs) LOGIC Figure 25. Digital Current vs. Logic Input Voltage Figure 28. Full-Scale Settling Time, ±5 V Range 12 0.010 ±5V RANGE, CODE = 0xFFFF ±10V RANGE, CODE = 0xFFFF +10V RANGE, CODE = 0xFFFF +5V RANGE, CODE = 0xFFFF 0.005 10 ±5V RANGE, CODE = 0x0000 ±10V RANGE, CODE = 0x0000 0 8 –0.005 6 –0.010 4 –0.015 2 –0.020 0 –3 –1 13579 11 –25 –20 –15 –10 –5 0 5 10 15 20 25 TIME (µs) OUTPUT CURRENT (mA) Figure 26. Output Source and Sink Capability Figure 29. Full-Scale Settling Time, +10 V Range Rev. D | Page 13 of 32 OUTPUT VOLTAGE DELTA (V) DI (µA) GAIN ERROR (% FSR) CC 06467-048 06467-043 06467-040 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 06467-024 06467-023 06467-022 AD5722/AD5732/AD5752 6 5 4 3 1 2 1 RANGE = ±5V RANGE = +10V 0 RANGE = +5V RANGE = ±10V –3 –1 13579 11 TIME (µs) CH1 5µV M5s LINE 73.8V Figure 30. Full-Scale Settling Time, +5 V Range Figure 33. Peak-to-Peak Noise, 100 kHz Bandwidth 0.10 0.020 AV /AV = ±16.5V ±10V RANGE, 0x7FF±F TO 0x8000 DD SS ±10V RANGE, 0x8000 TO 0x7FFF AV = +16.5V, AVSS = 0V DD ±5V RANGE, 0x7FFF TO 0x8000 0.08 0.015 ±5V RANGE, 0x8000 TO 0x7FFF +10V RANGE, 0x7FFF TO 0x8000 +10V RANGE, 0x8000 TO 0x7FFF 0.06 0.010 +5V RANGE, 0x7FFF TO 0x8000 +5V RANGE, 0x8000 TO 0x7FFF 0.04 0.005 0.02 0 0 –0.005 –0.02 –0.010 –0.04 –0.06 –0.015 –1 0 1234 5 –50 –30 –10 1030507090 TIME (µs) TIME (µs) Figure 34. Output Glitch on Power-Up Figure 31. Digital-to-Analog Glitch Energy 15 AV /AV = +12V/0V, RANGE = +10V DD SS AV /AV = ±12V, RANGE = ±10V DD SS 10 AV /AV = ±6.5V, RANGE = ±5V DD SS AV /AV = +6.5V/0V, RANGE = +5V DD SS 5 0 –5 –10 1 –15 –20 –25 –30 RANGE = ±5V RANGE = +10V –35 RANGE = +5V RANGE = ±10V 0 1000 2000 3000 4000 5000 6000 CODE CH1 5µV M 5s LINE 73.8V Figure 35. AD5752 Total Unadjusted Error vs. Code Figure 32. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth Rev. D | Page 14 of 32 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 06467-026 06467-025 06467-039 TUE (LSB) OUTPUT VOLTAGE (V) 06467-027 06467-019 06467-041 AD5722/AD5732/AD5752 4 1.0 AV /AV = +12V/0V, RANGE = +10V AV /AV = +12V/0V, RANGE = +10V DD SS DD SS AV /AV = ±12V, RANGE = ±10V AV /AV = ±12V, RANGE = ±10V DD SS DD SS AV /AV = ±6.5V, RANGE = ±5V AV /AV = ±6.5V, RANGE = ±5V DD SS DD SS 2 0.5 AV /AV = +6.5V/0V, RANGE = +5V AV /AV = +6.5V/0V, RANGE = +5V DD SS DD SS 0 0 –2 –0.5 –4 –1.0 –6 –1.5 –8 –2.0 –10 –2.5 0 2000 4000 6000 8000 10000 12000 14000 16000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 36. AD5732 Total Unadjusted Error vs. Code Figure 37. AD5722 Total Unadjusted Error vs. Code Rev. D | Page 15 of 32 TUE (LSB) 06467-020 TUE (LSB) 06467-021 AD5722/AD5732/AD5752 TERMINOLOGY Slew Rate Relative Accuracy or Integral Nonlinearity (INL) The slew rate of a device is a limitation in the rate of change of For the DAC, relative accuracy, or integral nonlinearity, is a the output voltage. The output slewing speed of a voltage output measure of the maximum deviation in LSBs from a straight line DAC is usually limited by the slew rate of the amplifier used at passing through the endpoints of the DAC transfer function. A its output. Slew rate is measured from 10% to 90% of the output typical INL vs. code plot can be seen in Figure 6. signal and is given in V/μs. Differential Nonlinearity (DNL) Gain Error Differential nonlinearity is the difference between the measured Gain error is a measure of the span error of the DAC. It is the change and the ideal 1 LSB change between any two adjacent deviation in slope of the DAC transfer characteristic from the codes. A specified differential nonlinearity of ±1 LSB maximum ideal and is expressed in % FSR. A plot of gain error vs. ensures monotonicity. This DAC is guaranteed monotonic by temperature can be seen in Figure 24. design. A typical DNL vs. code plot can be seen in Figure 9. Gain TC Monotonicity Gain TC is a measure of the change in gain error with changes A DAC is monotonic if the output either increases or remains in temperature. Gain TC is expressed in ppm FSR/°C. constant for increasing digital input code. The AD5722/ AD5732/AD5752 are monotonic over their full operating Total Unadjusted Error (TUE) temperature range. Total unadjusted error is a measure of the output error taking all the various errors into account, namely INL error, offset Bipolar Zero Error error, gain error, and output drift over supplies, temperature, Bipolar zero error is the deviation of the analog output from the and time. TUE is expressed in % FSR. ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement Digital-to-Analog Glitch Impulse coding). A plot of bipolar zero error vs. temperature can be seen Digital-to-analog glitch impulse is the impulse injected into the in Figure 23. analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally Bipolar Zero TC specified as the area of the glitch in nV-sec and is measured Bipolar zero TC is a measure of the change in the bipolar zero when the digital input code is changed by 1 LSB at the major error with a change in temperature. It is expressed in ppm FSR/°C. carry transition (0x7FFF to 0x8000). See Figure 31. Zero-Scale Error or Negative Full-Scale Error Glitch Impulse Peak Amplitude Zero-scale error is the error in the DAC output voltage when Glitch impulse peak amplitude is the peak amplitude of the 0x0000 (straight binary coding) or 0x8000 (twos complement impulse injected into the analog output when the input code in coding) is loaded to the DAC register. Ideally, the output voltage the DAC register changes state. It is specified as the amplitude should be negative full-scale − 1 LSB. A plot of zero-scale error of the glitch in mV and is measured when the digital input code vs. temperature can be seen in Figure 22. is changed by 1 LSB at the major carry transition (0x7FFF to Zero-Scale TC 0x8000). See Figure 31. Zero-scale TC is a measure of the change in zero-scale error with a Digital Feedthrough change in temperature. Zero-scale TC is expressed in ppm FSR/°C. Digital feedthrough is a measure of the impulse injected into Output Voltage Settling Time the analog output of the DAC from the digital inputs of the Output voltage settling time is the amount of time required for DAC but is measured when the DAC output is not updated. It is the output to settle to a specified level for a full-scale input change. specified in nV-sec and measured with a full-scale code change A plot for full-scale settling time can be seen in Figure 27. on the data bus. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. It is measured by superimposing a 50 Hz/60 Hz, 200 mV p-p sine wave on the supply voltages and measuring the proportion of the sine wave that transfers to the outputs. Rev. D | Page 16 of 32 AD5722/AD5732/AD5752 DC Crosstalk DAC-to-DAC Crosstalk This is the dc change in the output level of one DAC in response DAC-to-DAC crosstalk is the glitch impulse transferred to the to a change in the output of another DAC. It is measured with a output of one DAC due to a digital code change and a subsequent full-scale output change on one DAC while monitoring another output change of another DAC. This includes both digital and DAC. It is expressed in LSBs. analog crosstalk. It is measured by loading one of the DACs Digital Crosstalk with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The Digital crosstalk is a measure of the impulse injected into the energy of the glitch is expressed in nV-sec. analog output of one DAC from the digital inputs of another DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Rev. D | Page 17 of 32 AD5722/AD5732/AD5752 THEORY OF OPERATION REFIN The AD5722/AD5732/AD5752 are dual, 12-/14-/16-bit, serial input, unipolar/bipolar, voltage output DACs. They operate R from unipolar supply voltages of +4.5 V to +16.5 V or bipolar supply voltages of ±4.5 V to ±16.5 V. In addition, the parts have software-selectable output ranges of +5 V, +10 V, +10.8 V, ±5 V, R ±10 V, and ±10.8 V. Data is written to the AD5722/AD5732/ AD5752 in a 24-bit word format via a 3-wire serial interface. TO OUTPUT R The devices also offer an SDO pin to facilitate daisy-chaining AMPLIFIER or readback. The AD5722/AD5732/AD5752 incorporate a power-on reset circuit to ensure that the DAC registers power up loaded with 0x0000. When powered on, the outputs are clamped to 0 V via a low impedance path. R ARCHITECTURE The DAC architecture consists of a string DAC followed by an R output amplifier. Figure 38 shows a block diagram of the DAC architecture. The reference input is buffered before being applied to the DAC. Figure 39. Resistor String Structure REFIN Output Amplifiers The output amplifiers are capable of generating both unipolar REF (+) and bipolar output voltages. They are capable of driving a load RESISTOR DAC REGISTER V X OUT STRING of 2 kΩ in parallel with 4000 pF to GND. The source and sink CONFIGURABLE REF (–) capabilities of the output amplifiers can be seen in Figure 26. OUTPUT AMPLIFIER The slew rate is 3.5 V/μs with a full-scale settling time of 10 μs. GND Reference Buffers OUTPUT RANGE CONTROL The AD5722/AD5732/AD5752 require an external reference Figure 38. DAC Architecture Block Diagram source. The reference input has an input range of 2 V to 3 V, The resistor string structure is shown in Figure 39. It is a string with 2.5 V for specified performance. This input voltage is then of resistors, each of value R. The code loaded to the DAC register buffered before it is applied to the DAC cores. determines the node on the string where the voltage is to be SERIAL INTERFACE tapped off and fed into the output amplifier. The voltage is The AD5722/AD5732/AD5752 are controlled over a versatile tapped off by closing one of the switches connecting the string 3-wire serial interface that operates at clock rates up to 30 MHz. to the amplifier. Because it is a string of resistors, it is guaranteed It is compatible with SPI, QSPI™, MICROWIRE™, and DSP monotonic. standards. Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, three register select bits, three DAC address bits, and 16 data bits. The timing diagram for this operation is shown in Figure 2. Rev. D | Page 18 of 32 06467-006 06467-007 AD5722/AD5732/AD5752 Standalone Operation Daisy-Chain Operation The serial interface works with both a continuous and noncon- For systems that contain several devices, the SDO pin can be tinuous serial clock. A continuous SCLK source can be used used to daisy-chain several devices together. Daisy-chain mode only if SYNC is held low for the correct number of clock cycles. can be useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of SYNC starts the In gated clock mode, a burst clock containing the exact number SYNC write cycle. SCLK is continuously applied to the input shift of clock cycles must be used, and must be taken high SYNC after the final clock to latch the data. The first falling edge of register when is low. If more than 24 clock pulses are SYNC applied, the data ripples out of the shift register and appears on starts the write cycle. Exactly 24 falling clock edges must the SDO line. This data is clocked out on the rising edge of SYNC be applied to SCLK before is brought high again. If th SCLK and is valid on the falling edge. By connecting the SDO SYNC is brought high before the 24 falling SCLK edge, the of the first device to the SDIN input of the next device in the data written is invalid. If more than 24 falling SCLK edges are chain, a multidevice interface is constructed. Each device in the applied before SYNC is brought high, the input data is also system requires 24 clock pulses. Therefore, the total number of invalid. The input register addressed is updated on the rising clock cycles must equal 24 × N, where N is the total number of SYNC SYNC edge of . For another serial transfer to take place, AD5722/AD5732/AD5752 devices in the chain. When the serial must be brought low again. After the end of the serial data SYNC transfer to all devices is complete, is taken high. This transfer, data is automatically transferred from the input shift latches the input data in each device in the daisy chain and register to the addressed register. prevents any further data from being clocked into the input shift When the data has been transferred into the chosen register of register. The serial clock can be a continuous or a gated clock. the addressed DAC, all DAC registers and outputs can be A continuous SCLK source can only be used if SYNC is held updated by taking LDAC low while SYNC is high. low for the correct number of clock cycles. In gated clock mode, AD5722/ a burst clock containing the exact number of clock cycles must * AD5732/ 68HC11 SYNC AD5752* be used, and must be taken high after the final clock to SDIN MOSI latch the data. SCK SCLK Readback Operation PC7 SYNC Readback mode is invoked by setting the R/W bit = 1 in the PC6 LDAC SDO write operation to the serial input shift register. (If the SDO MISO output is disabled via the SDO disable bit in the control register, it is automatically enabled for the duration of the read operation, SDIN W after which it is disabled again.) With R/ = 1, Bit A2 to Bit A0, AD5722/ AD5732/ in association with Bit REG2 to Bit REG0, select the register to AD5752* be read. The remaining data bits in the write sequence are don’t SCLK care bits. During the next SPI write, the data appearing on the SDO SYNC output contains the data from the previously addressed register. LDAC For a read of a single register, the NOP command can be used in SDO clocking out the data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the DAC register of Channel A, the SDIN AD5722/ following sequence should be implemented: AD5732/ AD5752* 1. Write 0x800000 to the AD5722/AD5732/AD5752 input SCLK register. This configures the part for read mode with the SYNC DAC register of Channel A selected. Note that all the data LDAC bits, DB15 to DB0, are don’t care bits. SDO 2. Follow this with a second write, a NOP condition, 0x180000. During this write, the data from the register is clocked out * ADDITIONAL PINS OMITTED FOR CLARITY. on the SDO line. Figure 40. Daisy Chaining the AD5722/AD5732/AD5752 Rev. D | Page 19 of 32 06467-008 AD5722/AD5732/AD5752 LOAD DAC (LDAC) CONFIGURING THE AD5722/AD5732/AD5752 When the power supplies are applied to the AD5722/AD5732/ After data has been transferred into the input register of the AD5752, the power-on reset circuit ensures that all registers DACs, there are two ways to update the DAC registers and DAC default to 0. This places all channels in power-down mode. The SYNC LDAC outputs. Depending on the status of both and , one DV should be brought high before any of the interface lines CC of two update modes is selected: individual DAC updating or are powered. If this is not done the first write to the device may simultaneous updating of all DACs. be ignored. The first communication to the AD5722/AD5732/ OUTPUT AMPLIFIER AD5752 should be to set the required output range on all 12-/14-/16-BIT REFIN V X OUT channels (the default range is the 5 V unipolar range) by writing DAC to the output range select register. The user should then write to the power control register to power on the required channels. To DAC LDAC REGISTER program an output value on a channel, that channel must first be powered up; any writes to a channel while it is in power-down mode are ignored. The AD5722/ AD5732/AD5752 operate with a INPUT wide power supply range. It is important that the power supply REGISTER applied to the parts provide adequate headroom to support the chosen output ranges. SCLK INTERFACE SDO SYNC LOGIC TRANSFER FUNCTION SDIN Figure 41. Simplified Diagram of Input Loading Circuitry for One DAC Table 7 to Table 15 show the relationships of the ideal input code to output voltage for the AD5752, AD5732, and AD5722, Individual DAC Updating respectively, for all output voltage ranges. For unipolar output LDAC In this mode, is held low while data is clocked into the ranges, the data coding is straight binary. For bipolar output input shift register. The addressed DAC output is updated on 2sCOMP ranges, the data coding is user selectable via the BIN/ SYNC the rising edge of . pin and can be either offset binary or twos complement. Simultaneous Updating of All DACs For a unipolar output range, the output voltage expression is In this mode, LDAC is held high while data is clocked into the given by input shift register. All DAC outputs are asynchronously updated D ⎡ ⎤ V =V ×Gain LDAC SYNC by taking low after has been taken high. The OUT REFIN N ⎢ ⎥ ⎣2 ⎦ LDAC update now occurs on the falling edge of . For a bipolar output range, the output voltage expression is given by ASYNCHRONOUS CLEAR (CLR) Gain×V D ⎡ ⎤ REFIN V =V ×Gain − CLR REFIN is an active low clear that allows the outputs to be cleared OUT N ⎢ ⎥ 2 2 ⎣ ⎦ to either zero-scale code or midscale code. The clear code value is where: user-selectable via the CLR select bit of the control register (see D is the decimal equivalent of the code loaded to the DAC. CLR the Control Register section). It is necessary to maintain low N is the bit resolution of the DAC. for a minimum amount of time to complete the operation (see V is the reference voltage applied at the REFIN pin. REFIN Figure 2). When the CLR signal is returned high, the output Gain is an internal gain whose value depends on the output remains at the cleared value until a new value is programmed. range selected by the user, as shown in Table 6. The outputs cannot be updated with a new value while the CLR pin is low. A clear operation can also be performed via the clear Table 6. Internal Gain Values command in the control register. Output Range (V) Gain Value +5 2 +10 4 +10.8 4.32 ±5 4 ±10 8 ±10.8 8.64 Rev. D | Page 20 of 32 06467-009 AD5722/AD5732/AD5752 Ideal Output Voltage to Input Code Relationship—AD5752 Table 7. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 1111 1111 1111 1111 +2 × REFIN × (32,767/32,768) +4 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,767/32,768) 1111 1111 1111 1110 +2 × REFIN × (32,766/32,768) +4 × REFIN × (32,766/32,768) +4.32 × REFIN × (32,766/32,768) … … … … … … … 1000 0000 0000 0001 +2 × REFIN × (1/32,768) +4 × REFIN × (1/32,768) +4.32 × REFIN × (1/32,768) 1000 0000 0000 0000 0 V 0 V 0 V 0111 1111 1111 1111 −2 × REFIN × (1/32,768) −4 × REFIN × (1/32,768) −4.32 × REFIN × (32,766/32,768) … … … … … … … 0000 0000 0000 0001 −2 × REFIN × (32,766/32,768) −4 × REFIN × (32,766/32,768) −4.32 × REFIN × (32,766/32,768) 0000 0000 0000 0000 −2 × REFIN × (32,767/32,768 −4 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,767/32,768) Table 8. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 0111 1111 1111 1111 +2 × REFIN × (32,767/32,768) +4 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,767/32,768) 0111 1111 1111 1110 +2 × REFIN × (32,766/32,768) +4 × REFIN × (32,766/32,768) +4.32 × REFIN × (32,766/32,768) … … … … … … … 0000 0000 0000 0001 +2 × REFIN × (1/32,768) +4 × REFIN × (1/32,768) +4.32 × REFIN × (1/32,768) 0000 0000 0000 0000 0 V 0 V 0 V 1111 1111 1111 1111 −2 × REFIN × (1/32,768) −4 × REFIN × (1/32,768) −4.32 × REFIN × (1/32,768) … … … … … … … 1000 0000 0000 0001 −2 × REFIN × (32,766/32,768) −4 × REFIN × (32,766/32,768) −4.32 × REFIN × (32,766/32,768) 1000 0000 0000 0000 −2 × REFIN × (32,767/32,768) −4 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,767/32,768) Table 9. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 1111 1111 1111 1111 +2 × REFIN × (65,535/65,536) +4 × REFIN × (65,535/65,536) +4.32 × REFIN × (65,535/65,536) 1111 1111 1111 1110 +2 × REFIN × (65,534/65,536) +4 × REFIN × (65,534/65,536) +4.32 × REFIN × (65,534/65,536) … … … … … … … 1000 0000 0000 0001 +2 × REFIN × (32,769/65,536) +4 × REFIN × (32,769/65,536) +4.32 × REFIN × (32,769/65,536) 1000 0000 0000 0000 +2 × REFIN × (32,768/65,536) +4 × REFIN × (32,768/65,536) +4.32 × REFIN × (32,768/65,536) 0111 1111 1111 1111 +2 × REFIN × (32,767/65,536) +4 × REFIN × (32,767/65,536) +4.32 × REFIN × (32,767/65,536) … … … … … … … 0000 0000 0000 0001 +2 × REFIN × (1/65,536) +4 × REFIN × (1/65,536) +4.32 × REFIN × (1/65,536) 0000 0000 0000 0000 0 V 0 V 0 V Rev. D | Page 21 of 32 AD5722/AD5732/AD5752 Ideal Output Voltage to Input Code Relationship—AD5732 Table 10. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 11 1111 1111 1111 +2 × REFIN × (8191/8192) +4 × REFIN × (8191/8192) +4.32 × REFIN × (8191/8192) 11 1111 1111 1110 +2 × REFIN × (8190/8192) +4 × REFIN × (8190/8192) +4.32 × REFIN × (8190/8192) … … … … … … … 10 0000 0000 0001 +2 × REFIN × (1/8192) +4 × REFIN × (1/8192) +4.32 × REFIN × (1/8192) 10 0000 0000 0000 0 V 0 V 0 V 01 1111 1111 1111 −2 × REFIN × (1/8192) −4 × REFIN × (1/8192) −4.32 × REFIN × (1/8192) … … … … … … … 00 0000 0000 0001 −2 × REFIN × (8190/8192) −4 × REFIN × (8190/8192) −4.32 × REFIN × (8190/8192) 00 0000 0000 0000 −2 × REFIN × (8191/8191) −4 × REFIN × (8191/8192) −4.32 × REFIN × (8191/8192) Table 11. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 01 1111 1111 1111 +2 × REFIN × (8191/8192) +4 × REFIN × (8191/8192) +4.32 × REFIN × (8191/8192) 01 1111 1111 1110 +2 × REFIN × (8190/8192) +4 × REFIN × (8190/8192) +4.32 × REFIN × (8190/8192) … … … … … … … 00 0000 0000 0001 +2 × REFIN × (1/8192) +4 × REFIN × (1/8192) +4.32 × REFIN × (1/8192) 00 0000 0000 0000 0 V 0 V 0 V 11 1111 1111 1111 −2 × REFIN × (1/8192) −4 × REFIN × (1/8192) −4.32 × REFIN × (1/8192) … … … … … … … 10 0000 0000 0001 −2 × REFIN × (8190/8192) −4 × REFIN × (8190/8192) −4.32 × REFIN × (8190/8192) 10 0000 0000 0000 −2 × REFIN × (8191/8192) −4 × REFIN × (8191/8192) −4.32 × REFIN × (8191/8192) Table 12. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 11 1111 1111 1111 +2 × REFIN × (16,383/16,384) +4 × REFIN × (16,383/16,384) +4.32 × REFIN × (16,383/16,384) 11 1111 1111 1110 +2 × REFIN × (16,382/16,384) +4 × REFIN × (16,382/16,384) +4.32 × REFIN × (16,382/16,384) … … … … … … … 10 0000 0000 0001 +2 × REFIN × (8193/16,384) +4 × REFIN × (8193/16,384) +4.32 × REFIN × (8193/16,384) 10 0000 0000 0000 +2 × REFIN × (8192/16,384) +4 × REFIN × (8192/16,384) +4.32 × REFIN × (8192/16,384) 01 1111 1111 1111 +2 × REFIN × (8191/16,384) +4 × REFIN × (8191/16,384) +4.32 × REFIN × (8191/16,384) … … … … … … … 00 0000 0000 0001 +2 × REFIN × (1/16,384) +4 × REFIN × (1/16,384) +4.32 × REFIN × (1/16,384) 00 0000 0000 0000 0 V 0 V 0 V Rev. D | Page 22 of 32 AD5722/AD5732/AD5752 Ideal Output Voltage to Input Code Relationship—AD5722 Table 13. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 1111 1111 1111 +2 × REFIN × (2047/2048) +4 × REFIN × (2047/2048) +4.32 × REFIN × (2047/2048) 1111 1111 1110 +2 × REFIN × (2046/2048) +4 × REFIN × (2046/2048) +4.32 × REFIN × (2046/2048) … … … … … … 1000 0000 0001 +2 × REFIN × (1/2048) +4 × REFIN × (1/2048) +4.32 × REFIN × (1/2048) 1000 0000 0000 0 V 0 V 0 V 0111 1111 1111 −2 × REFIN × (1/2048) −4 × REFIN × (1/2048) −4.32 × REFIN × (1/2048) … … … … … … 0000 0000 0001 −2 × REFIN × (2046/2048) −4 × REFIN × (2046/2048) −4.32 × REFIN × (2046/2048) 0000 0000 0000 −2 × REFIN × (2047/2047) −4 × REFIN × (2047/2048) −4.32 × REFIN × (2047/2048) Table 14. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 0111 1111 1111 +2 × REFIN × (2047/2048) +4 × REFIN × (2047/2048) +4.32 × REFIN × (2047/2048) 0111 1111 1110 +2 × REFIN × (2046/2048) +4 × REFIN × (2046/2048) +4.32 × REFIN × (2046/2048) … … … … … … 0000 0000 0001 +2 × REFIN × (1/2048) +4 × REFIN × (1/2048) +4.32 × REFIN × (1/2048) 0000 0000 0000 0 V 0 V 0 V 1111 1111 1111 −2 × REFIN × (1/2048) −4 × REFIN × (1/2048) −4.32 × REFIN × (1/2048) … … … … … … 1000 0000 0001 −2 × REFIN × (2046/2048) −4 × REFIN × (2046/2048) −4.32 × REFIN × (2046/2048) 1000 0000 0000 −2 × REFIN × (2047/2048) −4 × REFIN × (2047/2048) −4.32 × REFIN × (2047/2048) Table 15. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 1111 1111 1111 +2 × REFIN × (4095/4096) +4 × REFIN × (4095/4096) +4.32 × REFIN × (4095/4096) 1111 1111 1110 +2 × REFIN × (4094/4096) +4 × REFIN × (4094/4096) +4.32 × REFIN × (4094/4096) … … … … … … 1000 0000 0001 +2 × REFIN × (2049/4096) +4 × REFIN × (2049/4096) +4.32 × REFIN × (2049/4096) 1000 0000 0000 +2 × REFIN × (2048/4096) +4 × REFIN × (2048/4096) +4.32 × REFIN × (2048/4096) 0111 1111 1111 +2 × REFIN × (2047/4096) +4 × REFIN × (2047/4096) +4.32 × REFIN × (2047/4096) … … … … … … 0000 0000 0001 +2 × REFIN × (1/4096) +4 × REFIN × (1/4096) +4.32 × REFIN × (1/4096) 0000 0000 0000 0 V 0 V 0 V Rev. D | Page 23 of 32 AD5722/AD5732/AD5752 INPUT SHIFT REGISTER The input shift register is 24 bits wide and consists of a read/write bit (R/W), a reserved bit (zero) that must always be set to 0, three register select bits (REG0, REG1, REG2), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB first on the SDIN pin. Table 16 shows the register format, and Table 17 describes the function of each bit in the register. All registers are read/write registers. Table 16. Input Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB0 R/W Zero REG2 REG1 REG0 A2 A1 A0 Data Table 17. Input Register Bit Functions Bit Mnemonic Description R/W Indicates a read from or a write to the addressed register. REG2, REG1, REG0 Used in association with the address bits to determine if a write operation is to the DAC register, the output range select register, the power control register, or the control register. REG2 REG1 REG0 Function 0 0 0 DAC register 0 0 1 Output range select register 0 1 0 Power control register 0 1 1 Control register A2, A1, A0 These DAC address bits are used to decode the DAC channels. A2 A1 A0 Channel Address 0 0 0 DAC A 0 1 0 DAC B 1 0 0 Both DACs Data Data bits. Rev. D | Page 24 of 32 AD5722/AD5732/AD5752 DAC REGISTER The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel in which the data transfer is to take place (see Table 17). The data bits are in positions DB15 to DB0 for the AD5752 (see Table 18), DB15 to DB2 for the AD5732 (see Table 19), and DB15 to DB4 for the AD5722 (see Table 20). Table 18. Programming the AD5752 DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB0 0 0 0 0 0 DAC address 16-bit DAC data Table 19. Programming the AD5732 DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0 0 0 0 0 0 DAC address 14-bit DAC data X X Table 20. Programming the AD5722 DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 DAC address 12-bit DAC data X X X X OUTPUT RANGE SELECT REGISTER The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel, and the range bits (R2, R1, R0) select the required output range (see Table 21 and Table 22). Table 21. Programming the Required Output Range MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB3 DB2 DB1 DB0 0 0 0 0 1 DAC address Don’t care R2 R1 R0 Table 22. Output Range Options R2 R1 R0 Output Range (V) 0 0 0 +5 0 0 1 +10 0 1 0 +10.8 0 1 1 ±5 1 0 0 ±10 1 0 1 ±10.8 Rev. D | Page 25 of 32 AD5722/AD5732/AD5752 CONTROL REGISTER The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the control function selected. The control register options are shown in Table 23 and Table 24. Table 23. Programming the Control Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 0 0 0 NOP, data = don’t care 0 0 0 1 1 0 0 1 Don’t care TSD enable Clamp enable CLR select SDO disable 0 0 0 1 1 1 0 0 Clear, data = don’t care 0 0 0 1 1 1 0 1 Load, data = don’t care Table 24. Explanation of Control Register Options Option Description NOP No operation instruction used in readback operations. Clear Addressing this function sets the DAC registers to the clear code and updates the outputs. Load Addressing this function updates the DAC registers and, consequently, the DAC outputs. SDO Disable Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). CLR Select See Table 25 for a description of the CLR select operation. Clamp Enable Set by the user to enable the current-limit clamp. The channel does not power down upon detection of an overcurrent; the current is clamped at 20 mA (default). Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent. TSD Enable Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown feature (default). Table 25. CLR Select Options Output CLR Value CLR Select Setting Unipolar Output Range Bipolar Output Range 0 0 V 0 V 1 Midscale Negative full-scale POWER CONTROL REGISTER The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power and thermal status of the AD5722/AD5732/AD5752. The power control register options are shown in Table 26 and Table 27. Table 26. Programming the Power Control Register MSB LSB DB15 to R/W Zero REG2 REG1 REG0 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 0 0 0 X 0 OC X OC X TSD X X PU X PU B A B A Table 27. Power Control Register Functions Option Description PU DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down A mode (default). After setting this bit to power DAC A, a power-up time of 10 μs is required. During this power-up time, the DAC ) section). If the clamp enable bit of the control register register should not be loaded to the DAC output (see the Load DAC (LDAC is cleared, DAC A powers down automatically on detection of an overcurrent, and PUA is cleared to reflect this. PUB DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down mode (default). After setting this bit to power DAC B, a power-up time of 10 μs is required. During this power-up time, the DAC register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register is cleared, DAC B powers down automatically on detection of an overcurrent, and PU is cleared to reflect this. B TSD Thermal shutdown alert (read-only bit). In the event of an overtemperature situation, both DACs are powered down and this bit is set. OCA DAC A overcurrent alert (read-only bit). In the event of an overcurrent situation on DAC A, this bit is set. OCB DAC B overcurrent alert (read-only bit). In the event of an overcurrent situation on DAC B, this bit is set. Rev. D | Page 26 of 32 AD5722/AD5732/AD5752 DESIGN FEATURES OVERCURRENT PROTECTION ANALOG OUTPUT CONTROL Each DAC channel of the AD5722/AD5732/AD5752 incorporates In many industrial process control applications, it is vital that individual overcurrent protection. The user has two options for the output voltage be controlled during power-up. When the the configuration of the overcurrent protection: constant current supply voltages change during power-up, the V x pins are OUT clamp or automatic channel power-down. The configuration of clamped to 0 V via a low impedance path (approximately 4 kΩ). the overcurrent protection is selected via the clamp enable bit in To prevent the output amplifiers from being shorted to 0 V the control register. during this time, Transmission Gate G1 is also opened (see Figure 42). These conditions are maintained until the power Constant Current Clamp (Clamp Enable = 1) supplies have stabilized and a valid word is written to a DAC If a short circuit occurs in this configuration, the current is register. At this time, G2 opens and G1 closes. clamped at 20 mA. This event is signaled to the user by the VOLTAGE setting of the appropriate overcurrent (OCX) bit in the power MONITOR AND control register. Upon removal of the short-circuit fault, the CONTROL OCX bit is cleared. G1 Automatic Channel Power-Down (Clamp Enable = 0) V A OUT G2 If a short circuit occurs in this configuration, the shorted channel powers down and its output is clamped to ground via a resistance of approximately 4 kΩ. At this time, the output of the amplifier is disconnected from the output pin. The short-circuit event is Figure 42. Analog Output Control Circuitry signaled to the user via the overcurrent (OCX) bits, and the POWER-DOWN MODE power-up (PU ) bits indicate which DACs have powered down. X Each DAC channel of the AD5722/AD5732/AD5752 can be After the fault is rectified, the channels can be powered up again individually powered down. By default, all channels are in by setting the PU bits. X power-down mode. The power status is controlled by the power THERMAL SHUTDOWN control register (see Table 26 and Table 27 for details). When a The AD5722/AD5732/AD5752 incorporate a thermal shutdown channel is in power-down mode, its output pin is clamped to feature that automatically shuts down the device if the core ground through a resistance of approximately 4 kΩ, and the temperature exceeds approximately 150°C. The thermal shutdown output of the amplifier is disconnected from the output pin. feature is disabled by default and can be enabled via the TSD enable bit of the control register. In the event of a thermal shutdown, the TSD bit of the power control register is set. Rev. D | Page 27 of 32 06467-010 AD5722/AD5732/AD5752 APPLICATIONS INFORMATION GALVANICALLY ISOLATED INTERFACE +5 V/±5 V OPERATION In many process control applications, it is necessary to provide When operating from a single +5 V supply or a dual ±5 V supply, an isolation barrier between the controller and the unit being an output range of +5 V or ±5 V is not achievable because suffi- controlled to protect and isolate the controlling circuitry from cient headroom for the output amplifier is not available. In this any hazardous common-mode voltages that may occur. The situation, a reduced reference voltage can be used. For example, iCoupler® family of products from Analog Devices, Inc., provides a 2 V reference voltage produces an output range of +4 V or ±4 V, voltage isolation in excess of 2.5 kV. The serial loading structure and the 1 V of headroom is more than enough for full operation. of the AD5722/AD5732/AD5752 makes them ideal for isolated A standard value voltage reference of 2.048 V can be used to interfaces because the number of interface lines is kept to a produce output ranges of +4.096 V and ±4.096 V. minimum. Figure 43 shows a 4-channel isolated interface to the LAYOUT GUIDELINES AD5722/AD5732/AD5752 using an ADuM1400. For further In any circuit where accuracy is important, careful consideration information, visit http://www.analog.com/icouplers. of the power supply and ground return layout helps to ensure MICROCONTROLLER ADuM1400* the rated performance. The printed circuit board on which the V V IA OA SERIAL CLOCK OUT ENCODE DECODE TO SCLK AD5722/AD5732/AD5752 are mounted should be designed so V V IB OB SERIAL DATA OUT ENCODE DECODE TO SDIN that the analog and digital sections are separated and confined V V IC OC to certain areas of the board. If the AD5722/AD5732/AD5752 SYNC OUT ENCODE DECODE TO SYNC are in a system where multiple devices require an AGND-to- V V ID OD CONTROL OUT ENCODE DECODE TO LDAC DGND connection, the connection should be made at one *ADDITIONAL PINS OMITTED FOR CLARITY. point only. The star ground point should be established as close as possible to the device. Figure 43. Isolated Interface The AD5722/AD5732/AD5752 should have ample supply bypass- ing of a 10 μF capacitor in parallel with a 0.1 μF capacitor on VOLTAGE REFERENCE SELECTION each supply located as close to the package as possible, ideally To achieve optimum performance from the AD5722/AD5732/ right up against the device. The 10 μF capacitor is the tantalum AD5752 over their full operating temperature range, a precision bead type. The 0.1 μF capacitor should have low effective series voltage reference must be used. Thought should be given to the resistance (ESR) and low effective series inductance (ESI) such selection of a precision voltage reference. The voltage applied to as the common ceramic types, which provide a low impedance the reference inputs is used to provide a buffered positive and path to ground at high frequencies to handle transient currents negative reference for the DAC cores. Therefore, any error in due to internal logic switching. the voltage reference is reflected in the outputs of the device. The power supply lines of the AD5722/AD5732/AD5752 should There are four possible sources of error to consider when use as large a trace as possible to provide low impedance paths choosing a voltage reference for high accuracy applications: and reduce the effects of glitches on the power supply line. Fast initial accuracy, temperature coefficient of the output voltage, switching signals, such as a data clock, should be shielded with long-term drift, and output voltage noise. digital ground to avoid radiating noise to other parts of the • Initial accuracy error on the output voltage of an external board, and they should never be run near the reference inputs. reference can lead to a full-scale error in the DAC. To A ground line routed between the SDIN and SCLK lines helps minimize these errors, a reference with low initial accuracy reduce crosstalk between them (this is not required on a error specification is preferred. Choosing a reference with multilayer board that has a separate ground plane, but separating an output trim adjustment, such as the ADR421, allows a the lines does help). It is essential to minimize noise on the system designer to trim out system errors by setting the REFIN line because any unwanted signals can couple through reference voltage to a voltage other than the nominal. The to the DAC outputs. trim adjustment can also be used to trim out temperature- Avoid crossover of digital and analog signals. Traces on induced errors. opposite sides of the board should run at right angles to each • The temperature coefficient of a reference output voltage other. This reduces the effects of feedthrough on the board. A affects INL, DNL, and TUE. A reference with a tight microstrip technique is by far the best method, but it is not temperature coefficient specification should be chosen to always possible with a double-sided board. In this technique, reduce the dependence of the DAC output voltage on the component side of the board is dedicated to a ground plane, ambient conditions. and signal traces are placed on the solder side. • Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight Rev. D | Page 28 of 32 06467-011 AD5722/AD5732/AD5752 long-term drift specification ensures that the overall For all interfaces, the DAC output update can be initiated solution remains relatively stable over its entire lifetime. automatically when all the data is clocked in, or it can be LDAC • Reference output voltage noise needs to be considered in performed under the control of . The contents of the high accuracy applications that have relatively low noise registers can be read using the readback function. budgets. It is important to choose a reference with as low AD5722/AD5732/AD5752 to Blackfin® DSP Interface an output noise voltage as practical for the required system Figure 44 shows how the AD5722/AD5732/AD5752 can be resolution. Precision voltage references such as the ADR431 interfaced to the Analog Devices Blackfin DSP. The Blackfin has (XFET® design) produce low output noise in the 0.1 Hz to an integrated SPI port that can be connected directly to the SPI 10 Hz range. However, as the circuit bandwidth increases, pins of the AD5722/AD5732/AD5752 and the programmable I/O filtering the output of the reference may be required to pins that can be used to set the state of a digital input such as minimize the output noise. the LDAC pin. MICROPROCESSOR INTERFACING SPISELx SYNC Microprocessor interfacing to the AD5722/AD5732/AD5752 is SCK SCLK via a serial bus that uses a standard protocol compatible with MOSI SDIN microcontrollers and DSP processors. The communications AD5722/ channel is a 3-wire (minimum) interface consisting of a clock AD5732/ ADSP-BF531 AD5752 signal, a data signal, and a synchronization signal. The AD5722/ AD5732/AD5752 require a 24-bit data-word with data valid on PF10 LDAC the falling edge of SCLK. Figure 44. AD5722/AD5732/AD5752 to Blackfin Interface Table 28. Some Precision References Recommended for Use with the AD5722/AD5732/AD5752 Part No. Initial Accuracy (mV max) Long-Term Drift (ppm typ) Temp Drift (ppm/°C max) 0.1 Hz to 10 Hz Noise (μV p-p typ) ADR431 ±1 40 3 3.5 ADR421 ±1 50 3 1.75 ADR03 ±2.5 50 3 6 ADR291 ±2 50 8 8 AD780 ±1 20 3 4 Rev. D | Page 29 of 32 06467-012 AD5722/AD5732/AD5752 OUTLINE DIMENSIONS 5.02 7.90 5.00 7.80 4.95 7.70 24 13 4.50 3.25 EXPOSED PAD 4.40 3.20 (Pins Up) 4.30 3.15 6.40 BSC 1 12 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 1.05 1.20 MAX THE PIN CONFIGURATION AND 1.00 8° FUNCTION DESCRIPTIONS 0.80 SECTION OF THIS DATA SHEET. 0° 0.20 0.15 0.30 0.65 0.75 SEATING 0.09 0.05 BSC 0.19 PLANE 0.60 0.10 COPLANARITY 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-ADT Figure 45. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters ORDERING GUIDE 1 Model Resolution (Bits) Temperature Range INL TUE (% FSR) Package Description Package Option AD5722AREZ 12 −40°C to +85°C ±1 LSB ±0.3 24-Lead TSSOP_EP RE-24 AD5722AREZ-REEL7 12 −40°C to +85°C ±1 LSB ±0.3 24-Lead TSSOP_EP RE-24 AD5732AREZ 14 −40°C to +85°C ±4 LSB ±0.3 24-Lead TSSOP_EP RE-24 AD5732AREZ-REEL7 14 −40°C to +85°C ±4 LSB ±0.3 24-Lead TSSOP_EP RE-24 AD5752AREZ 16 −40°C to +85°C ±16 LSB ±0.3 24-Lead TSSOP_EP RE-24 AD5752AREZ-REEL7 16 −40°C to +85°C ±16 LSB ±0.3 24-Lead TSSOP_EP RE-24 1 Z = RoHS Compliant Part. Rev. D | Page 30 of 32 061708-A AD5722/AD5732/AD5752 NOTES Rev. D | Page 31 of 32 AD5722/AD5732/AD5752 NOTES ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06467-0-7/11(D) Rev. D | Page 32 of 32