ANALOG DEVICES AD5684R

Quad, 16-/14-/12-Bit nanoDAC+ with 2 ppm/°C Reference, SPI Interface Data Sheet AD5686R/AD5685R/AD5684R FEATURES FUNCTIONAL BLOCK DIAGRAM High relative accuracy (INL): ±2 LSB maximum @ 16 bits Low drift 2.5 V reference: 2 ppm/°C typical V GND V DD REF Tiny package: 3 mm × 3 mm, 16-lead LFCSP AD5686R/AD5685R/AD5684R 2.5V REFERENCE V Total unadjusted error (TUE): ±0.1% of FSR maximum LOGIC INPUT DAC STRING V A OUT DAC A REGISTER REGISTER Offset error: ±1.5 mV maximum SCLK BUFFER Gain error: ±0.1% of FSR maximum INPUT DAC STRING V B OUT REGISTER REGISTER DAC B High drive capability: 20 mA, 0.5 V from supply rails SYNC BUFFER User selectable gain of 1 or 2 (GAIN pin) INPUT DAC STRING SDIN V C Reset to zero scale or midscale (RSTSEL pin) OUT REGISTER REGISTER DAC C BUFFER 1.8 V logic compatibility SDO INPUT DAC STRING 50 MHz SPI with readback or daisy chain V D OUT REGISTER REGISTER DAC D BUFFER Low glitch: 0.5 nV-sec POWER- POWER-ON GAIN Robust 4 kV HBM and 1.5 kV FICDM ESD rating RESET ×1/×2 DOWN LOGIC Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply LDAC RESET RSTSEL GAIN −40°C to +105°C temperature range Figure 1. APPLICATIONS Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems Table 1. Quad nanoDAC+ Devices GENERAL DESCRIPTION Interface Reference 16-Bit 14-Bit 12-Bit The AD5686R/AD5685R/AD5684R, members of the SPI Internal AD5686R AD5685R AD5684R nanoDAC+® family, are low power, quad, 16-/14-/12-bit 2 IC Internal AD5696R AD5695R AD5694R buffered voltage output DACs. The devices include a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from a single 2.7 V to 5.5 V PRODUCT HIGHLIGHTS supply, are guaranteed monotonic by design, and exhibit less 1. High Relative Accuracy (INL). than 0.1% FSR gain error and 1.5 mV offset error performance. AD5686R (16-bit): ±2 LSB maximum The devices are available in a 3 mm × 3 mm LFCSP and a AD5685R (14-bit): ±1 LSB maximum TSSOP package. AD5684R (12-bit): ±1 LSB maximum The AD5686R/AD5685R/AD5684R also incorporate a power- 2. Low Drift 2.5 V On-Chip Reference. on reset circuit and a RSTSEL pin that ensures that the DAC 2 ppm/°C typical temperature coefficient outputs power up to zero scale or midscale and remains there 5 ppm/°C maximum temperature coefficient until a valid write takes place. Each part contains a per-channel 3. Two Package Options. power-down feature that reduces the current consumption of 3 mm × 3 mm, 16-lead LFCSP the device to 4 μA at 3 V while in power-down mode. 16-lead TSSOP The AD5686R/AD5685R/AD5684R employ a versatile SPI interface that operates at clock rates up to 50 MHz, and all devices contain a VLOGIC pin intended for 1.8 V/3 V/5 V logic. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 10485-001 AD5686R/AD5685R/AD5684R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Write and Update Commands .................................................. 22 Applications ....................................................................................... 1 Daisy-Chain Operation ............................................................. 23 Functional Block Diagram .............................................................. 1 Readback Operation .................................................................. 23 General Description ......................................................................... 1 Power-Down Operation ............................................................ 24 Product Highlights ........................................................................... 1 LDAC Load DAC (Hardware Pin) ........................................... 25 Revision History ............................................................................... 2 LDAC Mask Register ................................................................. 25 Specif ica t ions ..................................................................................... 3 Hardware Reset ( ) .......................................................... 26 RESET AC Characteristics ........................................................................ 5 Reset Select Pin (RSTSEL) ........................................................ 26 Timing Characteristics ................................................................ 6 Internal Reference Setup ........................................................... 26 Daisy-Chain and Readback Timing Characteristics ............... 7 Solder Heat Reflow ..................................................................... 26 Absolute Maximum Ratings ............................................................ 9 Long-Term Temperature Drift ................................................. 26 ESD Caution .................................................................................. 9 Thermal Hysteresis .................................................................... 27 Pin Configuration and Function Descriptions ........................... 10 Applications Information .............................................................. 28 Typical Performance Characteristics ........................................... 11 Microprocessor Interfacing ....................................................... 28 Terminology .................................................................................... 18 AD5686R/AD5685R/AD5684R to ADSP-BF531 Interface .. 28 Theory of Operation ...................................................................... 20 AD5686R/AD5685R/AD5684R to SPORT Interface ............ 28 Digital-to-Analog Converter .................................................... 20 Layout Guidelines....................................................................... 28 Transfer Function ....................................................................... 20 Galvanically Isolated Interface ................................................. 29 DAC Architecture ....................................................................... 20 Outline Dimensions ....................................................................... 30 Serial Interface ............................................................................ 21 Ordering Guide .......................................................................... 31 Standalone Operation ................................................................ 22 REVISION HISTORY 4/12—Revision 0: Initial Version Rev. 0 | Page 2 of 32 Data Sheet AD5686R/AD5685R/AD5684R SPECIFICATIONS VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF. Table 2. 1 1 B Grade A Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments 2 STATIC PERFORMANCE AD5686R Resolution 16 16 Bits Relative Accuracy ±2 ±8 ±1 ±2 LSB Gain = 2 ±2 ±8 ±1 ±3 Gain = 1 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design AD5685R Resolution 14 14 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design AD5684R Resolution 12 12 Bits Relative Accuracy ±0.12 ±2 ±0.12 ±1 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design Zero-Code Error 0.4 4 0.4 1.5 mV All zeros loaded to DAC register Offset Error +0.1 ±4 +0.1 ±1.5 mV Full-Scale Error +0.01 ±0.2 +0.01 ±0.1 % of All ones loaded to DAC register FSR Gain Error ±0.02 ±0.2 ±0.02 ±0.1 % of FSR Total Unadjusted Error ±0.01 ±0.25 ±0.01 ±0.1 % of External reference; gain = 2; TSSOP FSR % of ±0.25 ±0.2 Internal reference; gain = 1; TSSOP FSR 3 Offset Error Drift ±1 ±1 µV/°C Gain Temperature ±1 ±1 ppm Of FSR/°C 3 Coefficient DC Power Supply Rejection 0.15 0.15 mV/V DAC code = midscale; VDD = 5 V ± 10% 3 Ratio 3 DC Crosstalk ±2 ±2 µV Due to single channel, full-scale output change ±3 ±3 µV/mA Due to load current change ±2 ±2 µV Due to powering down (per channel) 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 V 0 V V Gain = 1 REF REF 0 2 × V 0 2 × V V Gain = 2, see Figure 34 REF REF Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF R = 1 kΩ L 4 Resistive Load 1 1 kΩ Load Regulation 80 80 µV/mA 5 V ± 10%, DAC code = midscale; −30 mA ≤ I ≤ 30 mA OUT 80 80 µV/mA 3 V ± 10%, DAC code = midscale; −20 mA ≤ I ≤ 20 mA OUT 5 Short-Circuit Current 40 40 mA 6 Load Impedance at Rails 25 25 Ω See Figure 34 Coming out of power-down mode; Power-Up Time 2.5 2.5 µs VDD = 5 V Rev. 0 | Page 3 of 32 AD5686R/AD5685R/AD5684R Data Sheet 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments REFERENCE OUTPUT 7 Output Voltage 2.4975 2.5025 2.4975 2.5025 V At ambient 8, 9 Reference TC 5 20 2 5 ppm/°C See the Terminology section 3 0.04 0.04 Ω Output Impedance 3 12 12 0.1 Hz to 10 Hz Output Voltage Noise µV p-p Output Voltage Noise 240 240 nV/√Hz At ambient; f = 10 kHz, CL = 10 nF 3 Density 3 Load Regulation Sourcing 20 20 µV/mA At ambient 3 40 40 µV/mA At ambient Load Regulation Sinking Output Current Load mA VDD ≥ 3 V ±5 ±5 3 Capability 3 100 100 µV/V At ambient Line Regulation 3 12 12 ppm After 1000 hours at 125°C Long-Term Stability/Drift 3 Thermal Hysteresis 125 125 ppm First cycle 25 25 ppm Additional cycles 3 LOGIC INPUTS Input Current ±2 ±2 µA Per pin V , Input Low Voltage 0.3 × V 0.3 × V V INL LOGIC LOGIC V , Input High Voltage 0.7 × V 0.7 × V V INH LOGIC LOGIC Pin Capacitance 2 2 pF 3 LOGIC OUTPUTS (SDO) Output Low Voltage, V 0.4 0.4 V OL ISINK = 200 μA Output High Voltage, V V − 0.4 V − 0.4 V OH LOGIC LOGIC ISOURCE = 200 μA Floating State Output 4 4 pF Capacitance POWER REQUIREMENTS V 1.8 5.5 1.8 5.5 V LOGIC ILOGIC 3 3 µA V 2.7 5.5 2.7 5.5 V Gain = 1 DD V V + 1.5 5.5 V + 1.5 5.5 V Gain = 2 DD REF REF I V = V , V = GND, V = 2.7 V to 5.5 V DD IH DD IL DD 10 Normal Mode 0.59 0.7 0.59 0.7 mA Internal reference off 1.1 1.3 1.1 1.3 mA Internal reference on, at full scale All Power-Down 1 4 1 4 µA −40°C to +85°C 11 Modes 6 6 µA −40°C to +105°C 1 Temperature range: A and B grade: −40°C to +105°C. 2 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 = V with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5686R), 64 to 16,320 (AD5685R), and 12 to 4080 (AD5684R). DD 3 Guaranteed by design and characterization; not production tested. 4 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to 30 mA up to a junction temperature of 110°C. 5 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. Operation above the specified maximum operation junction temperature may impair device reliability. 6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 34). 7 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section. 8 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C. 9 Reference temperature coefficient calculated as per the box method. See the Terminology section for further information. 10 Interface inactive. All DACs active. DAC outputs unloaded. 11 All DACs powered down. Rev. 0 | Page 4 of 32 Data Sheet AD5686R/AD5685R/AD5684R AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise 1 noted. Table 3. 2 3 Parameter Min Typ Max Unit Test Conditions/Comments Output Voltage Settling Time AD5686R 5 8 µs ¼ to ¾ scale settling to ±2 LSB AD5685R 5 8 µs ¼ to ¾ scale settling to ±2 LSB AD5684R 5 7 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry Digital Feedthrough 0.13 nV-sec Digital Crosstalk 0.1 nV-sec Analog Crosstalk 0.2 nV-sec DAC-to-DAC Crosstalk 0.3 nV-sec 4 Total Harmonic Distortion −80 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT Output Noise Spectral Density 300 nV/√Hz DAC code = midscale, 10 kHz; gain = 2 Output Noise 6 µV p-p 0.1 Hz to 10 Hz SNR 90 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz SFDR 83 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT SINAD 80 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical @ 25°C. 4 Digitally generated sine wave @ 1 kHz. Rev. 0 | Page 5 of 32 AD5686R/AD5685R/AD5684R Data Sheet TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREFIN = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. < 2.7 V 2.7 V ≤ V ≤ 5.5 V 1.8 V ≤ VLOGIC LOGIC 1 Parameter Symbol Min Max Min Max Unit SCLK Cycle Time t 33 20 ns 1 SCLK High Time t 16 10 ns 2 SCLK Low Time t3 16 10 ns SYNC to SCLK Falling Edge Setup Time t4 15 10 ns Data Setup Time t5 5 5 ns Data Hold Time t 5 5 ns 6 SCLK Falling Edge to SYNC Rising Edge t 15 10 ns 7 Minimum High Time (Single, Combined or All Channel Update) t 20 20 ns SYNC 8 SYNC Falling Edge to SCLK Fall Ignore t9 16 10 ns LDAC Pulse Width Low t10 25 15 ns SCLK Falling Edge to LDAC Rising Edge t11 30 20 ns SCLK Falling Edge to LDAC Falling Edge t 20 20 ns 12 RESET Minimum Pulse Width Low t 30 30 ns 13 Pulse Activation Time t 30 30 ns RESET 14 2 Power-Up Time 4.5 4.5 µs 1 Maximum SCLK frequency is 50 MHz at V = 2.7 V to 5.5 V, 1.8 V ≤ V ≤ V . Guaranteed by design and characterization; not production tested. DD LOGIC DD 2 nd Time to exit power-down to normal mode of AD5686R/AD5685R/AD5684R operation, 32 clock edge to 90% of DAC midscale value, with output unloaded. t 9 t 1 SCLK t 2 t 8 t t 3 7 t 4 SYNC t 6 t 5 SDIN DB23 DB0 t 10 t 12 1 LDAC t 11 2 LDAC t RESET 13 t V 14 OUT 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Write Operation Rev. 0 | Page 6 of 32 10485-002 Data Sheet AD5686R/AD5685R/AD5684R DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD = 2.7 V to 5.5 V. Table 5. 1.8 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V 1 Parameter Symbol Min Max Min Max Unit SCLK Cycle Time t 66 40 ns 1 SCLK High Time t 33 20 ns 2 SCLK Low Time t3 33 20 ns SYNC to SCLK Falling Edge t4 33 20 ns Data Setup Time t 5 5 ns 5 Data Hold Time t 5 5 ns 6 SCLK Falling Edge to Rising Edge t 15 10 ns SYNC 7 Minimum SYNC High Time t8 60 30 ns Minimum SYNC High Time t9 60 30 ns SDO Data Valid from SCLK Rising Edge t 36 25 ns 10 5 SCLK Falling Edge to SYNC Rising Edge t 15 10 ns 11 5 SYNC Rising Edge to SCLK Rising Edge t12 15 10 ns 1 Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested. Circuit and Timing Diagrams 200µA I OL TO OUTPUT V (MIN) OH PIN C L 20pF 200µA I OH Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications SCLK 24 48 t t 11 8 t 12 t 4 SYNC t 6 t 5 DB23 DB0 DB23 DB0 SDIN INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 t 10 DB23 DB0 SDO UNDEFINED INPUT WORD FOR DAC N Figure 4. Daisy-Chain Timing Diagram Rev. 0 | Page 7 of 32 10485-003 10485-004 AD5686R/AD5685R/AD5684R Data Sheet t 1 SCLK 24 24 1 1 t 3 t 7 t t t 9 4 2 t 8 SYNC t 6 t 5 DB23 DB0 DB23 DB0 SDIN INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ t 10 SDO DB23 DB0 DB23 DB0 UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 5. Readback Timing Diagram Rev. 0 | Page 8 of 32 10485-005 Data Sheet AD5686R/AD5685R/AD5684R ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute V to GND −0.3 V to +7 V LOGIC maximum rating conditions for extended periods may affect VOUT to GND −0.3 V to VDD + 0.3 V device reliability. VREF to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to V + 0.3 V LOGIC Operating Temperature Range −40°C to +105°C ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature 125°C 16-Lead TSSOP, θJA Thermal 112.6°C/W Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, θ Thermal 70°C/W JA Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak 260°C Temperature, Pb Free (J-STD-020) 1 ESD 4 kV FICDM 1.5 kV 1 Human body model (HBM) classification. Rev. 0 | Page 9 of 32 AD5686R/AD5685R/AD5684R Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD5686R/AD5685R/AD5684R 1 V A 12 SDIN OUT GND 2 11 SYNC V 1 16 RSTSEL REF V 3 10 SCLK DD 2 15 RESET V B OUT 4 9 V V C AD5686R/ OUT LOGIC V A 3 14 SDIN OUT AD5685R/ AD5684R 4 13 SYNC GND TOP VIEW V 5 12 SCLK DD (Not to Scale) V C 6 11 V OUT LOGIC TOP VIEW (Not to Scale) 7 10 V D GAIN OUT SDO 8 9 LDAC NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. Figure 6. 16-Lead LFCSP Pin Configuration Figure 7. 16-Lead TSSOP Pin Configuration Table 6. Pin Function Descriptions Pin No. LFCSP TSSOP Mnemonic Description 1 3 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 2 4 GND Ground Reference Point for All Circuitry on the Part. 3 5 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be DD decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4 6 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 5 7 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 6 8 SDO Serial Data Output. Can be used to daisy-chain a number of AD5686R/AD5685R/AD5684R devices together or can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 7 9 LDAC LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can also be tied permanently low. 8 10 GAIN Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to V . If this REF pin is tied to V , all four DACs output a span of 0 V to 2 × V . DD REF 9 11 VLOGIC Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V. 10 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. 11 13 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 24 clocks. 12 14 SDIN Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 15 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to 14 16 RSTSEL V powers up all four DACs to midscale. DD 15 1 VREF Reference Voltage. The AD5686R/AD5685R/AD5684R have a common reference pin. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference output. 16 2 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND. Rev. 0 | Page 10 of 32 10485-006 10485-007 V D 5 16 V B OUT OUT SDO 6 15 V REF LDAC 7 14 RSTSEL GAIN 8 13 RESET Data Sheet AD5686R/AD5685R/AD5684R TYPICAL PERFORMANCE CHARACTERISTICS 2.5020 0 HOUR V = 5.5V DD DEVICE 1 V = 5V DD 60 168 HOURS DEVICE 2 2.5015 500 HOURS DEVICE 3 1000 HOURS DEVICE 4 50 DEVICE 5 2.5010 2.5005 40 2.5000 30 2.4995 20 2.4990 10 2.4985 0 2.4980 2.498 2.499 2.500 2.501 2.502 –40 –20 0 20 40 60 80 100 120 V (V) TEMPERATURE (°C) REF Figure 8. Internal Reference Voltage vs. Temperature (Grade B) Figure 11. Reference Long-Term Stability/Drift 1600 2.5020 V = 5V DD DEVICE 1 T = 25°C A DEVICE 2 1400 2.5015 DEVICE 3 DEVICE 4 DEVICE 5 1200 2.5010 1000 2.5005 800 2.5000 600 2.4995 400 2.4990 200 2.4985 V = 5V DD 0 2.4980 10 100 1k 10k 100k 1M –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) FREQUENCY (MHz) Figure 9. Internal Reference Voltage vs. Temperature (Grade A) Figure 12. Internal Reference Noise Spectral Density vs. Frequency 90 V = 5V DD V = 5V DD T 80 T = 25°C A 70 60 50 1 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CH1 10µV M1.0s A CH1 160mV TEMPERATURE DRIFT (ppm/°C) Figure 13. Internal Reference Noise, 0.1 Hz to 10 Hz Figure 10. Reference Output Temperature Drift Histogram Rev. 0 | Page 11 of 32 NUMBER OF UNITS V (V) V (V) REF REF 10485-109 10485-212 10485-250 NSD (nV/ Hz) HITS 10485-112 10485-251 10485-111 AD5686R/AD5685R/AD5684R Data Sheet 2.5000 10 V = 5V DD T = 25°C A 8 2.4999 6 2.4998 4 2 2.4997 0 2.4996 –2 –4 2.4995 –6 2.4994 V = 5V DD –8 T = 25°C A INTERNAL REFERENCE = 2.5V 2.4993 –10 –0.005 –0.003 –0.001 0.001 0.003 0.005 0 2500 5000 7500 10000 12500 15000 16348 I (A) LOAD CODE Figure 14. Internal Reference Voltage vs. Load Current Figure 17. AD5685R INL 2.5002 10 T = 25°C A D1 8 2.5000 6 4 2.4998 D3 2 2.4996 0 –2 2.4994 –4 –6 2.4992 D2 V = 5V DD –8 T = 25°C A 2.4990 INTERNAL REFERENCE = 2.5V –10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 625 1250 1875 2500 3125 3750 4096 V (V) DD CODE Figure 15. Internal Reference Voltage vs. Supply Voltage Figure 18. AD5684R INL 10 1.0 0.8 8 6 0.6 4 0.4 0.2 2 0 0 –2 –0.2 –0.4 –4 –6 –0.6 V = 5V V = 5V DD DD –8 –0.8 T = 25°C T = 25°C A A INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V –1.0 –10 0 10000 20000 30000 40000 50000 60000 0 10000 20000 30000 40000 50000 60000 CODE CODE Figure 16. AD5686R INL Figure 19. AD5686R DNL Rev. 0 | Page 12 of 32 V (V) REF V (V) REF INL (LSB) 10485-118 10485-117 10485-113 INL (LSB) INL (LSB) DNL (LSB) 10485-121 10485-120 10485-119 Data Sheet AD5686R/AD5685R/AD5684R 10 1.0 8 0.8 6 0.6 4 0.4 2 0.2 INL 0 0 DNL –2 –0.2 –4 –0.4 –6 –0.6 V = 5V V = 5V DD DD –8 –0.8 T = 25°C T = 25°C A A INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V –10 –1.0 05 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5.0 0 2500 5000 7500 10000 12500 15000 16383 V (V) CODE REF Figure 20. AD5685R DNL Figure 23. INL Error and DNL Error vs. V REF 1.0 10 8 0.8 0.6 6 4 0.4 0.2 2 INL 0 0 DNL –2 –0.2 –0.4 –4 –6 –0.6 V = 5V V = 5V DD DD –0.8 –8 T = 25°C T = 25°C A A INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V –1.0 –10 2.7 3.2 3.7 4.2 4.7 5.2 0 625 1250 1875 2500 3125 3750 4096 CODE SUPPLY VOLTAGE (V) Figure 24. INL Error and DNL Error vs. Supply Voltage Figure 21. AD5684R DNL 10 0.10 8 0.08 6 0.06 4 0.04 FULL-SCALE ERROR 2 0.02 INL 0 0 DNL GAIN ERROR –2 –0.02 –4 –0.04 –6 –0.06 V = 5V V = 5V DD DD –8 –0.08 T = 25°C T = 25°C A A INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V –10 –0.10 –40 10 60 110 –40 –20 0 20406080 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 22. INL Error and DNL Error vs. Temperature Figure 25. Gain Error and Full-Scale Error vs. Temperature Rev. 0 | Page 13 of 32 DNL (LSB) DNL (LSB) ERROR (LSB) 10485-124 10485-123 10485-122 ERROR (LSB) ERROR (% of FSR) ERROR (LSB) 10485-127 10485-126 10485-125 AD5686R/AD5685R/AD5684R Data Sheet 0.10 V = 5V V = 5V DD DD 1.4 T = 25°C T = 25°C A 0.09 A INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V 0.08 1.2 0.07 1.0 0.06 0.8 0.05 0.6 0.04 0.03 0.4 ZERO-CODE ERROR 0.02 0.2 0.01 OFFSET ERROR 0 0 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 26. Zero-Code Error and Offset Error vs. Temperature Figure 29. TUE vs. Temperature 0.10 0.10 0.08 0.08 0.06 0.06 0.04 0.04 0.02 0.02 GAIN ERROR 0 0 FULL-SCALE ERROR –0.02 –0.02 –0.04 –0.04 –0.06 –0.06 V = 5V V = 5V DD DD –0.08 –0.08 T = 25°C T = 25°C A A INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V –0.10 –0.10 2.7 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 30. TUE vs. Supply, Gain = 1 Figure 27. Gain Error and Full-Scale Error vs. Supply 1.5 0 –0.01 1.0 –0.02 0.5 –0.03 ZERO-CODE ERROR –0.04 0 –0.05 OFFSET ERROR –0.06 –0.5 –0.07 –1.0 V = 5V –0.08 DD T = 25°C A V = 5V DD INTERNAL REFERENCE = 2.5V –0.09 T = 25°C A –1.5 INTERNAL REFERENCE = 2.5V 2.7 3.2 3.7 4.2 4.7 5.2 –0.10 0 10000 20000 30000 40000 50000 60000 65535 SUPPLY VOLTAGE (V) CODE Figure 28. Zero-Code Error and Offset Error vs. Supply Figure 31. TUE vs. Code Rev. 0 | Page 14 of 32 ERROR (mV) ERROR (% of FSR) ERROR (mV) 10485-130 10485-129 10485-128 TOTAL UNADJUSTED ERROR (% of FSR) TOTAL UNADJUSTED ERROR (% of FSR) TOTAL UNADJUSTED ERROR (% of FSR) 10485-132 10485-131 10485-133 Data Sheet AD5686R/AD5685R/AD5684R 7 V = 5V DD V = 5V DD 25 T = 25°C A T = 25°C A 6 EXTERNAL GAIN = 2 REFERENCE = 2.5V INTERNAL 0xFFFF 5 REFERENCE = 2.5V 20 4 0xC000 15 3 0x8000 2 0x4000 10 1 0x0000 0 5 –1 0 –2 540 560 580 600 620 640 –0.06 –0.04 –0.02 0 0.02 0.04 0.06 I (V) DD LOAD CURRENT (A) Figure 32. I Histogram with External Reference, 5 V Figure 35. Source and Sink Capability at 5 V DD 5 V = 5V DD V = 5V DD 30 T = 25°C A T = 25°C A INTERNAL 4 EXTERNAL REFERENCE = 2.5V REFERENCE = 2.5V GAIN = 1 25 0xFFFF 3 0xC000 20 2 0x8000 15 1 0x4000 10 0 0x0000 5 –1 0 –2 1000 1020 1040 1060 1080 1100 1120 1140 –0.06 –0.04 –0.02 0 0.02 0.04 0.06 I FULLSCALE (V) DD LOAD CURRENT (A) Figure 36. Source and Sink Capability at 3 V Figure 33. IDD Histogram with Internal Reference, VREFOUT = 2.5 V, Gain = 2 1.0 1.4 0.8 0.6 1.2 FULL-SCALE 0.4 1.0 ZERO CODE SINKING 2.7V 0.2 SINKING 5V 0.8 0 EXTERNAL REFERENCE, FULL-SCALE –0.2 0.6 SOURCING 5V –0.4 0.4 –0.6 SOURCING 2.7V 0.2 –0.8 –1.0 0 0 5 10 15 20 25 30 –40 10 60 110 LOAD CURRENT (mA) TEMPERATURE (°C) Figure 34. Headroom/Footroom vs. Load Current Figure 37. Supply Current vs. Temperature Rev. 0 | Page 15 of 32 ΔV (V) OUT HITS HITS 10485-135 10485-136 10485-200 V (V) V (V) OUT OUT CURRENT (mA) 10485-140 10485-139 10485-138 AD5686R/AD5685R/AD5684R Data Sheet 2.5008 4.0 DAC A DAC B 3.5 DAC C DAC D 3.0 2.5003 2.5 2.4998 2.0 1.5 CHANNEL B 1.0 2.4993 T = 25°C A V = 5.25V V = 5V DD DD INTERNAL REFERENCE 0.5 T = 25°C A CODE = 7FFF TO 8000 INTERNAL REFERENCE = 2.5V ENERGY = 0.227206nV-sec ¼ TO ¾ SCALE 0 2.4988 0 2 4 6 8 10 12 10 20 40 80 160 320 TIME (µs) TIME (µs) Figure 38. Settling Time, 5.25 V Figure 41. Digital-to-Analog Glitch Impulse 0.06 6 0.003 CH A CH B CH B CH C CH C 0.05 5 CH D CH D V 0.002 DD 0.04 4 0.001 0.03 3 0.02 2 0 0.01 1 –0.001 0 0 T = 25°C A INTERNAL REFERENCE = 2.5V –0.01 –1 –0.002 –10 –5 0 5 10 15 0 5 10 15 20 25 TIME (µs) TIME (µs) Figure 39. Power-On Reset to 0 V Figure 42. Analog Crosstalk, Channel A 3 CH A CH B T CH C GAIN = 2 CH D SYNC 2 GAIN = 1 1 1 V = 5V DD V = 5V T = 25°C DD A T = 25°C INTERNAL REFERENCE = 2.5V A 0 EXTERNAL REFERENCE = 2.5V –5 0 5 10 TIME (µs) CH1 10µV M1.0s A CH1 802mV Figure 40. Exiting Power-Down to Midscale Figure 43. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Rev. 0 | Page 16 of 32 V (V) V (V) OUT OUT V (V) OUT 10485-143 V (V) DD 10485-142 10485-141 V (V) V AC-COUPLED (V) OUT OUT 10485-146 10485-145 10485-144 Data Sheet AD5686R/AD5685R/AD5684R 4.0 0nF V = 5V DD 0.1nF T = 25°C A 3.9 T 10nF INTERNAL REFERENCE = 2.5V 0.22nF 3.8 4.7nF 3.7 3.6 3.5 1 3.4 3.3 3.2 3.1 V = 5V DD T = 25°C A 3.0 INTERNAL REFERENCE = 2.5V 1.590 1.595 1.600 1.605 1.610 1.615 1.620 1.625 1.630 TIME (ms) CH1 10µV M1.0s A CH1 802mV Figure 47. Settling Time vs. Capacitive Load Figure 44. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference 0 1600 V = 5V DD FULL-SCALE T = 25°C A MIDSCALE 1400 –10 INTERNAL REFERENCE = 2.5V ZERO-SCALE 1200 –20 1000 –30 800 600 –40 400 –50 V = 5V DD 200 T = 25°C A EXTERNAL REFERENCE = 2.5V, ±0.1V p-p –60 0 10k 100k 1M 10M 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 48. Multiplying Bandwidth, External Reference = 2.5 V, ±0.1 V p-p, Figure 45. Noise Spectral Density 10 kHz to 10 MHz 20 V = 5V DD T = 25°C A 0 INTERNAL REFERENCE = 2.5V –20 –40 –60 –80 –100 –120 –140 –160 –180 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 FREQUENCY (Hz) Figure 46. Total Harmonic Distortion @ 1 kHz Rev. 0 | Page 17 of 32 THD (dBV) NSD (nV/ Hz) 10485-147 10485-148 10485-149 V (V) BANDWIDTH (dB) OUT 10485-151 10485-150 AD5686R/AD5685R/AD5684R Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Output Voltage Settling Time For the DAC, relative accuracy or integral nonlinearity is a This is the amount of time it takes for the output of a DAC to measurement of the maximum deviation, in LSBs, from a settle to a specified level for a ¼ to ¾ full-scale input change straight line passing through the endpoints of the DAC transfer and is measured from the rising edge of SYNC. function. A typical INL vs. code plot is shown in Figure 16. Digital-to-Analog Glitch Impulse Differential Nonlinearity (DNL) Digital-to-analog glitch impulse is the impulse injected into the Differential nonlinearity is the difference between the measured analog output when the input code in the DAC register changes change and the ideal 1 LSB change between any two adjacent state. It is normally specified as the area of the glitch in nV-sec, codes. A specified differential nonlinearity of ±1 LSB maximum and is measured when the digital input code is changed by ensures monotonicity. This DAC is guaranteed monotonic by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see design. A typical DNL vs. code plot can be seen in Figure 19. Figure 41). Zero-Code Error Digital Feedthrough Zero-code error is a measurement of the output error when Digital feedthrough is a measure of the impulse injected into the zero code (0x0000) is loaded to the DAC register. Ideally, the analog output of the DAC from the digital inputs of the DAC, output should be 0 V. The zero-code error is always positive in but is measured when the DAC output is not updated. It is the AD5686R because the output of the DAC cannot go below specified in nV-sec, and measured with a full-scale code change 0 V due to a combination of the offset errors in the DAC and on the data bus, that is, from all 0s to all 1s and vice versa. the output amplifier. Zero-code error is expressed in mV. A plot Reference Feedthrough of zero-code error vs. temperature can be seen in Figure 26. Reference feedthrough is the ratio of the amplitude of the signal Full-Scale Error at the DAC output to the reference input when the DAC output Full-scale error is a measurement of the output error when full- is not being updated. It is expressed in dB. scale code (0xFFFF) is loaded to the DAC register. Ideally, the Noise Spectral Density output should be V − 1 LSB. Full-scale error is expressed in DD This is a measurement of the internally generated random percent of full-scale range (% of FSR). A plot of full-scale error noise. Random noise is characterized as a spectral density vs. temperature can be seen in Figure 25. (nV/√Hz). It is measured by loading the DAC to midscale and Gain Error measuring noise at the output. It is measured in nV/√Hz. A plot This is a measure of the span error of the DAC. It is the deviation of noise spectral density is shown in Figure 45. in slope of the DAC transfer characteristic from the ideal DC Crosstalk expressed as % of FSR. DC crosstalk is the dc change in the output level of one DAC in Offset Error Drift response to a change in the output of another DAC. It is This is a measurement of the change in offset error with a measured with a full-scale output change on one DAC (or soft change in temperature. It is expressed in µV/°C. power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. Gain Temperature Coefficient This is a measurement of the change in gain error with changes DC crosstalk due to load current change is a measure of the in temperature. It is expressed in ppm of FSR/°C. impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in μV/mA. Offset Error Offset error is a measure of the difference between V (actual) Digital Crosstalk OUT and V (ideal) expressed in mV in the linear region of the This is the glitch impulse transferred to the output of one DAC OUT at midscale in response to a full-scale code change (all 0s to all transfer function. Offset error is measured on the AD5686R with Code 512 loaded in the DAC register. It can be negative 1s and vice versa) in the input register of another DAC. It is or positive. measured in standalone mode and is expressed in nV-sec. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V to OUT a change in V for full-scale output of the DAC. It is measured DD in mV/V. VREF is held at 2 V, and VDD is varied by ±10%. Rev. 0 | Page 18 of 32 Data Sheet AD5686R/AD5685R/AD5684R Analog Crosstalk Total Harmonic Distortion (THD) This is the glitch impulse transferred to the output of one DAC This is the difference between an ideal sine wave and its due to a change in the output of another DAC. It is measured by attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). Then execute a software LDAC harmonics present on the DAC output. It is measured in dB. and monitor the output of the DAC whose digital code was not Voltage Reference TC changed. The area of the glitch is expressed in nV-sec. Voltage reference TC is a measure of the change in the reference DAC-to-DAC Crosstalk output voltage with a change in temperature. The reference TC This is the glitch impulse transferred to the output of one DAC is calculated using the box method, which defines the TC as the due to a digital code change and subsequent analog output maximum change in the reference output over a given tempera- change of another DAC. It is measured by loading the attack ture range expressed in ppm/°C, as follows; channel with a full-scale code change (all 0s to all 1s and vice   V −V 6 REFmax REFmin versa), using the write to and update commands while monitor- TC= ×10   V × TempRange  REFnom  ing the output of the victim channel that is at midscale. The   energy of the glitch is expressed in nV-sec. where: Multiplying Bandwidth V is the maximum reference output measured over the REFmax The amplifiers within the DAC have a finite bandwidth. The total temperature range. multiplying bandwidth is a measure of this. A sine wave on the V is the minimum reference output measured over the total REFmin reference (with full-scale code loaded to the DAC) appears on temperature range. the output. The multiplying bandwidth is the frequency at VREFnom is the nominal reference output voltage, 2.5 V. which the output amplitude falls to 3 dB below the input. TempRange is the specified temperature range of −40°C to +105°C. Rev. 0 | Page 19 of 32 AD5686R/AD5685R/AD5684R Data Sheet THEORY OF OPERATION V REF DIGITAL-TO-ANALOG CONVERTER The AD5686R/AD5685R/AD5684R are quad 16-/14-/12-bit, R serial input, voltage output DACs with an internal reference. The parts operate from supply voltages of 2.7 V to 5.5 V. Data is R written to the AD5686R/AD5685R/AD5684R in a 24-bit word format via a 3-wire serial interface. The AD5686R/AD5685R/ TO OUTPUT R AMPLIFIER AD5684R incorporate a power-on reset circuit to ensure that the DAC output powers up to a known output state. The devices also have a software power-down mode that reduces the typical current consumption to typically 4 µA. TRANSFER FUNCTION R The internal reference is on by default. To use an external reference, only a nonreference option is available. Because the R input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by Figure 50. Resistor String Structure D   V = V × Gain REF OUT N   2   Internal Reference where: The AD5686R/AD5685R/AD5684R on-chip reference is on at D is the decimal equivalent of the binary code that is loaded to power-up but can be disabled via a write to a control register. the DAC register as follows: See the Internal Reference Setup section for details. 0 to 4,095 for the 12-bit device. The AD5686R/AD5685R/AD5684R have a 2.5 V, 2 ppm/°C 0 to 16,383 for the 14-bit device. reference, giving a full-scale output of 2.5 V or 5 V, depending 0 to 65,535 for the 16-bit device. on the state of the GAIN pin. The internal reference associated N is the DAC resolution. with the device is available at the V pin. This buffered REF Gain is the gain of the output amplifier and is set to 1 by default. reference is capable of driving external loads of up to 10 mA. This can be set to ×1 or ×2 using the gain select pin. When this Output Amplifiers pin is tied to GND, all four DAC outputs have a span from 0 V The output buffer amplifier can generate rail-to-rail voltages on to V . If this pin is tied to V , all four DACs output a span of REF DD its output, which gives an output range of 0 V to V . The actual 0 V to 2 × V . DD REF range depends on the value of V , the GAIN pin, offset error, REF DAC ARCHITECTURE and gain error. The GAIN pin selects the gain of the output. The DAC architecture consists of a string DAC followed by an • If this pin is tied to GND, all four outputs have a gain of 1 output amplifier. Figure 49 shows a block diagram of the DAC and the output range is 0 V to V . REF architecture. , all four outputs have a gain of 2 • If this pin is tied to VLOGIC V REF and the output range is 0 V to 2 × VREF. 2.5V REF These amplifiers are capable of driving a load of 1 kΩ in parallel REF (+) with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale INPUT DAC RESISTOR V X OUT REGISTER REGISTER STRING settling time of 5 µs. REF (–) GAIN (GAIN = 1 OR 2) GND Figure 49. Single DAC Channel Architecture Block Diagram The resistor string structure is shown in Figure 50. It is a string of resistors, each of Value R. The code loaded to the DAC register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Rev. 0 | Page 20 of 32 10485-052 10485-053 Data Sheet AD5686R/AD5685R/AD5684R Table 7. Command Definitions SERIAL INTERFACE Command The AD5686R/AD5685R/AD5684R have a 3-wire serial C3 C2 C1 C0 Description SYNC, SCLK, and SDIN) that is compatible with interface ( 0 0 0 0 No operation SPI, QSPI, and MICROWIRE interface standards as well as 0 0 0 1 Write to Input Register n (dependent on LDAC) most DSPs. See Figure 2 for a timing diagram of a typical Update DAC Register n with contents of Input 0 0 1 0 write sequence. The AD5686R/AD5685R/AD5684R contain Register n an SDO pin to allow the user to daisy-chain multiple devices 0 0 1 1 Write to and update DAC Channel n 0 1 0 0 Power down/power up DAC together (see the Daisy-Chain Operation section) or for 0 1 0 1 Hardware LDAC mask register readback. 0 1 1 0 Software reset (power-on reset) Input Shift Register 0 1 1 1 Internal reference setup register The input shift register of the AD5686R/AD5685R/AD5684R is 1 0 0 0 Set up DCEN register (daisy-chain enable) 24 bits wide. Data is loaded MSB first (DB23) and the first four 1 0 0 1 Set up readback register (readback enable) 1 0 1 0 Reserved bits are the command bits, C3 to C0 (see Table 7), followed by … … … … Reserved the 4-bit DAC address bits, DAC A, DAC B, DAC C, DAC D 1 1 1 1 Reserved (see Table 8), and finally the bit data-word. The data-word comprises 16-bit, 14-bit, or 12-bit input code, Table 8. Address Commands followed by zero, two or four don’t care bits for the AD5686R, Address (n) 1 AD5685R, and AD5684R, respectively (see Figure 51, Figure 52, DAC D DAC C DAC B DAC A Selected DAC Channel and Figure 53). These data bits are transferred to the input 0 0 0 1 DAC A register on the 24 falling edges of SCLK and are updated on the 0 0 1 0 DAC B 0 1 0 0 DAC C rising edge of SYNC. 1 0 0 0 DAC D Commands can be executed on individual DAC channels, 0 0 1 1 DAC A and DAC B combined DAC channels, or on all DACs, depending on the 1 1 1 1 All DACs address bits selected. 1 Any combination of DAC channels can be selected using the address bits. DB23 (MSB) DB0 (LSB) DAC DAC DAC DAC C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D C B A DATA BITS COMMAND BITS ADDRESS BITS Figure 51. AD5686R Input Shift Register Content DB23 (MSB) DB0 (LSB) DAC DAC DAC DAC C3 C2 C1 C0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X D C B A DATA BITS COMMAND BITS ADDRESS BITS Figure 52. AD5685R Input Shift Register Content DB23 (MSB) DB0 (LSB) DAC DAC DAC DAC C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X D C B A DATA BITS COMMAND BITS ADDRESS BITS Figure 53. AD5684R Input Shift Register Content Rev. 0 | Page 21 of 32 10485-056 10485-055 10485-054 AD5686R/AD5685R/AD5684R Data Sheet STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDAC) The write sequence begins by bringing the SYNC line low. Data from the SDIN line is clocked into the 24-bit input shift register Command 0001 allows the user to write to each DAC’s on the falling edge of SCLK. After the last of 24 data bits is dedicated input register individually. When LDAC is low, SYNC clocked in, should be brought high. The programmed the input register is transparent (if not controlled by the LDAC function is then executed, that is, an -dependent change LDAC mask register). in DAC register contents and/or a change in the mode of Update DAC Register n with Contents of Input Register n th operation. If SYNC is taken high at a clock before the 24 clock, Command 0010 loads the DAC registers/outputs with the it is considered a valid frame and invalid data may be loaded to contents of the input registers selected and updates the DAC the DAC. SYNC must be brought high for a minimum of outputs directly. 20 ns (single channel, see t8 in Figure 2) before the next write SYNC Write to and Update DAC Channel n (Independent of sequence so that a falling edge of can initiate the next ) LDAC SYNC write sequence. should be idled at rails between write sequences for even lower power operation of the part. Command 0011 allows the user to write to the DAC registers The SYNC line is kept low for 24 falling edges of SCLK, and the and update the DAC outputs directly. DAC is updated on the rising edge of SYNC. When the data has been transferred into the input register of the addressed DAC, all DAC registers and outputs can be LDAC SYNC updated by taking low while the line is high. Rev. 0 | Page 22 of 32 Data Sheet AD5686R/AD5685R/AD5684R SYNC DAISY-CHAIN OPERATION DAC. When the serial transfer to all devices is complete, is taken high. This latches the input data in each device in the For systems that contain several DACs, the SDO pin can be daisy chain and prevents any further data from being clocked used to daisy-chain several devices together and is enabled into the input shift register. The serial clock can be continuous or through a software executable daisy-chain enable (DCEN) a gated clock. A continuous SCLK source can be used only command. Command 1000 is reserved for this DCEN function if SYNC can be held low for the correct number of clock cycles. (see Table 7). The daisy-chain mode is enabled by setting In gated clock mode, a burst clock containing the exact number Bit DB0 in the DCEN register. The default setting is standalone SYNC of clock cycles must be used, and must be taken high after mode, where DB0 = 0. Table 9 shows how the state of the bit the final clock to latch the data. corresponds to the mode of operation of the device. READBACK OPERATION Table 9. Daisy-Chain Enable (DCEN) Register Readback mode is invoked through a software executable DB0 Description readback command. If the SDO output is disabled via the daisy- 0 Standalone mode (default) chain mode disable bit in the control register, it is automatically 1 DCEN mode enabled for the duration of the read operation, after which it is AD5686R/ disabled again. Command 1001 is reserved for the readback AD5685R/ 68HC11* AD5684R function. This command, in association with selecting one of SDIN MOSI address bits, DAC A to DAC D, selects the register to read. Note SCK SCLK that only one DAC register can be selected during readback. PC7 SYNC The remaining three address bits must be set to Logic 0. The PC6 LDAC remaining data bits in the write sequence are don’t care bits. If SDO MISO more than one or no bits are selected, DAC Channel A is read back by default. During the next SPI write, the data appearing SDIN on the SDO output contains the data from the previously AD5686R/ addressed register. AD5685R/ AD5684R For example, to read back the DAC register for Channel A, the SCLK following sequence should be implemented: SYNC 1. Write 0x900000 to the AD5686R/AD5685R/AD5684R LDAC input register. This configures the part for read mode with SDO the DAC register of Channel A selected. Note that all data bits, DB15 to DB0, are don’t care bits. 2. Follow this with a second write, a NOP condition, SDIN AD5686R/ 0x000000. During this write, the data from the register is AD5685R/ clocked out on the SDO line. DB23 to DB20 contain AD5684R SCLK undefined data, and the last 16 bits contain the DB19 to SYNC DB4 DAC register contents. LDAC SDO *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 54. Daisy-Chaining the AD5686R/AD5685R/AD5684R The SCLK pin is continuously applied to the input shift register SYNC when is low. If more than 24 clock pulses are applied, the data ripples out of the input shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting this line to the SDIN input on the next DAC in the chain, a daisy-chain interface is constructed. Each DAC in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of devices that are updated. SYNC If is taken high at a clock that is not a multiple of 24, it is considered a valid frame and invalid data may be loaded to the Rev. 0 | Page 23 of 32 10485-057 AD5686R/AD5685R/AD5684R Data Sheet output stage is also internally switched from the output of the POWER-DOWN OPERATION amplifier to a resistor network of known values. This has the The AD5686R/AD5685R/AD5684R contain three separate advantage that the output impedance of the part is known while power-down modes. Command 0100 is designated for the power- the part is in power-down mode. There are three different down function (see Table 7). These power-down modes are power-down options. The output is connected internally to software-programmable by setting eight bits, Bit DB7 to Bit DB0, GND through either a 1 kΩ or a 100 kΩ resistor, or it is left in the input shift register. There are two bits associated with each open-circuited (three-state). The output stage is illustrated in DAC channel. Table 10 shows how the state of the two bits Figure 55. corresponds to the mode of operation of the device. Table 10. Modes of Operation AMPLIFIER V X DAC OUT Operating Mode PDx1 PDx0 Normal Operation 0 0 Power-Down Modes 1 kΩ to GND 0 1 POWER-DOWN RESISTOR CIRCUITRY NETWORK 100 kΩ to GND 1 0 Three-State 1 1 Figure 55. Output Stage During Power-Down Any or all DACs (DAC A to DAC D) can be powered down to the selected mode by setting the corresponding bits. See The bias generator, output amplifier, resistor string, and other Table 11 for the contents of the input shift register during the associated linear circuitry are shut down when the power-down power-down/power-up operation. mode is activated. However, the contents of the DAC register are unaffected when in power-down. The DAC register can be When both Bit PDx1 and Bit PDx0 (where x is the channel updated while the device is in power-down mode. The time selected) in the input shift register are set to 0, the parts work required to exit power-down is typically 4.5 µs for VDD = 5 V. normally with its normal power consumption of 4 mA at 5 V. However, for the three power-down modes, the supply current To reduce the current consumption further, the on-chip reference falls to 4 μA at 5 V. Not only does the supply current fall, but the can be powered off. See the Internal Reference Setup section. 1 Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation DB15 to DB0 DB23 DB22 DB21 DB20 DB19 to DB16 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 (LSB) 0 1 0 0 X X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 Command bits (C3 to C0) Address bits Power-Down Power-Down Power-Down Power-Down Don’t care Select DAC D Select DAC C Select DAC B Select DAC A 1 X = don’t care. Rev. 0 | Page 24 of 32 10485-058 Data Sheet AD5686R/AD5685R/AD5684R LOAD DAC (HARDWARE LDAC PIN) LDAC MASK REGISTER The AD5686R/AD5685R/AD5684R DACs have double Command 0101 is reserved for this software LDAC function. buffered interfaces consisting of two banks of registers: Address bits are ignored. Writing to the DAC, using Command input registers and DAC registers. The user can write to LDAC 0101, loads the 4-bit register (DB3 to DB0). The default any combination of the input registers. Updates to the DAC LDAC for each channel is 0; that is, the pin works normally. LDAC register are controlled by the pin. Setting the bits to 1 forces this DAC channel to ignore transitions OUTPUT LDAC LDAC on the pin, regardless of the state of the hardware AMPLIFIER pin. This flexibility is useful in applications where the user V 16-/14-/12-BIT REF V X OUT DAC wishes to select which channels respond to the LDAC pin. Table 12. LDAC Overwrite Definition DAC LDAC REGISTER Load LDAC Register LDAC Bits LDAC Pin LDAC Operation (DB3 to DB0) INPUT REGISTER 0 1 or 0 Determined by the LDAC pin. 1 1 X DAC channels update and SCLK override the LDAC pin. DAC INTERFACE SDO SYNC LOGIC channels see LDAC as 1. SDIN 1 Figure 56. Simplified Diagram of Input Loading Circuitry for a Single DAC X = don’t care. LDAC The register gives the user extra flexibility and control LDAC Instantaneous DAC Updating ( Held Low) LDAC LDAC over the hardware pin (see Table 12). Setting the LDAC is held low while data is clocked into the input register bits (DB0 to DB3) to 0 for a DAC channel means that this using Command 0001. Both the addressed input register and channel’s update is controlled by the hardware LDAC pin. the DAC register are updated on the rising edge of SYNC and the output begins to change (see Table 13). LDAC Deferred DAC Updating ( is Pulsed Low) LDAC is held high while data is clocked into the input register using Command 0001. All DAC outputs are asynchronously updated by taking LDAC low after SYNC has been taken high. The update now occurs on the falling edge of LDAC. 1 Table 13. Write Commands and LDAC Pin Truth Table Hardware LDAC Input Register Commands Description Pin State Contents DAC Register Contents 0001 Write to Input Register n (dependent on LDAC) VLOGIC Data update No change (no update) 2 GND Data update Data update 0010 Update DAC Register n with contents of Input VLOGIC No change Updated with input register Register n contents GND No change Updated with input register contents 0011 Write to and update DAC Channel n V Data update Data update LOGIC GND Data update Data update 1 LDAC A high to low hardware pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that are not masked (blocked) by the LDAC mask register. 2 When LDAC is permanently tied low, the LDAC mask bits are ignored. Rev. 0 | Page 25 of 32 10485-059 AD5686R/AD5685R/AD5684R Data Sheet HARDWARE RESET ( ) RESET SOLDER HEAT REFLOW RESET is an active low reset that allows the outputs to be As with all IC reference voltage circuits, the reference value cleared to either zero scale or midscale. The clear code value is experiences a shift induced by the soldering process. Analog user selectable via the RESET select pin. It is necessary to keep Devices, Inc., performs a reliability test called precondition to mimic the effect of soldering a device to a board. The output RESET low for a minimum amount of time to complete the voltage specification quoted previously includes the effect of RESET operation (see Figure 2). When the signal is returned this reliability test. high, the output remains at the cleared value until a new value is programmed. The outputs cannot be updated with a new value Figure 57 shows the effect of solder heat reflow (SHR) as while the RESET pin is low. There is also a software executable measured through the reliability test (precondition). reset function that resets the DAC to the power-on reset code. POSTSOLDER Command 0110 is designated for this software reset function 60 HEAT REFLOW LDAC RESET (see Table 7). Any events on or during power-on PRESOLDER 50 HEAT REFLOW reset are ignored. RESET SELECT PIN (RSTSEL) 40 The AD5686R/AD5685R/AD5684R contain a power-on reset 30 circuit that controls the output voltage during power-up. By connecting the RSTSEL pin low, the output powers up to zero 20 scale. Note that this is outside the linear region of the DAC; by connecting the RSTSEL pin high, V powers up to midscale. OUT 10 The output remains powered up at this level until a valid write 0 sequence is made to the DAC. 2.498 2.499 2.500 2.501 2.502 V (V) REF INTERNAL REFERENCE SETUP Figure 57. SHR Reference Voltage Shift The on-chip reference is on at power-up by default. To reduce the LONG-TERM TEMPERATURE DRIFT supply current, this reference can be turned off by setting software programmable bit, DB0, in the control register. Figure 58 shows the change in V value after 1000 hours in life REF Table 14 shows how the state of the bit corresponds to the mode test at 150°C. of operation. Command 0111 is reserved for setting up the 0 HOUR internal reference (see Figure 9). Table 14 shows how the state 168 HOURS 60 500 HOURS of the bits in the input shift register corresponds to the mode of 1000 HOURS operation of the device during internal reference setup. 50 Table 14. Reference Setup Register 40 Internal Reference Setup Register (DB0) Action 30 0 Reference on (default) 20 1 Reference off 10 0 2.498 2.499 2.500 2.501 2.502 V (V) REF Figure 58. Reference Drift Through to 1000 Hours Rev. 0 | Page 26 of 32 HITS HITS 10485-060 10485-061 Data Sheet AD5686R/AD5685R/AD5684R 9 THERMAL HYSTERESIS FIRST TEMPERATURE SWEEP 8 SUBSEQUENT TEMPERATURE SWEEPS Thermal hysteresis is the voltage difference induced on the 7 reference voltage by sweeping the temperature from ambient to cold, to hot, and then back to ambient. 6 Thermal hysteresis data is shown in Figure 59. It is measured 5 by sweeping the temperature from ambient to −40°C, then 4 to +105°C, and returning to ambient. The VREF delta is then 3 measured between the two ambient measurements and shown in blue in Figure 59. The same temperature sweep 2 and measurements were immediately repeated and the 1 results are shown in red in Figure 59. 0 –200 –150 –100 –50 0 50 DISTORTION (ppm) Figure 59. Thermal Hysteresis 1 Table 15. 24-Bit Input Shift Register Contents for Internal Reference Setup Command DB23 (MSB) DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 (LSB) 0 1 1 1 X X X X X 1/0 Command bits (C3 to C0) Address bits (A2 to A0) Don’t care Reference setup register 1 X = don’t care. Rev. 0 | Page 27 of 32 HITS 10485-062 AD5686R/AD5685R/AD5684R Data Sheet APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING LAYOUT GUIDELINES Microprocessor interfacing to the AD5686R/AD5685R/ In any circuit where accuracy is important, careful consider- AD5684R is via a serial bus that uses a standard protocol that ation of the power supply and ground return layout helps to is compatible with DSP processors and microcontrollers. ensure the rated performance. The PCB on which the AD5686R/ The communications channel requires a 3- or 4-wire interface AD5685R/AD5684R are mounted should be designed so that consisting of a clock signal, a data signal, and a synchronization the AD5686R/AD5685R/AD5684R lie on the analog plane. signal. The devices require a 24-bit data-word with data valid The AD5686R/AD5685R/AD5684R should have ample SYNC on the rising edge of . supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible, ideally right AD5686R/AD5685R/AD5684R TO ADSP-BF531 up against the device. The 10 µF capacitors are the tantalum INTERFACE bead type. The 0.1 µF capacitor should have low effective series The SPI interface of the AD5686R/AD5685R/AD5684R is resistance (ESR) and low effective series inductance (ESI) such designed to be easily connected to industry-standard DSPs and as the common ceramic types, which provide a low impedance microcontrollers. Figure 60 shows the AD5686R/AD5685R/ path to ground at high frequencies to handle transient currents AD5684R connected to the Analog Devices Blackfin® DSP. The due to internal logic switching. Blackfin has an integrated SPI port that can be connected In systems where there are many devices on one board, it is directly to the SPI pins of the AD5686R/AD5685R/AD5684R. often useful to provide some heat sinking capability to allow AD5686R/ the power to dissipate easily. AD5685R/ AD5684R The AD5686R/AD5685R/AD5684R have an exposed paddle ADSP-BF531 beneath the device. Connect this paddle to the GND supply for SPISELx SYNC the part. For optimum performance, use special considerations SCK SCLK to design the motherboard and to mount the package. For MOSI SDIN enhanced thermal, electrical, and board level performance, PF9 LDAC solder the exposed paddle on the bottom of the package to the PF8 RESET corresponding thermal land paddle on the PCB. Design thermal Figure 60. ADSP-BF531 Interface vias into the PCB land paddle area to further improve heat dissipation. AD5686R/AD5685R/AD5684R TO SPORT INTERFACE The GND plane on the device can be increased (as shown in Figure 62) to provide a natural heat sinking effect. The Analog Devices ADSP-BF527 has one SPORT serial port. Figure 61 shows how one SPORT interface can be used to AD5686R/ AD5685R/ control the AD5686R/AD5685R/AD5684R. AD5684R AD5686R/ AD5685R/ AD5684R ADSP-BF527 GND PLANE SPORT_TFS SYNC SPORT_TSCK SCLK SPORT_DTO SDIN BOARD GPIO0 LDAC GPIO1 RESET Figure 62. Paddle Connection to Board Figure 61. SPORT Interface Rev. 0 | Page 28 of 32 10485-165 10485-164 10485-166 Data Sheet AD5686R/AD5685R/AD5684R 1 CONTROLLER GALVANICALLY ISOLATED INTERFACE ADuM1400 V V IA OA SERIAL TO In many process control applications, it is necessary to ENCODE DECODE SCLK CLOCK IN provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling V V IB OB TO SERIAL ENCODE DECODE SDIN circuitry from any hazardous common-mode voltages that DATA OUT may occur. iCoupler® products from Analog Devices provide V V IC OC TO voltage isolation in excess of 2.5 kV. The serial loading struc- ENCODE DECODE SYNC OUT SYNC ture of the AD5686R/AD5685R/AD5684R makes the part V V ideal for isolated interfaces because the number of interface ID OD LOAD DAC TO ENCODE DECODE OUT LDAC lines is kept to a minimum. Figure 63 shows a 4-channel isolated interface to the AD5686R/AD5685R/AD5684R using an ADuM1400. For further information, visit 1 ADDITIONAL PINS OMITTED FOR CLARITY. http://www.analog.com/icouplers. Figure 63. Isolated Interface Rev. 0 | Page 29 of 32 10485-167 AD5686R/AD5685R/AD5684R Data Sheet OUTLINE DIMENSIONS 3.10 0.30 3.00 SQ 0.23 2.90 PIN 1 0.18 INDICATOR 13 16 0.50 12 1 BSC EXPOSED 1.75 PAD 1.60 SQ 1.45 9 4 8 5 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 65. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. 0 | Page 30 of 32 PIN 1 INDICATOR 08-16-2010-E Data Sheet AD5686R/AD5685R/AD5684R ORDERING GUIDE Reference Temperature Tempco Package Package 1 Model Resolution Range Accuracy (ppm/°C) Description Option Branding AD5686RACPZ-RL7 16 Bits −40°C to +105°C ±8 LSB INL ±5 (typ) 16-Lead LFCSP_WQ CP-16-22 DJM AD5686RBCPZ-RL7 16 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead LFCSP_WQ CP-16-22 DJN AD5686RARUZ 16 Bits −40°C to +105°C ±8 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5686RARUZ-RL7 16 Bits −40°C to +105°C ±8 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5686RBRUZ 16 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5686RBRUZ-RL7 16 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5685RBCPZ-RL7 14 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead LFCSP_WQ CP-16-22 DJK AD5685RARUZ 14 Bits −40°C to +105°C ±4 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5685RARUZ-RL7 14 Bits −40°C to +105°C ±4 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5685RBRUZ 14 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5685RBRUZ-RL7 14 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5684RBCPZ-RL7 12 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead LFCSP_WQ CP-16-22 DJG AD5684RARUZ 12 Bits −40°C to +105°C ±2 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5684RARUZ-RL7 12 Bits −40°C to +105°C ±2 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5684RBRUZ 12 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5684RBRUZ-RL7 12 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead TSSOP RU-16 EVAL-AD5686RSDZ AD5686R TSSOP Evaluation Board EVAL-AD5684RSDZ AD5684R TSSOP Evaluation Board 1 Z = RoHS Compliant Part. Rev. 0 | Page 31 of 32 AD5686R/AD5685R/AD5684R Data Sheet NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10485-0-4/12(0) Rev. 0 | Page 32 of 32