ANALOG DEVICES AD5669R

2 Octal, 12-/16-Bit, I C, denseDACs with 5 ppm/°C On-Chip Reference AD5629R/AD5669R FEATURES FUNCTIONAL BLOCK DIAGRAM V V /V DD REFIN REFOUT Low power octal DACs AD5629R/AD5669R 1.25V/2.5V REF AD5629R: 12 bits BUFFER AD5669R: 16 bits LDAC INPUT DAC STRING V A OUT REGISTER REGISTER DAC A 16-lead LFCSP and 16-lead TSSOP SCL BUFFER On-chip 1.25 V/2.5 V, 5 ppm/°C reference INPUT DAC STRING V B OUT REGISTER REGISTER DAC B Power down to 400 nA at 5 V, 200 nA at 3 V BUFFER 2.7 V to 5.5 V power supply INPUT DAC STRING V C OUT Guaranteed monotonic by design REGISTER REGISTER DAC C BUFFER Power-on reset to zero scale or midscale SDA INPUT DAC STRING V D OUT 3 power-down functions REGISTER REGISTER DAC D LDAC CLR BUFFER Hardware and functions INPUT DAC STRING 2 V E OUT I C-compatible serial interface supports standard (100 kHz) REGISTER REGISTER DAC E BUFFER and fast (400 kHz) modes A0 INPUT DAC STRING V F OUT REGISTER REGISTER DAC F APPLICATIONS BUFFER INPUT DAC STRING Process control V G OUT REGISTER REGISTER DAC G Data acquisition systems BUFFER INPUT DAC STRING Portable battery-powered instruments V H OUT REGISTER REGISTER DAC H Digital gain and offset adjustment POWER-ON RESET POWER-DOWN LOGIC Programmable voltage and current sources LDAC CLR GND Figure 1. GENERAL DESCRIPTION The AD5629R/AD5669R devices are low power, octal, 12-/16- The parts incorporate a power-on reset circuit to ensure that the bit, buffered voltage-output DACs. All devices are guaranteed DAC output powers up to 0 V (AD5629R-1/AD5629R-2, monotonic by design. AD5669R-1/AD5669R-2) or midscale (AD5629R-3/AD5669R-3) and remains powered up at this level until a valid write takes The AD5629R/AD5669R have an on-chip reference with an place. The part contains a power-down feature that reduces the internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V, current consumption of the device to 400 nA at 5 V and 5 ppm/°C reference, giving a full-scale output range of 2.5 V. provides software-selectable output loads while in power-down The AD5629R-2/AD5629R-3 and the AD5669R-2/AD5669R-3 mode for any or all DAC channels. have a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V depending on the option selected. Devices with 1.25 V PRODUCT HIGHLIGHTS reference selected operate from a single 2.7 V to 5.5 V supply. 1. Octal, 12-/16-bit DACs. Devices with 2.5 V reference selected operate from 4.5 V to 5.5 V. 2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference. The on-chip reference is off at power-up, allowing the use of an 3. Available in 16-lead LFCSP and TSSOP. external reference. The internal reference is enabled via a 4. Power-on reset to 0 V or midscale. software write. 5. Power-down capability. When powered down, the DAC typically consumes 200 nA at 3 V and 400 nA at 5 V. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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INTERFACE LOGIC 08819-001 AD5629R/AD5669R TABLE OF CONTENTS Features .............................................................................................. 1 Resistor String............................................................................. 20 Applications....................................................................................... 1 Internal Reference ...................................................................... 20 Functional Block Diagram .............................................................. 1 Output Amplifier........................................................................ 21 General Description ......................................................................... 1 Serial Interface ............................................................................ 21 Product Highlights ........................................................................... 1 Write Operation.......................................................................... 21 Revision History ............................................................................... 2 Read Operation........................................................................... 21 Specifications..................................................................................... 3 Input Shift Register .................................................................... 22 AC Characteristics........................................................................ 6 Multiple Byte Operation............................................................ 22 2 I C Timing Characteristics.......................................................... 7 Internal Reference Register....................................................... 23 Absolute Maximum Ratings............................................................ 9 Power-On Reset.......................................................................... 23 ESD Caution.................................................................................. 9 Power-Down Modes .................................................................. 24 Pin Configuration and Function Descriptions........................... 10 Clear Code Register ................................................................... 24 Typical Performance Characteristics ........................................... 11 LDAC Function .......................................................................... 26 Terminology .................................................................................... 18 Power Supply Bypassing and Grounding................................ 26 Theory of Operation ...................................................................... 20 Outline Dimensions....................................................................... 27 Digital-to-Analog Converter (DAC) Section ......................... 20 Ordering Guide .......................................................................... 28 REVISION HISTORY 12/10—Rev. 0 to Rev. A Changes to Features, General Description, and Product Highlights Sections........................................................................... 1 Changes to AD5629R Relative Accuracy Parameter, Reference Output (1.25 V) Reference Input Range Parameter, and Reference Output (2.5 V) Reference Input Range Parameter (Table 1) ...... 3 Changes to Relative Accuracy Parameter, Reference Tempco Parameter (Table 2) .......................................................................... 5 Changes to Output Voltage Settling Time Parameter (Table 3) . 6 Changes to Table 5............................................................................ 9 CLR Changes to Pin Description (Table 6)................................. 10 Added Figure 32 and Figure 33..................................................... 15 Added Figure 46.............................................................................. 17 Changes to Internal Reference Section........................................ 20 Changes to Power-On Reset Section............................................ 23 Changes to Clear Code Register Section..................................... 24 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 28 10/10—Revision 0: Initial Version Rev. A | Page 2 of 28 AD5629R/AD5669R SPECIFICATIONS VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments 2 STATIC PERFORMANCE AD5629R Resolution 12 12 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 6 Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 8) AD5669R Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 5 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 7) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 18) Zero-Code Error Drift ±2 ±2 μV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 19) Gain Error ±1 ±1 % FSR Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C Offset Error ±6 ±19 ±6 ±19 mV DC Power Supply Rejection –80 –80 dB VDD ± 10% Ratio DC Crosstalk 10 10 μV Due to full-scale output change, (External Reference) R = 2 kΩ to GND or V L DD 5 5 μV/mA Due to load current change 10 10 μV Due to powering down (per channel) DC Crosstalk 25 25 μV Due to full-scale output change, (Internal Reference) RL = 2 kΩ to GND or VDD 10 10 μV/mA Due to load current change 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF R = 2 kΩ L DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 5 V Power-Up Time 4 4 μs Coming out of power-down mode, VDD = 5 V REFERENCE INPUTS Reference Current 40 50 40 50 μA VREFIN = VDD = 5.5 V (per DAC channel) Reference Input Range 0 VDD 0 VDD V Reference Input Impedance 14.6 14.6 kΩ REFERENCE OUTPUT (1.25 V) Output Voltage 1.247 1.253 1.247 1.253 μA TA = 25°C Reference Input Range ppm/°C ±15 ±5 ±15 Output Impedance 7.5 7.5 kΩ REFERENCE OUTPUT (2.5 V) Output Voltage 2.495 2.505 2.495 2.505 μA TA = 25°C Reference Input Range ppm/°C ±15 ±5 ±10       Output Impedance 7.5 7.5 kΩ Rev. A | Page 3 of 28 AD5629R/AD5669R 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments 3 LOGIC INPUTS Input Current ±3 ±3 μA All digital inputs Input Low Voltage, V 0.8 0.8 V V = 5 V INL DD Input High Voltage, V 2 2 V V = 5 V INH DD Pin Capacitance 3 3 pF POWER REQUIREMENTS V 4.5 5.5 4.5 5.5 V DD All digital inputs at 0 or VDD, DAC active, excludes load current 4 IDD (Normal Mode) VIH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 1.3 1.8 1.3 1.8 mA Internal reference off 2 2.5 2 2.5 mA Internal reference on 5 I (All Power-Down Modes) DD VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 μA VIH = VDD and VIL = GND 1 Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code 4064) and the AD5669R (Code 512 to 65,024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. Rev. A | Page 4 of 28 AD5629R/AD5669R V = 2.7 V to 3.6 V, R = 2 kΩ to GND, C = 200 pF to GND, V = V . All specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 2. 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE AD5629R Resolution 12 12 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 6 Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 8) AD5669R Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 5 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 7) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 18) Zero-Code Error Drift ±2 ±2 μV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 19) Gain Error ±1 ±1 % FSR Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C Offset Error ±6 ±19 ±6 ±19 mV DC Power Supply Rejection –80 –80 dB VDD ± 10% Ratio DC Crosstalk 10 10 μV Due to full-scale output change, (External Reference) R = 2 kΩ to GND or V L DD 5 5 μV/mA Due to load current change 10 10 μV Due to powering down (per channel) DC Crosstalk 25 25 μV Due to full-scale output change, (Internal Reference) R = 2 kΩ to GND or V L DD 10 10 μV/mA Due to load current change 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 V 0 V V DD DD Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 3 V Power-Up Time 4 4 μs Coming out of power-down mode, V = 3 V DD REFERENCE INPUTS Reference Current 40 50 40 50 μA VREFIN = VDD = 3.6 V (per DAC channel) Reference Input Range 0 V 0 V DD DD Reference Input Impedance 14.6 14.6 kΩ REFERENCE OUTPUT Output Voltage AD5629R/AD5669R 1.247 1.253 1.247 1.253 V T = 25°C A 3 Reference Tempco ±15 ±5 ±15 ppm/°C Reference Output Impedance 7.5 7.5 kΩ 3 LOGIC INPUTS Input Current ±3 ±3 μA All digital inputs Input Low Voltage, VINL 0.8 0.8 V VDD = 3 V Input High Voltage, VINH 2 2 V VDD = 3 V Pin Capacitance 3 3 pF Rev. A | Page 5 of 28 AD5629R/AD5669R 1 1 A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Conditions/Comments POWER REQUIREMENTS V 2.7 3.6 2.7 3.6 V All digital inputs at 0 or V , DD DD DAC active, excludes load current 4 I (Normal Mode) V = V and V = GND DD IH DD IL VDD = 2.7 V to 3.6 V 1.0 1.5 1.0 1.5 mA Internal reference off 1.8 2.25 1.7 2.25 mA Internal reference on 5 IDD (All Power-Down Modes) V = 2.7 V to 3.6 V 0.2 1 0.2 1 μA V = V and V = GND DD IH DD IL 1 Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code 4064) and the AD5669R (Code 512 to 65,024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. AC CHARACTERISTICS V = 2.7 V to 5.5 V, R = 2 kΩ to GND, C = 200 pF to GND, V = V . All specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 3. 1, 2 3 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time 2.5 7 μs ¼ to ¾ scale settling to ±2 LSB Slew Rate 1.2 V/μs Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB change around major carry (see Figure 34) 19 nV-s From Code 59904 to Code 59903 Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dB VREFIN = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz Digital Crosstalk 0.2 nV-s Analog Crosstalk 0.4 nV-s DAC-to-DAC Crosstalk 0.8 nV-s Multiplying Bandwidth 320 kHz VREFIN = 2 V ± 0.2 V p-p Total Harmonic Distortion −80 dB VREFIN = 2 V ± 0.1 V p-p, frequency = 10 kHz Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400, 1 kHz 100 nV/√Hz DAC code = 0x8400, 10 kHz 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical at 25°C. Rev. A | Page 6 of 28 AD5629R/AD5669R 2 I C TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 400 kHz, unless otherwise noted. Table 4. Parameter Conditions Min Max Unit Description 1 f Standard mode 100 kHz Serial clock frequency SCL Fast mode 400 kHz t1 Standard mode 4 μs tHIGH, SCL high time Fast mode 0.6 μs t Standard mode 4.7 μs t , SCL low time 2 LOW Fast mode 1.3 μs t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns t4 Standard mode 0 3.45 μs tHD;DAT, data hold time Fast mode 0 0.9 μs t Standard mode 4.7 μs t , setup time for a repeated start condition 5 SU;STA Fast mode 0.6 μs t6 Standard mode 4 μs tHD;STA, hold time (repeated) start condition Fast mode 0.6 μs t7 Standard mode 4.7 μs tBUF, bus-free time between a stop and a start condition Fast mode 1.3 μs t Standard mode 4 μs t , setup time for a stop condition 8 SU;STO Fast mode 0.6 μs t9 Standard mode 1000 ns tRDA, rise time of SDA signal Fast mode 300 ns t Standard mode 300 ns t , fall time of SDA signal 10 FDA Fast mode 300 ns t Standard mode 1000 ns t , rise time of SCL signal 11 RCL Fast mode 300 ns t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit Fast mode 300 ns t Standard mode 300 ns t , fall time of SCL signal 12 FCL Fast mode 300 ns t13 Standard mode 10 ns LDAC pulse width low Fast mode 10 ns t14 Standard mode 300 ns Falling edge of ninth SCL clock pulse of last byte of a valid write to the LDAC falling edge Fast mode 300 ns t15 Standard mode 20 ns CLR pulse width low Fast mode 20 ns 2 tSP Fast mode 0 50 ns Pulse width of spike suppressed 1 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC behavior of the part. 2 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode. Rev. A | Page 7 of 28 AD5629R/AD5669R t t 11 12 t 6 t 2 SCL t t t 6 1 5 t 8 t 4 t t t 3 10 9 SDA t 7 PS S P t 14 t 13 LDAC* t 15 CLR *ASYNCHRONOUS LDAC UPDATE MODE. Figure 2. Serial Write Operation Rev. A | Page 8 of 28 08819-002 AD5629R/AD5669R ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings TA = 25°C, unless otherwise noted. may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to GND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect Digital Input Voltage to GND −0.3 V to V + 0.3 V DD device reliability. VOUT to GND −0.3 V to VDD + 0.3 V VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V Operating Temperature Range ESD CAUTION Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T ) +150°C J MAX Power Dissipation (TJ MAX − TA)/θJA Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 112.6°C/W 16-Lead LFCSP (4-Layer Board) 30.4°C/W Reflow Soldering Peak Temperature Pb Free 260°C Rev. A | Page 9 of 28 AD5629R/AD5669R PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD5629R/AD5669R V 1 12 GND DD V A 2 11 V B OUT OUT TOP VIEW (Not to Scale) 3 10 V D LDAC 1 16 SCL V C OUT OUT V E 4 9 V F A0 2 15 SDA OUT OUT V 3 14 GND DD AD5629R/ 4 AD5669R 13 V A V B OUT OUT TOP VIEW 5 12 V C V D OUT OUT (Not to Scale) 6 11 V E V F OUT OUT 7 10 V G V H OUT OUT 8 9 V /V CLR REFIN REFOUT NOTES 1. EXPOSED PAD MUST BE TIED TO GND. Figure 4. 16-Lead TSSOP (RU-16) Figure 3. 16-Lead LFCSP (CP-16-17) Table 6. Pin Function Descriptions Pin No. 16-Lead 16-Lead LFCSP TSSOP Mnemonic Description 15 1 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. 16 2 A0 Address Input. Sets the least significant bit of the 7-bit slave address. 1 3 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 2 4 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 3 5 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 4 6 VOUTE Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. 5 7 VOUTG Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. 6 8 VREFIN/VREFOUT The AD5629R/AD5669R have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. 7 9 Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC CLR pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero scale, midscale, or full scale. The default setting clears the output to 0 V. 8 10 V H Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. OUT 9 11 V F Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. OUT 10 12 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 11 13 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 12 14 GND Ground Reference Point for All Circuitry on the Parts. 13 15 SDA Serial Data Input. This is used in conjunction with the SCL line to clock data into or out of the 32-bit input shift register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. 14 16 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 32-bit input shift register. 17 N/A Exposed Pad (EPAD) The exposed pad must be tied to GND. Rev. A | Page 10 of 28 08819-003 08819-004 V G 5 16 A0 OUT V /V 6 15 LDAC REFIN REFOUT CLR 7 14 SCL V H 8 13 SDA OUT AD5629R/AD5669R TYPICAL PERFORMANCE CHARACTERISTICS 10 0.20 V = 5V V = 5V DD DD EXT REF = 5V EXT REF = 5V 8 T = 25°C 0.15 T = 25°C A A 6 0.10 4 0.05 2 0 0 –2 –0.05 –4 –0.10 –6 –0.15 –8 –0.20 –10 0 10k 20k 30k 40k 50k 60k 65535 0 500 1000 1500 2000 2500 3000 3500 4095 CODES CODES Figure 5. INL AD5669R—External Reference Figure 8. DNL AD5629R—External Reference 1.0 10 V = 5V DD V = 5V DD EXT REF = 5V INT REF = 2.5V 0.8 T = 25°C A T = 25°C A 0.6 5 0.4 0.2 0 0 –0.2 –0.4 –5 –0.6 –0.8 –1.0 –10 0 500 1000 1500 2000 2500 3000 3500 4095 0 10k 20k 30k 40k 50k 60k 65535 CODES CODES Figure 6. INL AD5629R—External Reference Figure 9. INL AD5669R-2—Internal Reference 1.0 1.0 V = 5V DD V = 5V DD EXT REF = 5V INT REF = 2.5V 0.8 T = 25°C A T = 25°C A 0.6 0.5 0.4 0.2 0 0 –0.2 –0.4 –0.5 –0.6 –0.8 –1.0 –1.0 0 10k 20k 30k 40k 50k 60k 65535 0 500 1000 1500 2000 2500 3000 3500 4095 CODES CODES Figure 7. DNL AD5669R—External Reference Figure 10. INL AD5629R-2—Internal Reference Rev. A | Page 11 of 28 DNL (LSB) INL (LSB) INL (LSB) 08819-108 08819-109 08819-106 INL (LSB) INL (LSB) DNL (LSB) 08819-114 08819-111 08819-112 AD5629R/AD5669R 1.0 1.0 V = 5V V = 3V DD DD INT REF = 2.5V INT REF = 1.25V T = 25°C T = 25°C A A 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 0 10k 20k 30k 40k 50k 60k 65535 0 500 1000 1500 2000 2500 3000 3500 4095 CODES CODES Figure 11. DNL AD5669R-2—Internal Reference Figure 14. INL AD5629R-1—Internal Reference 0.20 1.0 V = 5V DD V = 3V DD INT REF = 2.5V INT REF = 1.25V 0.15 T = 25°C A T = 25°C A 0.10 0.5 0.05 0 0 –0.05 –0.10 –0.5 –0.15 –0.20 –1.0 0 500 1000 1500 2000 2500 3000 3500 4095 0 10k 20k 30k 40k 50k 60k 65535 CODES CODES Figure 12. DNL AD5629R-2— Internal Reference Figure 15. DNL AD5669R-1—Internal Reference 10 0.20 V = 3V V = 3V DD DD INT REF = 1.25V INT REF = 1.25V 8 0.15 T = 25°C T = 25°C A A 6 0.10 4 0.05 2 0 0 –2 –0.05 –4 –0.10 –6 –0.15 –8 –10 –0.20 0 10k 20k 30k 40k 50k 60k 65535 0 500 1000 1500 2000 2500 3000 3500 4095 CODES CODES Figure 13. INL AD5669R-1—Internal Reference Figure 16. DNL AD5629R-1—Internal Reference Rev. A | Page 12 of 28 INL (LSB) DNL (LSB) DNL (LSB) 08819-117 08819-118 08819-115 DNL (LSB) DNL (LSB) INL (LSB) 08819-123 08819-120 08819-121 AD5629R/AD5669R 0 1.95 V = 5V DD T = 25°C A 1.90 –0.05 1.85 OFFSET ERROR –0.10 1.80 FULL-SCALE ERROR –0.15 1.75 –0.20 1.70 ZERO-CODE ERROR GAIN ERROR 1.65 –0.25 1.60 –0.30 1.55 –40 –25 –10 5 20 35 50 65 80 95 110 125 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 TEMPERATURE (°C) V (V) DD Figure 17. Gain Error and Full-Scale Error vs. Temperature Figure 20. Zero-Code Error and Offset Error vs. Supply Voltage 21 6 V = 5V DD 18 5 OFFSET ERROR 15 4 ZERO-CODE ERROR 12 3 9 2 6 1 3 0 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 0.85 0.90 0.95 1.00 1.05 I WITH EXTERNAL REFERENCE (mA) TEMPERATURE (°C) DD Figure 21. I Histogram with External Reference Figure 18. Zero-Code Error and Offset Error vs. Temperature DD –0.16 18 T = 25°C A FULL-SCALE ERROR –0.17 16 –0.18 14 –0.19 12 –0.20 10 –0.21 8 –0.22 6 –0.23 4 –0.24 GAIN ERROR 2 –0.25 –0.26 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 1.65 1.70 1.75 1.80 1.85 1.90 I WITH INTERNAL REFERENCE (mA) V (V) DD DD Figure 22. IDD Histogram with Internal Reference Figure 19. Gain Error and Full-Scale Error vs. Supply Voltage Rev. A | Page 13 of 28 ERROR (% FSR) ERROR (mV) ERROR (% FSR) 08819-126 08819-125 08819-124 NUMBER OF HITS NUMBER OF HITS ERROR (mV) 08819-127 08819-129 08819-128 AD5629R/AD5669R 0.4 1.8 T = 25°C A T = 25°C A 1.7 0.3 1.6 0.2 V = 5V DD 1.5 0.1 V = 3V, INT REF = 1.25V 1.4 DD 0 V = 3V DD 1.3 –0.1 1.2 –0.2 1.1 –0.3 1.0 V = 5V, INT REF = 2.5V DD –0.4 0.9 –0.5 0.8 –10 –8 –6 –4 –2 02468 10 0 10k 20k 30k 40k 50k 60k SOURCE/SINK CURRENT (mA) DIGITAL CODES (Decimal) Figure 23. Headroom at Rails vs. Source and Sink Figure 26. Supply Current vs. Code 6 2.0 V = 5V T = 25°C DD A INT REF = 2.5V FULL SCALE 1.9 T = 25°C 5 A 1.8 4 3/4 SCALE 1.7 1.6 V = 5.5V DD 3 MIDSCALE 1.5 V = 3.6V DD 2 1.4 1/4 SCALE 1.3 1 1.2 0 ZERO CODE 1.1 –1 1.0 –0.03 –0.02 –0.01 0 0.01 0.02 0.03 –40 –25 –10 5 20 35 50 65 80 95 110 125 SOURCE AND SINK CURRENT (mA) TEMPERATURE (°C) Figure 24. AD5669R-2 Source and Sink Capability Figure 27. Supply Current vs. Temperature 1.48 4.0 T = 25°C V = 3V A DD INT REF = 1.25V 3.5 T = 25°C 1.46 A 3.0 FULL SCALE 1.44 2.5 3/4 SCALE 2.0 1.42 1.5 MIDSCALE 1.40 1.0 1/4 SCALE 0.5 1.38 ZERO CODE 0 1.36 –0.5 1.34 –1.0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 –0.03 –0.02 –0.01 0 0.01 0.02 0.03 V (V) SOURCE AND SINK CURRENT (mA) DD Figure 25. AD5669R-1 Source and Sink Capability Figure 28. Supply Current vs. Supply Voltage Rev. A | Page 14 of 28 V (V) V (V) OUT OUT ERROR VOLTAGE (V) 08819-130 08819-132 08819-131 I (mA) I (mA) DD DD I (mA) DD 08819-133 08819-135 08819-134 AD5629R/AD5669R 5.5 V = 5V DD 2.3 5.0 EXT REF = 5V T = 25°C A T = 25°C A 4.5 2.1 4.0 V DD 1.9 3.5 3.0 1.7 2.5 V =5V DD V A OUT 1.5 2.0 1.5 1.3 1.0 1.1 0.5 V =3V DD 0 0.9 –0.5 –0.0010 –0.0006 –0.0002 0.0002 0.0006 0.0010 0.7 TIME (s) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V (V) LOGIC Figure 29. Supply Current vs. Logic Input Voltage Figure 32. Power-On Reset to Midscale 5.5 TH 6 V = 5V 24 CLK RISING EDGE DD V = 5V DD 5.0 EXT REF = 5V EXT REF = 5V T = 25°C A 4.5 T = 25°C A 5 4.0 3.5 4 3.0 2.5 3 V A OUT 2.0 1.5 2 1.0 0.5 1 0 –0.5 0 –10 –5 0 5 10 –2 0 2 4 6 8 TIME (µs) TIME (µs) Figure 30. Full-Scale Settling Time, 5 V Figure 33. Exiting Power-Down to Midscale 5.5 V = 5V DD T V = 5V DD 5.0 EXT REF = 5V EXT REF = 5V T = 25°C A T = 25°C 4.5 A 4.0 V DD 3.5 3.0 V A OUT 2.5 3 2.0 1.5 1.0 TH 24 CLK RISING EDGE 0.5 V A OUT 0 –0.5 4 –0.0010 –0.0006 –0.0002 0.0002 0.0006 0.0010 M400ns A CH4 1.50V B TIME (s) CH3 10.0mV CH4 5.0V T 17.0% W Figure 31. Power-On Reset to 0 V Figure 34. Digital-to-Analog Glitch Impulse (Negative) Rev. A | Page 15 of 28 VOLTAGE (V) I (mA) V (V) DD OUT 08819-137 08819-136 08819-138 VOLTAGE (V) VOLTAGE (V) 08819-141 08819-140 08819-139 AD5629R/AD5669R 0.0010 0.20 EXT REF = 2.5V V = 5V DD DAC CODE = 0xFF00 EXT REF = 5V 0.15 T = 25°C A 0.0005 0.10 0.05 0 0 –0.0005 –0.05 –0.10 –0.0010 –0.15 –0.0015 –0.20 09 1 2 3 4 5 6 7 8 01 1 2 3 4 5 6 7 890 TIME (µs) TIME (s) Figure 35. Analog Crosstalk Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference 0.0020 0.20 V = 5V INT REF = 1.25V DD EXT REF = 5V DAC CODE = 0xFF00 T = 25°C 0.15 0.0015 A 0.10 0.0010 0.05 0.0005 0 0 –0.05 –0.0005 –0.10 –0.0010 –0.15 –0.0015 –0.20 08 1 2 3 4 5 6 7 01 1 2 3 4 5 6 7 890 TIME (µs) TIME (s) Figure 36. DAC-to-DAC Crosstalk Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference 800 0.06 V = 5.5V DD V = 5.5V DD DAC CODE = 0x8400 EXT REF = 5V 700 DAC CODE = 0xFF00 0.04 600 0.02 500 0 400 V = 2.5V REF –0.02 300 –0.04 200 –0.06 100 V = 1.25V REF 0 –0.08 100 1k 10k 100k 1M 01 1 2 3 4 5 6 7 890 FREQUENCY (Hz) TIME (s) Figure 40. Noise Spectral Density, Internal Reference Figure 37. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Rev. A | Page 16 of 28 OUTPUT VOLTAGE (V) GLITCH AMPLITUDE (V) GLITCH AMPLITUDE (V) 08819-144 08819-143 08819-142 OUTPUT NOISE (V) OUTPUT NOISE (V) OUTPUT NOISE (nV/ Hz) 08819-147 08819-146 08819-145 AD5629R/AD5669R 0 10 V = 5.5V DD EXT REF = 5V 0 T = 25°C –20 A V = 2V ± 0.1V p-p REF –10 FREQUENCY = 10kHz –40 –20 –60 –30 –40 –80 CH A –50 CH B –100 CH C CH D –60 CH E V = 5.5V DD CH F –120 EXT REF = 5V CH G –70 T = 25°C CH H A V = 2V ± 0.2V p-p –3dB REF –140 –80 0 2000 4000 6000 8000 10,000 10 100 1k 1k0 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 41. Total Harmonic Distortion Figure 44. Multiplying Bandwidth 1.2510 V = 5.5V DD 9 1.2508 T = 25°C A 8 1.2506 V = EXTERNAL REFERENCE = 5V DD 7 1.2504 1.2502 6 1.2500 5 1.2498 4 1.2496 3 V = EXTERNAL REFERENCE = 3V DD 1.2494 2 1.2492 1 1.2490 –40 25 105 0 TEMPERATURE (°C) 01 1 2 3 4 5 6 7 8 90 CAPACITIVE LOAD (nF) Figure 42. Settling Time vs. Capacitive Load Figure 45. 1.25 V Reference Temperature Coefficient vs. Temperature 2.503 5.5 EXT REF = 5V 2.502 5.0 4.5 2.501 4.0 2.500 3.5 3.0 2.499 V A OUT 2.5 2.498 2.0 1.5 2.497 CLR PULSE 1.0 2.496 0.5 0 2.495 105 25 –40 –0.5 TEMPERATURE (°C) –10 –5 0 5 10 TIME (µs) Figure 43. Hardware CLR Figure 46. 2.5 V Reference Temperature Coefficient vs. Temperature Rev. A | Page 17 of 28 THD (dB) VOLTAGE (V) SETTLING TIME (µs) 08819-150 08819-149 08819-148 REFERENCE (ppm/°C) V (dBm) REFERENCE (ppm/°C) OUT 08819-153 08819-152 08819-151 AD5629R/AD5669R TERMINOLOGY Digital-to-Analog Glitch Impulse Relative Accuracy Digital-to-analog glitch impulse is the impulse injected into the For the DAC, relative accuracy, or integral nonlinearity (INL), is analog output when the input code in the DAC register changes a measure of the maximum deviation in LSBs from a straight line state. It is normally specified as the area of the glitch in nV-s and passing through the endpoints of the DAC transfer function. is measured when the digital input code is changed by 1 LSB at Figure 5, Figure 6, Figure 9, Figure 10, Figure 13, and Figure 14 the major carry transition (0x7FFF to 0x8000). Figure 34 shows show plots of typical INL vs. code. a typical digital-to-analog glitch impulse plot. Differential Nonlinearity DC Power Supply Rejection Ratio (PSRR) Differential nonlinearity (DNL) is the difference between the PSRR indicates how the output of the DAC is affected by changes measured change and the ideal 1 LSB change between any two in the supply voltage. PSRR is the ratio of the change in VOUT to adjacent codes. A specified differential nonlinearity of ±1 LSB a change in VDD for full-scale output of the DAC. VREF is held at maximum ensures monotonicity. This DAC is guaranteed 2 V, and VDD is varied ±10%. It is measured in decibels. monotonic by design. Figure 7, Figure 8, Figure 11, Figure 12, Figure 15, and Figure 16 show plots of typical DNL vs. code. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in Offset Error response to a change in the output of another DAC. It is measured Offset error is a measure of the difference between the actual with a full-scale output change on one DAC (or soft power-down VOUT and the ideal VOUT, expressed in millivolts in the linear and power-up) while monitoring another DAC kept at midscale. region of the transfer function. Offset error is measured on the It is expressed in microvolts. AD5669R between Code 512 and Code 65024 loaded into the DAC register. It can be negative or positive and is expressed in DC crosstalk due to load current change is a measure of the millivolts. impact that a change in load current on one DAC has on another DAC kept at midscale. It is expressed in microvolts per milliamp. Zero-Code Error Zero-code error is a measure of the output error when zero Digital Feedthrough code (0x0000) is loaded into the DAC register. Ideally, the Digital feedthrough is a measure of the impulse injected into output should be 0 V. The zero-code error is always positive the analog output of a DAC from the digital input pins of the because the output of the DAC cannot go below 0 V. It is due to device, but is measured when the DAC is not being written to. It a combination of the offset errors in the DAC and output is specified in nV-s and measured with a full-scale change on amplifier. Zero-code error is expressed in millivolts. Figure 18 the digital input pins, that is, from all 0s to all 1s or vice versa. shows a plot of typical zero-code error vs. temperature. Digital Crosstalk Gain Error Digital crosstalk is the glitch impulse transferred to the output Gain error is a measure of the span error of the DAC. It is the of one DAC at midscale in response to a full-scale code change deviation in slope of the DAC transfer characteristic from the (all 0s to all 1s or vice versa) in the input register of another DAC. ideal, expressed as a percentage of the full-scale range. It is measured in standalone mode and is expressed in nV-s. Zero-Code Error Drift Analog Crosstalk Zero-code error drift is a measure of the change in zero-code Analog crosstalk is the glitch impulse transferred to the output error with a change in temperature. It is expressed in μV/°C. of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale Gain Error Drift LDAC code change (all 0s to all 1s or vice versa) while keeping Gain error drift is a measure of the change in gain error with LDAC high and then pulsing low and monitoring the output of changes in temperature. It is expressed in (ppm of full-scale the DAC whose digital code has not changed. The area of the range)/°C. glitch is expressed in nV-s. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V − 1 LSB. Full-scale error is expressed as REF a percentage of the full-scale range. Figure 17 shows a plot of typical full-scale error vs. temperature. Rev. A | Page 18 of 28 AD5629R/AD5669R DAC-to-DAC Crosstalk Total Harmonic Distortion (THD) DAC-to-DAC crosstalk is the glitch impulse transferred to the Total harmonic distortion is the difference between an ideal output of one DAC due to a digital code change and subsequent sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs measure of the harmonics present on the DAC output. It is with a full-scale code change (all 0s to all 1s or vice versa) with measured in decibels. LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Rev. A | Page 19 of 28 AD5629R/AD5669R THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) SECTION RESISTOR STRING The AD5629R/AD5669R are fabricated on a CMOS process. The resistor string section is shown in Figure 49. It is simply a The architecture consists of a string of DACs followed by an string of resistors, each of value R. The code loaded into the output buffer amplifier. Each part includes an internal DAC register determines at which node on the string the 1.25 V/2.5 V, 5 ppm/°C reference with an internal gain of 2. voltage is tapped off to be fed into the output amplifier. The Figure 47 and Figure 48 show block diagrams of the DAC voltage is tapped off by closing one of the switches connecting architecture. the string to the amplifier. Because it is a string of resistors, it V /V is guaranteed monotonic. REFIN REFOUT R INTERNAL 1 REFERENCE OUTPUT AMPLIFIER GAIN = ×2 REF (+) R DAC RESISTOR V OUT REGISTER STRING REF (–) TO OUTPUT R AMPLIFIER 1 CAN BE OVERDRIVEN BY V /V . REFIN REFOUT GND Figure 47. DAC Architecture for Internal Reference Configuration R V /V REFIN REFOUT R REF BUFFER R OUTPUT AMPLIFIER Figure 49. Resistor String GAIN = ×2 REF (+) R INTERNAL REFERENCE RESISTOR V OUT STRING The AD5629R/AD5669R have an on-chip reference with an REF (–) internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V, 5 ppm/°C reference, giving a full-scale output of 2.5 V or the AD5629R-2/AD5629R-3/AD5669R-2/AD5629R-3 have a 2.5 V, GND 5 ppm/°C reference, working between a supply from 4.5 V to Figure 48. DAC Architecture for External Reference Configuration 5.5 V giving a full-scale output of 5 V. The on-board reference is off at power-up, allowing the use of an external reference. The Because the input coding to the DAC is straight binary, the ideal internal reference is enabled via a write to the control register output voltage when using an external reference is given by (see Table 8). D ⎛ ⎞ V = V × ⎜ ⎟ OUT REFIN N The internal reference associated with each part is available at ⎝ 2 ⎠ the V pin. A buffer is required if the reference output is REFOUT The ideal output voltage when using the internal reference is used to drive external loads. When using the internal reference, given by it is recommended that a 100 nF capacitor be placed between D the reference output and GND for reference stability. ⎛ ⎞ V =2 ×V × ⎜ ⎟ OUT REFOUT N ⎝ 2 ⎠ Individual channel power-down is not supported while using the internal reference. where: D = decimal equivalent of the binary code that is loaded to the DAC register as follows: 0 to 4095 for AD5629R (12 bits). 0 to 65,535 for AD5669R (16 bits). N = the DAC resolution. Rev. A | Page 20 of 28 08819-046 08819-045 08819-047 AD5629R/AD5669R address corresponding to the transmitted address responds OUTPUT AMPLIFIER by pulling SDA low during the ninth clock pulse (this is The output buffer amplifier can generate rail-to-rail voltages termed the acknowledge bit). At this stage, all other devices on its output, which gives an output range of 0 V to VDD. The on the bus remain idle while the selected device waits for amplifier is capable of driving a load of 2 kΩ in parallel with data to be written to or read from its shift register. 1000 pF to GND. The source and sink capabilities of the output 2. Data is transmitted over the serial bus in sequences of nine amplifier can be seen in Figure 24 and Figure 25. The slew rate clock pulses (eight data bits followed by an acknowledge is 1.5 V/μs with a ¼ to ¾ scale settling time of 10 μs. bit). The transitions on the SDA line must occur during SERIAL INTERFACE the low period of SCL and remain stable during the high 2 period of SCL. The AD5629R/AD5669R have 2-wire I C-compatible serial 2 3. When all data bits have been read or written, a stop interfaces (refer to The I C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). The condition is established. In write mode, the master pulls th 2 the SDA line high during the 10 clock pulse to establish AD5629R/AD5669R can be connected to an I C bus as a slave a stop condition. In read mode, the master issues a no device under the control of a master device. See Figure 2 for a acknowledge for the ninth clock pulse (that is, the SDA timing diagram of a typical write sequence. line remains high). The master brings the SDA line low The AD5629R/AD5669R support standard (100 kHz) and fast th th before the 10 clock pulse and then high during the 10 (400 kHz) modes. High speed operation is only available on clock pulse to establish a stop condition. selected models. See the Ordering Guide for a full list of models. Support is not provided for 10-bit addressing and WRITE OPERATION general call addressing. When writing to the AD5629R/AD5669R, the user must begin The AD5629R/AD5669R each have a 7-bit slave address. W with a start command followed by an address byte (R/ = 0), The parts have a slave address whose five MSBs are 10101, after which the DAC acknowledges that it is prepared to receive and the two LSBs are set by the state of the A0 address pin, data by pulling SDA low. The AD5629R/AD5669R require two which determines the state of the A0 and A1 address bits. bytes of data for the DAC and a command byte that controls various DAC functions. Three bytes of data must, therefore, be The facility to make hardwired changes to the A0 pin allows the written to the DAC, the command byte followed by the most user to incorporate up to three of these devices on one bus, as significant data byte and the least significant data byte, as shown in outlined in Table 7. Figure 50. After these data bytes are acknowledged by the Table 7. ADDR Pin Settings AD5629R/AD5669R, a stop condition follows. A0 Pin Connection A1 A0 READ OPERATION V 0 0 DD NC 1 0 When reading data back from the AD5629R/AD5669R, the GND 1 1 user begins with a start command followed by an address byte W (R/ = 1), after which the DAC acknowledges that it is prepared The 2-wire serial bus protocol operates as follows: to transmit data by pulling SDA low. Two bytes of data are then 1. The master initiates data transfer by establishing a start read from the DAC, which are both acknowledged by the master as condition when a high-to-low transition on the SDA line shown in Figure 51. A stop condition follows. occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave 19 1 9 SCL 1 0 1 0 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 SDA START BY ACK. BY ACK. BY MASTER AD5629R/AD5669R AD5629R/AD5669R FRAME 1 FRAME 2 SLAVE ADDRESS COMMAND BYTE 19 1 9 SCL (CONTINUED) SDA DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (CONTINUED) STOP BY ACK. BY ACK. BY MASTER AD5629R/AD5669R AD5629R/AD5669R FRAME 3 FRAME 4 MOST SIGNIFICANT LEAST SIGNIFICANT DATA BYTE DATA BYTE 2 Figure 50. I C Write Operation Rev. A | Page 21 of 28 08819-048 AD5629R/AD5669R 19 1 9 SCL 1 0 1 0 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 SDA START BY ACK. BY ACK. BY MASTER AD5629R/AD5669R MASTER FRAME 1 FRAME 2 SLAVE ADDRESS COMMAND BYTE 19 1 9 SCL (CONTINUED) SDA DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (CONTINUED) STOP BY ACK. BY NO ACK. MASTER MASTER FRAME 3 FRAME 4 MOST SIGNIFICANT LEAST SIGNIFICANT DATA BYTE DATA BYTE 2 Figure 51. I C Read Operation Table 8. Command Definitions INPUT SHIFT REGISTER Command The input shift register is 24 bits wide. Data is loaded into the C3 C2 C1 C0 Description device as a 24-bit word under the control of a serial clock input, 0 0 0 0 Write to Input Register n SCL. The input register contents for this operation is shown in 0 0 0 1 Update DAC Register n Figure 52 and Figure 53. The eight MSBs make up the command 0 0 1 0 Write to Input Register n; update all byte. DB23 to DB20 are the command bits, C3, C2, C1, and C0, (software LDAC) that control the mode of operation of the device (see Table 9 for 0 0 1 1 Write to and update DAC Channel n details). The last four bits of the first byte are the address bits, 0 1 0 0 Power down/power up DAC A3, A2, A1, and A0, (see Table 9 for details). The rest of the bits 0 1 0 1 Load clear code register are the 16-/12-bit data-word. 0 1 1 0 Load LDAC register The AD5669R data-word comprises the 16-bit input code (see 0 1 1 1 Reset (power-on reset) Figure 52) while the AD5629R data word is comprised of 12- 1 0 0 0 Set up internal REF register bits followed by four don’t cares (see Figure 53). 1 0 0 1 Enable multiple byte mode 1 0 1 0 Reserved MULTIPLE BYTE OPERATION – – – – Reserved Multiple byte operation is supported on the AD5629R/ AD5669R. 1 1 1 1 Reserved Command 1001 is reserved for multiple byte operation (see Table 8) A 2-byte operation is useful for applications that Table 9. Address Commands require fast DAC updating and do not need to change the Address (n) command byte. The S bit (DB22) in the command register A3 A2 A1 A0 Selected DAC Channel can be set to 1 for the 2-byte mode of operation. For standard 0 0 0 0 DAC A 3-byte and 4-byte operation, the S bit (DB22) in the command 0 0 0 1 DAC B byte should be set to 0. 0 0 1 0 DAC C 0 0 1 1 DAC D 0 1 0 0 DAC E 0 1 0 1 DAC F 0 1 1 0 DAC G 0 1 1 1 DAC H 1 1 1 1 All DACs Rev. A | Page 22 of 28 08819-049 AD5629R/AD5669R INTERNAL REFERENCE REGISTER POWER-ON RESET The internal reference is available on all versions. The on-board The AD5629R/AD5669R contain a power-on reset circuit that reference is off at power-up by default. The on-board reference controls the output voltage during power-up. The AD5629R/ can be turned off or on by a user-programmable internal REF AD5669R DAC output powers up to 0 V and the AD5669R-3 register by setting Bit DB0 high or low (see Table 10). DB1 DAC output powers up to midscale. The output remains selects the internal reference value. Command 1000 is reserved powered up at this level until a valid write sequence is made for setting the internal REF register (see Table 8). Table 11 to the DAC. This is useful in applications where it is important shows how the state of the bits in the input shift register to know the state of the output of the DAC while it is in the corresponds to the mode of operation of the device. process of powering up. There is also a software executable reset function that resets the DAC to the power-on reset code. Command 0111 is reserved for this reset function (see Table 8). LDAC CLR Any events on or during power-on reset are ignored. DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND DAC ADDRESS DAC DATA DAC DATA COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE Figure 52. AD5669R Input Register Contents DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X COMMAND DAC ADDRESS DAC DATA DAC DATA COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE Figure 53. AD5629R Input Register Contents Rev. A | Page 23 of 28 08819-052 08819-050 AD5629R/AD5669R The bias generator of the selected DAC(s), output amplifier, POWER-DOWN MODES resistor string, and other associated linear circuitry is shut down The AD5629R/AD5669R contain four separate modes of when the power-down mode is activated. The internal reference operation. Command 0100 is reserved for the power-down is powered down only when all channels are powered down. function (see Table 8). These modes are software-programmable However, the contents of the DAC register are unaffected when by setting two bits, Bit DB9 and Bit DB8, in the control register. in power-down. The time to exit power-down is typically 4 μs Table 12 shows how the state of the bits corresponds to the for VDD = 5 V and for VDD = 3 V. mode of operation of the device. Any or all DACs (DAC H to Any combination of DACs can be powered up by setting PD1 DAC A) can be powered down to the selected mode by setting and PD0 to 0 (normal operation). The output powers up to the the corresponding eight bits (DB7 to DB0) to 1. See Table 13 for LDAC value in the input register ( low) or to the value in the the contents of the input shift register during power-down/power- LDAC DAC register before powering down ( high). up operation. CLEAR CODE REGISTER When both bits are set to 0, the part works normally with its normal power consumption of 1.3 mA at 5 V. However, for the CLR The AD5629R/AD5669R have a hardware pin that three power-down modes, the supply current falls to 0.4 μA at CLR is an asynchronous clear input. The input is falling edge 5 V (0.2 μA at 3 V). Not only does the supply current fall, but CLR sensitive. Bringing the line low clears the contents of the the output stage is also internally switched from the output of input register and the DAC registers to the data contained in the amplifier to a resistor network of known values. This has the the user-configurable CLR register and sets the analog outputs advantage that the output impedance of the part is known while accordingly. This function can be used in system calibration to load the part is in power-down mode. There are three different zero scale, midscale, or full scale to all channels together. These options. The output is connected internally to GND through clear code values are user-programmable by setting two bits, Bit either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited CLR DB1 and Bit DB0, in the control register (see Table 15). (three-state). The output stage is illustrated in Figure 54. The default setting clears the outputs to 0 V. Command 0101 is reserved for loading the clear code register (see Table 8). RESISTOR AMPLIFIER V OUT The part exits clear code mode at the end of the next valid write STRING DAC to the part. If CLR is activated during a write sequence, the write is aborted. POWER-DOWN CLR CLR The pulse activation time (the falling edge of to when RESISTOR CIRCUITRY NETWORK the output starts to change) is typically 280 ns. However, if outside the DAC linear region, it typically takes 520 ns after Figure 54. Output Stage During Power-Down CLR executing for the output to start changing (see Figure 43). See Table 14 for the contents of the input shift register during the loading clear code register operation. Table 10. Internal Reference Register Internal REF Register (DB0) Action 0 Reference off (default) 1 Reference on Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 1 0 0 0 X X X X X 1/0 Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Internal REF on/off Rev. A | Page 24 of 28 08819-051 AD5629R/AD5669R Table 12. Power-Down Modes of Operation DB9 DB8 Operating Mode 0 0 Normal operation Power-down modes 0 1 1 kΩ to GND 1 0 100 kΩ to GND 1 1 Three-state Table 13. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function MSB LSB DB23 DB22 DB21 DB20 DB19 to DB16 DB15 to DB10 DB9 DB8 DB7 to DB1 DB0 0 1 0 0 X X PD1 PD0 DAC H to DAC B DAC A Command bits (C3 to C0) Address bits (A3 to A0)— Don’t cares Power- Power-down/power-up channel selection— don’t cares down mode set bit to 1 to select Table 14. 32-Bit Input Shift Register Contents for Clear Code Function MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB2 DB1 DB0 0 1 0 1 X X X X X CR1 CR0 Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Clear code register Table 15. Clear Code Register Clear Code Register DB1 DB0 CR1 CR0 Clears to Code 0 0 0x0000 0 1 0x8000 1 0 0xFFFF 1 1 No operation Rev. A | Page 25 of 28 AD5629R/AD5669R POWER SUPPLY BYPASSING AND GROUNDING LDAC FUNCTION When accuracy is important in a circuit, it is helpful to carefully The outputs of all DACs can be updated simultaneously using consider the power supply and ground return layout on the board. the hardware LDAC pin. The printed circuit board containing the AD5629R/AD5669R Synchronous LDAC should have separate analog and digital sections. If the AD5629R/ AD5669R are in a system where other devices require an The DAC registers are updated after new data is read in. LDAC AGND-to-DGND connection, the connection should be made can be permanently low or pulsed as in Figure 2. at one point only. This ground point should be as close as LDAC Asynchronous possible to the AD5629R/AD5669R. The outputs are not updated at the same time that the input The power supply to the AD5629R/AD5669R should be registers are written to. When LDAC goes low, the DAC bypassed with 10 μF and 0.1 μF capacitors. The capacitors registers are updated with the contents of the input register. should be as physically close as possible to the device, with the Alternatively, the outputs of all DACs can be updated simulta- 0.1 μF capacitor ideally right up against the device. The 10 μF LDAC capacitors are the tantalum bead type. It is important that the neously using the software function by writing to Input 0.1 μF capacitor have low effective series resistance (ESR) and Register n and updating all DAC registers. Command 0011 is LDAC low effective series inductance (ESI), such as is typical of reserved for this software function. common ceramic types of capacitors. This 0.1 μF capacitor LDAC An register gives the user extra flexibility and control provides a low impedance path to ground for high frequencies over the hardware LDAC pin. Setting the LDAC bit register caused by transient currents due to internal logic switching. to 0 for a DAC channel means that this channel’s update is The power supply line should have as large a trace as possible to controlled by the LDAC pin. If this bit is set to 1, this channel provide a low impedance path and reduce glitch effects on the updates synchronously; that is, the DAC register is updated supply line. Clocks and other fast switching digital signals should LDAC after new data is read, regardless of the state of the pin. be shielded from other parts of the board by digital ground. Avoid It effectively sees the LDAC pin as being tied low. See Table 16 crossover of digital and analog signals if possible. When traces for the LDAC register mode of operation. cross on opposite sides of the board, ensure that they run at right This flexibility is useful in applications where the user wants angles to each other to reduce feedthrough effects through the to simultaneously update select channels while the rest of the board. The best board layout technique is the microstrip technique, channels are synchronously updating. Writing to the DAC where the component side of the board is dedicated to the ground LDAC plane only and the signal traces are placed on the solder side. using command 0110 loads the 8-bit register (DB7 to However, this is not always possible with a 2-layer board. LDAC DB0). The default for each channel is 0, that is, the pin works normally. Setting the bits to 1 means the DAC channel is updated regardless of the state of the LDAC pin. See Table 17 for the contents of the input shift register during the load LDAC register mode of operation. Table 16. LDAC Register Load DAC Register LDAC Bits (DB7 to DB0) LDAC Pin LDAC Operation 0 1/0 Determined by LDAC pin. 1 X—don’t care pin. DAC channels see LDAC as 0. DAC channels update, overriding the LDAC Table 17. 32-Bit Input Shift Register Contents for LDAC Register Function MSB LSB DB15 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 X X X X X DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A Command bits (C3 to C0) Address bits (A3 to A0)— Don’t Setting LDAC bit to 1 overrides LDAC pin don’t cares cares Rev. A | Page 26 of 28 AD5629R/AD5669R OUTLINE DIMENSIONS 4.10 0.35 4.00 SQ 0.30 3.90 PIN 1 0.25 INDICATOR 13 16 0.65 12 BSC 1 EXPOSED 2.70 PAD 2.60 SQ 2.50 4 9 8 5 0.45 0.20 MIN TOP VIEW BOTTOM VIEW 0.40 0.35 0.80 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0.65 0° 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 56. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. A | Page 27 of 28 PIN 1 INDICATOR 08-16-2010-C AD5629R/AD5669R ORDERING GUIDE Package Power-On Internal 1 Model Temperature Range Package Description Option Reset to Code Accuracy Reference AD5629RARUZ-1 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 1.25 V AD5629RARUZ-1-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 1.25 V AD5629RBRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V AD5629RBRUZ-2-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V AD5629RACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±4 LSB INL 2.5 V AD5629RACPZ-3-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Midscale ±4 LSB INL 2.5 V AD5629RBCPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±1 LSB INL 1.25 V AD5629RBCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±1 LSB INL 2.5 V AD5669RARUZ-1 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 1.25 V AD5669RARUZ-1-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 1.25 V AD5669RBRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V AD5669RBRUZ-2-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V AD5669RACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±32 LSB INL 2.5 V AD5669RACPZ-3-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Midscale ±32 LSB INL 2.5 V AD5669RBCPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 1.25 V AD5669RBCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 2.5 V AD5669RBCPZ-1500R7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 1.25 V AD5669RBCPZ-2500R7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 2.5 V EVAL-AD5629REBRZ Evaluation Board EVAL-AD5669REBRZ Evaluation Board 1 Z = RoHS Compliant Part. 2 I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08819-0-12/10(A) Rev. A | Page 28 of 28