ANALOG DEVICES AD5627

® Dual, 12-/14-/16-Bit nanoDACs with 2 ® 5 ppm/°C On-Chip Reference, I C Interface AD5627R/AD5647R/AD5667R, AD5627/AD5667 FEATURES FUNCTIONAL BLOCK DIAGRAMS V V /V GND DD REFIN REFOUT Low power, smallest pin-compatible, dual nanoDACs AD5627R/AD5647R/AD5667R AD5627R/AD5647R/AD5667R 1.25V/2.5V REF 12-/14-/16-bit BUFFER ADDR INPUT DAC STRING V A On-chip 1.25 V/2.5 V, 5 ppm/°C reference OUT REGISTER REGISTER DAC A AD5627/AD5667 SCL BUFFER 12-/16-bit INPUT DAC STRING V B OUT REGISTER REGISTER DAC B SDA External reference only POWER-ON POWER-DOWN 3 mm x 3 mm LFCSP and 10-lead MSOP RESET LOGIC 2.7 V to 5.5 V power supply LDAC CLR Guaranteed monotonic by design Figure 1. AD5627R/AD5647R/AD5667R Power-on reset to zero scale V V Per channel power-down DD GND REFIN LDAC CLR Hardware and functions AD5627/AD5667 2 I C-compatible serial interface supports standard (100 kHz), BUFFER ADDR fast (400 kHz), and high speed (3.4 MHz) modes INPUT DAC STRING V A OUT REGISTER REGISTER DAC A SCL BUFFER APPLICATIONS INPUT DAC STRING V B OUT REGISTER REGISTER DAC B SDA Process control POWER-ON POWER-DOWN Data acquisition systems RESET LOGIC Portable battery-powered instruments LDAC CLR Digital gain and offset adjustment Figure 2. AD5627/AD5667 Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5627R/AD5647R/AD5667R, AD5627/AD5667 software-selectable output loads while in power-down mode. members of the nanoDAC family are low power, dual, 12-, 14-, The low power consumption of this part in normal operation 16-bit buffered voltage-out DACs with/without on-chip makes it ideally suited to portable battery-operated equipment. reference. All devices operate from a single 2.7 V to 5.5 V The on-chip precision output amplifier enables rail-to-rail 2 supply, are guaranteed monotonic by design, and have an I C- output swing. compatible serial interface. 2 The AD56x7R/AD56x7 use a 2-wire I C-compatible serial The AD5627R/AD5647R/AD5667R have an on-chip reference. interface that operates in standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes. The AD56x7RBCPZ have a 1.25 V, 5 ppm/°C reference, giving a full-scale output range of 2.5 V; the AD56x7RBRMZ have a Table 1. Related Devices 2.5 V, 5 ppm/°C reference, giving a full-scale output range of 5 Part No. Description V. The on-chip reference is off at power-up, allowing the use of AD5663 2.7 V to 5.5 V, dual 16-bit DAC, an external reference. The internal reference is enabled via a external reference, SPI® interface software write. The AD5667 and AD5627 require an external AD5623R/AD5643R/AD5663R 2.7 V to 5.5 V, dual 12-, 14-, 16-bit reference voltage to set the output range of the DAC. DACs, internal reference, SPI interface The AD56x7R/AD56x7 incorporate a power-on reset circuit AD5625R/AD5645R/AD5665R, 2.7 V to 5.5 V, quad 12-, 14-, 16-bit that ensures the DAC output powers up to 0 V, and remains AD5625/AD5665 DACs, with/without internal there until a valid write takes place. The part contains a per- 2 reference, I C interface channel power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INTERFACE INTERFACE LOGIC LOGIC 06342-002 06342-001 AD5627R/AD5647R/AD5667R, AD5627/AD5667 TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 21 Applications....................................................................................... 1 Write Operation.......................................................................... 21 Functional Block Diagrams............................................................. 1 Read Operation........................................................................... 21 General Description ......................................................................... 1 High Speed Mode....................................................................... 21 Revision History ............................................................................... 2 Input Shift Register .................................................................... 23 Specifications..................................................................................... 3 Multiple Byte Operation............................................................ 23 AC Characteristics........................................................................ 5 Broadcast Mode.......................................................................... 23 2 I C Timing Specifications............................................................ 6 LDAC Function .......................................................................... 23 Absolute Maximum Ratings............................................................ 8 Power-Down Modes .................................................................. 25 ESD Caution.................................................................................. 8 Power-On Reset and Software Reset ....................................... 26 Pin Configuration and Function Descriptions............................. 9 Clear Pin (CLR).......................................................................... 26 Typical Performance Characteristics ........................................... 10 Internal Reference Setup (R Versions) .................................... 26 Terminology .................................................................................... 18 Application Information................................................................ 27 Theory of Operation ...................................................................... 20 Using a Reference as a Power Supply for the AD56x7R/AD56x7..................................................................... 27 D/A Section................................................................................. 20 Bipolar Operation Using the AD56x7R/AD56x7 .................. 27 Resistor String............................................................................. 20 Power Supply Bypassing and Grounding................................ 27 Output Amplifier........................................................................ 20 Outline Dimensions....................................................................... 28 Internal reference........................................................................ 20 Ordering Guide .......................................................................... 29 External reference....................................................................... 20 REVISION HISTORY 1/07—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE AD5667R/AD5667 Resolution 16 Bits Relative Accuracy ±8 ±12 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design AD5647R Resolution 14 Bits Relative Accuracy ±2 ±4 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design AD5627R/AD5627 Resolution 12 Bits Relative Accuracy ±0.5 ±1 LSB Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design Zero-Code Error 2 10 mV All 0s loaded to DAC register Offset Error ±1 ±10 mV Full-Scale Error −0.1 ±1 % of FSR All 1s loaded to DAC register Gain Error ±1.5 % of FSR Zero-Code Error Drift ±2 μV/°C Gain Temperature Coefficient ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 dB DAC code = midscale ; VDD = 5 V ± 10% DC Crosstalk (External Reference) 15 μV Due to full-scale output change, R = 2 kΩ to GND or 2 kΩ to V L DD 10 μV/mA Due to load current change 8 μV Due to powering down (per channel) DC Crosstalk (Internal Reference) 25 μV Due to full-scale output change, RL = 2 kΩ to GND or 2 kΩ to VDD 20 μV/mA Due to load current change 10 μV Due to powering down (per channel) 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 VDD V Capacitive Load Stability 2 nF R = ∞ L 10 nF R = 2 kΩ L DC Output Impedance 0.5 Ω Short-Circuit Current 30 mA VDD = 5 V Power-Up Time 4 μs Coming out of power-down mode; VDD = 5 V REFERENCE INPUTS Reference Current 110 130 μA VREF = VDD = 5.5 V Reference Input Range 0.75 VDD V Reference Input Impedance 50 kΩ REFERENCE OUTPUT (LFCSP_WD PACKAGE) Output Voltage 1.247 1.253 V At ambient 3 Reference TC ±10 ppm/°C Output Impedance 7.5 kΩ REFERENCE OUTPUT (MSOP PACKAGE) Output Voltage 2.495 2.505 V At ambient 3 Reference TC ±5 ±10 ppm/°C Output Impedance 7.5 kΩ Rev. 0 | Page 3 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 1 Parameter Min Typ Max Unit Conditions/Comments 3 LOGIC INPUTS (ADDR, CLR, LDAC) IIN, Input Current ±1 μA VINL, Input Low Voltage 0.15 × VDD V V , Input High Voltage 0.85 × V V INH DD C , Pin Capacitance 2 pF ADDR IN 20 pF CLR, LDAC VHYST, Input Hysteresis 0.1 × VDD V LOGIC INPUTS (SDA, SCL) I , Input Current ±1 μA IN VINL, Input Low Voltage 0.3 × VDD V VINH, Input High Voltage 0.7 × VDD V C , Pin Capacitance 2 pF IN V , Input Hysteresis 0.1 × V V HYST DD LOGIC OUTPUTS (OPEN-DRAIN) V , Output Low Voltage 0.4 V I = 3 mA OL SINK 0.6 V I = 6 mA SINK Floating-State Leakage Current ±1 μA Floating-State Output Capacitance 2 pF POWER REQUIREMENTS V 2.7 5.5 V DD 4 IDD (Normal Mode) VIH = VDD, VIL = GND VDD = 4.5 V to 5.5 V 0.4 0.5 mA Internal reference off V = 2.7 V to 3.6 V 0.35 0.45 mA Internal reference off DD V = 4.5 V to 5.5 V 0.95 1.15 mA Internal reference on DD V = 2.7 V to 3.6 V 0.8 0.95 mA Internal reference on DD 5 IDD (All Power-Down Modes) 0.48 1 μA VIH = VDD, VIL = GND 1 Temperature range: B grade: −40°C to +105°C. 2 Linearity calculated using a reduced code range: AD5567R/AD5667 (Code 512 to Code 65,024); AD5647R (Code 128 to Code 16,256); AD5627R/AD5627 (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down. Rev. 0 | Page 4 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 AC CHARACTERISTICS 1 VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 3. 2 3 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time AD5627R/AD5627 3 4.5 μs ¼ to ¾ scale settling to ±0.5 LSB AD5647R 3.5 5 μs ¼ to ¾ scale settling to ±0.5 LSB AD5667R/AD5667 4 7 μs ¼ to ¾ scale settling to ±2 LSB Slew Rate 1.8 V/μs Digital-to-Analog Glitch Impulse 15 nV-s 1 LSB change around major carry transition Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dB V = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz REF Digital Crosstalk 0.1 nV-s Analog Crosstalk 1 nV-s External reference 4 nV-s Internal reference DAC-to-DAC Crosstalk 1 nV-s External reference 4 nV-s Internal reference Multiplying Bandwidth 340 kHz V = 2 V ± 0.1 V p-p REF Total Harmonic Distortion −80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz 100 nV/√Hz DAC code = midscale, 10 kHz Output Noise 15 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical @ 25°C. Rev. 0 | Page 5 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 2 I C TIMING SPECIFICATIONS 1 VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted. Table 4. 2 Parameter Conditions Min Max Unit Description 3 f Standard mode 100 kHz Serial clock frequency SCL Fast mode 400 kHz High speed mode, CB = 100 pF 3.4 MHz High speed mode, CB = 400 pF 1.7 MHz t Standard mode 4 μs t , SCL high time 1 HIGH Fast mode 0.6 μs High speed mode, CB = 100 pF 60 ns High speed mode, CB = 400 pF 120 ns t2 Standard mode 4.7 μs tLOW, SCL low time Fast mode 1.3 μs High speed mode, C = 100 pF 160 ns B High speed mode, C = 400 pF 320 ns B t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns High speed mode 10 ns t Standard mode 0 3.45 μs t , data hold time 4 HD;DAT Fast mode 0 0.9 μs High speed mode, C = 100 pF 0 70 ns B High speed mode, CB = 400 pF 0 150 ns t5 Standard mode 4.7 μs tSU;STA, setup time for a repeated start condition Fast mode 0.6 μs High speed mode 160 ns t Standard mode 4 μs t , hold time (repeated) start condition 6 HD;STA Fast mode 0.6 μs High speed mode 160 ns t7 Standard mode 4.7 μs tBUF, bus free time between a stop and a start condition Fast mode 1.3 μs t Standard mode 4 μs t , setup time for a stop condition 8 SU;STO Fast mode 0.6 μs High speed mode 160 ns t9 Standard mode 1000 ns tRDA, rise time of SDA signal Fast mode 300 ns High speed mode, C = 100 pF 10 80 ns B High speed mode, C = 400 pF 20 160 ns B t10 Standard mode 300 ns tFDA, fall time of SDA signal Fast mode 300 ns High speed mode, CB = 100 pF 10 80 ns High speed mode, C = 400 pF 20 160 ns B t Standard mode 1000 ns t , rise time of SCL signal 11 RCL Fast mode 300 ns High speed mode, CB = 100 pF 10 40 ns High speed mode, CB = 400 pF 20 80 ns t11A Standard mode 1000 ns t , rise time of SCL signal after a repeated start condition and after RCL1 an acknowledge bit Fast mode 300 ns High speed mode, C = 100 pF 10 80 ns B High speed mode, CB = 400 pF 20 160 ns Rev. 0 | Page 6 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 2 Parameter Conditions Min Max Unit Description t12 Standard mode 300 ns tFCL, fall time of SCL signal Fast mode 300 ns High speed mode, CB = 100 pF 10 40 ns High speed mode, C = 400 pF 20 80 ns B t Standard mode 10 ns LDAC pulse width low 13 Fast mode 10 ns High speed mode 10 ns th t14 Standard mode 300 ns Falling edge of 9 SCL clock pulse of last byte of valid write to LDAC falling edge Fast mode 300 ns High speed mode 30 ns t15 Standard mode 20 ns CLR pulse width low Fast mode 20 ns High speed mode 20 ns 4 t Fast mode 0 50 ns Pulse width of spike suppressed SP High speed mode 0 10 ns 1 See Figure 3. High speed mode timing specification applies only to the AD5627RBRMZ-2/AD5627BRMZ-2REEL7 and AD5667RBRMZ-2/AD5667BRMZ-2REEL7. 2 CB refers to the capacitance on the bus line. 3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 4 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode. t t 11 12 t 6 t 2 SCL t t t 6 1 5 t 8 t 4 t t t 3 10 9 SDA t 7 PS S P t 14 t 13 LDAC* t 15 CLR *ASYNCHRONOUS LDAC UPDATE MODE. Figure 3. 2-Wire Serial Interface Timing Diagram Rev. 0 | Page 7 of 32 06342-003 AD5627R/AD5647R/AD5667R, AD5627/AD5667 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute VOUT to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V device reliability. Digital Input Voltage to GND −0.3 V to V + 0.3 V DD Operating Temperature Range, Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C ESD CAUTION Junction Temperature (TJ maximum) 150°C Power Dissipation (TJ max − TA)/θJA θ Thermal Impedance JA LFCSP_WD Package (4-Layer Board) 61°C/W MSOP Package 150.4°C/W Reflow Soldering Peak Temperature, Pb-Free 260°C ± 5°C Rev. 0 | Page 8 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V A 1 10 V V A 1 10 V /V OUT REFIN OUT REFIN REFOUT AD5627/ AD5627R/ V B 2 9 V V B 2 9 V OUT DD OUT DD AD5667 AD5647R/ GND 3 8 SDA GND 3 8 SDA AD5667R 4 7 4 7 LDAC SCL LDAC SCL TOP VIEW TOP VIEW (Not to Scale) (Not to Scale) CLR 5 6 ADDR CLR 5 6 ADDR EXPOSED PAD TIED TO GND EXPOSED PAD TIED TO GND ON LFCSP PACKAGE. ON LFCSP PACKAGE. Figure 4. AD5627/AD5667 Pin Configuration Figure 5. AD5627R/AD5647R/AD5667R Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 2 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 3 GND Ground reference point for all circuitry on the part. 4 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the inputs have new data. This allows simultaneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low. 5 CLR Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits th clear code mode on the falling edge of the 9 clock pulse of the last byte of valid write. If CLR is activated during a write sequence, the write is aborted. If CLR is activated during high speed mode the part will exit high speed mode. 6 ADDR Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address. 7 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register. 8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 24-bit input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. 9 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a DD 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 10 VREFIN/VREFOUT The AD56x7R have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. (The internal reference and reference output are only available on R suffix versions.) The AD56x7 has a reference input pin only. Rev. 0 | Page 9 of 32 06342-101 06342-102 AD5627R/AD5647R/AD5667R, AD5627/AD5667 TYPICAL PERFORMANCE CHARACTERISTICS 10 1.0 V = V = 5V DD REF V = V = 5V DD REF T = 25°C 0.8 T = 25°C 8 A A 0.6 6 0.4 4 2 0.2 0 0 –0.2 –2 –4 –0.4 –0.6 –6 –8 –0.8 –10 –1.0 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 0 10k 20k 30k 40k 50k 60k CODE CODE Figure 9. AD5667 DNL, External Reference Figure 6. AD5667 INL, External Reference 4 0.5 V = V = 5V DD REF V = V = 5V DD REF T = 25°C A 0.4 T = 25°C A 3 0.3 2 0.2 1 0.1 0 0 –0.1 –1 –0.2 –2 –0.3 –3 –0.4 –4 –0.5 0 2500 5000 7500 10000 12500 15000 0 2500 5000 7500 10000 12500 15000 CODE CODE Figure 7. AD5647R INL, External Reference Figure 10. DNL AD5647R, External Reference 1.0 0.20 V = V = 5V V = V = 5V DD REF DD REF T = 25°C T = 25°C 0.8 A A 0.15 0.6 0.10 0.4 0.05 0.2 0 0 –0.2 –0.05 –0.4 –0.10 –0.6 –0.15 –0.8 –1.0 –0.20 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 8. AD5627 INL, External Reference Figure 11. AD5627 DNL, External Reference Rev. 0 | Page 10 of 32 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 06342-006 06342-100 06342-005 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 06342-008 06342-009 06342-007 AD5627R/AD5647R/AD5667R, AD5627/AD5667 1.0 10 V =5V V = 5V DD DD 0.8 V =2.5V 8 V = 2.5V REFOUT REFOUT T =25°C T = 25°C A A 0.6 6 4 0.4 0.2 2 0 0 –0.2 –2 –4 –0.4 –6 –0.6 –8 –0.8 –1.0 –10 CODE CODE Figure 12. AD5667R INL, 2.5 V Internal Reference Figure 15. AD5667R DNL, 2.5 V Internal Reference 4 0.5 V =5V DD V = 5V DD V =2.5V REFOUT 0.4 V = 2.5V REFOUT 3 T =25°C A T = 25°C A 0.3 2 0.2 1 0.1 0 0 –0.1 –1 –0.2 –2 –0.3 –3 –0.4 –4 –0.5 CODE CODE Figure 13. AD5647R INL, 2.5 V Internal Reference Figure 16. AD5647R DNL, 2.5 V Internal Reference 1.0 0.20 V =5V DD V = 5V DD 0.8 V =2.5V REFOUT V = 2.5V REFOUT 0.15 T = 25°C A T = 25°C A 0.6 0.10 0.4 0.05 0.2 0 0 –0.2 –0.05 –0.4 –0.10 –0.6 –0.15 –0.8 –1.0 –0.20 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 14. AD5627R INL, 2.5 V Internal Reference Figure 17. AD5627R DNL, 2.5 V Internal Reference Rev. 0 | Page 11 of 32 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 0 0 1250 5000 2500 10000 3750 15000 5000 20000 6250 25000 7500 30000 8750 35000 10000 40000 11250 45000 12500 50000 13750 55000 15000 60000 16250 65000 06342-011 06342-010 06342-012 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 0 0 1250 5000 2500 10000 3750 15000 5000 20000 6250 25000 7500 30000 8750 35000 10000 40000 11250 45000 50000 12500 13750 55000 15000 60000 16250 65000 06342-015 06342-014 06342-013 AD5627R/AD5647R/AD5667R, AD5627/AD5667 10 1.0 V = 3V V = 3V DD DD 8 V = 1.25V 0.8 V = 1.25V REFOUT REFOUT T = 25°C T = 25°C A A 6 0.6 4 0.4 2 0.2 0 0 –2 –0.2 –4 –0.4 –6 –0.6 –8 –0.8 –10 –1.0 CODE CODE Figure 18. AD5667R INL,1.25 V Internal Reference Figure 21. AD5667R DNL,1.25 V Internal Reference 4 0.5 V = 3V V = 3V DD DD 0.4 V = 1.25V V = 1.25V REFOUT REFOUT 3 T = 25°C T = 25°C A A 0.3 2 0.2 1 0.1 0 0 –0.1 –1 –0.2 –2 –0.3 –3 –0.4 –4 –0.5 CODE CODE Figure 19. AD5647R INL, 1.25 V Internal Reference Figure 22. AD5647R DNL,1.25 V Internal Reference 1.0 0.20 V = 3V V = 3V DD DD 0.8 V = 1.25V V = 1.25V REFOUT REFOUT 0.15 T = 25°C T = 25°C A A 0.6 0.10 0.4 0.05 0.2 0 0 –0.2 –0.05 –0.4 –0.10 –0.6 –0.15 –0.8 –1.0 –0.20 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 20. AD5627R INL,1.25 V Internal Reference Figure 23. AD5627R DNL, 1.25 V Internal Reference Rev. 0 | Page 12 of 32 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 0 0 1250 5000 10000 2500 15000 3750 20000 5000 25000 6250 30000 7500 35000 8750 40000 10000 45000 11250 50000 12500 55000 13750 60000 15000 16250 65000 06342-018 06342-017 06342-016 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 0 0 5000 1250 10000 2500 15000 3750 20000 5000 25000 6250 30000 7500 35000 8750 40000 10000 45000 11250 50000 12500 55000 13750 60000 15000 16250 65000 06342-021 06342-020 06342-019 AD5627R/AD5647R/AD5667R, AD5627/AD5667 8 0 V = 5V DD –0.02 6 MAX INL V = V = 5V DD REF –0.04 GAIN ERROR 4 –0.06 2 –0.08 MAX DNL 0 –0.10 MIN DNL –0.12 –2 –0.14 FULL-SCALE ERROR –4 –0.16 MIN INL –6 –0.18 –8 –0.20 –40 –2001 20 40 60 8000 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 24. INL Error and DNL Error vs. Temperature Figure 27. Gain Error and Full-Scale Error vs. Temperature 10 1.5 8 MAX INL 1.0 ZERO-SCALE ERROR 6 V = 5V 0.5 DD 4 T = 25°C A 0 2 MAX DNL –0.5 0 MIN DNL –2 –1.0 –4 –1.5 OFFSET ERROR –6 MIN INL –2.0 –8 –10 –2.5 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 –40 –2008 20 40 600 100 V (V) TEMPERATURE (°C) REF Figure 28. Zero-Scale Error and Offset Error vs. Temperature Figure 25. INL and DNL Error vs. VREF 8 1.0 6 MAX INL 0.5 T = 25°C A 4 GAIN ERROR 0 2 MAX DNL FULL-SCALE ERROR 0 –0.5 MIN DNL –2 –1.0 –4 MIN INL –1.5 –6 –8 –2.0 2.7 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2 V (V) V (V) DD DD Figure 26. INL and DNL Error vs. Supply Figure 29. Gain Error and Full-Scale Error vs. Supply Rev. 0 | Page 13 of 32 ERROR (LSB) ERROR (LSB) ERROR (LSB) 06342-022 06342-024 06342-023 ERROR (% FSR) ERROR (mV) ERROR (% FSR) 06342-026 06342-025 06342-027 AD5627R/AD5647R/AD5667R, AD5627/AD5667 1.0 0.5 T = 25°C DAC LOADED WITH DAC LOADED WITH A 0.4 FULL-SCALE ZERO-SCALE 0.5 SOURCING CURRENT SINKING CURRENT ZERO-SCALE ERROR 0.3 0 0.2 V = 3V 0.1 DD –0.5 V = 1.25V REFOUT 0 –1.0 –0.1 –0.2 –1.5 V = 5V –0.3 DD V = 2.5V –2.0 REFOUT OFFSET ERROR –0.4 –2.5 –0.5 2.7 3.2 3.7 4.2 4.7 5.2 –10 –8 –6 –4 –2 0 2 461 8 0 V (V) CURRENT (mA) DD Figure 30. Zero-Scale Error and Offset Error vs. Supply Figure 33. Headroom at Rails vs. Source and Sink 6 V = 3.6V DD V = 5V DD FULL SCALE V = 2.5V V = 5.5V DD REFOUT 5 T = 25°C A 3/4 SCALE 4 3 MIDSCALE 2 1/4 SCALE 1 0 ZERO SCALE –1 0.30 0.32 0.34 0.36 0.38 0.40 0.42 0.44 –30 –20 –10 0 10 20 30 I (mA) CURRENT (mA) DD Figure 34. AD56x7R with 2.5 V Reference, Source and Sink Capability Figure 31. I Histogram with External Reference DD 4 V = 3.6V DD V = 3V DD V = 1.25V REFOUT V = 1.25V V = 5.5V DD REFOUT T = 25°C A 3 FULL SCALE 3/4 SCALE 2 V = 2.5V REFOUT MIDSCALE 1 1/4 SCALE 0 ZERO SCALE –1 –30 –20 –10 0 10 20 30 CURRENT (mA) I (mA) DD Figure 32. IDD Histogram with Internal Reference Figure 35. AD56x7R with 1.25 V Reference, Source and Sink Capability Rev. 0 | Page 14 of 32 18 16 14 12 10 8 6 4 2 0 14 12 10 8 6 4 2 0 NUMBER OF DEVICES NUMBER OF DEVICES ERROR (mV) 0.74 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 06342-029 06342-030 06342-028 V (V) V (V) ERROR VOLTAGE (V) OUT OUT 06342-047 06342-046 06342-031 AD5627R/AD5647R/AD5667R, AD5627/AD5667 0.9 T = 25°C A 0.8 V = 5V, V = 2.5V DD REFOUT 0.7 V = V = 5V DD REF 0.6 T = 25°C A FULL-SCALE CODE CHANGE 0.5 0x0000 TO 0xFFFF V = V = 5V DD REF OUTPUT LOADED WITH 2kΩ AND 200pF TO GND 0.4 0.3 V = 909mV/DIV OUT 0.2 1 0.1 0 512 10512 20512 30512 40512 50512 60512 TIME BASE = 4µs/DIV CODE Figure 36. Supply Current vs. Code Figure 39. Full-Scale Settling Time, 5 V 0.40 V = V = 5V DD REF T = 25°C A 0.35 0.30 0.25 0.20 V DD 1 0.15 0.10 MAX(C2) 420.0mV 2 0.05 V OUT T = 25°C A 0 CH1 2.0V CH2 500mV M100µs 125MS/s 8.0ns/pt 3.7 4.2 4.7 5.2 2.7 3.2 A CH1 1.28V SUPPLY VOLTAGE (V) Figure 37. Supply Current vs. Supply Voltage Figure 40. Power-On Reset to 0 V 0.45 SYNC V = V = 5V DD REFIN 0.40 1 SLCK 0.35 3 V = V = 3V DD REFIN 0.30 0.25 0.20 0.15 V OUT 0.10 V = 5V DD 2 0.05 0 CH1 5.0V CH2 500mV M400ns A CH1 1.4V –40 –20 0 20 40 60 80 100 CH3 5.0V TEMPERATURE (°C) Figure 38. Supply Current vs. Temperature Figure 41. Exiting Power-Down to Midscale Rev. 0 | Page 15 of 32 I (mA) I (mA) DD I (mA) DD DD 06342-061 06342-060 06342-063 06342-050 06342-049 06342-048 AD5627R/AD5647R/AD5667R, AD5627/AD5667 2.538 V = V = 5V V = V = 5V DD REF DD REF 2.537 T = 25°C T = 25°C A A 2.536 DAC LOADED WITH MIDSCALE 5ns/SAMPLE NUMBER 2.535 GLITCH IMPULSE = 9.494nV 2.534 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF) 2.533 2.532 2.531 2.530 1 2.529 2.528 2.527 2.526 2.525 2.524 2.523 2.522 2.521 0 50 100 150 200 250 300 350 400 450 512 4s/DIV SAMPLE NUMBER Figure 42. Digital-to-Analog Glitch Impulse (Negative) Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference 2.498 V = 5V V = V = 5V DD DD REF V = 2.5V T = 25°C REFOUT A T = 25°C 5ns/SAMPLE NUMBER A 2.497 DAC LOADED WITH MIDSCALE ANALOG CROSSTALK = 0.424nV 2.496 2.495 1 2.494 2.493 2.492 2.491 0 50 100 150 200 250 300 350 400 450 512 5s/DIV SAMPLE NUMBER Figure 43. Analog Crosstalk, External Reference Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference 2.496 V = 3V DD 2.494 V = 1.25V REFOUT 2.492 T = 25°C A 2.490 DAC LOADED WITH MIDSCALE 2.488 2.486 2.484 2.482 2.480 2.478 1 2.476 2.474 2.472 2.470 2.468 2.466 V = 5V DD 2.464 V = 2.5V REFOUT 2.462 T = 25°C A 2.460 5ns/SAMPLE NUMBER 2.458 ANALOG CROSSTALK = 4.462nV 2.456 0 50 100 150 200 250 300 350 400 450 512 4s/DIV SAMPLE NUMBER Figure 44. Analog Crosstalk, Internal Reference Figure 47. 0.1 Hz to 10 Hz Output Noise Plot,1.25 V Internal Reference Rev. 0 | Page 16 of 32 V (V) V (V) V (V) OUT OUT OUT 06342-062 06342-059 06342-058 5µV/DIV 10µV/DIV 2µV/DIV 06342-051 06342-053 06342-052 AD5627R/AD5647R/AD5667R, AD5627/AD5667 800 16 T = 25°C V = V A REF DD MIDSCALE LOADED T = 25°C A 700 14 600 V = 3V DD 12 500 400 10 300 V = 5V DD 8 V = 5V DD V = 2.5V REFOUT 200 6 100 V = 3V DD V = 1.25V REFOUT 0 4 100 1k 10k 100k 1M 01 2 3 4 5 6781 9 0 FREQUENCY (Hz) CAPACITANCE (nF) Figure 48. Noise Spectral Density, Internal Reference Figure 50. Settling Time vs. Capacitive Load –20 5 V = 5V V = 5V DD DD T = 25°C T = 25°C A A 0 –30 DAC LOADED WITH FULL SCALE V = 2V ± 0.3V p-p REF –5 –40 –10 –50 –15 –60 –20 –70 –25 –80 –30 –90 –35 –100 –40 2k 4k 6k 8k 10k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 49. Total Harmonic Distortion Figure 51. Multiplying Bandwidth Rev. 0 | Page 17 of 32 OUTPUT NOISE (nV/√Hz) (dB) 06342-055 06342-054 (dB) TIME (µs) 06342-056 06342-057 AD5627R/AD5647R/AD5667R, AD5627/AD5667 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Digital-to-Analog Glitch Impulse For the DAC, relative accuracy or integral nonlinearity is a Digital-to-analog glitch impulse is the impulse injected into the measurement of the maximum deviation, in LSBs, from a straight analog output when the input code in the DAC register changes line passing through the endpoints of the DAC transfer function. state. It is normally specified as the area of the glitch in nV-s, and is measured when the digital input code is changed by Differential Nonlinearity (DNL) 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Differential nonlinearity is the difference between the measured Figure 42). change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures Digital Feedthrough monotonicity. This DAC is guaranteed monotonic by design. Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the Zero-Code Error DAC, but is measured when the DAC output is not updated. It Zero-code error is a measurement of the output error when is specified in nV-s, and measured with a full-scale code change zero scale (0x0000) is loaded to the DAC register. Ideally, the on the data bus, that is, from all 0s to all 1s and vice versa. output should be 0 V. The zero-code error is always positive in the AD5667R because the output of the DAC cannot go below Reference Feedthrough 0 V due to a combination of the offset errors in the DAC and Reference feedthrough is the ratio of the amplitude of the signal the output amplifier. Zero-code error is expressed in mV. at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. Full-Scale Error Full-scale error is a measurement of the output error when full- Output Noise Spectral Density scale code (0xFFFF) is loaded to the DAC register. Ideally, the Output noise spectral density is a measurement of the internally output should be VDD − 1 LSB. Full-scale error is expressed in % generated random noise. Random noise is characterized as a of full-scale range (FSR). spectral density. It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. A Gain Error plot of noise spectral density can be seen in Figure 48. Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal DC Crosstalk expressed in % of FSR. DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is Zero-Code Error Drift measured with a full-scale output change on one DAC (or soft Zero-code error drift is a measurement of the change in zero- power-down and power-up) while monitoring another DAC kept code error with a change in temperature. It is expressed in μV/°C. at midscale. It is expressed in μV. Gain Temperature Coefficient DC crosstalk due to load current change is a measure of the Gain temperature coefficient is a measurement of the change in impact that a change in load current on one DAC has to gain error with changes in temperature. It is expressed in ppm another DAC kept at midscale. It is expressed in μV/mA. of FSR/°C. Digital Crosstalk Offset Error Digital crosstalk is the glitch impulse transferred to the output Offset error is a measure of the difference between VOUT (actual) of one DAC at midscale in response to a full-scale code change and VOUT (ideal) expressed in mV in the linear region of the (all 0s to all 1s and vice versa) in the input register of another transfer function. Offset error is measured on the AD5667R DAC. It is measured in standalone mode and is expressed in nV-s. with code 512 loaded in the DAC register. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) DC PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V and VDD is varied by ±10%. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change and is measured from the rising edge of the stop condition. Rev. 0 | Page 18 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 Analog Crosstalk Multiplying Bandwidth Analog crosstalk is the glitch impulse transferred to the output The multiplying bandwidth is a measure of the finite bandwidth of one DAC due to a change in the output of another DAC. It is of the amplifiers within the DAC. A sine wave on the reference measured by loading one of the input registers with a full-scale (with full-scale code loaded to the DAC) appears on the output. code change (all 0s to all 1s and vice versa), then executing a The multiplying bandwidth is the frequency at which the output software LDAC and monitoring the output of the DAC whose amplitude falls to 3 dB below the input. digital code was not changed. The area of the glitch is expressed Total Harmonic Distortion (THD) in nV-s. THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the DAC-to-DAC Crosstalk reference for the DAC, and the THD is a measurement of the DAC-to-DAC crosstalk is the glitch impulse transferred to the harmonics present on the DAC output. It is measured in dB. output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-s. Rev. 0 | Page 19 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 THEORY OF OPERATION D/A SECTION R The AD56x7R/AD56x7 DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by R an output buffer amplifier. Figure 52 shows a block diagram of the DAC architecture. TO OUTPUT R AMPLIFIER V DD OUTPUT AMPLIFIER GAIN = +2 REF (+) DAC RESISTOR V OUT REGISTER STRING REF (–) R GND R Figure 52. DAC Architecture Because the input coding to the DAC is straight binary, the ideal Figure 53. Resistor String output voltage when using an external reference is given by INTERNAL REFERENCE D ⎛ ⎞ V = V × ⎜ ⎟ OUT REFIN N ⎝ 2 ⎠ The AD5627R/AD5647R/AD5667R feature an on-chip reference. Versions without the R suffix require an external The ideal output voltage when using the internal reference is reference. The on-chip reference is off at power-up and is given by enabled via a write to a control register. See the Internal D ⎛ ⎞ Reference Setup section for details. V = 2×V × ⎜ ⎟ OUT REFOUT N ⎝ 2 ⎠ Versions packaged in a 10-lead LFCSP package have a 1.25 V where: reference, giving a full-scale output of 2.5 V. These parts can be operated with a VDD supply of 2.7 V to 5.5 V. Versions packaged D is the decimal equivalent of the binary code that is loaded to in a 10-lead MSOP package have a 2.5 V reference, giving a full- the DAC register: scale output of 5 V. The parts are functional with a VDD supply 0 to 4095 for AD5627R/AD5627 (12-bit). of 2.7 V to 5.5 V, but with a V supply of less than 5 V, the DD 0 to 16,383 for AD5647R (14-bit). output is clamped to V . See the Ordering Guide for a full list DD 0 to 65,535 for AD5667R/AD5667 (16-bit). of models. The internal reference associated with each part is N is the DAC resolution. available at the V pin. REFOUT RESISTOR STRING A buffer is required if the reference output is used to drive external loads. When using the internal reference, it is The resistor string is shown in Figure 53. It is simply a string of recommended that a 100 nF capacitor be placed between the resistors, each of value R. The code loaded to the DAC register reference output and GND for reference stability. determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by EXTERNAL REFERENCE closing one of the switches connecting the string to the amplifier. The AD5627/AD5667 require an external reference, which is Because it is a string of resistors, it is guaranteed monotonic. applied at the VREFIN pin. The VREFIN pin on the AD56x7R allows OUTPUT AMPLIFIER the use of an external reference if the application requires it. The default condition of the on-chip reference is off at power- The output buffer amplifier can generate rail-to-rail voltages on up. All devices can be operated from a single 2.7 V to 5.5 V supply. its output, which gives an output range of 0 V to V . It can drive DD a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 33 and Figure 34. The slew rate is 1.8 V/μs with a ¼ to ¾ full-scale settling time of 7 μs. Rev. 0 | Page 20 of 32 06342-032 06342-033 AD5627R/AD5647R/AD5667R, AD5627/AD5667 SERIAL INTERFACE WRITE OPERATION 2 The AD56x7R/AD56x7 have 2-wire I C-compatible serial When writing to the AD56x7R/AD56x7, the user must begin 2 interfaces (refer to I C-Bus Specification, Version 2.1, January 2000, with a start command followed by an address byte (R/W= 0), available from Philips Semiconductor). The AD56x7R/AD56x7 after which the DAC acknowledges that it is prepared to receive 2 can be connected to an I C bus as a slave device, under the control data by pulling SDA low. The AD56x7R/AD56x7 requires two of a master device. See Figure 3 for a timing diagram of a bytes of data for the DAC and a command byte that controls typical write sequence. various DAC functions. Three bytes of data must therefore be written to the DAC, the command byte followed by the most The AD56x7R/AD56x7 support standard (100 kHz), fast significant data byte and the least significant data byte, as (400 kHz), and high speed (3.4 MHz) data transfer modes. shown in Figure 54. All these data bytes are acknowledged by High speed operation is only available on select models. See the AD56x7R/AD56x7. A stop condition follows. the Ordering Guide for a full list of models. Support is not provided for 10-bit addressing and general call addressing. READ OPERATION The AD56x7R/AD56x7 each have a 7-bit slave address. The five When reading data back from the AD56x7R/AD56x7, the user MSBs are 00011 and the two LSBs (A1, A0) are set by the state begins with a start command followed by an address byte of the ADDR address pin. The facility to make hardwired (R/W = 1), after which the DAC acknowledges that it is changes to ADDR allows the user to incorporate up to three of prepared to transmit data by pulling SDA low. Three bytes of these devices on one bus, as outlined in Table 7. data are then read from the DAC, which are acknowledged by the master, as shown in Figure 55. A stop condition follows. Table 7. Device Address Selection HIGH SPEED MODE ADDR Pin Connection A1 A0 V 0 0 DD The AD5627RBRMZ and the AD5667RBRMZ offer high speed No Connection 1 0 serial communication with a clock frequency of 3.4 MHz. See GND 1 1 the Ordering Guide for details. The 2-wire serial bus protocol operates as follows: High speed mode communication commences after the master addresses all devices connected to the bus with the Master Code 1. The master initiates data transfer by establishing a start 00001XXX to indicate that a high speed mode transfer is to condition when a high-to-low transition on the SDA line begin (see Figure 56). No device connected to the bus is occurs while SCL is high. The following byte is the address permitted to acknowledge the high speed master code. byte, which consists of the 7-bit slave address. The slave Therefore, the code is followed by a no acknowledge. The address corresponding to the transmitted address responds master must then issue a repeated start followed by the device th by pulling SDA low during the 9 clock pulse (this is address. The selected device then acknowledges its address. termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is data to be written to, or read from, its shift register. issued, the devices return to standard/fast mode. The part also 2. Data is transmitted over the serial bus in sequences of nine returns to standard/fast mode when CLR is activated while the clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the part is in high speed mode. low period of SCL and remain stable during the high period of SCL. 3. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls th the SDA line high during the 10 clock pulse to establish a stop condition. In read mode, the master issues a no th acknowledge for the 9 clock pulse (that is, the SDA line remains high). The master then brings the SDA line low th th before the 10 clock pulse, and then high during the 10 clock pulse to establish a stop condition. Rev. 0 | Page 21 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 19 1 9 SCL 0 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 SDA START BY ACK. BY ACK. BY MASTER AD56x7 AD56x7 FRAME 1 FRAME 2 SLAVE ADDRESS COMMAND BYTE 19 1 9 SCL (CONTINUED) SDA DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB8 (CONTINUED) ACK. BY ACK. BY STOP BY AD56x7 AD56x7 MASTER FRAME 3 FRAME 4 MOST SIGNIFICANT LEAST SIGNIFICANT DATA BYTE DATA BYTE 2 Figure 54. I C Write Operation 19 1 9 SCL 0 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 SDA START BY ACK. BY ACK. BY MASTER AD56x7 MASTER FRAME 1 FRAME 2 SLAVE ADDRESS COMMAND BYTE 19 1 9 SCL (CONTINUED) SDA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 (CONTINUED) ACK. BY NO ACK. STOP BY MASTER MASTER FRAME 3 FRAME 4 MOST SIGNIFICANT LEAST SIGNIFICANT DATA BYTE DATA BYTE 2 Figure 55. I C Read Operation FAST MODE HIGH-SPEED MODE 1919 SCL SDA 0 0 0 0 1 X X X 0 0 0 1 1 A1 A0 R/W NO ACK SR START BY ACK. BY MASTER AD56x7 HS-MODE SERIAL BUS MASTER CODE ADDRESS BYTE Figure 56. Placing the AD5627RBRMZ-2/AD5667RBRMZ-2 in High Speed Mode Rev. 0 | Page 22 of 32 06342-105 06342-104 06342-103 AD5627R/AD5647R/AD5667R, AD5627/AD5667 INPUT SHIFT REGISTER Table 9. DAC Address Command The input shift register is 24 bits wide. Data is loaded into the A2 A1 A0 ADDRESS (n) device as a 24-bit word under the control of a serial clock input, 0 0 0 DAC A SCL. The timing diagram for this operation is shown in Figure 3. 0 0 1 DAC B The 8 MSBs make up the command byte. DB23 is reserved and 1 1 1 Both DACs should always be set to 0 when writing to the device. DB22 (S) LDAC FUNCTION is used to select multiple byte operation The next three bits are the command bits (C2, C1, C0) that control the mode of operation The AD56x7R/AD56x7 DACs have double-buffered interfaces of the device. See Table 8 for details. The last 3 bits of first byte consisting of two banks of registers, input registers and DAC are the address bits (A2, A1, A0). See Table 9 for details. The registers. The input registers are connected directly to the input rest of the bits are the 16-, 14-, 12-bit data word. The data word shift register, and the digital code is transferred to the relevant comprises the 16-, 14-, 12-bit input code followed by two or four input register on completion of a valid write sequence. The don’t cares for the AD5647R and the AD5627R/AD5627, DAC registers contain the digital codes used by the resistor strings. respectively (see Figure 59 through Figure 61). LDAC Access to the DAC registers is controlled by the pin. MULTIPLE BYTE OPERATION LDAC When the pin is high, the DAC registers are latched and Multiple byte operation is supported on the AD56x7R/AD56x7. the input registers can change state without affecting the A 2-byte operation is useful for applications that require fast LDAC contents of the DAC registers. When is brought low, DAC updating and do not need to change the command byte. however, the DAC registers become transparent and the contents The S bit (DB22) in the command register can be set to 1 for 2- of the input registers are transferred to them. The double- byte mode of operation (see Figure 57). For standard 3-byte buffered interface is useful if the user requires simultaneous and 4-byte operation, the S bit (DB22) in the command byte updating of all DAC outputs. The user can write to one of the should be set to 0 (see Figure 58). LDAC input registers individually and then, by bringing low when writing to the other DAC input register, all outputs BROADCAST MODE update simultaneously. Broadcast addressing is supported on the AD56x7R/AD56x7. These parts each contain an extra feature whereby a DAC Broadcast addressing can be used to synchronously update or register is not updated unless its input register has been updated power down multiple AD56x7R/AD56x7 devices. Using the since the last time LDAC was brought low. Normally, when LDAC broadcast address, the AD56x7R/AD56x7 responds regardless of the states of the address pins. Broadcast is supported only in write is brought low, the DAC registers are filled with the contents of the mode. The AD56x7R/AD56x7 broadcast address is 00010000. input registers. In the case of the AD56x7R/AD56x7, the DAC register updates only if the input register has changed since the Table 8. Command Definition last time the DAC register was updated, thereby removing C2 C1 C0 Command unnecessary digital crosstalk. 0 0 0 Write to input register n The outputs of all DACs can be simultaneously updated, using 0 0 1 Update DAC register n the hardware LDAC pin. 0 1 0 Write to input register n, update all (software LDAC) 0 1 1 Write to and update DAC channel n 1 0 0 Power up/power down 1 0 1 Reset 1 1 0 LDAC register setup 1 1 1 Internal reference setup (on/off ) Rev. 0 | Page 23 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 BLOCK 1 BLOCK 2 BLOCK n S = 1 S = 1 S = 1 SLAVE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT MOST SIGNIFICANT LEAST SIGNIFICANT MOST SIGNIFICANT LEAST SIGNIFICANT STOP ADDRESS BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE Figure 57. Multiple Block Write with Initial Command Byte Only (S = 1) BLOCK 1 BLOCK 2 BLOCK n S = 0 S = 0 S = 0 SLAVE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT STOP ADDRESS BYTE DATA BYTE DATA BYTE BYTE DATA BYTE DATA BYTE BYTE DATA BYTE DATA BYTE Figure 58. Multiple Block Write with Command Byte in Each Block (S = 0) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R S C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND DAC ADDRESS DAC DATA DAC DATA COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE Figure 59. AD5667R/AD5667 Input Shift Register (16-Bit DAC) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R S C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X COMMAND DAC ADDRESS DAC DATA DAC DATA COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE Figure 60. AD5647R Input Shift Register (14-Bit DAC) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R S C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X COMMAND DAC ADDRESS DAC DATA DAC DATA COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE Figure 61. AD5627R/AD5627 Input Shift Register (12-Bit DAC) Rev. 0 | Page 24 of 32 RESERVED RESERVED RESERVED BYTE BYTE BYTE SELECTION SELECTION SELECTION 06342-106 06342-110 06342-109 06342-108 06342-107 AD5627R/AD5647R/AD5667R, AD5627/AD5667 LDAC amplifier, as shown in Table 11. Bit DB1and Bit DB0 determine Synchronous to which DAC or DACs the power-up/down command is The DAC registers are updated after new data is read in. LDAC applied. Setting one of these bits to 1 applies the power-up/down can be permanently low or pulsed. state defined by DB5 and DB4 to the corresponding DAC. If a Asynchronous LDAC bit is 0, the state of the DAC is unchanged. Figure 65 shows the contents of the input shift register for the power up/down The outputs are not updated at the same time that the input command. LDAC registers are written to. When goes low, the DAC registers are updated with the contents of the input register. When Bit DB5 and Bit DB4 are set to 0, the part works normally with its normal power consumption of 400 μA at 5 V. However, The LDAC register gives the user full flexibility and control over for the three power-down modes, the supply current falls to the hardware LDAC pin. This register allows the user to select 480 nA at 5 V. Not only does the supply current fall, but the which combination of channels to simultaneously update when output stage is also internally switched from the output of the LDAC LDAC the hardware pin is executed. Setting the bit amplifier to a resistor network of known values. This allows the register to 0 for a DAC channel means that the update of this output impedance of the part to be known while the part is in LDAC channel is controlled by the pin. If this bit is set to 1, this power-down mode. The outputs can either be connected channel synchronously updates, that is, the DAC register is internally to GND through a 1 kΩ or 100 kΩ resistor, or left updated after new data is read in, regardless of the state of the open-circuited (three-state) as shown in Figure 62. LDAC pin. It effectively sees the LDAC pin as being pulled low. See Table 10 for the LDAC register mode of operation. This Table 11. Modes of Operation for the AD56x7R/AD56x7 flexibility is useful in applications when the user wants to DB5 DB4 Operating Mode simultaneously update select channels while the rest of the 0 0 Normal operation channels are synchronously updating. Power-down modes 0 1 1 kΩ pull-down to GND LDAC Writing to the DAC using Command 110 loads the 2-bit 1 0 100 kΩ pull-down to GND register [DB1:DB0]. The default for each channel is 0, that is, 1 1 Three-state, high impedance the LDAC pin works normally. Setting the bits to 1 means the DAC register is updated, regardless of the state of the LDAC pin. See Figure 63 for contents of the input shift register during the LDAC register setup command. RESISTOR AMPLIFIER V OUT STRING DAC LDAC Table 10. Register Mode of Operation: Load DAC Register LDAC Bits POWER-DOWN RESISTOR CIRCUITRY LDAC Pin LDAC Operation (DB1 to DB0) NETWORK 0 1/0 Determined by LDAC pin. Figure 62. Output Stage During Power-Down 1 x = don’t care The DAC registers are updated after new data is read in. The bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shut down when power- POWER-DOWN MODES down mode is activated. However, the contents of the DAC Command 100 is reserved for the power-up/down function. register are unaffected when in power-down. The time to exit The power-up/down modes are programmed by setting Bit power-down is typically 4 μs for VDD = 5 V. DB5 and Bit DB4. This defines the output state of the DAC R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 X 1 1 0 A2 A1 A0 X X X X X X X X X X X X X X DACB DACA DAC ADDRESS COMMAND DON’T CARE DON’T CARE (DON’T CARE) DAC SELECT (0 = LDAC PIN ENABLED) Figure 63. LDAC Setup Command Rev. 0 | Page 25 of 32 RESERVED DON’T CARE 06342-038 06342-111 AD5627R/AD5647R/AD5667R, AD5627/AD5667 POWER-ON RESET AND SOFTWARE RESET CLEAR PIN (CLR) The AD56x7R/AD56x7 contain a power-on reset circuit that The AD56x7R/AD56x7 has an asynchronous clear input. The controls the output voltage during power-up. The device powers CLR input is falling-edge sensitive. While CLR is low, all LDAC up to 0 V and the output remains powered up at this level until CLR pulses are ignored. When is activated, zero scale is loaded a valid write sequence is made to the DAC. This is useful in to all input and DAC registers. This clears the output to 0 V. The applications where it is important to know the state of the th part exits clear code mode on the on the falling edge of the 9 output of the DAC while it is in the process of powering up. Any CLR clock pulse of the last byte of valid write. If is activated events on LDAC or CLR during power-on reset are ignored. during a write sequence, the write is aborted. If CLR is activated There is also a software reset function. Command 101 is the during high speed mode, the part exits high speed mode to software reset command. The software reset command contains standard/fast mode. two reset modes that are software programmable by setting Bit INTERNAL REFERENCE SETUP (R VERSIONS) DB0 in the input shift register. The on-chip reference is off at power-up by default. It can be Table 12 shows how the state of the bit corresponds to the turned on by sending the reference setup command (111) and software reset modes of operation of the devices. Figure 64 setting DB0 in the input shift register. Table 13 shows how the shows the contents of the input shift register during the state of the bit corresponds to the mode of operation. See Figure 66 software reset mode of operation. for the contents of the input shift register during the internal reference setup command. Table 12. Software Reset Modes for the AD56x7R/AD56x7 DB0 Registers reset to zero Table 13. Reference Setup Command 0 DAC register DB0 Action Input shift register 0 Internal reference off (default) 1 (Power-On Reset) DAC register 1 Internal reference on Input shift register LDAC register Power-down register Internal reference setup register X S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 X 1 0 1 X X X X X X X X X X X X X X X X X X RST DAC ADDRESS COMMAND DON’T CARE DON’T CARE (DON’T CARE) Figure 64. Software Reset Command R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 X 1 0 0 X X X X X X X X X X X X X PD1 PD0 X X DACB DACA DAC ADDRESS POWER- COMMAND DON’T CARE DON’T CARE DON’T CARE (DON’T CARE) DOWN MODE DAC SELECT (1 = DAC SELECTED) Figure 65. Power Up/Down Command R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 X 1 1 1 X X X X X X X X X X X X X X X X X X REF DAC ADDRESS COMMAND DON’T CARE DON’T CARE (DON’T CARE) Figure 66. Reference Setup Command Rev. 0 | Page 26 of 32 RESERVED RESERVED RESERVED DON’T DON’T DON’T CARE CARE CARE REFERENCE RESET MODE MODE 06342-114 06342-113 06342-112 AD5627R/AD5647R/AD5667R, AD5627/AD5667 APPLICATION INFORMATION R2 = 10kΩ USING A REFERENCE AS A POWER SUPPLY FOR +5V THE AD56x7R/AD56x7 R1 = 10kΩ Because the supply current required by the AD56x7R/AD56x7 is V O AD820/ ±5V OP295 extremely low, an alternative option is to use a voltage reference +5V V V DD OUT to supply the required voltage to the part (see Figure 67). This is 10µF 0.1µF AD5627R/ –5V especially useful if the power supply is quite noisy, or if the AD5647R/ AD5667R/ system supply voltages are at some value other than 5 V or 3 V, AD5627/ for example, 15 V. The voltage reference outputs a steady supply AD5667 voltage for the AD56x7R/AD56x7. If the low dropout REF195 is GND SCL SDA used, it must supply 450 μA of current to the AD56x7R/AD56x7 with no load on the output of the DAC. When the DAC output is 2-WIRE loaded, the REF195 also needs to supply the current to the load. SERIAL INTERFACE The total current required (with a 5 kΩ load on the DAC Figure 68. Bipolar Operation with the AD56x7R/AD56x7 output) is POWER SUPPLY BYPASSING AND GROUNDING 450 μA + (5 V/5 kΩ) = 1.45 mA When accuracy is important in a circuit, it is helpful to carefully The load regulation of the REF195 is typically 2 ppm/mA, consider the power supply and ground return layout on the resulting in a 2.9 ppm (14.5 μV) error for the 1.45 mA current board. The printed circuit board containing the AD56x7R/AD56x7 drawn from it. This corresponds to a 0.191 LSB error. should have separate analog and digital sections, each having its 15V own area of the board. If the AD56x7R/AD56x7 are in a system 5V REF195 where other devices require an AGND to DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD56x7R/AD56x7. V DD SCL AD5627R/ V = 0V TO 5V 2-WIRE OUT The power supply to the AD56x7R/AD56x7 should be bypassed SERIAL AD5647R/ INTERFACE AD5667R/ SDA with 10 μF and 0.1 μF capacitors. The capacitors should be AD5627/ located as close as possible to the device, with the 0.1 μF capacitor AD5667 GND ideally right up against the device. The 10 μF capacitor should be the tantalum bead type. It is important that the 0.1 μF capacitor have low effective series resistance (ESR) and effective series Figure 67. REF195 as Power Supply to the AD56x7R/AD56x7 inductance (ESI), for example, common ceramic types of BIPOLAR OPERATION USING THE capacitors. This 0.1 μF capacitor provides a low impedance path AD56x7R/AD56x7 to ground for high frequencies caused by transient currents due to internal logic switching. The AD56x7R/AD56x7 has been designed for single-supply operation, but a bipolar output range is also possible using the The power supply line itself should have as large a trace as circuit in Figure 68. The circuit gives an output voltage range of possible to provide a low impedance path and to reduce glitch ±5 V. Rail-to-rail operation at the amplifier output is achieved effects on the supply line. Clocks and other fast switching using an AD820 or an OP295 as the output amplifier. digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals The output voltage for any input code can be calculated as if possible. When traces cross on opposite sides of the board, follows: ensure that they run at right angles to each other to reduce ⎡ D R1+ R2 R2 ⎤ ⎛ ⎞ ⎛ ⎞ ⎛ ⎞ feedthrough effects through the board. The best board layout V = V × × V ⎜ ⎟ − × ⎜ ⎟ ⎜ ⎟ O ⎢ DD DD ⎥ 65,536 ⎝ R1 ⎠ ⎝ R1⎠ ⎝ ⎠ ⎣ ⎦ technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the where D represents the input code in decimal (0 to 65535). signal traces are placed on the solder side. However, this is not With V = 5 V, R1 = R2 = 10 kΩ, DD always possible with a two-layer board. ⎛ 10× D⎞ V =⎜ ⎟− 5 V O 65,536 ⎝ ⎠ This is an output voltage range of ±5 V, with 0x0000 corre- sponding to a −5 V output, and 0xFFFF corresponding to a +5 V output. Rev. 0 | Page 27 of 32 06342-043 06342-044 AD5627R/AD5647R/AD5667R, AD5627/AD5667 OUTLINE DIMENSIONS INDEX AREA 3.00 PIN 1 INDICATOR BSC SQ 10 1 1.50 BCS SQ 0.50 2.48 EXPOSED BSC 2.38 PAD TOP VIEW (BOTTOM VIEW) 2.23 6 5 0.50 1.74 0.40 1.64 0.80 MAX 0.30 0.80 1.49 0.55 TYP 0.75 0.05 MAX SIDE VIEW 0.70 0.02 NOM SEATING 0.30 0.20 REF PLANE 0.23 0.18 Figure 69. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.33 0.60 SEATING 0.23 0° 0.05 0.17 PLANE 0.40 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 70. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev. 0 | Page 28 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 ORDERING GUIDE 2 Temperature On-Chip Max I C Package Package Model Range Accuracy Reference Speed Description Option Branding 1 AD5627BCPZ-R2 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10 -9 DA1 1 AD5627BCPZ-REEL7 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 DA1 1 AD5627BRMZ −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead MSOP RM-10 DA1 1 AD5627BRMZ-REEL7 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead MSOP RM-10 DA1 1 AD5627RBCPZ-R2 −40°C to +105°C ±1 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D9J 1 AD5627RBCPZ-REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D9J 1 AD5627RBRMZ-1 −40°C to +105°C ±1 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA7 1 AD5627RBRMZ-1REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA7 1 AD5627RBRMZ-2 −40°C to +105°C ±1 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA8 1 AD5627RBRMZ-2REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA8 1 AD5647RBCPZ-R2 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD RU-14 D9G 1 AD5647RBCPZ-REEL7 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD RU-14 D9G 1 AD5647RBRMZ −40°C to +105°C ±4 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 D9G 1 AD5647RBRMZ-REEL7 −40°C to +105°C ±4 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 D9G 1 AD5667BCPZ-R2 −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 D9Z 1 AD5667BCPZ-REEL7 −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 D9Z 1 AD5667BRMZ −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead MSOP RM-10 D9Z 1 AD5667BRMZ-REEL7 −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead MSOP RM-10 D9Z 1 AD5667RBCPZ-R2 −40°C to +105°C ±12 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D8X 1 AD5667RBCPZ-REEL7 −40°C to +105°C ±12 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D8X 1 AD5667RBRMZ-1 −40°C to +105°C ±12 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA5 1 AD5667RBRMZ-1REEL7 −40°C to +105°C ±12 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA5 1 AD5667RBRMZ-2 −40°C to +105°C ±12 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA6 1 AD5667RBRMZ-2REEL7 −40°C to +105°C ±12 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA6 1 EVAL-AD5667REBZ Evaluation Board 1 Z = Pb-free part. Rev. 0 | Page 29 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 NOTES Rev. 0 | Page 30 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 NOTES Rev. 0 | Page 31 of 32 AD5627R/AD5647R/AD5667R, AD5627/AD5667 NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06342-0-1/07(0) Rev. 0 | Page 32 of 32