ANALOG DEVICES AD5590

16 Input, 16 Output Analog I/O Port with Integrated Amplifiers AD5590 FEATURES Low input bias current: 1 pA maximum Single supply operation Input channels Low noise: 22 nV/√Hz 12-bit successive approximation ADC Unity gain stable 16 inputs with sequencer Flexible serial interface Fast throughput rate: 1 MSPS SPI-/QSPI-/MICROWIRE-/DSP-compatible Wide input bandwidth: 70 dB SNR at f = 50 kHz IN −40°C to +85°C operation Output channels Available in 80-ball CSP_BGA package 16 outputs with 12-bit DACs On-chip 2.5 V reference APPLICATIONS Hardware LDAC and LDAC override function Optical line cards CLR function to programmable code Base stations Rail-to-rail operation General-purpose analog I/O Operational amplifiers Monitoring and control Offset voltage: 2.2 mV maximum FUNCTIONAL BLOCK DIAGRAM ADCV DACV (×2) V1+ V2+ V1– V2– V /V REFIN1 REFOUT1 DD DD POWER-ON POWER-DOWN RESET LOGIC LDAC 2.5V REF BUFFER INPUT DAC STRING VOUT0 DSCLK REGISTER REGISTER DAC 0 DSYNC1 BUFFER DSYNC2 INPUT DAC STRING VOUT7 REGISTER REGISTER DAC 7 DDIN DAC LDAC INTERFACE LOGIC BUFFER CLR INPUT DAC STRING VOUT8 REGISTER REGISTER DAC 8 BUFFER DAC INPUT STRING VOUT15 REGISTER REGISTER DAC 15 POWER-DOWN LOGIC V 2.5V REF V /V DRIVE REFIN2 REFOUT2 VIN0 ASCLK SEQUENCER ADC ASYNC INTERFACE 12-BIT LOGIC INPUT SUCCESSIVE ADIN T/H MUX APPROXIMATION ADOUT ADC VIN15 AD5590 V REFA IN0(–) IN7(–) IN7(+) OUT7 IN0(+) OUT0 DACGND (×2) ADCGND Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved. 07691-001 AD5590 TABLE OF CONTENTS Features .............................................................................................. 1 DAC .............................................................................................. 14 Applications ....................................................................................... 1 ADC ............................................................................................. 18 Functional Block Diagram .............................................................. 1 Amplifier ..................................................................................... 19 Revision History ............................................................................... 2 Terminology .................................................................................... 23 General Description ......................................................................... 3 Theory of Operation ...................................................................... 26 Specifications ..................................................................................... 4 DAC Section................................................................................ 26 ADC Specifications ...................................................................... 4 ADC Section ............................................................................... 27 DAC Specifications....................................................................... 6 ADC Converter Operation ....................................................... 27 Operational Amplifier Specifications ........................................ 8 Amplifier Section ....................................................................... 29 Timing Specifications .................................................................. 9 Serial Interface ................................................................................ 30 Absolute Maximum Ratings .......................................................... 11 Accessing the DAC Block .......................................................... 30 Thermal Resistance .................................................................... 11 Accessing the ADC Block ......................................................... 34 ESD Caution ................................................................................ 11 Outline Dimensions ....................................................................... 42 Pin Configuration and Function Descriptions ........................... 12 Ordering Guide .......................................................................... 42 Typical Performance Characteristics ........................................... 14 REVISION HISTORY 7/11—Rev. 0 to Rev. A Changes to Features Section and Figure 1..................................... 1 Changes to VOUT10 Pin Number in Table 10 ........................... 13 10/08—Revision 0: Initial Version Rev. A | Page 2 of 44 AD5590 GENERAL DESCRIPTION The AD5590 is a 16-channel input and 16-channel output The DAC section of the AD5590 comprises sixteen 12-bit DACs analog I/O port with eight uncommitted amplifiers, operating divided into two groups of eight. Each group has an on-chip from a single 4.5 V to 5.25 V supply. The AD5590 comprises reference. The on-board references are off at power-up, allowing 16 input channels multiplexed into a 1 MSPS, 12-bit successive the use of external references. The internal references are enabled approximation ADC with a sequencer to allow a preprogrammed via a software write. selection of channels to be converted sequentially. The ADC The AD5590 incorporates a power-on reset circuit that ensures contains a low noise, wide bandwidth track-and-hold amplifier that the DAC outputs power up to 0 V and remain powered up that can handle input frequencies in excess of 1 MHz. at this level until a valid write takes place. The DAC contains a The conversion process and data acquisition are controlled using power-down feature that reduces the current consumption of ASYNC and the serial clock signal, allowing the device to easily the device and provides software-selectable output loads while in power-down mode for any or all DAC channels. The outputs interface with microprocessors or DSPs. The input signal is LDAC ASYNC of all DACs can be updated simultaneously using the sampled on the falling edge of and conversion is also function, with the added functionality of user-selectable DAC initiated at this point. There are no pipeline delays associated channels to simultaneously update. There is also an asynchronous with the ADC. By setting the relevant bits in the control register, the analog input range for the ADC can be selected to be a 0 V CLR that updates all DACs to a user-programmable code: zero to VREFA input or a 0 V to 2 × VREFA with either straight binary scale, midscale, or full scale. or twos complement output coding. The conversion time is The AD5590 contains eight low noise, single-supply amplifiers. determined by the ASCLK frequency because it is also used These amplifiers can be used for signal conditioning for the as the master clock to control the conversion. ADCs, DACs, or other independent circuitry, if required. Rev. A | Page 3 of 44 AD5590 SPECIFICATIONS ADC SPECIFICATIONS 1 ADCV = V = 2.7 V to 5.25 V = 2.5 V, f = 20 MHz, T = T to T , unless otherwise noted. DD DRIVE REFA SCLK A MIN MAX Table 1. 2 Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz 3 Signal-to-(Noise + Distortion) (SINAD) 68.5 70 dB @ 5 V 70.5 dB @ 3 V 3 Signal-to-Noise Ratio (SNR) 69 70 dB @ 5 V 70.5 dB @ 3 V 3 Total Harmonic Distortion (THD) −74 −82 dB @ 5 V −82 dB @ 3 V 3 Peak Harmonic or Spurious Noise (SFDR) −75 −86 dB @ 5 V −80 dB @ 3 V 3, 4 Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −85 dB Third-Order Terms −85 dB 4 Aperture Delay 10 ns 4 Aperture Jitter 50 ps 3, 4 Channel-to-Channel Isolation −82 dB f = 400 kHz IN 4 Full Power Bandwidth 8.2 MHz @ 3 dB 1.6 MHz @ 0.1 dB 3 DC ACCURACY Resolution 12 Bits Integral Nonlinearity −1 +1 LSB Differential Nonlinearity −1 +1.5 LSB Guaranteed no missing codes to 12 bits 0 V to V Input Range Straight binary output coding REFA Offset Error −10 ±0.6 +10 LSB Offset Error Match 3.5 LSB Gain Error −2 +2 LSB Gain Error Match −0.8 +0.8 LSB 0 V to 2 × V Input Range −V to +V biased about V with REFA REFA REFA REFA twos complement output coding offset Positive Gain Error −2 +2 LSB Positive Gain Error Match −0.8 +0.8 LSB Zero-Code Error −8 ±0.6 +8 LSB Zero-Code Error Match 2 LSB Negative Gain Error −1 +1 LSB Negative Gain Error Match −0.8 +0.8 LSB ANALOG INPUT Input Voltage Ranges 0 to V V Range bit set to 1 REFA 0 to 2 × V V Range bit set to 0, ADCV /V = 4.75 V REFA DD DRIVE to 5.25 V for 0 V to 2 × VREFAS DC Leakage Current −1 +1 µA 4 Input Capacitance 20 pF REFERENCE INPUT VREFA Input Voltage 2.5 V ±1% specified performance DC Leakage Current −1 +1 µA 4 V Input Impedance 36 kΩ f = 1 MSPS REFA SAMPLE Rev. A | Page 4 of 44 AD5590 2 Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V Input Low Voltage, VINL 0.3 × VDRIVE V Input Current, I −1 +1 µA Typically 10 nA IN 1, 4 Input Capacitance, C 10 pF IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V I = 200 µA; V = 2.7 V to 5.25 V OH DRIVE SOURCE DD Output Low Voltage, V 0.4 V I = 200 µA OL SINK Floating State Leakage Current ±10 µA weak/TRI bit set to 0 4 Floating State Output Capacitance 10 pF weak/TRI bit set to 0 Output Coding Straight (Natural) Binary coding bit set to 1 Twos Complement coding bit set to 0 4 CONVERSION RATE Conversion Time 800 ns 16 ASCLK cycles, ASCLK = 20 MHz 3 Track-and-Hold Acquisition Time 300 ns Sine wave input 300 ns Full-scale step input Throughput Rate 1 MSPS @ 5 V (see the Serial Interface section) POWER REQUIREMENTS ADCV 2.7 5.25 V DD V 2.7 5.25 V DRIVE IDRIVE 0.15 µA 5 IDD Digital inputs = 0 V or VDRIVE Normal Mode, Static 750 µA V = 4.75 V to 5.25 V, ASCLK on or off DD Normal Mode, Operational 2.5 mA V = 4.75 V to 5.25 V, f = 20 MHz DD SCLK (fS = Maximum Throughput) Autostandby Mode 1.55 mA fSAMPLE = 500 kSPS 100 µA Static Autoshutdown Mode 960 µA fSAMPLE = 250 kSPS 0.5 µA Static Full Shutdown Mode 0.02 0.5 µA ASCLK on or off Power Dissipation Normal Mode, Operational 12.5 mW ADCVDD = 5 V, fSCLK = 20 MHz Autostandby Mode, Static 500 µW ADCVDD = 5 V Autoshutdown Mode, Static 2.5 µW ADCV = 5 V DD Full Shutdown Mode 2.5 µW ADCV = 5 V DD 1 Specifications apply for fSCLK up to 20 MHz. For serial interfacing requirements, see the Timing Specifications section. 2 Temperature range: −40°C to +85°C. 3 See the Terminology section. 4 Guaranteed by design and characterization. Not production tested. 5 See the ADC Power vs. Throughput Rate section. Rev. A | Page 5 of 44 AD5590 DAC SPECIFICATIONS DACVDD = 4.5 V to 5.25 V, RL = 2 kΩ to DACGND, CL = 200 pF to DACGND, VREFIN1 = VREFIN1 = DACVDD. All specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE Resolution 12 Bits Integrated Nonlinearity (INL) −3 ±0.5 +3 LSB See Figure 6 Differential Nonlinearity (DNL) −0.25 +0.25 LSB Guaranteed monotonic by design; see Figure 7 Zero-Code Error 1 12 mV All 0s loaded to DAC register; see Figure 11 3 Zero-Code Error Drift ±2 µV/°C Full-Scale Error −1 −0.2 % FSR All 1s loaded to DAC register Gain Error −1 +1 % FSR 3 Gain Temperature Coefficient ±2.5 ppm Of FSR/°C Offset Error −11 ±5 +11 mV 3 DC Power Supply Rejection Ratio –80 dB DACV ± 10% DD 3 DC Crosstalk External Reference 10 µV Due to full-scale output change, RL = 2 kΩ to DACGND or DACVDD 5 µV/mA Due to load current change 10 µV Due to powering down (per channel) Internal Reference 25 µV Due to full-scale output change, RL = 2 kΩ to DACGND or DACVDD 10 µV/mA Due to load current change 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 DACVDD V Capacitive Load Stability 2 nF RL = ∞ 10 nF R = 2 kΩ L DC Output Impedance 0.5 Ω Short-Circuit Current 30 mA DACV = 5 V DD Power-Up Time 4 µs Coming out of power-down mode, DACVDD = 5 V REFERENCE INPUTS Reference Current 40 50 µA VREFINx = DACVDD = 5.5 V (per DAC channel) Reference Input Range 0 DACVDD V 3 Reference Input Impedance 14.6 kΩ REFERENCE OUTPUT Output Voltage 2.495 2.505 V At ambient 3 Reference Temperature Coefficient ±10 ppm/°C 3 Reference Output Impedance 7.5 kΩ LOGIC INPUTS Input Current −3 +3 µA All digital inputs Input Low Voltage, V 0.8 V DACV = 5 V INL DD Input High Voltage, V 2 V DACV = 5 V INH DD 3 Pin Capacitance 5 pF Rev. A | Page 6 of 44 AD5590 1 Parameter Min Typ Max Unit Conditions/Comments POWER REQUIREMENTS DACVDD 4.5 5.5 V All digital inputs at 0 or DACVDD, DAC active, excludes load current 4 I (Normal Mode) V = DACV = 4.5 V to 5.5 V, V = DACGND DD IH DD IL 2.6 3.2 mA Internal reference off 4 5 mA Internal reference on 5 DACIDD (All Power-Down Modes) DACVDD 0.8 2 µA VIH = DACVDD = 4.5 V to 5.5 V, VIL = DACGND 1 Temperature range is −40°C to +85°C, typical at 25°C. 2 Linearity calculated using a reduced code range of Code 32 to Code 4064. Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All sixteen DACs powered down. DAC AC Characteristics DACVDD = 4.5 V to 5.25 V, RL = 2 kΩ to DACGND, CL = 200 pF to DACGND, VREFIN1 = VREFIN1 = DACVDD. All specifications TMIN to TMAX, unless otherwise noted. Table 3. 1, 2 3 Parameter Min Typ Max Unit Conditions/Comments Output Voltage Settling Time 6 10 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 1.5 V/µs Digital-to-Analog Glitch Impulse 4 nV-sec 1 LSB change around major carry (see Figure 17) Digital Feedthrough 0.1 nV-sec Reference Feedthrough −90 dB V = V = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz REFIN1 REFIN2 Digital Crosstalk 0.5 nV-sec Analog Crosstalk 2.5 nV-sec DAC-to-DAC Crosstalk 3 nV-sec Multiplying Bandwidth 340 kHz V = V = 2 V ± 0.2 V p-p REFIN1 REFIN2 Total Harmonic Distortion −80 dB V = V = 2 V ± 0.1 V p-p, frequency = 10 kHz REFIN1 REFIN2 Output Noise Spectral Density 120 nV/√Hz DAC Code = 0x8400, 1 kHz 100 nV/√Hz DAC Code = 0x8400, 10 kHz Output Noise 15 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +85°C, typical at 25°C. Rev. A | Page 7 of 44 AD5590 OPERATIONAL AMPLIFIER SPECIFICATIONS Electrical characteristics @ VSY = 5 V, VCM = VSY/2, TA = 25°C, unless otherwise noted. Table 4. Parameter Symbol Min Typ Max Unit Conditions INPUT CHARACTERISTICS Offset Voltage VOS 0.4 2.2 mV −0.3 V < VCM < +5.3 V 2.2 mV −40°C < TA < +85°C, −0.3 V < VCM < +5.2 V 1 Offset Voltage Drift ∆V /∆T 1 4.5 µV/°C −40°C < T < +85°C OS A 1 Input Bias Current I 0.2 1 pA B 110 pA −40°C < T < +85°C A 1 Input Offset Current IOS 0.1 0.5 pA 50 pA −40°C < TA < +85°C Common-Mode Rejection Ratio CMRR 95 dB 0 V < VCM < 5 V 68 dB −40°C < T < +85°C A Large Signal Voltage Gain A 235 400 V/mV R = 10 kΩ, 0.5 V < V < 4.5 V VO L OUT 1 Input Capacitance CDIFF 2 pF CCM 7 pF OUTPUT CHARACTERISTICS Output Voltage High V 4.95 4.98 V I = 1 mA OH L 4.9 V −40°C to +85°C 4.7 V IL = 10 mA 4.50 V −40°C to +85°C Output Voltage Low V 20 30 mV I = 1 mA OL L 50 mV −40°C to +85°C 190 275 mV IL = 10 mA 335 mV −40°C to +85°C 1 Short-Circuit Current ISC ±80 mA 1 Closed-Loop Output Impedance Z 15 Ω f = 10 kHz, A = 1 OUT V POWER SUPPLY Power Supply Span (V+ to V−) 5 V Power Supply Rejection Ratio PSRR 67 94 dB 1.8 V < V < 5 V SY 64 dB −40°C < T < +85°C A Supply Current per Amplifier I 38 µA V = V /2 SY OUT SY 50 60 µA −40°C