ANALOG DEVICES AD5422

Single Channel, 12-/16-Bit, Serial Input, Current Source and Voltage Output DACs, HART Connectivity Data Sheet AD5412/AD5422 FEATURES GENERAL DESCRIPTION 12-/16-bit resolution and monotonicity The AD5412/AD5422 are low-cost, precision, fully integrated Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, 12-/16-bit digital-to-analog converters (DAC) offering a pro- 0 mA to 24 mA grammable current source and programmable voltage output ±0.01 % FSR typical total unadjusted error (TUE) designed to meet the requirements of industrial process control ±3 ppm/°C output drift applications. Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V The output current range is programmable at 4 mA to 20 mA, 10% overrange 0 mA to 20 mA, or an overrange function of 0 mA to 24 mA. ±0.01 % FSR typical total unadjusted error (TUE) The LFCSP version of this product has a CAP2 pin so that the ±2 ppm/°C output drift HART signals can be coupled onto the current output of the Flexible serial digital interface AD5412/AD5422. On-chip output fault detection On-chip reference: 10 ppm/°C maximum Voltage output is provided from a separate pin that can be Optional regulated DV output CC configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V Asynchronous clear function output ranges; an overrange of 10% is available on all ranges. Power supply range Analog outputs are short and open-circuit protected and can AV : 10.8 V to 40 V DD drive capacitive loads of 1 µF. AV : −26.4 V to −3 V/0 V SS The device operates with an AV power supply range from DD Output loop compliance: AV – 2.5 V DD 10.8 V to 40 V. Output loop compliance is 0 V to AVDD − 2.5 V. Temperature range: −40°C to +85°C TSSOP and LFCSP packages The flexible serial interface is SPI- and MICROWIRE™- compatible and can be operated in 3-wire mode to minimize APPLICATIONS the digital isolation required in isolated applications. Process control The device also includes a power-on-reset function, ensuring Actuator control that the device powers up in a known state. The part also PLC includes an asynchronous clear pin (CLEAR) that sets the HART network connectivity (LFCSP package only) outputs to zero-scale/midscale voltage output or the low end of the selected current range. The total output error is typically ±0.01% in current mode and ±0.01% in voltage mode. Table 1. Pin-Compatible Devices Part Number Description AD5410 Single channel, 12-bit, serial input current source DAC AD5420 Single channel, 16-bit, serial input current source DAC COMPANION PRODUCTS HART Modem: AD5700, AD5700-1 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009-2012 Analog Devices, Inc. All rights reserved. AD5412/AD5422 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Fault Alert .................................................................................... 32 Applications ....................................................................................... 1 Voltage Output Short Circuit Protection ................................ 32 General Description ......................................................................... 1 Voltage Output Overrange ........................................................ 32 Companion Products ....................................................................... 1 Voltage Output Force-Sense ..................................................... 32 Revision History ............................................................................... 3 Asynchronous Clear (CLEAR) ................................................. 32 Functional Block Diagram .............................................................. 4 Internal Reference ...................................................................... 32 Specifications ..................................................................................... 5 External Current Setting Resistor ............................................ 32 AC Performance Characteristics ................................................ 8 Digital Power Supply .................................................................. 33 Timing Characteristics ................................................................ 9 External Boost Function............................................................ 33 Absolute Maximum Ratings .......................................................... 11 External Compensation Capacitor........................................... 33 ESD Caution ................................................................................ 11 HART Communication ............................................................. 33 Pin Configurations and Function Descriptions ......................... 12 Digital Slew Rate Control .......................................................... 33 Typical Performance Characteristics ........................................... 14 I Filtering Capacitors (LFCSP Package) ............................. 34 OUT General ......................................................................................... 14 Applications Information .............................................................. 36 Voltage Output ............................................................................ 16 Voltage and Current Output Ranges on the Same Terminal 36 Current Output ........................................................................... 21 Driving Inductive Loads ............................................................ 36 Terminology .................................................................................... 25 Transient Voltage Protection .................................................... 36 Theory of Operation ...................................................................... 27 Galvanically Isolated Interface ................................................. 36 Architecture ................................................................................. 27 Microprocessor Interfacing ....................................................... 36 Serial Interface ............................................................................ 28 Layout Guidelines....................................................................... 37 Power-On State ........................................................................... 29 Thermal and Supply Considerations ....................................... 37 Data Register ............................................................................... 30 Industrial Analog Output Module ........................................... 38 Control Register .......................................................................... 30 Industrial HART Capable Analog Output Application ........ 38 Reset Register .............................................................................. 31 Outline Dimensions ....................................................................... 40 Status Register ............................................................................. 31 Ordering Guide .......................................................................... 40 AD5412/AD5422 Features ............................................................ 32 Rev. E | Page 2 of 40 Data Sheet AD5412/AD5422 REVISION HISTORY 5/12—Rev. D to Rev. E 2/10—Rev. A to Rev. B Reorganized Layout ........................................................... Universal Changes to Thermal and Supply Considerations Section and Changes to Product Title .................................................................. 1 Table 25 ............................................................................................. 36 Changes to Features Section, Applications Section, and General 8/09—Rev. 0 to Rev. A Description Section; Added Companion Products Section ............. 1 Changes to Table 2 ............................................................................ 4 Changes to Figure 1........................................................................... 3 Changes to Table 3 ............................................................................ 7 Change to Offset Error Temperature Coefficient (TC) Changes to Introduction to Table 4 ................................................ 8 Parameter, Table 1 ............................................................................. 4 Changes to Introduction to Table 5 and to Table 5 .................... 10 Changes to Table 6 .......................................................................... 12 Changes to Pin Configurations and Function Descriptions Changes to Power-On State Section ............................................. 29 Section, Added Figure 6, Renumbered Subsequent Figures ..... 11 Added HART Communication Section and Figure 68, Changes to Theory of Operation Section .................................... 26 Renumbered Sequentially .............................................................. 33 Changes to Architecture Section ................................................... 26 Added Voltage and Current Output Ranges on the Same Changes to AD5412/AD5422 Features Section .......................... 31 Terminal Section and Figure 74 .................................................... 36 Added IOUT Filtering Capacitors (LFCSP Package)Section, Added Industrial HART Capable Analog Output Application Including Figure 69 to Figure 72 and Table 24 ............................ 33 Section .............................................................................................. 38 Changes to Thermal and Supply Considerations Section ......... 36 Added Figure 79 .............................................................................. 39 Updated Outline Dimensions........................................................ 38 11/11—Rev. C to Rev. D Changes to Ordering Guide ........................................................... 39 Changes to Table 15 ........................................................................ 29 5/09—Revision 0: Initial Version 3/10—Rev. B to Rev. C Changes to AVSS to GND Parameter in Table 5 ......................... 10 Rev. E | Page 3 of 40 AD5412/AD5422 Data Sheet FUNCTIONAL BLOCK DIAGRAM DV CC SELECT DV AV AV CC *CAP1 *CAP2 SS DD CLEAR SELECT R2 R3 AD5412/AD5422 4.5V LDO BOOST CLEAR LATCH 12/16 INPUT SHIFT SCLK 12-/16-BIT REGISTER I OUT DAC AND CONTROL SDIN LOGIC SDO FAULT R SET POWER-ON R SET VREF RESET +V SENSE RANGE V OUT SCALING –V SENSE REFOUT REFIN GND C COMP *PINS ONLY ON LFCSP OPTION. Figure 1. Rev. E | Page 4 of 40 06996-001 Data Sheet AD5412/AD5422 SPECIFICATIONS AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V. VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter Min Typ Max Unit Test Conditions/Comments VOLTAGE OUTPUT Output Voltage Ranges 0 5 V 0 10 V −5 +5 V −10 +10 V Accuracy Output unloaded Resolution 16 Bits AD5422 12 Bits AD5412 Total Unadjusted Error (TUE) B Version −0.1 +0.1 % FSR −0.05 ±0.01 +0.05 % FSR T = 25°C A A Version −0.3 +0.3 % FSR −0.1 ±0.05 +0.1 % FSR TA = 25°C 2 Relative Accuracy (INL) −0.008 +0.008 % FSR AD5422 −0.032 +0.032 % FSR AD5412 Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Bipolar Zero Error −6 +6 mV Bipolar output range −1.5 ±0.2 +1.5 mV TA = 25°C, bipolar output range Bipolar Zero Error Temperature ±3 ppm FSR/°C Bipolar output range 3 Coefficient (TC) Zero-Scale Error −5 +5 mV −3.5 ±0.3 +3.5 mV T = 25°C A Zero-Scale Error Temperature ±2 ppm FSR/°C 3 Coefficient (TC) Offset Error −4 +4 mV Unipolar output range −1.5 ±0.2 +1.5 mV TA = 25°C, unipolar output range Offset Error Temperature ±2 ppm FSR/°C Unipolar output range 3 Coefficient (TC) Gain Error −0.07 +0.07 % FSR −0.05 ±0.004 +0.05 % FSR TA = 25°C Gain Error Temperature ±1 ppm FSR/°C 3 Coefficient (TC) Full-Scale Error −0.07 +0.07 % FSR −0.05 ±0.001 +0.05 % FSR T = 25°C A Full-Scale Error Temperature ±1 ppm FSR/°C 3 Coefficient (TC) 3 OUTPUT CHARACTERISTICS Headroom 0.5 0.8 V Output unloaded Output Voltage Drift vs. Time 90 ppm FSR Drift after 1000 hours, TA = 125°C Short-Circuit Current 20 mA Load 1 kΩ Capacitive Load Stability T = 25°C A R = ∞ 20 nF LOAD RLOAD = 1 kΩ 5 nF RLOAD = ∞ 1 µF External compensation capacitor of 4 nF connected DC Output Impedance 0.3 Ω Power-On Time 10 µs Rev. E | Page 5 of 40 AD5412/AD5422 Data Sheet 1 Parameter Min Typ Max Unit Test Conditions/Comments DC PSRR 90 130 µV/V 3 12 µV/V Output unloaded CURRENT OUTPUT Output Current Ranges 0 24 mA 0 20 mA 4 20 mA Accuracy (Internal R ) SET Resolution 16 Bits AD5422 12 Bits AD5412 Total Unadjusted Error (TUE) B Version −0.3 +0.3 % FSR −0.13 ±0.08 +0.13 % FSR T = 25°C A A Version −0.5 +0.5 % FSR −0.3 ±0.15 +0.3 % FSR T = 25°C A 4 Relative Accuracy (INL) −0.024 +0.024 % FSR AD5422 −0.032 +0.032 % FSR AD5412 Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.27 +0.27 % FSR −0.12 ±0.08 +0.12 % FSR T = 25°C A Offset Error Temperature ±16 ppm FSR/°C 3 Coefficient (TC) Gain Error −0.18 +0.18 % FSR AD5422 −0.03 ±0.006 +0.03 % FSR AD5422, T = 25°C A −0.22 +0.22 % FSR AD5412 −0.06 ±0.006 +0.06 % FSR AD5412, T = 25°C A 3 Gain Temperature Coefficient (TC) ±10 ppm FSR/°C Full-Scale Error −0.2 +0.2 % FSR −0.1 ±0.08 +0.1 % FSR TA = 25°C Full-Scale Temperature Coefficient ±6 ppm FSR/°C 3 (TC) Accuracy (External R ) SET Resolution 16 Bits AD5422 12 Bits AD5412 Total Unadjusted Error (TUE) B Version −0.15 +0.15 % FSR −0.06 ±0.01 +0.06 % FSR T = 25°C A A Version −0.3 +0.3 % FSR −0.1 ±0.02 +0.1 % FSR TA = 25°C 4 Relative Accuracy (INL) −0.012 +0.012 % FSR AD5422 −0.032 +0.032 % FSR AD5412 Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.1 +0.1 % FSR −0.03 ±0.006 +0.03 TA = 25°C Offset Error Temperature ±3 ppm FSR/°C 3 Coefficient (TC) Gain Error −0.08 +0.08 % FSR −0.05 ±0.003 +0.05 % FSR T = 25°C A 3 Gain Temperature Coefficient (TC) ±4 ppm FSR/°C Full-Scale Error −0.15 +0.15 % FSR −0.06 ±0.01 +0.06 % FSR TA = 25°C Full-Scale Temperature Coefficient ±7 ppm FSR/°C 3 (TC) Rev. E | Page 6 of 40 Data Sheet AD5412/AD5422 1 Parameter Min Typ Max Unit Test Conditions/Comments 3 OUTPUT CHARACTERISTICS Current Loop Compliance Voltage 0 AVDD − 2.5 V Output Current Drift vs. Time Drift after 1000 hours, TA = 125°C 50 ppm FSR Internal R SET 20 ppm FSR External R SET Resistive Load 1200 Ω Inductive Load 50 mH TA = 25 °C DC PSRR 1 µA/V Output Impedance 50 MΩ Output Current Leakage When 60 pA Output Is Disabled REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 4.95 5 5.05 V For specified performance DC Input Impedance 27 40 kΩ Reference Output Output Voltage 4.995 5 5.005 TA = 25°C Reference Temperature 1.8 10 ppm/°C 3, 5 Coefficient (TC) 3 Output Noise (0.1 Hz to 10 Hz) 10 µV p-p 3 Noise Spectral Density 100 nV/√Hz At 10 kHz 3 Output Voltage Drift vs. Time 50 ppm Drift after 1000 hours, TA = 125°C 3 Capacitive Load 600 nF 3 Load Current 5 mA 3 Short-Circuit Current 7 mA 3 Load Regulation 95 ppm/mA 3 DIGITAL INPUTS JEDEC compliant Input High Voltage, V 2 V IH Input Low Voltage, VIL 0.8 V Input Current −1 +1 µA Per pin Pin Capacitance 10 pF Per pin 3 DIGITAL OUTPUTS SDO Output Low Voltage, VOL 0.4 V Sinking 200 µA Output High Voltage, V DV − 0.5 V Sourcing 200 µA OH CC High Impedance Leakage Current −1 +1 µA High Impedance Output 5 pF Capacitance FAULT Output Low Voltage, V 0.4 V 10 kΩ pull-up resistor to DV OL CC Output Low Voltage, V 0.6 V At 2.5 mA OL Output High Voltage, V 3.6 V 10 kΩ pull-up resistor to DV OH CC POWER REQUIREMENTS AV 10.8 40 V DD AVSS −26.4 0 V |AVSS| + AVDD 10.8 52.8 V DVCC Input Voltage 2.7 5.5 V Internal supply disabled Output Voltage 4.5 V DV , which can be overdriven up to 5.5 V CC 3 Output Load Current 5 mA 3 Short-Circuit Current 20 mA Rev. E | Page 7 of 40 AD5412/AD5422 Data Sheet 1 Parameter Min Typ Max Unit Test Conditions/Comments AIDD Outputs unloaded 2.5 3 mA Outputs disabled 3.4 4 mA Current output enabled 3.9 4.4 mA Voltage output enabled AI Outputs unloaded SS 0.24 0.3 mA Outputs disabled 0.5 0.6 mA Current output enabled 1.1 1.4 mA Voltage output enabled DI 1 mA V = DV , V = GND CC IH CC IL Power Dissipation 128 mW AV = 40 V, AV = 0 V, outputs unloaded DD SS 120 mW AV = +24 V, AV = −24 V, outputs DD SS unloaded 1 Temperature range: −40°C to +85°C; typical at +25°C. 2 When the AD5412/AD5422 is powered with AVSS = 0 V, INL for the 0 V to 5 V and 0 V to 10 V ranges is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412. 3 Guaranteed by design and characterization; not production tested. 4 For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412. 5 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C. AC PERFORMANCE CHARACTERISTICS AV = 10.8 V to 26.4 V, AV = −26.4 V to −3 V/0 V, AV + |AV | < 52.8 V, GND = 0 V, REFIN = +5 V external; DV = 2.7 V to 5.5 V. DD SS DD SS CC V : R = 1 kΩ, C = 200 pF, I : R = 350 Ω; all specifications T to T , unless otherwise noted. OUT LOAD L OUT LOAD MIN MAX Table 3. 1 Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Voltage Output Output Voltage Settling Time 25 µs 10 V step to ±0.03 % FSR 32 µs 20 V step to ±0.03 % FSR 18 µs 5 V step to ±0.03 % FSR 8 µs 512 LSB step to ±0.03 % FSR (16-Bit LSB) Slew Rate 0.8 V/µs Power-On Glitch Energy 10 nV-sec Digital-to-Analog Glitch Energy 10 nV-sec Glitch Impulse Peak Amplitude 20 mV Digital Feedthrough 1 nV-sec Output Noise (0.1 Hz to 10 Hz 0.1 LSB p-p 16-bit LSB Bandwidth) Output Noise (100 kHz Bandwidth) 200 µV rms 1/f Corner Frequency 1 kHz Output Noise Spectral Density 150 nV/√Hz Measured at 10 kHz, midscale output, 10 V range AC PSRR −75 dB 200 mV 50 Hz/60 Hz sine wave superimposed on power supply voltage Current Output Output Current Settling Time 10 µs 16 mA step to 0.1% FSR 40 µs 16 mA step to 0.1% FSR, L = 1 mH AC PSRR −75 dB 200 mV 50 Hz/60 Hz sine wave superimposed on power supply voltage 1 Guaranteed by characterization, not production tested. Rev. E | Page 8 of 40 Data Sheet AD5412/AD5422 TIMING CHARACTERISTICS AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8V, GND = 0 V, REFIN = +5 V external; DVCC = 2.7 V to 5.5 V. VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 4. 1, 2, 3 Parameter Limit at TMIN, TMAX Unit Description WRITE MODE t1 33 ns min SCLK cycle time t2 13 ns min SCLK low time t 13 ns min SCLK high time 3 t 13 ns min LATCH delay time 4 t5 40 ns min LATCH high time t5 5 µs min LATCH high time (after a write to the control register) t6 5 ns min Data setup time t 5 ns min Data hold time 7 t 40 ns min LATCH low time 8 t 20 ns min CLEAR pulse width 9 t10 5 µs max CLEAR activation time READBACK MODE t 90 ns min SCLK cycle time 11 t12 40 ns min SCLK low time t13 40 ns min SCLK high time t14 13 ns min LATCH delay time t 40 ns min LATCH high time 15 t 5 ns min Data setup time 16 t17 5 ns min Data hold time t18 40 ns min LATCH low time 4 t19 35 ns max Serial output delay time (CL SDO = 15 pF) 4 t 35 ns max LATCH rising edge to SDO tristate (C = 15 pF) 20 L SDO DAISY-CHAIN MODE t21 90 ns min SCLK cycle time t 40 ns min SCLK low time 22 t 40 ns min SCLK high time 23 t 13 ns min LATCH delay time 24 t25 40 ns min LATCH high time t26 5 ns min Data setup time t27 5 ns min Data hold time t 40 ns min LATCH low time 28 4 t 35 ns max Serial output delay time (C = 15 pF) 29 L SDO 1 Guaranteed by characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 CL SDO = capacitive load on SDO output. Rev. E | Page 9 of 40 AD5412/AD5422 Data Sheet t 1 SCLK 1 2 24 t t 2 3 t t 4 5 LATCH t 7 t 8 t 6 SDIN DB23 DB0 t 9 CLEAR t 10 I /V OUT OUT Figure 2. Write Mode Timing Diagram t 11 SCLK 1 2 8 9 22 23 24 1 2 24 t t 12 13 t t 14 15 LATCH t 17 t 18 t 16 SDIN DB23 DB0 DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES t 20 t 19 REGISTER TO BE READ SDO X X X X DB15 DB0 FIRST 8 BITS ARE SELECTED REGISTER UNDEFINED DATA DON’T CARE BITS DATA CLOCKED OUT Figure 3. Readback Mode Timing Diagram t 21 SCLK 26 48 1 2 24 25 t t 22 23 t t 24 25 LATCH t t 27 28 t 26 SDIN DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N – 1 t 29 t 20 DB23 DB0 DB0 SDO DB23 UNDEFINED INPUT WORD FOR DAC N Figure 4. Daisy-Chain Mode Timing Diagram Rev. E | Page 10 of 40 06996-002 06996-004 06996-003 Data Sheet AD5412/AD5422 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to Stresses above those listed under Absolute Maximum Ratings 80 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 5. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute AV to GND −0.3 V to +48 V DD maximum rating conditions for extended periods may affect AVSS to GND +0.3 V to −28 V device reliability. AVDD to AVSS −0.3 V to +60 V DVCC to GND −0.3 V to +7 V ESD CAUTION Digital Inputs to GND −0.3 V to DV + 0.3 V or 7 V CC (whichever is less) Digital Outputs to GND −0.3 V to DV + 0.3 V or 7 V CC (whichever is less) REFIN/REFOUT to GND −0.3 V to +7 V VOUT to GND AVSS to AVDD I to GND −0.3 V to AV OUT DD Operating Temperature Range (T ) A 1 Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 125°C 24-Lead TSSOP Package θ Thermal Impedance 42°C/W JA 40-Lead LFCSP Package θJA Thermal Impedance 28°C/W Power Dissipation (TJ max – TA)/θJA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 2 kV 1 Power dissipated on chip must be derated to keep the junction temperature below 125°C, assuming that the maximum power dissipation condition is sourcing 24 mA into GND from I with a 4 mA on-chip current. OUT Rev. E | Page 11 of 40 AD5412/AD5422 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 24 AV 1 AV SS DD 2 23 DV –V CC SENSE 3 22 FAULT +V SENSE NC 1 PIN 1 30 NC 4 21 GND V AD5412/ OUT INDICATOR 2 29 CAP2 FAULT AD5422 GND 3 28 CAP1 5 20 BOOST CLEAR SELECT 27 BOOST TOP VIEW CLEAR SELECT 4 AD5412/AD5422 I CLEAR 5 26 OUT CLEAR 6 19 (Not to Scale) I OUT LATCH 6 TOP VIEW 25 NC SCLK 7 24 C (Not to Scale) COMP LATCH 7 18 NC SDIN 8 23 DV SELECT CC SDO 9 22 NC 8 SCLK 17 C COMP 21 NC NC 10 SDIN 9 16 DV SELECT CC SDO 10 15 REFIN 11 14 GND REFOUT GND 12 13 R SET NOTES NOTES 1. NC = NO CONNECT. 1. NC = NO CONNECT 2. THE EXPOSED PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT VOLTAGE RANGE IS UNIPOLAR. THE EXPOSED PADDLE CAN BE LEFT 2. THE PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT VOLTAGE RANGE ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION IS UNIPOLAR. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE AV PIN. IT IS IS MADE AT THE AV PIN. IT IS RECOMMENDED THAT THE PADDLE BE SS SS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. THERMAL PERFORMANCE. Figure 5. TSSOP Pin Configuration Figure 6. LFCSP Pin Configuration Table 6. Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description 1 14, 37 AV Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be SS connected to 0 V if the output voltage range is unipolar. 2 39 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. This pin can also be configured as a 4.5 V LDO output by leaving the DVCC SELECT pin floating. 3 2 FAULT Fault Alert. This pin is asserted low when an open circuit is detected in current mode or an overtemperature is detected. Open drain output must be connected to a pull-up resistor. 4, 12 3, 15 GND These pins must be connected to 0 V. 18 1, 10, 11, 19, 20, NC No Connection. Do not connect to these pins. 21, 22, 25, 30, 31, 35, 38, 40 5 4 CLEAR Selects the voltage output clear value, either zero-scale or midscale code (see Table 21). SELECT 6 5 CLEAR Active High Input. Asserting this pin sets the current output to the bottom of the selected range or sets the voltage output to the user selected value (zero-scale or midscale). 7 6 LATCH Positive Edge Sensitive Latch. A rising LATCH edge parallel loads the input shift register data into the DAC register, also updating the output. 8 7 SCLK Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This operates at clock speeds of up to 30 MHz. 9 8 SDIN Serial Data Input. Data must be valid on the rising edge of SCLK. 10 9 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is valid on the rising edge of SCLK (see Figure 3 and Figure 4). 11 12, 13 GND Ground Reference Pin. 13 16 R An external, precision, low drift 15 kΩ current setting resistor can be connected to this SET pin to improve the I temperature drift performance. See the AD5412/AD5422 Features OUT section. 14 17 REFOUT Internal Reference Voltage Output. REFOUT = 5 V ± 2 mV. 15 18 REFIN External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for a specified performance. Rev. E | Page 12 of 40 06996-005 06996-006 NC 11 40 NC GND 12 39 DV CC GND 13 38 NC AV 14 37 AV SS SS GND 15 36 AV DD R 16 35 NC SET 17 34 –V REFOUT SENSE REFIN 18 33 +V SENSE V NC 19 32 OUT NC 20 31 NC Data Sheet AD5412/AD5422 Pin No. TSSOP LFCSP Mnemonic Description 16 23 DV When connected to GND, this pin disables the internal supply, and an external supply CC SELECT must be connected to the DVCC pin. Leave this pin unconnected to enable the internal supply. See the AD5412/AD5422 Features section. 17 24 CCOMP Optional compensation capacitor connection for the voltage output buffer. Connecting a 4 nF capacitor between this pin and the V pin allows the voltage output to drive up OUT to 1 µF. It should be noted that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 19 26 IOUT Current Output Pin. 20 27 BOOST Optional External Transistor Connection. Connecting an external transistor reduces the power dissipated in the AD5412/AD5422. See theAD5412/AD5422 Features section. N/A 28, 29 CAP1, CAP2 Connection for Optional Output Filtering Capacitor. See the AD5412/AD5422 Features section. 21 32 VOUT Buffered Analog Output Voltage. The output amplifier is capable of directly driving a 1 kΩ, 2000 pF load. 22 33 +VSENSE Sense connection for the positive voltage output load connection. 23 34 −V Sense connection for the negative voltage output load connection. SENSE 24 36 AV Positive Analog Supply Pin. Voltage ranges from 10.8 V to 60 V. DD 25 (EPAD) 41 (EPAD) Exposed Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This paddle can be paddle connected to 0 V if the output voltage range is unipolar. The paddle can be left electrically unconnected provided that a supply connection is made at the AVSS pin. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. E | Page 13 of 40 AD5412/AD5422 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS GENERAL 900 9 T = 25°C A 800 T = 25°C 8 A 700 7 600 6 DV = 5V CC 500 5 400 4 300 3 200 2 DV = 3V CC 100 1 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –21 –19 –17 –15 –13 –11 –9 –7 –5 –3 –1 1 LOGIC VOLTAGE (V) LOAD CURRENT (mA) Figure 7. DICC vs. Logic Input Voltage Figure 10. DVCC Output Voltage vs. Load Current 5 AI DD 4 3 AV DD T = 25°C A V = 0V 2 OUT OUTPUT UNLOADED 3 1 REFERENCE OUTPUT 0 AI SS –1 1 –2 CH1 2.00V M200µs CH3 2.1V 10 12 14 16 18 20 22 24 26 28 CH3 5.00V AV /|AV | (V) DD SS Figure 8. AIDD/AISS vs. AVDD/|AVSS| Figure 11. REFOUT Turn-on Transient 5.0 T = 25°C A 4.5 I = 0mA OUT 4.0 3.5 3.0 1 2.5 2.0 1.5 1.0 0.5 0 CH1 2µV M2.00s LINE 1.8V 10 15 20 25 30 35 40 AV (V) DD Figure 9. AIDD vs. AVDD Figure 12. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth) Rev. E | Page 14 of 40 DI (µA) AI (mA) AI /AI (mA) CC DD DD SS 06996-023 06996-108 06996-022 DV OUTPUT VOLTAGE (V) CC 06996-026 06996-025 06996-024 Data Sheet AD5412/AD5422 45 AV = 24V 40 DD 35 30 25 1 20 15 10 5 0 CH1 20µV M2.00s LINE 0V 0 1 2 3 4 5 6 7 8 9 10 TEMPERATURE COEFFICIENT (ppm/°C) Figure 13. REFOUT Output Noise (100 kHz Bandwidth) Figure 15. Reference Temperature Coefficient Histogram 5.003 5.0005 50 DEVICES SHOWN T = 25°C A 5.0000 AV = 24V DD AV = 24V DD 5.002 4.9995 4.9990 5.001 4.9985 5.000 4.9980 4.9975 4.999 4.9970 4.9965 4.998 4.9960 4.997 4.9955 –40 –20 0 20 40 60 80 0 1 2 3 4 5 6 7 8 9 TEMPERATURE (°C) LOAD CURRENT (mA) Figure 14. Reference Voltage vs. Temperature Figure 16. Reference Voltage vs. Load Current Rev. E | Page 15 of 40 REFERENCE OUTPUT VOLTAGE (V) 06996-027 06996-029 REFERENCE OUTPUT VOLTAGE (V) POPULATION (%) 06996-030 06996-031 AD5412/AD5422 Data Sheet VOLTAGE OUTPUT 0.0025 1.0 AV = +24V DD +5V RANGE AV = 24V AV = –24V 0.0020 SS 0.8 DD AV = 0V T = 25°C +10V RANGE A SS T = 25°C A 0.0015 0.6 0.0010 0.4 0.0005 0.2 0 0 –0.0005 –0.2 –0.0010 –0.4 ±10V RANGE –0.0015 –0.6 ±5V RANGE +5V RANGE –0.0020 –0.8 +10V RANGE –0.0025 –1.0 0 10,000 20,000 30,000 40,000 50,000 60,000 0 10,000 20,000 30,000 40,000 50,000 60,000 CODE CODE Figure 17. Integral Nonlinearity Error vs. DAC Code, Dual Supply Figure 20. Differential Nonlinearity Error vs. DAC Code, Single Supply 0.0025 0.005 AV = +24V DD +5V RANGE AV = 24V 0.0020 DD AV = –24V SS +10V RANGE AV = 0V SS 0.003 T = 25°C A T = 25°C A 0.0015 0.0010 0.001 0.0005 –0.001 0 –0.003 –0.0005 –0.0010 –0.005 ±10V RANGE –0.0015 ±5V RANGE –0.007 –0.0020 +5V RANGE +10V RANGE –0.0025 –0.009 0 10,000 20,000 30,000 40,000 50,000 60,000 0 10,000 20,000 30,000 40,000 50,000 60,000 CODE CODE Figure 18. Integral Nonlinearity Error vs. DAC Code, Single Supply Figure 21. Total Unadjusted Error vs. DAC Code, Dual Supply 1.0 0.030 AV = +24V DD AV = –24V +5V RANGE AV = 24V 0.8 DD SS 0.025 T = 25°C +10V RANGE AV = 0V SS A T = 25°C 0.6 A 0.020 0.4 0.015 0.2 0 0.010 –0.2 0.005 –0.4 0 ±10V RANGE –0.6 ±5V RANGE +10V RANGE –0.005 –0.8 +5V RANGE –1.0 –0.010 0 10,000 20,000 30,000 40,000 50,000 60,000 0 10,000 20,000 30,000 40,000 50,000 60,000 CODE CODE Figure 19. Differential Nonlinearity Error vs. DAC Code, Dual Supply Figure 22. Total Unadjusted Error vs. DAC Code, Single Supply Rev. E | Page 16 of 40 INL ERROR (% FSR) INL ERROR (% FSR) DNL ERROR (LSB) 06996-119 06996-118 06996-117 TOTAL UNADJUSTED ERROR (% FSR) TOTAL UNADJSUTED ERROR (% FSR) DNL ERROR (LSB) 06996-120 06996-122 06996-221 Data Sheet AD5412/AD5422 0.0015 0.012 AV = +24V DD 0.010 AV = +24V DD AV = –24V SS AV = –24V SS 0.0010 0.008 OUTPUT UNLOADED 0.006 0.0005 0.004 0 0.002 0 –0.0005 –0.002 +5V RANGE –0.004 +10V RANGE –0.0010 +5V RANGE MAX INL +10V RANGE MAX INL ±5V RANGE ±5V RANGE MAX INL ±10V RANGE MAX INL –0.006 ±10V RANGE +5V RANGE MIN INL +10V RANGE MIN INL ±5V RANGE MIN INL ±10V RANGE MIN INL –0.0015 –0.008 –40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 23. Integral Nonlinearity Error vs. Temperature Figure 26. Full-Scale Error vs. Temperature 1.0 1.5 AV = +24V DD AV = +24V DD 0.8 AV = –24V SS AV = –24V SS ALL RANGES 1.0 OUTPUT UNLOADED 0.6 +10V RANGE 0.4 0.5 0.2 0 +5V RANGE 0 –0.2 –0.5 –0.4 –0.6 –1.0 –0.8 –1.0 –1.5 –40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 24. Differential Nonlinearity Error vs. Temperature Figure 27. Offset Error vs. Temperature 1.5 0.015 AV = +24V DD AV = +24V DD AV = –24V SS AV = –24V SS 0.010 1.0 OUTPUT UNLOADED OUTPUT UNLOADED +10V RANGE 0.005 0.5 0 0 +5V RANGE –0.5 –0.005 +5V RANGE +10V RANGE –1.0 –0.010 ±5V RANGE ±10V RANGE –1.5 –0.015 –40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 25. Total Unadjusted Error vs. Temperature Figure 28. Bipolar Zero Error vs. Temperature Rev. E | Page 17 of 40 INL ERROR (% FSR) TOTAL UNADJSUTED ERROR (% FSR) DNL ERROR (LSB) 06996-124 06996-101 06996-121 FULL-SCALE ERROR (% FSR) BIPOLAR ZERO ERROR (mV) OFFSET ERROR (mV) 06996-130 06996-129 06996-100 AD5412/AD5422 Data Sheet 0.014 1.0 AVDD = +24V T = 25°C A AVSS = –24V 0.012 0.8 ±10V RANGE OUTPUT UNLOADED 0.010 0.6 0.008 0.4 0.006 0.2 0.004 0 0.002 –0.2 0 –0.4 –0.002 +5V RANGE –0.6 –0.004 +10V RANGE ±5V RANGE –0.8 –0.006 ±10V RANGE –0.008 –1.0 –40 –20 0 20 40 60 80 10 12 14 16 18 20 22 24 26 28 TEMPERATURE (°C) AV /|AV | (V) DD SS Figure 32. Differential Nonlinearity Error vs. AVDD/|AVSS| Figure 29. Gain Error vs. Temperature 0.0050 1.3 AV = +24V DD 0.0045 AV = –24V SS OUTPUT UNLOADED 0.0040 0.8 0.0035 T = 25°C A ±10V RANGE 0.0030 0.3 0.0025 0.0020 –0.2 0.0015 +5V RANGE –0.7 0.0010 +10V RANGE ±5V RANGE 0.0005 ±10V RANGE –1.2 0 –40 –20 0 20 40 60 80 10 12 14 16 18 20 22 24 26 28 TEMPERATURE (°C) AV /|AV | (V) DD SS Figure 30. Zero-Scale Error vs. Temperature Figure 33. Total Unadjusted Error vs. AVDD/|AVSS| 0.0015 0.05 T = 25°C A 0.04 AV = +15V ±10V RANGE DD AV = –15V 0.0010 SS 0.03 T = 25°C A ±10V RANGE 0.02 0.0005 0.01 0 0 –0.01 –0.0005 –0.02 –0.03 –0.0010 –0.04 –0.05 –0.0015 10 12 14 16 18 20 22 24 26 28 –20 –15 –10 –5 0 5 10 15 20 AV /|AV | (V) SOURCE/SINK CURRENT (mA) DD SS Figure 31. Integral Nonlinearity Error vs. AVDD/|AVSS| Figure 34. Source and Sink Capability of Output Amplifier, Full-Scale Code Loaded Rev. E | Page 18 of 40 INL ERROR (% FSR) GAIN ERROR (% FSR) ZERO-SCALE ERROR (mV) 06996-102 06996-131 06996-231 TOTAL UNADJUSTED ERROR (% FSR) CHANGE IN OUTPUT VOLTAGE (V) DNL ERROR (LSB) 06996-132 06996-232 06996-033 Data Sheet AD5412/AD5422 0.05 12 AV = +15V DD 0.04 AV = –15V SS 8 T = 25°C 0.03 A ±10V RANGE 0.02 AV = +24V 4 DD AV = –24V SS 0.01 ±10V RANGE T = 25°C A 0 0 OUTPUT UNLOADED –0.01 –4 –0.02 –0.03 –8 –0.04 –0.05 –12 –20 –15 –10 –5 0 5 10 15 20 –10 –5 0 5 10 15 20 25 30 TIME (µs) SOURCE/SINK CURRENT (mA) Figure 35. Source and Sink Capability of Output Amplifier, Figure 37. Full-Scale Negative Step Zero-Scale Loaded 12 4 AV = +24V DD 2 AV = –24V SS 8 ±10V RANGE 0 T = 25°C A OUTPUT UNLOADED –2 4 0x8000 TO 0x7FFF –4 0x7FFF TO 0x8000 0 –6 –8 –4 –10 AV = +24V DD AV = –24V SS –12 T = 25°C –8 A ±10V RANGE –14 –12 –16 –1 1 3 5 7 9 11 13 15 –10 –5 0 5 10 15 20 25 30 TIME (µs) TIME (µs) Figure 36. Full-Scale Positive Step Figure 38. Digital-to-Analog Glitch Rev. E | Page 19 of 40 CHANGE IN OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 06996-136 06996-035 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 06996-137 06996-036 AD5412/AD5422 Data Sheet 35 AV = +15V DD AV = –15V SS 30 T = 25°C A 25 20 1 15 10 AV = +24V DD 5 AV = –24V SS T = 25°C A 0 CH1 5.0µV M 5.00ms LINE 1.8V 0 2 4 6 8 10 12 14 16 18 20 TIME (µs) Figure 39. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) Figure 41. V vs. Time on Power-Up OUT 1 AV = +24V DD AV = –24V SS T = 25°C A CH1 50.0µV M 5.00ms LINE 0V Figure 40. Peak-to-Peak Noise (100 kHz Bandwidth) Rev. E | Page 20 of 40 06996-037 06996-038 V (mV) OUT 06996-039 Data Sheet AD5412/AD5422 CURRENT OUTPUT 0.004 EXTERNAL R SET 0.004 AV = 24V DD INTERNAL R SET AV = –24V/0V SS EXTERNAL R , BOOST TRANSISTOR 0.002 SET 0mA TO 24mA RANGE 0.002 INTERNAL R , BOOST TRANSISTOR SET 0 0 –0.002 –0.002 –0.004 –0.004 –0.006 –0.006 AV = 24V DD AV = –24V/0V SS –0.008 –0.008 T = 25°C A R = 250Ω LOAD –0.010 –0.010 0 10,000 20,000 30,000 40,000 50,000 60,000 –40 –20 0 20 40 60 80 CODE TEMPERATURE (°C) Figure 42. Integral Nonlinearity vs. Code Figure 45. Integral Nonlinearity vs. Temperature, Internal RSET 1.0 0.003 AV = 24V DD AV = 24V DD AV = –24V/0V SS 0.8 AV = –24V/0V SS 0mA TO 24mA RANGE T = 25°C A 0.002 R = 250Ω 0.6 LOAD 0.4 0.001 0.2 0 0 –0.2 –0.001 –0.4 EXTERNAL R SET –0.6 INTERNAL R SET –0.002 EXTERNAL R , BOOST TRANSISTOR SET –0.8 INTERNAL R , BOOST TRANSISTOR SET –1.0 –0.003 0 10,000 20,000 30,000 40,000 50,000 60,000 –40 –20 0 20 40 60 80 CODE TEMPERATURE (°C) Figure 43. Differential Nonlinearity vs. Code Figure 46. Integral Nonlinearity vs. Temperature, External R SET 0.05 1.0 AV = 24V DD AV = –24V/0V SS 0.03 0.8 ALL RANGES INTERNAL AND EXTERNAL R SET 0.01 0.6 –0.01 0.4 –0.03 0.2 –0.05 AV = 24V 0 DD AV = –24V/0V SS –0.07 T = 25°C –0.2 A R = 250Ω LOAD –0.09 –0.4 EXTERNAL R SET –0.11 –0.6 INTERNAL R SET EXTERNAL R , BOOST TRANSISTOR –0.13 SET –0.8 INTERNAL R , BOOST TRANSISTOR SET –0.15 –1.0 0 10,000 20,000 30,000 40,000 50,000 60,000 –40 –20 0 20 40 60 80 CODE TEMPERATURE (°C) Figure 44. Total Unadjusted Error vs. Code Figure 47. Differential Nonlinearity vs. Temperature Rev. E | Page 21 of 40 TOTAL UNADJUSTED ERROR (% FSR) INL ERROR (% FSR) DNL ERROR (LSB) 06996-007 06996-008 06996-106 INL ERROR (% FSR) INL ERROR (% FSR) DNL ERROR (LSB) 06996-010 06996-009 06996-109 AD5412/AD5422 Data Sheet 0.10 0.015 AV = 24V DD T = 25°C A AV = –24V/0V SS 0mA TO 24mA RANGE 0.05 AV = 0V 0.010 SS 0 0.005 –0.05 0 –0.10 4mA TO 20mA INTERNAL R SET –0.005 0mA TO 20mA INTERNAL R –0.15 SET 0mA TO 24mA INTERNAL R SET 4mA TO 20mA EXTERNAL R SET –0.010 –0.20 0mA TO 20mA EXTERNAL R SET 0mA TO 24mA EXTERNAL R SET –0.25 –0.015 –40 –20 0 20 40 60 80 10 15 20 25 30 35 40 TEMPERATURE (°C) AV (V) DD Figure 48. Total Unadjusted Error vs. Temperature Figure 51. Integral Nonlinearity Error vs. AV , External R DD SET 0.10 0.020 AV = 24V DD 0.015 0.05 AV = –24V/0V T = 25°C SS A 0mA TO 24mA RANGE 0.010 AV = 0V SS 0 0.005 –0.05 0 –0.10 –0.005 4mA TO 20mA INTERNAL R SET 0mA TO 20mA INTERNAL R –0.15 SET –0.010 0mA TO 24mA INTERNAL R SET 4mA TO 20mA EXTERNAL R SET –0.20 0mA TO 20mA EXTERNAL R –0.015 SET 0mA TO 24mA EXTERNAL R SET –0.25 –0.020 –40 –20 0 20 40 60 80 10 15 20 25 30 35 40 TEMPERATURE (°C) AV (V) DD Figure 49. Offset Error vs. Temperature Figure 52. Integral Nonlinearity Error vs. AVDD, Internal RSET 0.06 1.0 AV = 24V DD 0.8 T = 25°C A 0.04 AV = –24V/0V SS 0mA TO 24mA RANG 0.6 AV = 0V SS 0.02 0.4 0 0.2 –0.02 0 –0.2 –0.04 4mA TO 20mA INTERNAL R SET 0mA TO 20mA INTERNAL R –0.4 SET –0.06 0mA TO 24mA INTERNAL R SET –0.6 4mA TO 20mA EXTERNAL R SET 0mA TO 20mA EXTERNAL R –0.08 SET –0.8 0mA TO 24mA EXTERNAL R SET –1.0 –0.10 –40 –20 0 20 40 60 80 10 15 20 25 30 35 40 AV (V) TEMPERATURE (°C) DD Figure 50. Gain Error vs. Temperature Figure 53. Differential Nonlinearity Error vs. AVDD, External RSET Rev. E | Page 22 of 40 OFFSET ERROR (% FSR) GAIN ERROR (% FSR) TOTAL UNADJUSTED ERROR (% FSR) 06996-018 06996-017 06996-013 INL ERROR (% FSR) INL ERROR (% FSR) DNL ERROR (LSB) 06996-012 06996-014 06996-011 Data Sheet AD5412/AD5422 1.0 2.5 AV = 15V DD AV = 0V SS 0.8 I = 24mA OUT T = 25°C A R = 500Ω LOAD 0.6 2.0 0mA TO 24mA RANGE AV = 0V SS 0.4 0.2 1.5 0 1.0 –0.2 –0.4 –0.6 0.5 –0.8 0 –1.0 10 15 20 25 30 35 40 –40 –20 0 20 40 60 80 AV (V) TEMPERATURE (°C) DD Figure 54. Differential Nonlinearity Error vs. AV , Internal R Figure 57. Compliance Voltage Headroom vs. Temperature DD SET 0.025 3.5 AV = 24V T = 25°C DD A AV = 0V 0.020 0mA TO 24mA RANGE SS 3.0 T = 25°C A AV = 0V SS R = 250Ω LOAD 0.015 2.5 0.010 2.0 0.005 1.5 0 1.0 –0.005 0.5 –0.010 –0.015 0 0 100 200 300 400 500 600 10 15 20 25 30 35 40 TIME (µs) AV (V) DD Figure 55. Total Unadjusted Error vs. AVDD, External RSET Figure 58. Output Current vs. Time on Power-Up 0.05 20 0.03 10 0.01 AV = 24V DD 0 –0.01 AV = 0V SS T = 25°C A –0.03 R = 250Ω –10 LOAD T = 25°C A –0.05 0mA TO 24mA RANGE AV = 0V SS –20 –0.07 –0.09 –30 –0.11 –40 –0.13 –0.15 –50 10 15 20 25 30 35 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TIME (µs) AV (V) DD Figure 56. Total Unadjusted Error vs. AVDD, Internal RSET Figure 59. Output Current vs. Time on Output Enable Rev. E | Page 23 of 40 TOTAL UNADJUSTED ERROR (% FSR) TOTAL UNADJUSTED ERROR (% FSR) DNL ERROR (LSB) 06996-032 06996-016 06996-015 OUTPUT CURRENT (µA) OUTPUT CURRENT (µA) HEADROOM VOLTAGE (V) 06996-019 06996-020 06996-021 AD5412/AD5422 Data Sheet 70 25 60 T = 25°C A AV = 24V 20 DD AV = 0V 50 SS R = 300Ω LOAD 40 15 30 10 20 T = 25°C A AV = 40V DD 10 AV = 0V SS 5 OUTPUT DISABLED 0 –10 0 0 5 10 15 20 25 30 35 40 45 –1 0 1 2 3 4 5 6 7 8 COMPLIANCE VOLTAGE (V) TIME (µs) Figure 60. Output Leakage Current vs. Compliance Voltage Figure 62. 4 mA to 20 mA Output Current Step 30 0x8000 TO 0x7FFF AV = 24V DD 0x7FFF TO 0x8000 AV = 0V SS 20 T = 25°C A R = 250Ω LOAD 10 0 –10 –20 –30 0 2 4 6 8 10 12 14 16 18 20 TIME (µs) Figure 61. Digital to Analog Glitch Rev. E | Page 24 of 40 OUTPUT CURRENT (µA) LEAKAGE CURRENT (pA) 06996-049 06996-028 OUTPUT CURRENT (mA) 06996-134 Data Sheet AD5412/AD5422 TERMINOLOGY Slew Rate Relative Accuracy or Integral Nonlinearity (INL) The slew rate of a device is a limitation in the rate of change For the DAC, relative accuracy, or INL, is a measure of the of the output voltage. The output slewing speed of a voltage- maximum deviation, in LSBs, from a straight line passing output DAC is usually limited by the slew rate of the amplifier through the endpoints of the DAC transfer function. A typical used at its output. Slew rate is measured from 10% to 90% of the INL vs. code plot can be seen in Figure 17. output signal and is expressed in V/µs. Differential Nonlinearity (DNL) Gain Error DNL is the difference between the measured change and the Gain error is a measure of the span error of the DAC. It is the ideal 1 LSB change between any two adjacent codes. A specified deviation in slope of the DAC transfer characteristic from the differential nonlinearity of ±1 LSB maximum ensures monoton- ideal expressed in % FSR. A plot of gain error vs. temperature icity. This DAC is guaranteed monotonic by design. A typical can be seen in Figure 29. DNL vs. code plot can be seen in Figure 19. Gain Error Temperature Coefficient (TC) Monotonicity Gain error TC is a measure of the change in gain error with A DAC is monotonic if the output either increases or remains changes in temperature. Gain error TC is expressed in ppm constant for increasing digital input code. The AD5412/AD5422 FSR/°C. are monotonic over their full operating temperature range. Total Unadjusted Error (TUE) Bipolar Zero Error TUE is a measure of the output error taking all the various Bipolar zero error is the deviation of the analog output from the errors into account, namely INL error, offset error, gain error, ideal half-scale output of 0 V when the DAC register is loaded and output drift over supplies, temperature, and time. TUE is with 0x8000 (straight binary coding) or 0x0000 (twos comple- expressed in % FSR. ment coding). A plot of bipolar zero error vs. temperature can be seen in Figure 28. Current Loop Voltage Compliance The maximum voltage at the I pin for which the output OUT Bipolar Zero Temperature Coefficient (TC) current is equal to the programmed value. Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog Full-Scale Error output when the AD5412/AD5422 is powered on. It is specified Full-scale error is a measure of the output error when full-scale as the area of the glitch in nV-sec. See Figure 41 and Figure 58. code is loaded to the DAC register. Ideally, the output should be full-scale − 1 LSB. Full-scale error is expressed in percent of Digital-to-Analog Glitch Impulse full-scale range (% FSR). Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes Negative Full-Scale Error/Zero-Scale Error state, but the output voltage remains constant. It is normally Negative full-scale error is the error in the DAC output voltage specified as the area of the glitch in nV-sec and is measured when 0x0000 (straight binary coding) or 0x8000 (twos comple- when the digital input code is changed by 1 LSB at the major ment coding) is loaded to the DAC register. Ideally, the output carry transition (0x7FFF to 0x8000). See Figure 38 and voltage should be negative full-scale − 1 LSB. A plot of zero- Figure 61. scale error vs. temperature can be seen in Figure 30. Glitch Impulse Peak Amplitude Zero-Scale Temperature Coefficient (TC) Glitch impulse peak amplitude is the peak amplitude of the Zero-scale TC is a measure of the change in zero-scale error impulse injected into the analog output when the input code in with a change in temperature. Zero-scale error TC is expressed the DAC register changes state. It is specified as the amplitude in ppm FSR/°C. of the glitch in millivolt and is measured when the digital input Output Voltage Settling Time code is changed by 1 LSB at the major carry transition (0x7FFF Output voltage settling time is the amount of time it takes for the to 0x8000). See Figure 38 and Figure 61. output to settle to a specified level for a full-scale input change. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Rev. E | Page 25 of 40 AD5412/AD5422 Data Sheet Power Supply Rejection Ratio (PSRR) where: PSRR indicates how the output of the DAC is affected by changes V is the maximum reference output measured over the REFmax in the power supply voltage. total temperature range. VREFmin is the minimum reference output measured over the total Voltage Reference TC temperature range. Voltage reference TC is a measure of the change in the reference VREFnom is the nominal reference output voltage, 5 V. output voltage with a change in temperature. The reference TC TempRange is the specified temperature range, −40°C to +85°C. is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature Load Regulation range expressed in ppm/°C, as follows: Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/mA.  V − V  6 REFmax REFmin TC= ×10   V ×TempRange  REFnom  Rev. E | Page 26 of 40 Data Sheet AD5412/AD5422 THEORY OF OPERATION The AD5412/AD5422 are precision digital-to-current loop and +V AD5412/AD5422 SENSE voltage output converters designed to meet the requirements of R1 industrial process control applications. They provide a high V OUT 12-/16-BIT RANGE SCALING DAC precision, fully integrated, low cost single-chip solution for R LOAD –V generating current loop and unipolar/bipolar voltage outputs. SENSE Current ranges are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA REFIN V –1V TO +3V CM to 20 mA; the voltage ranges available are 0 V to 5 V, ±5 V, 0 V to 10 V, and ±10 V; a 10% overrange is available on all voltage Figure 65. Voltage Output output ranges. The current and voltage outputs are available on separate pins, and only one is active at any time. The desired Voltage Output Amplifier output configuration is user selectable via the control register. The voltage output amplifier is capable of generating both ARCHITECTURE unipolar and bipolar output voltages. It is capable of driving a load of 1 kΩ in parallel with 1 µF (with an external compen- The DAC core architecture of the AD5412/AD5422 consists sation capacitor) to GND. The source and sink capabilities of of two matched DAC sections. A simplified circuit diagram is the output amplifier can be seen in Figure 35. The slew rate shown in Figure 63. The four MSBs of the 12-/16-bit data-word is 1 V/µs with a full-scale settling time of 25 µs maximum (10 V are decoded to drive 15 switches, E1 to E15. Each of these switches step). Figure 65 shows the voltage output driving a load, RLOAD, connects one of 15 matched resistors to either ground or the on top of a common-mode voltage (VCM) of −1 V to +3 V. In reference buffer output. The remaining 8/12 bits of the data- output module applications where a cable could possibly word drive the S0 to S7/S11 switches of an 8-/12-bit voltage become disconnected from +V , resulting in the amplifier SENSE mode R-2R ladder network. loop being broken and possibly resulting in large destructive V OUT voltages on V , include an optional resistor (R1) between OUT 2R 2R 2R 2R 2R 2R 2R +VSENSE and VOUT, as shown in Figure 65, of a value between S0 S1 S7/S11 E1 E2 E15 2 kΩ and 5 kΩ to ensure the amplifier loop is kept closed. If remote sensing of the load is not required, connect +VSENSE directly to VOUT and connect −VSENSE directly to GND. When changing ranges on the voltage output, a glitch may occur. For 8-12 BIT R-2R LADDER FOUR MSBs DECODED INTO this reason, it is recommended that the output be disabled by 15 EQUAL SEGMENTS setting the OUTEN bit of the control register to logic low before Figure 63. DAC Ladder Structure changing the output voltage range; this prevents a glitch from The voltage output from the DAC core is either converted to occurring. a current (see Figure 64) which is then mirrored to the supply Driving Large Capacitive Loads rail so that the application simply sees a current source output with respect to ground or it is buffered and scaled to output a The voltage output amplifier is capable of driving capacitive software selectable unipolar or bipolar voltage range (see loads of up to 1 µF with the addition of a nonpolarized 4 nF Figure 65). The current and voltage are output on separate compensation capacitor between the C and V pins. COMP OUT pins and cannot be output simultaneously. Without the compensation capacitor, up to 20 nF capacitive AV loads can be driven. DD R2 R3 T2 A2 T1 12-/16-BIT DAC I A1 OUT R SET Figure 64. Voltage-to-Current Conversion Circuitry Rev. E | Page 27 of 40 06996-058 06996-057 06996-059 AD5412/AD5422 Data Sheet SERIAL INTERFACE CONTROLLER AD5412/ 1 AD5422 The AD5412/AD5422 are controlled over a versatile 3-wire DATA OUT SDIN serial interface that operates at clock rates of up to 30 MHz. It is SERIAL CLOCK SCLK compatible with SPI, QSPI™, MICROWIRE, and DSP standards. CONTROL OUT LATCH Input Shift Register DATA IN SDO The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial SDIN clock input, SCLK. Data is clocked in on the rising edge of SCLK. The input register consists of eight address bits and AD5412/ 1 AD5422 16 data bits, as shown in Table 7. The 24-bit word is uncondi- SCLK tionally latched on the rising edge of the LATCH pin. Data LATCH continues to be clocked in irrespective of the state of LATCH. On the rising edge of LATCH, the data that is present in the SDO input register is latched; in other words, the last 24 bits to be clocked in before the rising edge of LATCH is the data that is SDIN latched. The timing diagram for this operation is shown in AD5412/ 1 Figure 2. AD5422 Table 7. Input Shift Register Format SCLK MSB LSB LATCH D23 to D16 D15 to D0 SDO Address byte Data-word 1 ADDITIONAL PINS OMITTED FOR CLARITY. Table 8. Address Byte Functions Address Word Function Figure 66. Daisy Chaining the AD5412/AD5422 00000000 No operation (NOP) Daisy-Chain Operation 00000001 Data register 00000010 Readback register value as per read address For systems that contain several devices, the SDO pin can be (see Table 9) used to daisy-chain the devices together as shown in Figure 66. 01010101 Control register This daisy-chain mode can be useful in system diagnostics and 01010110 Reset register in reducing the number of serial interface lines. Daisy-chain mode is enabled by setting the DCEN bit of the control register Standalone Operation to 1. The first rising edge of SCLK that clocks in the MSB of the data-word marks the beginning of the write cycle. SCLK is The serial interface works with both a continuous and noncon- continuously applied to the input shift register. If more than 24 tinuous serial clock. A continuous SCLK source can be used clock pulses are applied, the data ripples out of the shift register only if LATCH is taken high after the correct number of data and appears on the SDO line. This data is valid on the rising bits have been clocked in. In gated clock mode, a burst clock edge of SCLK, having been clocked out on the previous falling containing the exact number of clock cycles must be used, and SCLK edge. By connecting the SDO of the first device to the LATCH must be taken high after the final clock to latch the SDIN input of the next device in the chain, a multidevice data. The rising edge of SCLK that clocks in the MSB of the interface is constructed. Each device in the system requires data-word marks the beginning of the write cycle. Exactly 24 24 clock pulses. Therefore, the total number of clock cycles rising clock edges must be applied to SCLK before LATCH is th must equal 24 × n, where n is the total number of AD5412/ brought high. If LATCH is brought high before the 24 rising AD5422 devices in the chain. When the serial transfer to all SCLK edge, the data written is invalid. If more than 24 rising devices is complete, LATCH is taken high. This latches the SCLK edges are applied before LATCH is brought high, the input data in each device in the daisy chain. The serial clock can input data is also invalid. be a continuous or a gated clock. A continuous SCLK source can be used only if LATCH is taken high after the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and LATCH must be taken high after the final clock to latch the data (see Figure 4 for a timing diagram). Rev. E | Page 28 of 40 06996-060 Data Sheet AD5412/AD5422 Readback Operation Voltage Output Readback mode is invoked by setting the address byte and For a unipolar voltage output range, the output voltage can be read address when writing to the input register (see Table 9 and expressed as Table 11). The next write to the AD5412/AD5422 should be a D   V = V × Gain NOP command, which clocks out the data from the previously OUT REFIN N   2  addressed register as shown in Figure 3. For a bipolar voltage output range, the output voltage can be By default the SDO pin is disabled after having addressed the expressed as AD5412/AD5422 for a read operation; a rising edge on LATCH Gain×V enables the SDO pin in anticipation of data being clocked out. D   REFIN V = V × Gain − OUT REFIN N   After the data has been clocked out on SDO, a rising edge on 2  2 LATCH disables (tristate) the SDO pin. To read back the data where: register, for example, implement the following sequence: D is the decimal equivalent of the code loaded to the DAC. 1. Write 0x020001 to the input register. This configures the N is the bit resolution of the DAC. part for read mode with the data register selected. V is the reference voltage applied at the REFIN pin. REFIN 2. Follow this with a second write: a NOP condition, which is Gain is an internal gain whose value depends on the output 0x000000. During this write, the data from the register is range selected by the user as shown in Table 10. clocked out on the SDO line. Table 10. Internal Gain Value Output Range Gain Value Table 9. Read Address Decoding +5 V 1 Read Address Function +10 V 2 00 Read status register ±5 V 2 01 Read data register ±10 V 4 10 Read control register Current Output POWER-ON STATE For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA During power-on of the AD5412/AD5422, the power-on-reset current output ranges, the output current is respectively circuit ensures that all registers are loaded with zero-code. As expressed as such, both outputs are disabled; that is, the VOUT and IOUT pins 20 mA   are in tristate. The +V pin is internally connected to ground SENSE I = × D OUT  N  through a 40 kΩ resistor. Therefore, if the V and +V pins 2 OUT SENSE   are connected together, V is effectively clamped to ground OUT 24 mA   through a 40 kΩ resistor. Also upon power-on, internal I = × D OUT  N  2   calibration registers are read, and the data is applied to internal calibration circuitry. For a reliable read operation, there must be 16 mA   I = × D+ 4 mA sufficient voltage on the AVDD supply when the read event is OUT  N  2   triggered by the DV power supply powering up. Powering up CC where: the DV supply after the AV supply ensures this. If DV and CC DD CC D is the decimal equivalent of the code loaded to the DAC. AV are powered up simultaneously or the internal DV is DD CC N is the bit resolution of the DAC. enabled, the supplies should be powered up at a rate greater than, typically, 500 V/sec or 24 V/50 ms. If this cannot be achieved, issue a reset command to the AD5412/AD5422 after power-on; this performs a power-on-reset event, reading the calibration registers and ensures specified operation of the AD5412/AD5422. To ensure correct calibration and to allow the internal reference to settle to its correct trim value, 40 µs should be allowed after a successful power on reset. Table 11. Input Shift Register Contents for a Read Operation MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 to D2 D1 D0 1 0 0 0 0 0 0 1 0 X Read address 1 X = don’t care. Rev. E | Page 29 of 40 AD5412/AD5422 Data Sheet DATA REGISTER The data register is addressed by setting the address word of the input shift register to 0x01. The data to be written to the data register is entered in the D15 to D4 positions for the AD5412 and the D15 to D0 positions for the AD5422, as shown in Table 12 and Table 13. Table 12. Programming the AD5412 Data Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 12-bit data-word X X X X Table 13. Programming the AD5422 Data Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit data-word CONTROL REGISTER The control register is addressed by setting the address word of the input shift register to 0x55. The data to be written to the control register is entered in the D15 to D0 positions, as shown in Table 14. The control register functions are shown in Table 15. Table 14. Programming the Control Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLRSEL OVRRNG REXT OUTEN SR clock SR step SREN DCEN R2 R1 R0 Table 15. Control Register Functions Option Description CLRSEL See Table 21 for a description of the CLRSEL operation. OVRRNG Setting this bit increases the voltage output range by 10% (see the AD5412/AD5422 Features section). REXT Setting this bit selects the external current setting resistor (see the AD5412/AD5422 Features section). When using an external current setting resistor, it is recommended to only set REXT when also setting the OUTEN bit. Alternately, REXT can be set before the OUTEN bit is set, but the range (see Table 16) must be changed on the write in which the output is enabled. OUTEN Output enable. This bit must be set to enable the outputs. The range bits select which output is functional. SR clock Digital slew rate control (see the AD5412/AD5422 Features section). SR step Digital slew rate control (see the AD5412/AD5422 Features section). SREN Digital slew rate control enable. DCEN Daisy chain enable. R2, R1, R0 Output range select (see Table 16). Table 16. Output Range Options R2 R1 R0 Output Range Selected 0 0 0 0 V to 5 V voltage range 0 0 1 0 V to 10 V voltage range 0 1 0 ±5 V voltage range 0 1 1 ±10 V voltage range 1 0 1 4 mA to 20 mA current range 1 1 0 0 mA to 20 mA current range 1 1 1 0 mA to 24 mA current range Rev. E | Page 30 of 40 Data Sheet AD5412/AD5422 RESET REGISTER The reset register is addressed by setting the address word of the input shift register to 0x56. The data to be written to the reset register is entered in the D0 position as shown in Table 17. The reset register options are shown in Table 17 and Table 18. Table 17. Programming the Reset Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reset Table 18. Reset Register Functions Option Description Reset Setting this bit performs a reset operation, restoring the AD5412/AD5422 to its power-on state. STATUS REGISTER The status register is a read-only register. The status register functionality is shown in Table 19 and Table 20. Table 19. Decoding the Status Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Reserved I fault Slew active Over temp OUT Table 20. Status Register Functions Option Description I Fault This bit is set if a fault is detected on the I pin. OUT OUT Slew Active This bit is set while the output value is slewing (slew rate control enabled). Over Temp This bit is set if the AD5412/AD5422 core temperature exceeds ~150°C. Rev. E | Page 31 of 40 AD5412/AD5422 Data Sheet AD5412/AD5422 FEATURES ASYNCHRONOUS CLEAR (CLEAR) FAULT ALERT The CLEAR pin is an active high clear that allows the voltage FAULT The AD5412/AD5422 are equipped with a pin, which output to be cleared to either zero-scale code or midscale code, is an open-drain output allowing several AD5412/AD5422 user selectable via the CLEAR SELECT pin, or the CLRSEL bit devices to be connected together to one pull-up resistor for of the control register, as described in Table 21. (The clear select global fault detection. The FAULT pin is forced active by one feature is a logical OR function of the CLEAR SELECT pin and of the following fault scenarios: the CLRSEL bit.) The current output clears to the bottom of its • The voltage at IOUT attempts to rise above the compliance programmed range. It is necessary for CLEAR to be high for a range, due to an open-loop circuit or insufficient power minimum amount of time to complete the operation (see supply voltage. The IOUT current is controlled by a PMOS Figure 2). When the CLEAR signal is returned low, the output transistor and internal amplifier, as shown in Figure 64. remains at the cleared value. The preclear value can be restored The internal circuitry that develops the fault output avoids by pulsing the LATCH signal low without clocking any data. A using a comparator with window limits because this would new value cannot be programmed until the CLEAR pin is require an actual output error before the FAULT output returned low. becomes active. Instead, the signal is generated when the Table 21. CLRSEL Options internal amplifier in the output stage has less than ~1 V Output Value of remaining drive capability (when the gate of the output CLRSEL Unipolar Output Range Bipolar Output Range FAULT PMOS transistor nearly reaches ground). Thus, the 0 0 V 0 V output activates slightly before the compliance limit is 1 Midscale Negative full scale reached. Because the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and an output error In addition to defining the output value for a clear operation, does not occur before the FAULT output becomes active. the CLRSEL bit and CLEAR SELECT pin also define the default • If the core temperature of the AD5412/AD5422 exceeds output value. During selection of a new voltage range, the approximately 150°C. output value is as defined in Table 21. To avoid glitches on the output, it is recommended that, before changing voltage ranges, The IOUT fault and over temp bits of the status register are used the user disable the output by setting the OUTEN bit of the FAULT in conjunction with the pin to inform the user which control register to logic low. When OUTEN is set to logic high, FAULT one of the fault conditions caused the pin to be asserted the output goes to the default value as defined by CLRSEL and (see Table 19 and Table 20). CLEAR SELECT. VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION INTERNAL REFERENCE Under normal operation, the voltage output sinks/sources The AD5412/AD5422 contain an integrated 5 V voltage 10 mA. The maximum current that the voltage output delivers reference with initial accuracy of ±5 mV maximum and a is ~20 mA; this is the short-circuit current. temperature drift coefficient of ±10 ppm/°C maximum. The VOLTAGE OUTPUT OVERRANGE reference voltage is buffered and externally available for use An overrange facility is provided on the voltage output. When elsewhere within the system. See Figure 16 for a load regulation enabled via the control register, the selected output range is graph of the integrated reference. overranged by, typically, 10%. EXTERNAL CURRENT SETTING RESISTOR VOLTAGE OUTPUT FORCE-SENSE R is an internal sense resistor as part of the voltage-to-current SET The +VSENSE and −VSENSE pins are provided to facilitate remote conversion circuitry (see Figure 64). The stability of the output sensing of the load connected to the voltage output. If the load current over temperature is dependent on the stability of the is connected at the end of a long or high impedance cable, value of RSET. As a method of improving the stability of the sensing the voltage at the load allows the output amplifier to output current over temperature, an external precision 15 kΩ compensate and ensure that the correct voltage is applied across low drift resistor can be connected to the R pin of the SET the load. This function is limited only by the available power AD5412/AD5422 to be used instead of the internal resistor supply headroom. (R ). The external resistor is selected via the control register SET (see Table 14). Rev. E | Page 32 of 40 Data Sheet AD5412/AD5422 AVDD DIGITAL POWER SUPPLY C2 By default, the DVCC pin accepts a power supply of 2.7 V to CAP2 5.5 V. Alternatively, via the DVCC SELECT pin, an internal 4.5 V C1 HART MODEM power supply can be output on the DV pin for use as a digital OUTPUT CC power supply for other devices in the system or as a termination Figure 68. Coupling HART Signal for pull-up resistors. This facility offers the advantage of not In determining the absolute values of the capacitors, ensure that having to bring a digital supply across an isolation barrier. The the FSK output from the modem is passed undistorted. Thus, internal power supply is enabled by leaving the DVCC SELECT the bandwidth presented to the modem output signal must pass pin unconnected. To disable the internal supply, tie DVCC 1200 Hz and 2200 Hz frequencies. The recommended values SELECT to 0 V. DVCC is capable of supplying up to 5 mA of are C1 = 2.2 nF and C2 = 22 nF. Digitally controlling the slew current (for a load regulation graph, see Figure 10). rate of the output is necessary to meet the analog rate of change EXTERNAL BOOST FUNCTION requirements for HART. The addition of an external boost transistor, as shown in DIGITAL SLEW RATE CONTROL Figure 67, reduces the power dissipated in the AD5412/AD5422 The slew rate control feature of the AD5412/AD5422 allows the by reducing the current flowing in the on-chip output transistor user to control the rate at which the output voltage or current (dividing it by the current gain of the external circuit). A changes. With the slew rate control feature disabled, the output discrete NPN transistor with a breakdown voltage, BV , CEO changes at a rate limited by the output drive circuitry and the greater than 40 V can be used. The external boost capability attached load. See Figure 62 for current output step and has been developed for users who may wish to use the Figure 36 for voltage output step. To reduce the slew rate, enable AD5412/AD5422 at the extremes of the supply voltage, load the slew rate control feature. With the feature enabled via the current, and temperature range. The boost transistor can also SREN bit of the control register (see Table 14), the output, instead be used to reduce the amount of temperature-induced drift in of slewing directly between two values, steps digitally at a rate the part. This minimizes the temperature-induced drift of the defined by two parameters accessible via the control register, as on-chip voltage reference, which improves on drift and shown in Table 14. The parameters are set by the SR clock and linearity. SR step bits. SR clock defines the rate at which the digital slew is updated; SR step defines by how much the output value changes BOOST MJD31C at each update. Both parameters together define the rate of OR AD5412/ PBSS8110Z AD5422 change of the output voltage or current. Table 22 and Table 23 I OUT outline the range of values for both the SR clock and SR step parameters. Figure 69 shows the output current changing for 1kΩ 0.022µF R LOAD ramp times of 10 ms, 50 ms, and 100 ms. Table 22. Slew Rate Step Size Options Figure 67. External Boost Configuration AD5412 Step Size AD5422 Step EXTERNAL COMPENSATION CAPACITOR SR Step (LSB) Size (LSB) The voltage output can ordinarily drive capacitive loads of up to 000 1/16 1 20 nF; if there is a requirement to drive greater capacitive loads, 001 1/8 2 of up to 1 µF, an external compensation capacitor can be con- 010 1/4 4 nected between the CCOMP and VOUT pins. The addition of the 011 1/2 8 capacitor keeps the output voltage stable but also reduces the 100 1 16 bandwidth and increases the settling time of the voltage output. 101 2 32 110 4 64 HART COMMUNICATION 111 8 128 The AD5412/AD5422 (LFCSP version only) contain a CAP2 pin, into which a HART signal can be coupled. The HART signal appears on the current output if the output is enabled. To achieve a 1 mA peak-to-peak current, the signal amplitude at the CAP2 pin must be 48 mV peak-to-peak. Assuming that the modem output amplitude is 500 mV peak-to-peak, its output must be attenuated by 500/48 = 10.42. If this voltage is used, the current output should meet the HART amplitude specifications. Figure 68 shows the recommended circuit for attenuating and coupling in the HART signal. Rev. E | Page 33 of 40 06996-061 06996-051 AD5412/AD5422 Data Sheet 25 T = 25°C A AV = 24V DD Table 23. Slew Rate Update Clock Options R = 300Ω LOAD SR Clock Update Clock Frequency (Hz) 20 0000 257,730 0001 198,410 15 0010 152,440 0011 131,580 10 0100 115,740 0101 69,440 0110 37,590 5 10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5 0111 25,770 50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7 100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5 1000 20,160 0 1001 16,030 –10 0 10 20 30 40 50 60 70 80 90 100 110 TIME (ms) 1010 10,290 Figure 69. Output Current Slewing Under Control of the Digital Slew Rate 1011 8280 Control Feature 1100 6900 1101 5530 I FILTERING CAPACITORS (LFCSP PACKAGE) OUT 1110 4240 Capacitors can be placed between CAP1 and AVDD, and CAP2 1111 3300 and AVDD, as shown in Figure 70. AV DD The time it takes for the output to slew over a given output C1 C2 range can be expressed as follows: AV DD CAP1 Output Change AD5412/ Slew Time= (1) CAP2 AD5422 Step Size×Update Clock Frequency× LSB Size I GND OUT where: Slew Time is expressed in seconds. Output Change is expressed in amps for IOUT or volts for VOUT. Figure 70. IOUT Filtering Capacitors When the slew rate control feature is enabled, all output The CAP1 and CAP2 pins are available only on the LFCSP changes change at the programmed slew rate; if the CLEAR package. The capacitors form a filter on the current output pin is asserted, the output slews to the zero-scale value at the circuitry, as shown in Figure 71, reducing the bandwidth and programmed slew rate. The output can be halted at its current the slew rate of the output current. Figure 72 shows the effect value with a write to the control register. To avoid halting the the capacitors have on the slew rate of the output current. To output slew, the slew active bit (see Table 19) can be read to achieve significant reductions in the rate of change, very large check that the slew has completed before writing to any of the capacitor values are required, which may not be suitable in AD5410/AD5420 registers. The update clock frequency for any some applications. In this case, the digital slew rate control given value is the same for all output ranges. The step size, feature can be used. The capacitors can be used in conjunction however, varies across output ranges for a given value of step with the digital slew rate control feature as a means of size because the LSB size is different for each output range. smoothing out the steps caused by the digital code increments, Table 24 shows the range of programmable slew times for a full- as shown in Figure 73. scale change on any of the output ranges. The values in Table 24 were obtained using Equation 1. The digital slew rate control feature results in a staircase formation on the current output, as shown in Figure 73. This figure also shows how the staircase can be removed by connecting capacitors to the CAP1 and CAP2 pins, as described in the I Filtering Capacitors (LFCSP Package) section. OUT Rev. E | Page 34 of 40 OUTPUT CURRENT (mA) 06996-062 06996-139 Data Sheet AD5412/AD5422 C1 External Capacitors on the CAP1 and CAP2 Pins 6.8 C2 T = 25°C A AV 6.7 AV = 24V CAP1 CAP2 DD DD R = 300Ω LOAD 6.6 4kΩ 40Ω BOOST 6.5 6.4 DAC 12.5kΩ I OUT 6.3 NO EXTERNAL CAPS 6.2 10nF ON CAP1 R1 10nF ON CAP2 6.1 –1 0 1 2 3 4 5 6 7 8 TIME (ms) Figure 71. IOUT Filter Circuitry Figure 73. Smoothing Out the Steps Caused by the Digital Slew 25 Rate Control Feature 20 T = 25°C A 15 AV = 24V DD R = 300Ω LOAD 10 NO CAPACITOR 10nF ON CAP1 5 10nF ON CAP2 47nF ON CAP1 47nF ON CAP2 0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 TIME (ms) Figure 72. Slew Controlled 4 mA to 20 mA Output Current Step Using Table 24. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range Update Clock Step Size (LSB) Frequency (Hz) 1 2 4 8 16 32 64 128 257,730 0.25 0.13 0.06 0.03 0.016 0.008 0.004 0.0020 198,410 0.33 0.17 0.08 0.04 0.021 0.010 0.005 0.0026 152,440 0.43 0.21 0.11 0.05 0.027 0.013 0.007 0.0034 131,580 0.50 0.25 0.12 0.06 0.031 0.016 0.008 0.0039 115,740 0.57 0.28 0.14 0.07 0.035 0.018 0.009 0.0044 69,440 0.9 0.47 0.24 0.12 0.06 0.03 0.015 0.007 37,590 1.7 0.87 0.44 0.22 0.11 0.05 0.03 0.014 25,770 2.5 1.3 0.64 0.32 0.16 0.08 0.04 0.020 20,160 3.3 1.6 0.81 0.41 0.20 0.10 0.05 0.025 16,030 4.1 2.0 1.0 0.51 0.26 0.13 0.06 0.03 10,290 6.4 3.2 1.6 0.80 0.40 0.20 0.10 0.05 8280 7.9 4.0 2.0 1.0 0.49 0.25 0.12 0.06 6900 9.5 4.8 2.4 1.2 0.59 0.30 0.15 0.07 5530 12 5.9 3.0 1.5 0.74 0.37 0.19 0.09 4240 15 7.7 3.9 1.9 0.97 0.48 0.24 0.12 3300 20 9.9 5.0 2.5 1.24 0.62 0.31 0.16 Rev. E | Page 35 of 40 OUTPUT CURRENT (mA) 06996-142 06996-063 OUTPUT CURRENT (mA) 06996-043 AD5412/AD5422 Data Sheet APPLICATIONS INFORMATION AV DD VOLTAGE AND CURRENT OUTPUT RANGES ON THE SAME TERMINAL The current and voltage output pins can be connected together. AV DD A buffer amplifier is required however to prevent a current R P AD5412/ I leakage path through an internal 40k resistor on the +Vsense OUT AD5422 pin, when the device is in current output mode. In current R LOAD GND mode the VOUT pin is high impedance while in voltage output mode, the IOUT pin is high impedance and will not affect the voltage output. Figure 75. Output Transient Voltage Protection GALVANICALLY ISOLATED INTERFACE I OUT AD5412/ In many process control applications, it is necessary to provide OP07/OP184 AD5422 an isolation barrier between the controller and the unit being +V SENSE controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The V iCoupler® products from Analog Devices, Inc., provide voltage OUT I /V OUT OUT isolation in excess of 2.5 kV. The serial loading structure of the –V SENSE R AD5412/AD5422 makes the parts ideal for isolated interfaces SET because the number of interface lines is kept to a minimum. Figure 76 shows a 4-channel isolated interface to the AD5412/ AD5422 using an ADuM1400. For further information, visit http://www.analog.com/icouplers. Figure 74. Isolated Interface CONTROLLER 1 ADuM1400 DRIVING INDUCTIVE LOADS V V IA OA TO SERIAL When driving inductive or poorly defined loads, connect a ENCODE DECODE SCLK CLOCK IN 0.01 µF capacitor between I and GND. This ensures stability OUT V V with loads above 50 mH. There is no maximum capacitance IB OB TO SERIAL ENCODE DECODE SDIN DATA OUT limit. The capacitive component of the load may cause slower settling. The digital slew rate control feature may also prove V V IC OC TO SYNC OUT ENCODE DECODE useful in this situation. LATCH TRANSIENT VOLTAGE PROTECTION V V ID OD CONTROL TO ENCODE DECODE OUT The AD5412/AD5422 contain ESD protection diodes that CLEAR prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher 1 ADDITIONAL PINS OMITTED FOR CLARITY. transients. To protect the AD5412/AD5422 from excessively high voltage transients, external power diodes and a surge Figure 76. Isolated Interface current limiting resistor are required, as shown in Figure 75. MICROPROCESSOR INTERFACING The constraint on the resistor value is that, during normal operation, the output level at I must remain within its voltage OUT Microprocessor interfacing to the AD5412/AD5422 is via a serial compliance limit of AV – 2.5 V, and the two protection diodes DD bus that uses a protocol compatible with microcontrollers and and resistor must have appropriate power ratings. Further DSP processors. The communications channel is a 3-wire protection can be provided with transient voltage suppressors or minimum interface consisting of a clock signal, a data signal, transorbs; these are available as both unidirectional suppressors and a latch signal. The AD5412/AD5422 require a 24-bit data- (protect against positive high voltage transients) and word with data valid on the rising edge of SCLK. bidirectional suppressors (protect against both positive and For all interfaces, the DAC output update is initiated on the negative high voltage transients) and are available in a wide rising edge of LATCH. The contents of the registers can be range of standoff and breakdown voltage ratings. It is read using the readback function. recommended that all field connected nodes be protected. Rev. E | Page 36 of 40 06996-071 06996-064 06996-065 Data Sheet AD5412/AD5422 directly to ground. In this case, control the ambient temperature LAYOUT GUIDELINES or reduce AV . The conditions depend on the device package. DD In any circuit where accuracy is important, careful consideration of At the maximum ambient temperature of 85°C, the 24-lead TSSOP the power supply and ground return layout helps to ensure the rated performance. Design the printed circuit board (PCB) on package can dissipate 950 mW, and the 40-lead LFCSP package which the AD5412/AD5422 is mounted so that the analog and can dissipate 1.42 W. digital sections are separated and confined to certain areas of the To ensure that the junction temperature does not exceed 125°C board. If the AD5412/AD5422 is in a system where multiple while driving the maximum current of 24 mA directly into ground devices require an analog ground-to-digital ground connection, (also adding an on-chip current of 3 mA), reduce AV from the DD make the connection at one point only. Establish the star ground maximum rating to ensure that the package is not required to point as close as possible to the device. dissipate more power than previously stated (see Table 25, The AD5412/AD5422 should have ample supply bypassing of 10 Figure 77, and Figure 78). µF in parallel with 0.1 µF on each supply located as close to the 2.5 package as possible, ideally right up against the device. The 10 LFCSP µF capacitors are the tantalum bead type. The 0.1 µF capacitor 2.0 should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, 1.5 which provide a low impedance path to ground at high frequencies TSSOP to handle transient currents due to internal logic switching. 1.0 The power supply lines of the AD5412/AD5422 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching 0.5 signals such as clocks should be shielded with a digital ground to avoid radiating noise to other parts of the board. Never run these 0 near the reference inputs. A ground line routed between the SDIN 40 45 50 55 60 65 70 75 80 85 AMBIENT TEMPERATURE (°C) and SCLK lines helps reduce crosstalk between them (this is not Figure 77. Maximum Power Dissipation vs. Ambient Temperature required on a multilayer board that has a separate ground plane, 45 but separating the lines helps). It is essential to minimize noise on the REFIN line because it couples through to the DAC output. 43 LFCSP Avoid crossover of digital and analog signals. Traces on 41 opposite sides of the PCB should run at right angles to each 39 TSSOP other. This reduces the effects of feed through the board. A 37 microstrip technique is by far the best but not always possible 35 with a double-sided board. In this technique, the component 33 side of the board is dedicated to the ground plane, and signal 31 traces are placed on the solder side. 29 THERMAL AND SUPPLY CONSIDERATIONS 27 The AD5412/AD5422 are designed to operate at a maximum 25 junction temperature of 125°C. It is important that the devices 25 35 45 55 65 75 85 not be operated under conditions that cause the junction AMBIENT TEMPERATURE (°C) temperature to exceed this value. Excessive junction tempera- Figure 78. Maximum Supply Voltage vs. Ambient Temperature ture can occur if the AD5412/AD5422 are operated from the maximum AVDD while driving the maximum current (24 mA) Rev. E | Page 37 of 40 SUPPLY VOLTAGE (V) POWER DISSIPATION (W) 06996-066 06996-067 AD5412/AD5422 Data Sheet Table 25. Thermal and Supply Considerations for Each Package Considerations TSSOP LFCSP T max− T 125− 85 T max− T 125− 85 Maximum Allowed Power J A J A = = 950 mW = = 1.42W Dissipation When Operating at θ 28 θ 42 JA JA an Ambient Temperature of 85°C Maximum Allowed Ambient T max− P ×θ = 125− (40× 0.028)× 42= 78°C T max− P ×θ = 125− (40× 0.028)× 28= 94°C J D JA J D JA Temperature When Operating from a Supply of 40 V and Driving 24 mA Directly to Ground Maximum Allowed Supply T max− T 125− 85 T max− T 125− 85 J A J A = = 51 V = = 34 V Voltage When Operating at an AI ×θ 0.028× 28 AI ×θ 0.028× 42 DD JA DD JA Ambient Temperature of 85°C and Driving 24 mA Directly to Ground which both the voltage output and current output are available— INDUSTRIAL ANALOG OUTPUT MODULE one at a time—on one pin, thus reducing the number of screw Many industrial control applications have requirements for connections required. There is no conflict with tying the two output accurately controlled current and voltage output signals. The pins together because only the voltage output or the current output AD5412/AD5422 are ideal for such applications. Figure 80 shows can be enabled at any one time. the AD5412/AD5422 in a circuit design for an output module, The design provides for a HART-enabled current output, with specifically for use in an industrial control application. The design the HART capability provided by the AD5700/AD5700-1 HART provides for a current or voltage output. The module is powered modem, the industry’s lowest power and smallest footprint HART- from a field supply of 24 V. This supplies AVDD directly. An inverting compliant IC modem. For additional space-savings, the AD5700-1 buck regulator generates the negative supply for AVSS. For transient overvoltage protection, transient voltage suppressors (TVS) are offers a 0.5% precision internal oscillator. The HART_OUT signal placed on all field accessible connections. A 24 V volt TVS is placed from the AD5700 is attenuated and ac-coupled into the RSET pin on each I , V , +V , and −V connection, and a 36 V TVS of the AD5412/AD5422. Because the RSET pin is used to couple OUT OUT SENSE SENSE the HART signal into the AD5412/AD5422, either the TSSOP or is placed on the field supply input. For added protection, clamping LFCSP package option can be used for this configuration. It should diodes are connected from the IOUT, VOUT, +VSENSE, and −VSENSE be noted however, that since the TSSOP package does not have pins to the AVDD and AVSS power supply pins. If remote voltage load a CAP1 pin, C1 (see Figure 79) cannot be inserted in this case. sensing is not required, the +VSENSE pin can be directly connected to While the TSSOP equivalent circuit (as in Figure 79 but without the VOUT pin and the –VSENSE pin can be connected to GND. C1 in place) still passes the HART Communication Foundation Isolation between the AD5412/AD5422 and the backplane physical layer specs, the results with C1 in place are superior to circuitry is provided with ADuM1400 and ADuM1200 iCoupler those without C1 in place. Further information on an alternative digital isolators; further information on iCoupler products is configuration, whereby the HART signal is coupled into the CAP2 available at www.analog.com/icouplers. The internally generated pin can be found in Application Note AN-1065.This is based on the digital power supply of the AD5412/ AD5422 powers the field AD5410/AD5420 but can also be applied to the AD5412/AD5422. side of the digital isolaters, removing the need to generate a digital Use of either configuration results in the AD5700 HART modem power supply on the field side of the isolation barrier. The AD5412/ output modulating the 4 mA to 20 mA analog current without AD5422 digital supply output supplies up to 5 mA, which is more affecting the dc level of the current. This circuit adheres to the than enough to supply the 2.8 mA requirements of the ADuM1400 HART physical layer specifications as defined by the HART and ADuM1200 operating at a logic signal frequency of up to Communication Foundation. 1 MHz. To reduce the number of isolators required, nonessen- The module is powered from a field supply of ±10.8 V to ±26.4 V. tial signals such as CLEAR can be connected to GND. FAULT This supplies AV /AVSS directly. For transient overvoltage DD and SDO can be left unconnected, reducing the isolation protection, transient voltage suppressors (TVS) are placed on requirements to just three signals. both the IOUT and field supply connections. A 24 V TVS is INDUSTRIAL HART CAPABLE ANALOG OUTPUT placed on the IOUT connection, and a 36 V TVS is placed on the APPLICATION field supply input(s). For added protection, clamping diodes are Many industrial control applications have requirements for connected from the IOUT pin to the AVDD and GND power accurately controlled current output signals, and the AD5412/ supply pins. A 10 kΩ current limiting resistor is also placed in AD5422 are ideal for such applications. Figure 79 shows the series with the positive terminal of the +V buffer input. SENSE AD5412/AD5422 in a circuit design for a HART-enabled output This is to limit the current to an acceptable level during a module, specifically for use in an industrial control application in transient event. Rev. E | Page 38 of 40 Data Sheet AD5412/AD5422 10µF 10µF 10.8V 2.7V TO D4 TO 26.4V 0.1µF 0.1µF 5.5V C3 10kΩ DV CAP1 AV CC DD REFIN FAULT 0.1µF REFOUT D2 CLEAR DIGITAL R P I INTERFACE LATCH OUT 4mA TO 20mA SCLK CURRENTLOOP D3 D1 SDIN AD5412/ R L UART SDO AD5422 500Ω INTERFACE OP1177 +V SENSE R P 0V R 10kΩ SET TO –26.4V AV SS AV SS V 10µF OUT –V SENSE 0.1µF CAP2 GND 0.1µF C1 C2 V CC 2.2nF 22nF TXD HART_OUT AV DD RXD REF RTS 1µF 1.2MΩ AD5700 300pF 150kΩ CD ADC_IP AGND DGND 1.2MΩ 150pF Figure 79. AD5412/AD5422 in HART Configuration –15V INVERTING 24V FIELD SUPPLY BUCK 10µF 36V REGULATOR SMAJ36CA FIELD GROUND BACKPLANE 0.1µF SUPPLY 0.1µF ADuM1400 4nF 0.1µF 10kΩ V DD1 V DD2 V NC E2 AV C DV DV DD COMP CC CC V V IA OA SELECT +V SENSE V V +V IB SENSE OB CLEAR SELECT V V 4.7kΩ IC OC V V ID OD V +V CLEAR OUT OUT GND 100Ω GND 1 2 AD5412/ LATCH GND GND 1 2 1 SCLK AD5422 –V –V SENSE SENSE SDIN V V DD2 DD1 18Ω FAULT I V V OUT I OA IA OUT SDO V V OB IB 24V AV REFOUT REFIN GND SS GND GND 2 1 SMAJ24CA ADuM1200 0.1µF 10µF 0.1µF –15V 1 ADDITIONAL PINS OMITTED FOR CLARITY. Figure 80. AD5412/AD5422 in an Industrial Analog Output Module Application Rev. E | Page 39 of 40 BACKPLANE INTERFACE MICROCONTROLLER DIGITAL DIGITAL OUTPUTS INPUTS + + 06996-079 06996-068 AD5412/AD5422 Data Sheet OUTLINE DIMENSIONS 5.02 7.90 5.00 7.80 7.70 4.95 24 13 4.50 3.25 EXPOSED 4.40 PAD 3.20 (Pins Up) 4.30 3.15 6.40 BSC 1 12 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 1.05 1.20 MAX THE PIN CONFIGURATION AND 1.00 8° FUNCTION DESCRIPTIONS 0.80 SECTION OF THIS DATA SHEET. 0° 0.15 0.20 0.30 0.65 0.75 SEATING 0.09 0.05 BSC 0.19 PLANE 0.60 0.10 COPLANARITY 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-ADT Figure 81. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters 6.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 31 40 1 30 PIN 1 0.50 INDICATOR TOP 4.25 BSC 5.75 EXPOSED VIEW 4.10 SQ BSC SQ PAD 3.95 (BOT TOM VIEW) 0.50 21 10 0.40 11 20 0.30 0.25 MIN 4.50 12° MAX 0.80 MAX REF 0.65 TYP 0.05 MAX FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.02 NOM 1.00 THE PIN CONFIGURATION AND 0.30 0.85 FUNCTION DESCRIPTIONS 0.20 REF COPLANARITY SECTION OF THIS DATA SHEET. 0.23 0.80 SEATING 0.08 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 82. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Resolution IOUT TUE VOUT TUE Temperature Range Package Description Package Option AD5412AREZ 12 Bits 0.5% FSR max 0.3% FSR max −40°C to +85°C 24 Lead TSSOP_EP RE-24 AD5412AREZ-REEL7 12 Bits 0.5% FSR max 0.3% FSR max −40°C to +85°C 24 Lead TSSOP_EP RE-24 AD5412ACPZ-REEL 12 Bits 0.5% FSR max 0.3% FSR max −40°C to+85°C 40 Lead LFCSP_VQ CP-40-1 AD5412ACPZ-REEL7 12 Bits 0.5% FSR max 0.3% FSR max −40°C to+85°C 40 Lead LFCSP_VQ CP-40-1 AD5422AREZ 16 Bits 0.5% FSR max 0.3% FSR max −40°C to+85°C 24 Lead TSSOP_EP RE-24 AD5422AREZ-REEL 16 Bits 0.5% FSR max 0.3% FSR max −40°C to+85°C 24 Lead TSSOP_EP RE-24 AD5422BREZ 16 Bits 0.3% FSR max 0.1% FSR max −40°C to+85°C 24 Lead TSSOP_EP RE-24 AD5422BREZ-REEL 16 Bits 0.3% FSR max 0.1% FSR max −40°C to+85°C 24 Lead TSSOP_EP RE-24 AD5422ACPZ-REEL 16 Bits 0.5% FSR max 0.3% FSR max −40°C to+85°C 40 Lead LFCSP_VQ CP-40-1 AD5422ACPZ-REEL7 16 Bits 0.5% FSR max 0.3% FSR max −40°C to+85°C 40 Lead LFCSP_VQ CP-40-1 AD5422BCPZ-REEL 16 Bits 0.3% FSR max 0.1% FSR max −40°C to+85°C 40 Lead LFCSP_VQ CP-40-1 AD5422BCPZ-REEL7 16 Bits 0.3% FSR max 0.1% FSR max −40°C to+85°C 40 Lead LFCSP_VQ CP-40-1 EVAL-AD5422EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2009-2012 Analog Devices, Inc. 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