ANALOG DEVICES AD5420

Single-Channel, 12-/16-Bit, Serial Input, 4 mA to 20 mA, Current Source DAC, HART Connectivity Data Sheet AD5410/AD5420 FEATURES GENERAL DESCRIPTION 12-/16-bit resolution and monotonicity The AD5410/AD5420 are low cost, precision, fully integrated Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or 12-/16-bit converters offering a programmable current source 0 mA to 24 mA output designed to meet the requirements of industrial process ±0.01% FSR typical total unadjusted error (TUE) control applications. The output current range is programmable ±3 ppm/°C typical output drift at 4 mA to 20 mA, 0 mA to 20 mA, or an overrange function of Flexible serial digital interface 0 mA to 24 mA. The output is open-circuit protected. The On-chip output fault detection device operates with a power supply (AV ) range from 10.8 V DD On-chip reference (10 ppm/°C maximum) to 60 V. Output loop compliance is 0 V to AV − 2.5 V. DD Feedback/monitoring of output current The flexible serial interface is SPI, MICROWIRE™, QSPI™, and Asynchronous clear function DSP compatible and can be operated in 3-wire mode to Power supply (AV ) range DD minimize the digital isolation required in isolated applications. 10.8 V to 40 V; AD5410AREZ/AD5420AREZ The device also includes a power-on reset function, ensuring 10.8 V to 60 V; AD5410ACPZ/AD5420ACPZ that the device powers up in a known state, and an asynchronous Output loop compliance to AV − 2.5 V DD CLEAR pin that sets the output to the low end of the selected Temperature range: −40°C to +85°C current range. 24-lead TSSOP and 40-lead LFCSP packages The total unadjusted error is typically ±0.01% FSR. APPLICATIONS COMPANION PRODUCTS Process control Actuator control HART Modem: AD5700, AD5700-1 PLC HART network connectivity FUNCTIONAL BLOCK DIAGRAM DV CC SELECT DV CAP1 CAP2 AV CC DD R3 SENSE AD5410/AD5420 R2 R3 CLEAR BOOST LATCH I INPUT SHIFT OUT 12/16 SCLK REGISTER 12-/16-BIT AND CONTROL SDIN DAC LOGIC SDO FAULT POWER- R SET ON VREF RESET R SET REFOUT REFIN GND Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved. 07027-001 AD5410/AD5420 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 AD5410/AD5420 Features ............................................................ 20 Applications ....................................................................................... 1 Fault Alert .................................................................................... 20 General Description ......................................................................... 1 Asynchronous Clear (CLEAR) ................................................. 20 Companion Products ....................................................................... 1 Internal Reference ...................................................................... 20 Functional Block Diagram .............................................................. 1 External Current Setting Resistor ............................................ 20 Revision History ............................................................................... 2 Digital Power Supply .................................................................. 20 Specifications ..................................................................................... 3 External Boost Function............................................................ 20 AC Performance Characteristics ................................................ 5 HART Communication ............................................................. 21 Timing Characteristics ................................................................ 5 Digital Slew Rate Control .......................................................... 21 Absolute Maximum Ratings ............................................................ 7 IOUT Filtering Capacitors ............................................................ 23 ESD Caution .................................................................................. 7 Feedback/Monitoring of Output Current ............................... 23 Pin Configuration and Function Descriptions ............................. 8 Applications Information .............................................................. 25 Typical Performance Characteristics ........................................... 10 Driving Inductive Loads ............................................................ 25 Terminology .................................................................................... 15 Transient Voltage Protection .................................................... 25 Theory of Operation ...................................................................... 16 Layout Guidelines....................................................................... 25 Architecture ................................................................................. 16 Galvanically Isolated Interface ................................................. 25 Serial Interface ............................................................................ 16 Microprocessor Interfacing ....................................................... 26 Power-On State ........................................................................... 18 Thermal and Supply Considerations ....................................... 26 Transfer Function ....................................................................... 18 Industrial, HART Compatible Analog Output Application .................................................................................. 27 Data Register ............................................................................... 18 Outline Dimensions ....................................................................... 28 Control Register .......................................................................... 18 Ordering Guide .......................................................................... 28 Reset Register .............................................................................. 19 Status Register ............................................................................. 19 REVISION HISTORY 5/12—Rev. C to Rev. D 8/09—Rev. 0 to Rev. A Changes to Features and General Description ............................. 1 Reorganized Layout ............................................................ Universal Changes to Product Title ................................................................. 1 Changes to Table 1 ............................................................................. 3 Added Companion Products Section; Changes to Features Changes to Table 2 ............................................................................. 5 Section and Applications Section ................................................... 1 Changes to Introduction to Table 4 and to Table 4 ....................... 7 Changes to Table 5 ............................................................................ 9 Added Figure 6, Changes to Figure 5 and Table 5 ........................ 8 Change to Figure 8 ......................................................................... 11 Added Feedback/Monitoring of Output Current Section, Added HART Communication Section and Figure 41, Including Figure 45 to Figure 47; Renumbered Subsequent Renumbered Sequentially .............................................................. 21 Figures .............................................................................................. 23 Changes to Industrial, HART Compatible Analog Output Changes to Thermal and Supply Considerations Section and Application Section and Figure 54 ............................................... 27 Table 21 ............................................................................................ 26 Updated Outline Dimensions ....................................................... 28 11/11—Rev. B to Rev. C Changes to Ordering Guide .......................................................... 28 Changes to Table 10 ........................................................................ 18 3/09—Revision 0: Initial Version 2/10—Rev. A to Rev. B Changes to Figure 46 ..................................................................... 23 Rev. D | Page 2 of 28 Data Sheet AD5410/AD5420 SPECIFICATIONS AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT CURRENT RANGES 0 24 mA 0 20 mA 4 20 mA ACCURACY, INTERNAL RSET Resolution 16 Bits AD5420 12 Bits AD5410 Total Unadjusted Error (TUE) −0.3 +0.3 % FSR AD5420 −0.13 ±0.08 +0.13 % FSR AD5420, T = 25°C A −0.5 +0.5 % FSR AD5410 −0.3 ±0.15 +0.3 % FSR AD5410, T = 25°C A 2 Relative Accuracy (INL) −0.024 +0.024 % FSR AD5420 −0.032 +0.032 % FSR AD5410 Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.27 +0.27 % FSR −0.12 ±0.08 +0.12 % FSR TA = 25°C 3 Offset Error Temperature Coefficient (TC) ±16 ppm FSR/°C Gain Error −0.18 +0.18 % FSR AD5420 −0.03 ±0.006 +0.03 % FSR AD5420, T = 25°C A −0.22 +0.22 AD5410 −0.06 ±0.012 +0.06 AD5410, T = 25°C A 3 ±10 ppm FSR/°C Gain Error Temperature Coefficient (TC) Full-Scale Error −0.2 +0.2 % FSR −0.1 ±0.08 +0.1 % FSR TA = 25°C 3 Full-Scale Error Temperature Coefficient (TC) ±12 ppm FSR/°C ACCURACY, EXTERNAL R Assumes an ideal 15 kΩ resistor SET Resolution 16 Bits AD5420 12 Bits AD5410 Total Unadjusted Error (TUE) −0.15 +0.15 % FSR AD5420 −0.06 ±0.01 +0.06 % FSR AD5420, TA = 25°C −0.3 +0.3 % FSR AD5410 AD5410, TA = 25°C −0.1 ±0.02 +0.1 % FSR 2 Relative Accuracy (INL) −0.012 +0.012 % FSR AD5420 −0.032 +0.032 % FSR AD5410 Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.1 +0.1 % FSR −0.03 ±0.006 +0.03 % FSR TA = 25°C 3 ±3 ppm FSR/°C Offset Error Temperature Coefficient (TC) Gain Error −0.08 +0.08 % FSR −0.05 ±0.003 +0.05 % FSR TA = 25°C 3 Gain Error Temperature Coefficient (TC) ±4 ppm FSR/°C Full-Scale Error −0.15 +0.15 % FSR −0.06 ±0.01 +0.06 % FSR T = 25°C A 3 Full-Scale Error Temperature Coefficient (TC) ±7 ppm FSR/°C 3 OUTPUT CHARACTERISTICS Current Loop Compliance Voltage 0 AVDD − 2.5 V Output Current Drift vs. Time 50 ppm FSR Internal R , drift after 1000 hours at 125°C SET 20 ppm FSR External R , drift after 1000 hours at 125°C SET Resistive Load 1200 Ω Inductive Load 50 mH T = 25°C A DC Power Supply Rejection Ratio (PSRR) 1 µA/V Rev. D | Page 3 of 28 AD5410/AD5420 Data Sheet 1 Parameter Min Typ Max Unit Test Conditions/Comments Output Impedance 50 MΩ Output Current Leakage 60 pA Output disabled R3 Resistor Value 36 40 44 Ω TA = 25°C R3 Resistor Temperature Coefficient (TC) 30 ppm/°C IBIAS Current 399 444 489 µA IBIAS Current Temperature Coefficient (TC) 30 ppm/°C REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 4.95 5 5.05 V For specified performance DC Input Impedance 25 30 kΩ Reference Output Output Voltage 4.995 5.000 5.005 V T = 25°C A 3, 4 Reference TC 1.8 10 ppm/°C 3 18 µV p-p Output Noise (0.1 Hz to 10 Hz) 3 100 nV/√Hz @ 10 kHz Noise Spectral Density 3 Output Voltage Drift vs. Time 50 ppm Drift after 1000 hours, TA = 125°C 3 Capacitive Load 600 nF 3 Load Current 5 mA 3 7 mA Short-Circuit Current 3 95 ppm/mA Load Regulation 3 DIGITAL INPUTS JEDEC compliant Input High Voltage, V 2 V IH Input Low Voltage, VIL 0.8 V Input Current −1 +1 µA Per pin Pin Capacitance 10 pF Per pin 3 DIGITAL OUTPUTS SDO Output Low Voltage, VOL 0.4 V Sinking 200 µA Output High Voltage, V DV − 0.5 V Sourcing 200 µA OH CC High Impedance Leakage Current −1 +1 µA High Impedance Output Capacitance 5 pF FAULT Output Low Voltage, VOL 0.4 V 10 kΩ pull-up resistor to DVCC Output Low Voltage, VOL 0.6 V 2.5 mA load current Output High Voltage, V 3.6 V 10 kΩ pull-up resistor to DV OH CC POWER REQUIREMENTS AVDD 10.8 40 V TSSOP package 10.8 60 V LFCSP package DV CC Input Voltage 2.7 5.5 V Internal supply disabled Output Voltage 4.5 V DV can be overdriven up to 5.5 V CC 3 Output Load Current 5 mA 3 20 mA Short-Circuit Current AI 3 mA Output disabled DD 4 mA Output enabled DI 1 mA V = DV , V = GND CC IH CC IL Power Dissipation 144 mW AV = 40 V, I = 0 mA DD OUT 50 mW AVDD = 15 V, IOUT = 0 mA 1 Temperature range: −40°C to +85°C; typical at +25°C. 2 For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured from Code 256 for the AD5420 and Code 16 for the AD5410. 3 Guaranteed by design and characterization but not production tested. 4 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C. Rev. D | Page 4 of 28 Data Sheet AD5410/AD5420 AC PERFORMANCE CHARACTERISTICS AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. 1 Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE 2 Output Current Settling Time 10 µs 16 mA step, to 0.1% FSR 40 µs 16 mA step, to 0.1% FSR, L = 1 mH AC PSRR −75 dB 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage 1 Guaranteed by design and characterization; not production tested. 2 Digital slew rate control feature disabled and CAP1 = CAP2 = open circuit. TIMING CHARACTERISTICS AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3. 1, 2, 3 Parameter Limit at TMIN, TMAX Unit Description WRITE MODE t1 33 ns min SCLK cycle time t2 13 ns min SCLK low time t 13 ns min SCLK high time 3 t 13 ns min LATCH delay time 4 t5 40 ns min LATCH high time t5 5 µs min LATCH high time after a write to the control register t6 5 ns min Data setup time t 5 ns min Data hold time 7 t 40 ns min LATCH low time 8 t 20 ns min CLEAR pulse width 9 t10 5 µs max CLEAR activation time READBACK MODE t 90 ns min SCLK cycle time 11 t12 40 ns min SCLK low time t13 40 ns min SCLK high time t14 13 ns min LATCH delay time t 40 ns min LATCH high time 15 t 5 ns min Data setup time 16 t17 5 ns min Data hold time t18 40 ns min LATCH low time 4 t19 35 ns max Serial output delay time (CL SDO = 50 pF) t 35 ns max LATCH rising edge to SDO tristate 20 DAISY-CHAIN MODE t21 90 ns min SCLK cycle time t 40 ns min SCLK low time 22 t 40 ns min SCLK high time 23 t 13 ns min LATCH delay time 24 t25 40 ns min LATCH high time t26 5 ns min Data setup time t27 5 ns min Data hold time t 40 ns min LATCH low time 28 4 t 35 ns max Serial output delay time (C = 50 pF) 29 L SDO 1 Guaranteed by characterization but not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 CLSDO = capacitive load on SDO output. Rev. D | Page 5 of 28 AD5410/AD5420 Data Sheet t 1 SCLK 1 2 24 t t 2 3 t t 4 5 LATCH t t 7 8 t 6 SDIN DB23 DB0 t 9 CLEAR t 10 I OUT Figure 2. Write Mode Timing Diagram t 11 SCLK 1 2 1 2 24 8 9 22 23 24 t t 13 12 t t 14 15 LATCH t 18 t 17 t 16 SDIN DB23 DB0 DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES t REGISTER TO BE READ t 19 20 SDO X X X X DB15 DB0 UNDEFINED DATA FIRST 8 BITS ARE SELECTED REGISTER DON’T CARE BITS DATA CLOCKED OUT Figure 3. Readback Mode Timing Diagram t 21 26 48 SCLK 1 2 24 25 t t 22 23 t t 24 25 LATCH t t 27 28 t 26 SDIN DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N t INPUT WORD FOR DAC N – 1 29 SDO DB23 DB0 DB23 DB0 UNDEFINED INPUT WORD FOR DAC N Figure 4. Daisy-Chain Mode Timing Diagram Rev. D | Page 6 of 28 07027-002 07027-004 07027-003 Data Sheet AD5410/AD5420 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to Stresses above those listed under Absolute Maximum Ratings 80 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 4. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute AV to GND −0.3 V to +60 V DD maximum rating conditions for extended periods may affect DVCC to GND −0.3 V to +7 V device reliability. Digital Inputs to GND −0.3 V to DVCC + 0.3 V or +7 V ESD CAUTION (whichever is less) Digital Outputs to GND −0.3 V to DV + 0.3 V or +7 V CC (whichever is less) REFIN, REFOUT to GND −0.3 V to +7 V IOUT to GND −0.3 V to AVDD Operating Temperature Range 1 Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 125°C J 24-Lead TSSOP Package Thermal Impedance, θJA 42°C/W Thermal Impedance, θJC 9°C/W 40-Lead LFCSP Package Thermal Impedance, θ 28°C/W JA Thermal Impedance, θ 4°C/W JC Power Dissipation (TJ max − TA)/θJA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 2 kV 1 Power dissipated on chip must be derated to keep junction temperature below 125°C. The assumption is that the maximum power dissipation condition is sourcing 24 mA into ground from AVDD with a 4 mA on-chip current. Rev. D | Page 7 of 28 AD5410/AD5420 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 24 GND AV DD DV 2 23 NC CC FAULT 3 22 CAP2 PIN 1 GND 4 21 CAP1 NC 1 30 NC AD5410/ INDICATOR FAULT 2 29 CAP2 AD5420 28 CAP1 GND 5 20 BOOST GND 3 GND 4 27 BOOST TOP VIEW AD5410/AD5420 I CLEAR 5 26 OUT CLEAR 6 19 I (Not to Scale) OUT LATCH 6 TOP VIEW 25 R3 SENSE SCLK 7 (Not to Scale) 24 NC 18 LATCH 7 R3 SENSE SDIN 8 23 DV SELECT CC SDO 9 22 NC 8 17 SCLK NC NC 10 21 NC 9 16 SDIN DV SELECT CC 10 15 SDO REFIN GND 11 14 REFOUT GND 12 13 R SET NOTES NOTES 1. NC = NO CONNECT. 1. NC = NO CONNECT. 2. GROUND REFERENCE CONNECTION. IT IS RECOMMENDED THAT THE 2. GROUND REFERENCE CONNECTION. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. ENHANCED THERMAL PERFORMANCE. Figure 6. LFCSP Pin Configuration Figure 5. TSSOP Pin Configuration Table 5. Pin Function Descriptions TSSOP Pin No. LFCSP Pin No. Mnemonic Description 1, 4, 5, 12 3, 4, 14, 15, 37 GND These pins must be connected to ground. 2 39 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. 3 2 FAULT Fault Alert. This pin is asserted low when an open circuit is detected between IOUT and GND or an overtemperature is detected. The FAULT pin is an open-drain output and must be connected to DVCC through a pull-up resistor (typically 10 kΩ). 6 5 CLEAR Active High Input. Asserting this pin sets the output current to the zero-scale value, which is either 0 mA or 4 mA, depending on the output range programmed, that is, 0 mA to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA. 7 6 LATCH Positive Edge Sensitive Latch. A rising edge parallel loads the input shift register data into the relevant register. In the case of the data register, the output current is also updated. 8 7 SCLK Serial Clock Input. Data is clocked into the input shift register on the rising edge of SCLK. This operates at clock speeds of up to 30 MHz. 9 8 SDIN Serial Data Input. Data must be valid on the rising edge of SCLK. 10 9 SDO Serial Data Output. This pin is used to clock data from the device in daisy-chain or readback mode. Data is clocked out on the falling edge of SCLK. See Figure 3 and Figure 4. 11 12, 13 GND Ground Reference Pin. 13 16 R An external, precision, low drift 15 kΩ current setting resistor can be connected to this SET pin to improve the overall performance of the device. See the Specifications and AD5410/AD5420 Features sections. 14 17 REFOUT Internal Reference Voltage Output. VREFOUT = 5 V ± 5 mV at TA = 25°C. Typical temperature drift is 1.8 ppm/°C. 15 18 REFIN External Reference Voltage Input. V = 5 V ± 50 mV for specified performance. REFIN 16 23 DV This pin, when connected to GND, disables the internal supply, and an external supply CC SELECT must be connected to the DV pin. Leave this pin unconnected to enable the internal CC supply. See the AD5410/AD5420 Features section. 17, 23 1, 10, 11, 19, 20, NC Do not connect to these pins. 21, 22, 24, 30, 31, 32, 33, 34, 35, 38, 40 Rev. D | Page 8 of 28 07027-005 07027-053 NC 11 40 NC GND 12 39 DV CC GND 13 38 NC GND 14 37 GND GND 15 36 AV DD R SET 16 35 NC 34 NC REFOUT 17 REFIN 18 33 NC NC 19 32 NC NC 20 31 NC Data Sheet AD5410/AD5420 TSSOP Pin No. LFCSP Pin No. Mnemonic Description 18 25 R3SENSE The voltage measured between this pin and the BOOST pin is directly proportional to the output current and can be used as a monitor/feedback feature. This should be used as a voltage sense output only; current should not be sourced from this pin. See the AD5410/AD5420 Features section. 19 26 I Current Output Pin. OUT 20 27 BOOST Optional External Transistor Connection. Connecting an external transistor reduces the power dissipated in the AD5410/AD5420. See the AD5410/AD5420 Features section. 21 28 CAP1 Connection for Optional Output Filtering Capacitor. See the AD5410/AD5420 Features section. 22 29 CAP2 Connection for Optional Output Filtering Capacitor. See the AD5410/AD5420 Features section. Also HART Input Connection, see Device Features Section. 24 36 AVDD Positive Analog Supply Pin. Voltage ranges from 10.8 V to 40 V. 25 (EPAD) 41 (EPAD) Exposed Ground Reference Connection. It is recommended that the exposed pad be thermally pad connected to a copper plane for enhanced thermal performance. Rev. D | Page 9 of 28 AD5410/AD5420 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.004 EXTERNAL R SET 0.004 AV = 24V DD INTERNAL R SET 0mA TO 24mA RANGE EXTERNAL R , BOOST TRANSISTOR 0.002 SET 0.002 INTERNAL R , BOOST TRANSISTOR SET 0 0 –0.002 –0.002 –0.004 –0.004 –0.006 –0.006 AV = 2.4V DD T = 25°C –0.008 A –0.008 R = 250Ω LOAD –0.010 –0.010 0 10,000 20,000 30,000 40,000 50,000 60,000 –40 –20 0 20 40 60 80 CODE TEMPERATURE (°C) Figure 7. Integral Nonlinearity Error vs. Code Figure 10. Integral Nonlinearity Error vs. Temperature, Internal RSET 1.0 0.003 AV = 24V DD AV = 24V DD 0.8 T = 25°C 0mA TO 24mA RANGE A R = 250Ω LOAD 0.002 0.6 0.4 0.001 0.2 0 0 –0.2 –0.001 –0.4 EXTERNAL R SET –0.6 INTERNAL R SET –0.002 EXTERNAL R , BOOST TRANSISTOR SET –0.8 INTERNAL R , BOOST TRANSISTOR SET –1.0 –0.003 0 10,000 20,000 30,000 40,000 50,000 60,000 –40 –20 0 20 40 60 80 CODE TEMPERATURE (°C) Figure 8. Differential Nonlinearity Error vs. Code Figure 11. Integral Nonlinearity Error vs. Temperature, External RSET 0.05 1.0 AV = 24V DD 0.8 ALL RANGES 0.03 INTERNAL AND EXTERNAL R SET 0.01 0.6 –0.01 0.4 0.2 –0.03 –0.05 AV = 24V 0 DD T = 25°C A –0.07 –0.2 R = 250Ω LOAD –0.09 –0.4 EXTERNAL R SET –0.11 –0.6 INTERNAL R SET EXTERNAL R , BOOST TRANSISTOR –0.13 –0.8 SET INTERNAL R , BOOST TRANSISTOR SET –0.15 –1.0 0 10,000 20,000 30,000 40,000 50,000 60,000 –40 –20 0 20 40 60 80 CODE TEMPERATURE (°C) Figure 9. Total Unadjusted Error vs. Code Figure 12. Differential Nonlinearity Error vs. Temperature Rev. D | Page 10 of 28 TOTAL UNADJUSTED ERROR (% FSR) INL ERROR (% FSR) DNL ERROR (LSB) 07027-007 07027-008 07027-006 DNL ERROR (LSB) INL ERROR (% FSR) INL ERROR (% FSR) 07027-009 07027-010 07027-109 Data Sheet AD5410/AD5420 0.10 0.015 T = 25°C A 0mA TO 24mA RANGE 0.05 AV = 24V DD 0.010 0 0.005 –0.05 0 –0.10 4mA TO 20mA INTERNAL R SET –0.005 0mA TO 20mA INTERNAL R –0.15 SET 0mA TO 24mA INTERNAL R SET 4mA TO 20mA EXTERNAL R SET –0.010 –0.20 0mA TO 20mA EXTERNAL R SET 0mA TO 24mA EXTERNAL R SET –0.25 –0.015 –40 –20 0 20 40 60 80 10 15 20 25 30 35 40 TEMPERATURE (°C) AV (V) DD Figure 16. Integral Nonlinearity Error vs. AV , External R DD SET Figure 13. Total Unadjusted Error vs. Temperature 0.020 0.10 0.015 AV = 24V 0.05 DD T = 25°C A 0mA TO 24mA RANGE 0.010 0 0.005 –0.05 0 –0.10 –0.005 4mA TO 20mA INTERNAL R SET 0mA TO 20mA INTERNAL R –0.15 SET –0.010 0mA TO 24mA INTERNAL R SET 4mA TO 20mA EXTERNAL R SET –0.20 0mA TO 20mA EXTERNAL R –0.015 SET 0mA TO 24mA EXTERNAL R SET –0.020 –0.25 10 15 20 25 30 35 40 –40 –20 0 20 40 60 80 AV (V) TEMPERATURE (°C) DD Figure 14. Offset Error vs. Temperature Figure 17. Integral Nonlinearity Error vs. AVDD, Internal RSET 0.06 1.0 T = 25°C 0.8 A 0.04 AV = 24V DD 0mA TO 24mA RANGE 0.6 0.02 0.4 0 0.2 –0.02 0 –0.2 –0.04 4mA TO 20mA INTERNAL R SET 0mA TO 20mA INTERNAL R –0.4 SET –0.06 0mA TO 24mA INTERNAL R SET –0.6 4mA TO 20mA EXTERNAL R SET 0mA TO 20mA EXTERNAL R –0.08 SET –0.8 0mA TO 24mA EXTERNAL R SET –1.0 –0.10 –40 –20 0 20 40 60 80 10 15 20 25 30 35 40 AV (V) TEMPERATURE (°C) DD Figure 15. Gain Error vs. Temperature Figure 18. Differential Nonlinearity Error vs. AV , External R DD SET Rev. D | Page 11 of 28 GAIN ERROR (% FSR) TOTAL UNADJUSTED ERROR (%FSR) OFFSET ERROR (% FSR) 07027-017 07027-018 07027-013 INL ERROR (%FSR) INL ERROR (% FSR) DNL ERROR (LSB) 07027-012 07027-014 07027-011 AD5410/AD5420 Data Sheet 1.0 2.5 AV = 15V DD 0.8 I = 24mA OUT T = 25°C A R = 500Ω LOAD 0.6 2.0 0mA TO 24mA RANGE 0.4 0.2 1.5 0 1.0 –0.2 –0.4 –0.6 0.5 –0.8 0 –1.0 10 15 20 25 30 35 40 –40 –20 0 20 40 60 80 AV (V) TEMPERATURE (°C) DD Figure 19. Differential Nonlinearity Error vs. AV , Internal R DD SET Figure 22. Compliance Voltage Headroom vs. Temperature 0.025 3.5 T = 25°C A AV = 24V DD 0.020 0mA TO 24mA RANGE T = 25°C 3.0 A R = 250Ω LOAD 0.015 2.5 0.010 2.0 0.005 1.5 0 1.0 –0.005 0.5 –0.010 –0.015 0 0 100 200 300 400 500 600 10 15 20 25 30 35 40 TIME (µs) AV (V) DD Figure 20. Total Unadjusted Error vs. AV , External R Figure 23. Output Current vs. Time on Power-Up DD SET 20 0.05 0.03 10 0.01 AV = 24V DD 0 –0.01 T = 25°C A R = 250Ω LOAD –0.03 –10 T = 25°C A –0.05 0mA TO 24mA RANGE –20 –0.07 –0.09 –30 –0.11 –40 –0.13 –50 –0.15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 15 20 25 30 35 40 AV (V) TIME (µs) DD Figure 24. Output Current vs. Time on Output Enable Figure 21. Total Unadjusted Error vs. AV , Internal R DD SET Rev. D | Page 12 of 28 TOTAL UNADJUSTED ERROR (% FSR) DNL ERROR (LSB) TOTAL UNADJUSTED ERROR (%FSR) 07027-032 07027-016 07027-015 OUTPUT CURRENT (µA) OUTPUT CURRENT (µA) HEADROOM VOLTAGE (V) 07027-019 07027-020 07027-021 Data Sheet AD5410/AD5420 900 800 T = 25°C A 700 AV DD 600 DV = 5V CC 500 3 400 REFERENCE OUTPUT 300 200 DV = 3V 1 CC 100 0 CH1 2.00V M200µs CH3 2.1V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CH3 5.00V LOGIC VOLTAGE (V) Figure 25. DICC vs. Logic Input Voltage Figure 28. Reference Turn-on Transient 5.0 T = 25°C A 4.5 I = 0mA OUT 4.0 3.5 3.0 1 2.5 2.0 1.5 1.0 0.5 0 CH1 2µV M2.00s LINE 1.8V 10 15 20 25 30 35 40 AV (V) DD Figure 29. Reference Noise (0.1 Hz to 10 Hz Bandwidth) Figure 26. AIDD vs. AVDD 9 T = 25°C A 8 7 6 5 1 4 3 2 1 0 CH1 20µV M2.00s LINE 0V –21 –19 –17 –15 –13 –11 –9 –7 –5 –3 –1 1 LOAD CURRENT (mA) Figure 27. DV Output Voltage vs. Load Current CC Figure 30. Reference Noise (100 kHz Bandwidth) Rev. D | Page 13 of 28 DI (µA) AI (mA) DD CC DV OUTPUT VOLTAGE (V) CC 07027-024 07027-023 07027-022 07027-027 07027-026 07027-025 AD5410/AD5420 Data Sheet 70 5.0005 T = 25°C A 5.0000 60 AV = 24V DD 4.9995 50 4.9990 40 4.9985 30 4.9980 4.9975 20 T = 25°C 4.9970 A 10 AV = 40V DD OUTPUT DISABLED 4.9965 0 4.9960 –10 4.9955 0 5 10 15 20 25 30 35 40 45 0 1 2 3 4 5 6 7 8 9 COMPLIANCE VOLTAGE (V) LOAD CURRENT (mA) Figure 31. Output Leakage Current vs. Compliance Voltage Figure 34. Reference Output Voltage vs. Load Current 5.003 30 0x8000 TO 0x7FFF 50 DEVICES SHOWN AV = 24V DD AV = 24V DD 0x7FFF TO 0x8000 T = 25°C A 5.002 20 R = 250Ω LOAD 5.001 10 5.000 0 4.999 –10 4.998 –20 4.997 –30 –40 –20 0 20 40 60 80 0 2 4 6 8 10 12 14 16 18 20 TEMPERATURE (°C) TIME (µs) Figure 32. Reference Output Voltage vs. Temperature Figure 35. Digital-to-Analog Glitch 45 25 AV = 24V 40 DD T = 25°C A AV = 24V 20 DD 35 R = 300Ω LOAD 30 15 25 20 10 15 10 5 5 0 0 0 1 2 3 4 5 6 7 8 9 10 –1 0 1 2 3 4 5 6 7 8 TEMPERATURE COEFFICIENT (ppm/°C) TIME (µs) Figure 33. Reference Temperature Coefficient Histogram Figure 36. 4 mA to 20 mA Output Current Step Rev. D | Page 14 of 28 REFERENCE OUTPUT VOLTAGE (V) LEAKAGE CURRENT (pA) POPULATION (%) 07027-030 07027-028 07027-029 REFERENCE OUTPUT VOLTAGE (V) OUTPUT CURRENT (µA) OUTPUT CURRENT (mA) 07027-134 07027-049 07027-031 Data Sheet AD5410/AD5420 TERMINOLOGY Gain Error Temperature Coefficient (TC) Relative Accuracy or Integral Nonlinearity (INL) This is a measure of the change in gain error with changes in For the DAC, relative accuracy, or integral nonlinearity (INL), is temperature. Gain error TC is expressed in ppm FSR/°C. a measure of the maximum deviation, in % FSR, from a straight line passing through the endpoints of the DAC transfer Current Loop Compliance Voltage function. A typical INL vs. code plot is shown in Figure 7. This is the maximum voltage at the I pin for which the OUT output current is equal to the programmed value. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the Power Supply Rejection Ratio (PSRR) measured change and the ideal 1 LSB change between any two PSRR indicates how the output of the DAC is affected by adjacent codes. A specified differential nonlinearity of ±1 LSB changes in the power supply voltage. maximum ensures monotonicity. This DAC is guaranteed Voltage Reference Temperature Coefficient (TC) monotonic by design. A typical DNL vs. code plot can be seen Voltage reference TC is a measure of the change in the reference in Figure 8. output voltage with a change in temperature. The voltage Total Unadjusted Error (TUE) reference TC is calculated using the box method, which defines Total unadjusted error (TUE) is a measure of the output error the TC as the maximum change in the reference output over a taking all the various errors into account, namely INL error, given temperature range, expressed in ppm/°C as follows: offset error, gain error, and output drift over supplies and  V −V  REFmax REFmin 6 temperature. TUE is expressed in % FSR. A typical TUE vs. TC= ×10   V ×TempRange  REFnom  code plot can be seen in Figure 9. Monotonicity where: A DAC is monotonic if the output either increases or remains VREFmax is the maximum reference output measured over the constant for increasing digital input code. The AD5410/AD5420 total temperature range. are monotonic over their full operating temperature range. VREFmin is the minimum reference output measured over the total temperature range. Full-Scale Error V is the nominal reference output voltage, 5 V. REFnom Full-scale error is a measure of the output error when full-scale TempRange is the specified temperature range, −40°C to +85°C. code is loaded to the data register. Ideally, the output should be full-scale − 1 LSB. Full-scale error is expressed as a percentage Reference Load Regulation of the full-scale range (% FSR). Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/mA. Full-Scale Error Temperature Coefficient (TC) This is a measure of the change in full-scale error with changes in temperature. Full-scale error TC is expressed in ppm FSR/°C. Gain Error This is a measure of the span error of the DAC. It is the devia- tion in slope of the DAC transfer characteristic from the ideal expressed in % FSR. A plot of gain error vs. temperature can be seen in Figure 15. Rev. D | Page 15 of 28 AD5410/AD5420 Data Sheet THEORY OF OPERATION The AD5410/AD5420 are precision digital-to-current loop output SCLK. The input shift register consists of eight address bits and converters designed to meet the requirements of industrial 16 data bits, as shown in Table 6. The 24-bit word is uncondition- process control applications. They provide a high precision, ally latched on the rising edge of LATCH. Data continues to be fully integrated, low cost single-chip solution for generating clocked in irrespective of the state of LATCH. On the rising edge current loop outputs. The current ranges available are 0 mA of LATCH, the data that is present in the input shift register is to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. The desired latched; that is, the last 24 bits to be clocked in before the rising output configuration is user selectable via the control register. edge of LATCH is the data that is latched. The timing diagram for this operation is shown in Figure 2. ARCHITECTURE Standalone Operation The DAC core architecture of the AD5410/AD5420 consists of The serial interface works with both a continuous and noncon- two matched DAC sections. A simplified circuit diagram is shown tinuous SCLK. A continuous SCLK source can be used only if in Figure 37. The four MSBs of the 12-bit or 16-bit data-word LATCH is taken high after the correct number of data bits has are decoded to drive 15 switches, E1 to E15. Each of these switches been clocked in. In gated clock mode, a burst clock containing connects one of 15 matched resistors to either ground or the the exact number of clock cycles must be used, and LATCH reference buffer output. The remaining 8/12 bits of the data- must be taken high after the final clock to latch the data. The word drive Switch S0 to Switch S7 or Switch S0 to Switch S11 of an first rising edge of SCLK that clocks in the MSB of the data- 8-/12-bit voltage mode R-2R ladder network. word marks the beginning of the write cycle. Exactly 24 rising V OUT clock edges must be applied to SCLK before LATCH is brought th 2R 2R 2R 2R 2R 2R 2R high. If LATCH is brought high before the 24 rising SCLK S0 S1 S7/S11 E1 E2 E15 edge, the data written is invalid. If more than 24 rising SCLK V REFIN edges are applied before LATCH is brought high, the input data is also invalid. 8-/12-BIT R-2R LADDER FOUR MSBs DECODED INTO Table 6. Input Shift Register Format 15 EQUAL SEGMENTS MSB LSB Figure 37. DAC Ladder Structure DB23 to DB16 DB15 to DB0 The voltage output from the DAC core is converted to a current Address byte Data-word (see Figure 38) that is then mirrored to the supply rail so that Table 7. Address Byte Functions the application simply sees a current source output with respect Address Byte Function to ground. 00000000 No operation (NOP) AV DD 00000001 Data register 00000010 Readback register value as per read address R2 R3 (see Table 8) T2 01010101 Control register A2 01010110 Reset register 12-/16-BIT T1 I OUT Daisy-Chain Operation DAC A1 For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together, as shown in Figure 39. R SET This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Daisy-chain mode is enabled by setting the DCEN bit of the control register. Figure 38. Voltage-to-Current Conversion Circuitry The first rising edge of SCLK that clocks in the MSB of the data- SERIAL INTERFACE word marks the beginning of the write cycle. SCLK is continuously The AD5410/AD5420 are controlled over a versatile 3-wire applied to the input shift register. If more than 24 clock pulses serial interface that operates at clock rates of up to 30 MHz. They are applied, the data ripples out of the input shift register and are compatible with SPI, QSPI, MICROWIRE, and DSP appears on the SDO line. This data, having been clocked out on standards. the previous falling SCLK edge, is valid on the rising edge of SCLK. By connecting the SDO of the first device to the SDIN Input Shift Register input of the next device in the chain, a multidevice interface is The input shift register is 24 bits wide. Data is loaded into the constructed. Each device in the system requires 24 clock pulses. device MSB first as a 24-bit word under the control of a serial Therefore, the total number of clock cycles must equal 24 × N, clock input, SCLK. Data is clocked in on the rising edge of Rev. D | Page 16 of 28 07027-034 07027-033 Data Sheet AD5410/AD5420 where N is the total number of AD5410/AD5420 devices in the Readback Operation chain. When the serial transfer to all devices is complete, Readback mode is invoked by setting the address byte and read LATCH is taken high. This latches the input data in each device address as shown in Table 9 and Table 8 when writing to the in the daisy chain. The serial clock can be a continuous or a input shift register. The next write to the AD5410/AD5420 gated clock. should be a NOP command, which clocks out the data from the previously addressed register, as shown in Figure 3. By default, A continuous SCLK source can be used only if LATCH is taken the SDO pin is disabled. After having addressed the AD5410/ high after the correct number of clock cycles. In gated clock AD5420 for a read operation, a rising edge on LATCH enables mode, a burst clock containing the exact number of clock cycles must be used, and LATCH must be taken high after the final the SDO pin in anticipation of data being clocked out. After the clock to latch the data. See Figure 4 for a timing diagram. data has been clocked out on SDO, a rising edge on LATCH disables (tristate) the SDO pin once again. To read back the AD5410/ CONTROLLER data register, for example, the following sequence should be AD5420* implemented: DATA OUT SDIN SERIAL CLOCK SCLK 1. Write 0x020001 to the AD5410/AD5420 input shift CONTROL OUT LATCH register. This configures the part for read mode with the data register selected. DATA IN SDO 2. Follow this with a second write, a NOP condition, 0x000000. During this write, the data from the data register is clocked SDIN out on the SDO line. AD5410/ AD5420* Table 8. Read Address Decoding SCLK Read Address Function LATCH 00 Read status register 01 Read data register SDO 10 Read control register SDIN AD5410/ AD5420* SCLK LATCH SDO *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 39. Daisy Chaining the AD5410/AD5420 Table 9. Input Shift Register Contents for a Read Operation MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB2 DB1 DB0 1 0 0 0 0 0 0 1 0 X Read address 1 X = don’t care. Rev. D | Page 17 of 28 07027-035 AD5410/AD5420 Data Sheet POWER-ON STATE DATA REGISTER Upon power-on of the AD5410/AD5420, the power-on reset The data register is addressed by setting the address byte of the circuit ensures that all registers are loaded with zero code. As input shift register to 0x01. The data to be written to the data such, the output is disabled (tristate). Also upon power-on, register is entered in Position DB15 to Position DB4 for the internal calibration registers are read, and the data is applied to AD5410 and in Position DB15 to Position DB0 for the AD5420, internal calibration circuitry. For a reliable read operation, there as shown in Table 12 and Table 13, respectively must be sufficient voltage on the AV supply when the read event DD CONTROL REGISTER is triggered by the DVCC power supply powering up. Powering The control register is addressed by setting the address byte of up the DVCC supply after the AVDD supply ensures this. If DVCC the input shift register to 0x55. The data to be written to the and AVDD are powered up simultaneously or if the internal DVCC control register is entered in Position DB15 to Position DB0, is enabled, the supplies should be powered up at a rate greater as shown in Table 14. The control register bit functions are than, typically, 500 V/sec or 24 V per 50 ms. If this cannot be described in Table 10. achieved, simply issue a reset command to the AD5410/AD5420 after power-on. This performs a power-on reset event, reading Table 10. Control Register Bit Functions the calibration registers and ensuring specified operation of the Bit Description AD5410/AD5420. REXT Setting this bit selects the external current setting resistor. See the AD5410/AD5420 Features section TRANSFER FUNCTION for further details. When using an external current For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA setting resistor, it is recommended to only set REXT current output ranges, the output current is respectively when also setting the OUTEN bit. Alternately, REXT can be set before the OUTEN bit is set, but the expressed as range (see Table 11) must be changed on the write 20 mA   in which the output is enabled. I = × D OUT N   2 OUTEN Output enable. This bit must be set to enable the   output. 24 mA   SR Clock Digital slew rate control. See the AD5410/AD5420 I = × D OUT N   Features section. 2   SR Step Digital slew rate control. See the AD5410/AD5420 16 mA   Features section. I = × D+ 4 mA OUT N   2   SREN Digital slew rate control enable. DCEN Daisy-chain enable. where: R2, R1, R0 Output range select. See Table 11. D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. Table 11. Output Range Options R2 R1 R0 Output Range Selected 1 0 1 4 mA to 20 mA current range 1 1 0 0 mA to 20 mA current range 1 1 1 0 mA to 24 mA current range Table 12. Programming the AD5410 Data Register MSB LSB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 1 1 12-bit data-word X X X X 1 X = don’t care. Table 13. Programming the AD5420 Data Register MSB LSB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 16-bit data-word Table 14. Programming the Control Register MSB LSB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 REXT OUTEN SR clock SR step SREN DCEN R2 R1 R0 Rev. D | Page 18 of 28 Data Sheet AD5410/AD5420 Table 15. Status Register Bit Functions RESET REGISTER Bit Description The reset register is addressed by setting the address byte of the IOUT Fault This bit is set if a fault is detected on the IOUT pin. input shift register to 0x56. The reset register contains a single Slew Active This bit is set while the output value is slewing reset bit at Position DB0, as shown in Table 16. Writing a logic (slew rate control enabled). high to this bit performs a reset operation, restoring the part to Overtemp This bit is set if the AD5410/AD5420 core its power-on state. temperature exceeds approximately 150°C. STATUS REGISTER The status register is a read-only register. The status register bit functionality is shown in Table 15 and Table 17. Table 16. Programming the Reset Register MSB LSB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Reserved Reset Table 17. Decoding the Status Register MSB LSB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Reserved I fault Slew active Overtemp OUT Rev. D | Page 19 of 28 AD5410/AD5420 Data Sheet AD5410/AD5420 FEATURES EXTERNAL CURRENT SETTING RESISTOR FAULT ALERT In Figure 38, R is an internal sense resistor as part of the SET FAULT The AD5410/AD5420 are equipped with a pin, which is voltage-to-current conversion circuitry. The stability of the an open-drain output allowing several AD5410/AD5420 output current over temperature is dependent on the stability of devices to be connected together to one pull-up resistor for the value of RSET. An external precision 15 kΩ low drift resistor global fault detection. The FAULT pin is forced active by any can be connected from the RSET pin of the AD5410/AD5420 to one of the following fault scenarios: ground; this improves the overall performance of the AD5410/ • The voltage at IOUT attempts to rise above the compliance AD5420. The external resistor is selected via the control range, due to an open-loop circuit or insufficient power register. See Table 14. supply voltage. The IOUT current is controlled by a PMOS DIGITAL POWER SUPPLY transistor and internal amplifier, as shown in Figure 38. By default, the DVCC pin accepts a power supply of 2.7 V to The internal circuitry that develops the fault output avoids 5.5 V. Alternatively, via the DVCC SELECT pin, an internal 4.5 V using a comparator with window limits because this requires power supply can be output on the DV pin for use as a digital CC an actual output error before the FAULT output becomes power supply for other devices in the system or as a termination active. Instead, the signal is generated when the internal for pull-up resistors. This facility offers the advantage of not amplifier in the output stage has less than approximately having to bring a digital supply across an isolation barrier. The 1 V of remaining drive capability (when the gate of the internal power supply is enabled by leaving the DVCC SELECT output PMOS transistor nearly reaches ground). Thus, the pin unconnected. To disable the internal supply, DVCC SELECT FAULT output activates slightly before the compliance limit is should be tied to 0 V. DVCC is capable of supplying up to 5 mA reached. Because the comparison is made within the feed- of current. See Figure 27 for a load regulation graph. back loop of the output amplifier, the output accuracy is maintained by its open-loop gain and an output error does EXTERNAL BOOST FUNCTION not occur before the FAULT output becomes active. The addition of an external boost transistor, as shown in Figure 40, • If the core temperature of the AD5410/AD5420 exceeds reduces the power dissipated in the AD5410/AD5420 by reducing approximately 150°C. the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). A discrete NPN The IOUT fault and overtemp bits of the status register are used transistor with a breakdown voltage, BV , greater than 40 V CEO FAULT in conjunction with the pin to inform the user which can be used. FAULT fault condition caused the pin to be asserted. See Table 17 and Table 15. The external boost capability allows the AD5410/AD5420 to be used at the extremes of the supply voltage, load current, and ASYNCHRONOUS CLEAR (CLEAR) temperature range. The boost transistor can also be used to CLEAR is an active high clear that clears the current output to reduce the amount of temperature-induced drift in the part. the bottom of its programmed range. It is necessary to maintain This minimizes the temperature-induced drift of the on-chip CLEAR high for a minimum amount of time (see Figure 2) to voltage reference, which improves drift and linearity. complete the operation. When the CLEAR signal is returned MJD31C OR low, the output remains at the cleared value. The preclear value BOOST 2N3053 can be restored by pulsing the LATCH signal low without AD5410/ AD5420 clocking any data. A new value cannot be programmed until the I OUT CLEAR pin is returned low. 1kΩ INTERNAL REFERENCE 0.022µF R L The AD5410/AD5420 contain an integrated +5 V voltage reference with initial accuracy of ±5 mV maximum and a Figure 40. External Boost Configuration temperature drift coefficient of 10 ppm/°C maximum. The reference voltage is buffered and externally available for use elsewhere within the system. See Figure 34 for a load regulation graph of the integrated reference. Rev. D | Page 20 of 28 07027-036 Data Sheet AD5410/AD5420 HART COMMUNICATION Table 18. Slew Rate Update Clock Values The AD5410/AD54120 contain a CAP2 pin, into which a HART SR Clock Update Clock Frequency (Hz) signal can be coupled. The HART signal appears on the current 0000 257,730 output if the output is enabled. To achieve a 1 mA peak-to-peak 0001 198,410 current, the signal amplitude at the CAP2 pin must be 48 mV 0010 152,440 peak-to-peak. Assuming that the modem output amplitude is 500 0011 131,580 mV peak-to-peak, its output must be attenuated by 500/48 = 10.42. 0100 115,740 If this voltage is used, the current output should meet the HART 0101 69,440 amplitude specifications. Figure 41 shows the recommended 0110 37,590 circuit for attenuating and coupling in the HART signal. 0111 25,770 AVDD 1000 20,160 1001 16,030 C2 CAP2 1010 10,290 C1 1011 8280 HART MODEM OUTPUT 1100 6900 Figure 41. Coupling HART Signal 1101 5530 1110 4240 In determining the absolute values of the capacitors, ensure that 1111 3300 the FSK output from the modem is passed undistorted. Thus, the bandwidth presented to the modem output signal must pass Table 19. Slew Rate Step Size Options 1200 Hz and 2200 Hz frequencies. The recommended values SR Step AD5410 Step Size (LSB) AD5420 Step Size (LSB) are C1 = 2.2 nF and C2 = 22 nF. Digitally controlling the slew 000 1/16 1 rate of the output is necessary to meet the analog rate of change 001 1/8 2 requirements for HART. 010 1/4 4 DIGITAL SLEW RATE CONTROL 011 1/2 8 The slew rate control feature of the AD5410/AD5420 allows the 100 1 16 user to control the rate at which the output current changes. 101 2 32 With the slew rate control feature disabled, the output current 110 4 64 changes at a rate of approximately 16 mA in 10 µs (see Figure 36). 111 8 128 This varies with load conditions. To reduce the slew rate, enable 25 T = 25°C A the slew rate control feature. With the feature enabled via the AV = 24V DD R = 300Ω LOAD SREN bit of the control register (see Table 14), the output, instead 20 of slewing directly between two values, steps digitally at a rate defined by two parameters accessible via the control register, as 15 shown in Table 14. The parameters are SR clock and SR step. SR clock defines the rate at which the digital slew is updated, SR step defines by how much the output value changes at each 10 update. Both parameters together define the rate of change of the output current. Table 18 and Table 19 outline the range of 5 values for both the SR clock and SR step parameters. Figure 42 10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5 50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7 shows the output current changing for ramp times of 10 ms, 100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5 0 50 ms, and 100 ms. –10 0 10 20 30 40 50 60 70 80 90 100 110 TIME (ms) Figure 42. Output Current Slewing Under Control of the Digital Slew Rate Control Feature Rev. D | Page 21 of 28 07027-200 OUTPUT CURRENT (mA) 07027-139 AD5410/AD5420 Data Sheet The time it takes for the output current to slew over a given value with a write to the control register. To avoid halting the output range can be expressed as follows: output slew, the slew active bit can be read to check that the slew has completed before writing to any of the AD5410/ Slew Time= AD5420 registers (see Table 17). The update clock frequency for Output Change (1) any given value is the same for all output ranges. The step size, Step Size×Update Clock Frequency× LSB Size however, varies across output ranges for a given value of step size because the LSB size is different for each output range. where: Table 20 shows the range of programmable slew times for a full- Slew Time is expressed in seconds. scale change on any of the output ranges. The values in Table 20 Output Change is expressed in amps. were obtained using Equation 1. The digital slew rate control When the slew rate control feature is enabled, all output feature results in a staircase formation on the current output, as changes change at the programmed slew rate. If the CLEAR shown in Figure 46. Figure 46 also shows how the staircase can pin is asserted, the output slews to the zero-scale value at the be removed by connecting capacitors to the CAP1 and CAP2 programmed slew rate. The output can be halted at its current pins, as described in the IOUT Filtering Capacitors section. Table 20. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range Step Size (LSBs) Update Clock Frequency (Hz) 1 2 4 8 16 32 64 128 257,730 0.25 0.13 0.06 0.03 0.016 0.008 0.004 0.0020 198,410 0.33 0.17 0.08 0.04 0.021 0.010 0.005 0.0026 152,440 0.43 0.21 0.11 0.05 0.027 0.013 0.007 0.0034 131,580 0.50 0.25 0.12 0.06 0.031 0.016 0.008 0.0039 115,740 0.57 0.28 0.14 0.07 0.035 0.018 0.009 0.0044 69,440 0.9 0.47 0.24 0.12 0.06 0.03 0.015 0.007 37,590 1.7 0.87 0.44 0.22 0.11 0.05 0.03 0.014 25,770 2.5 1.3 0.64 0.32 0.16 0.08 0.04 0.020 20,160 3.3 1.6 0.81 0.41 0.20 0.10 0.05 0.025 16,030 4.1 2.0 1.0 0.51 0.26 0.13 0.06 0.03 10,290 6.4 3.2 1.6 0.80 0.40 0.20 0.10 0.05 8280 7.9 4.0 2.0 1.0 0.49 0.25 0.12 0.06 6900 9.5 4.8 2.4 1.2 0.59 0.30 0.15 0.07 5530 12 5.9 3.0 1.5 0.74 0.37 0.19 0.09 4240 15 7.7 3.9 1.9 0.97 0.48 0.24 0.12 3300 20 9.9 5.0 2.5 1.24 0.62 0.31 0.16 Rev. D | Page 22 of 28 Data Sheet AD5410/AD5420 6.8 I FILTERING CAPACITORS OUT T = 25°C A Capacitors can be placed between CAP1 and AVDD, and CAP2 6.7 AV = 24V DD R = 300Ω LOAD and AVDD, as shown in Figure 43. 6.6 AV DD C1 C2 6.5 AV DD CAP1 6.4 AD5410/ CAP2 AD5420 6.3 I OUT NO EXTERNAL CAPS GND 6.2 10nF ON CAP1 10nF ON CAP2 6.1 Figure 43. IOUT Filtering Capacitors –1 0 1 2 3 4 5 6 7 8 TIME (ms) The capacitors form a filter on the current output circuitry, as Figure 46. Smoothing Out the Steps Caused by the Digital Slew Rate Control shown in Figure 44, reducing the bandwidth and the slew rate Feature of the output current. Figure 45 shows the effect the capacitors FEEDBACK/MONITORING OF OUTPUT CURRENT have on the slew rate of the output current. To achieve significant For feedback or monitoring of the output current value, a sense reductions in the rate of change, very large capacitor values are resistor can be placed in series with the I output pin and the OUT required, which may not be suitable in some applications. In voltage drop across it measured. As well as being an additional this case, the digital slew rate control feature should be used. component, the resistor increases the compliance voltage The capacitors can be used in conjunction with the digital slew required. An alternative method is to use a resistor that is rate control feature as a means of smoothing out the steps caused already in place. R3 is such a resistor and is internal to the by the digital code increments, as shown in Figure 46. C1 AD5410/AD5420, as shown in Figure 47. By measuring the voltage between the R3 and BOOST pins, the value of the C2 SENSE output current can be calculated as follows: CAP1 CAP2 AV DD V R3 (2) I = − I OUT BIAS 40Ω R3 BOOST 4kΩ where: V is the voltage drop across R3 measured between the R3 R3 SENSE DAC 12.5kΩ and BOOST pins I OUT IBIAS is a constant bias current flowing through R3 with a typical value of 444 µA. R R3 is the resistance value of resistor R3 with a typical value of 40 Ω. SET Figure 44. I Filter Circuitry OUT AV DD R 25 METAL R3 SENSE R3 40Ω 20 BOOST T = 25°C A I OUT 15 AV = 24V DD R = 300Ω LOAD I 444µA BIAS 10 NO CAPACITOR 10nF ON CAP1 10nF ON CAP2 5 47nF ON CAP1 Figure 47. Structure of Current Output Circuit 47nF ON CAP2 0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 TIME (ms) Figure 45. Slew Controlled 4 mA to 20 mA Output Current Step Using External Capacitors on the CAP1 and CAP2 Pins Rev. D | Page 23 of 28 OUTPUT CURRENT (mA) 07027-037 07027-142 07027-038 OUTPUT CURRENT (mA) 07027-050 07027-043 AD5410/AD5420 Data Sheet R3 and I both have a tolerance of ±10% and a temperature To eliminate errors due to the tolerances of R3 and I , a two- BIAS BIAS coefficient of 30 ppm/°C. Connecting to R3 rather than measurement calibration can be performed as the following SENSE AV avoids incorporating into R3 internal metal connections example illustrates: DD that have large temperature coefficients and result in large 1. Progam code 0x1000 and measure IOUT and VR3. In this errors. See Figure 48 for a plot of R3 vs. ambient temperature example, the measured values are and Figure 49 for a plot of R3 vs. output current. IOUT = 1.47965 mA 40.98 VR3 = 79.55446 mV I = 12mA OUT 40.96 R3 = V /(12mA + 444µA) 2. Program Code 0xF000 and measure I and V again. R3 OUT R3 The measured values this time are 40.94 I = 22.46754 mA OUT 40.92 V = 946.39628 mV R3 40.90 Using this information and Equation 2, two simultaneous 40.88 equations can be generated from which the values of R3 and 40.86 IBIAS can be calculated as follows: 40.84 V R3 40.82 I = − I OUT BIAS R3 40.80 V R3 ⇒ I = − I 40.78 BIAS OUT –40 –20 0 20 40 60 80 100 R3 AMBIENT TEMPERATURE (°C) Figure 48. R3 Resistor Value vs. Temperature Simultaneous Equation 1 42.0 T = 25°C A 0.07955446 R3 = V /(I + 444µA) 41.8 R3 OUT I = − 0.00147965 BIAS R3 41.6 Simultaneous Equation 2 41.4 0.94639628 41.2 I = − 0.02246754 BIAS R3 41.0 From these two equations, 40.8 Ω and μA 40.6 R3= 41.302 I = 446.5 BIAS 40.4 And Equation 2 becomes 40.2 V R3 I = − 446.5µA 40.0 OUT 41.302 0 5 10 15 20 25 I (mA) OUT Figure 49. R3 Resistor Value vs. I OUT Rev. D | Page 24 of 28 R3 (Ω) R3 RESISTANCE (Ω) 07027-052 07027-051 Data Sheet AD5410/AD5420 APPLICATIONS INFORMATION capacitor should have low effective series resistance (ESR) DRIVING INDUCTIVE LOADS and low effective series inductance (ESI), such as the common When driving inductive or poorly defined loads, connect a 0.01 µF ceramic types, which provide a low impedance path to ground capacitor between I and GND. This ensures stability with OUT at high frequencies to handle transient currents due to internal loads beyond 50 mH. There is no maximum capacitance limit. logic switching. The capacitive component of the load may cause slower settling. The power supply lines of the AD5410/AD5420 should use as Alternatively, the capacitor can be connected from CAP1 and/or large a trace as possible to provide low impedance paths and to CAP2 to AVDD to reduce the slew rate of the current. The digital reduce the effects of glitches on the power supply line. Fast- slew rate control feature may also prove useful in this situation. switching signals such as clocks should be shielded with digital TRANSIENT VOLTAGE PROTECTION ground to avoid radiating noise to other parts of the board and The AD5410/AD5420 contain ESD protection diodes that prevent should never be run near the reference inputs. A ground line damage from normal handling. The industrial control environ- routed between the SDIN and SCLK lines helps reduce crosstalk ment can, however, subject I/O circuits to much higher transients. between them (not required on a multilayer board that has a To protect the AD5410/AD5420 from excessively high voltage separate ground plane, but separating the lines helps). It is transients, external power diodes and a surge current limiting essential to minimize noise on the REFIN line because noise resistor may be required, as shown in Figure 50. The constraint can couple through to the DAC output. on the resistor value is that during normal operation, the output Avoid crossover of digital and analog signals. Traces on level at IOUT must remain within its voltage compliance limit of opposite sides of the board should run at right angles to each AVDD − 2.5 V, and the two protection diodes and resistor must other. This reduces the effects of feedthrough on the board. have appropriate power ratings. Further protection can be pro- A microstrip technique is by far the best method but is not vided with transient voltage suppressors (TVS), or transorbs. always possible with a double-sided board. In this technique, These are available as both unidirectional suppressors (protect the component side of the board is dedicated to the ground against positive high voltage transients) and bidirectional plane, and signal traces are placed on the solder side. suppressors (protect against both positive and negative high GALVANICALLY ISOLATED INTERFACE voltage transients) and are available in a wide range of standoff and breakdown voltage ratings. It is recommended that all field In many process control applications, it is necessary to provide connected nodes be protected. an isolation barrier between the controller and the unit being AV controlled to protect and isolate the controlling circuitry from DD any hazardous common-mode voltages that may occur. The iCoupler® family of products from Analog Devices, Inc., AV DD provides voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5410/AD5420 is ideal for isolated interfaces R AD5410/ P I OUT AD5420 because the number of interface lines is kept to a minimum. Figure 51 shows a 4-channel isolated interface to the AD5410/ R L GND AD5420 using an ADuM1400. For further information, visit www.analog.com/icouplers. Figure 50. Output Transient Voltage Protection CONTROLLER ADuM1400* LAYOUT GUIDELINES SERIAL V V In any circuit where accuracy is important, careful consideration IA OA TO CLOCK ENCODE DECODE SCLK of the power supply and ground return layout helps to ensure OUT the rated performance. The printed circuit board (PCB) on SERIAL V V IB OB TO DATA ENCODE DECODE which the AD5410/AD5420 are mounted should be designed so SDIN OUT that the analog and digital sections are separated and confined V V IC OC to certain areas of the board. If the AD5410/AD5420 are in a SYNC TO ENCODE DECODE OUT LATCH system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. V V ID OD TO CONTROL ENCODE DECODE CLEAR The star ground point should be established as close as possible OUT to the device. *ADDITIONAL PINS OMITTED FOR CLARITY. The AD5410/AD5420 should have ample supply bypassing of Figure 51. Isolated Interface 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF Rev. D | Page 25 of 28 07027-039 07027-040 AD5410/AD5420 Data Sheet 2.5 MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5410/AD5420 is via a serial LFCSP 2.0 bus that uses a protocol compatible with microcontrollers and DSP processors. The communication channel is a 3-wire (mini- mum) interface consisting of a clock signal, a data signal, and a 1.5 TSSOP latch signal. The AD5410/AD5420 require a 24-bit data-word with data valid on the rising edge of SCLK. 1.0 For all interfaces, the DAC output update is initiated on the rising edge of LATCH. The contents of the registers can be read 0.5 using the readback function. THERMAL AND SUPPLY CONSIDERATIONS 0 40 45 50 55 60 65 70 75 80 85 The AD5410/AD5420 are designed to operate at a maximum AMBIENT TEMPERATURE (°C) junction temperature of 125°C. It is important that the device Figure 52. Maximum Power Dissipation vs. Ambient Temperature not be operated under conditions that cause the junction tempera- 65 ture to exceed this value. Excessive junction temperature can LFCSP occur if the AD5410/AD5420 are operated from the maximum 60 AV , while driving the maximum current (24 mA) directly to DD 55 ground. In this case, the ambient temperature should be controlled 50 or AVDD should be reduced. At the maximum ambient temperature of 85°C, the 24-lead 45 TSSOP can dissipate 950 mW, and the 40-Lead LFCSP can TSSOP 40 dissipate 1.42 W. 35 To ensure that the junction temperature does not exceed 125°C while driving the maximum current of 24 mA directly into 30 ground (also adding an on-chip current of 4 mA), AV should DD 25 be reduced from the maximum rating to ensure that the 25 35 45 55 65 75 85 AMBIENT TEMPERATURE (°C) package is not required to dissipate more power than previously Figure 53. Maximum Supply Voltage vs. Ambient Temperature stated (see Table 21, Figure 52, and Figure 53). Table 21. Thermal and Supply Considerations Consideration TSSOP LFCSP Maximum Allowed Power T max− T 125− 85 T max− T 125− 85 J A J A = = 950 mW = = 1.42 W Dissipation When Operating at Θ 42 Θ 28 an Ambient Temperature of 85°C JA JA Maximum Allowed Ambient Temperature When Operating T max− P ×Θ = 125−(40× 0.028)× 42= 78°C T max − P ×Θ = 125 −(60× 0.028)× 28= 78°C J D JA J D JA from a Supply of 40 V/60 V and Driving 24 mA Directly to Ground Maximum Allowed Supply Voltage When Operating at an T max− T 125− 85 T max− T 125− 85 J A J A = = 34 V = = 51 V Ambient Temperature of 85°C AI ×Θ 0.028× 42 AI ×Θ 0.028× 28 and Driving 24 mA Directly to DD JA DD JA Ground Rev. D | Page 26 of 28 POWER DISSIPATION (W) SUPPLY VOLTAGE (V) 07027-054 07027-055 Data Sheet AD5410/AD5420 supply connections. A 24 V TVS is placed on the I connection, OUT INDUSTRIAL, HART COMPATIBLE ANALOG and a 36 V TVS is placed on the field supply input. For added OUTPUT APPLICATION protection, clamping diodes are connected from the I pin to the OUT Many industrial control applications have requirements for AVDD and GND power supply pins. The recommended external accurately controlled current output signals, and the AD5410/ band-pass filter for the AD5700 HART modem includes a 150 kΩ AD5420 are ideal for such applications. Figure 54 shows the resistor, which limits current to a sufficiently low level to adhere AD5410/AD5420 in a circuit design for an output module spe- to intrinsic safety requirements. In this case, the input has higher cifically for use in an industrial control application. The design transient voltage protection and should, therefore, not require provides for a HART-enabled current output, with the HART additional protection circuitry, even in the most demanding of capability provided by the AD5700/AD5700-1 HART modem, the industrial environments. industry’s lowest power and smallest footprint HART-compliant IC Isolation between the AD5410/AD5420 and the backplane modem. For additional space-savings, the AD5700-1 offers a 0.5% circuitry is provided with the ADuM1400 and ADuM1200 precision internal oscillator. The HART_OUT signal from the iCoupler digital isolators; further information on iCoupler AD5700 is attenuated and ac-coupled into the CAP2 pin of the products is available at www.analog.com/icouplers. The internally AD5420. Further information on this configuration can be found generated digital power supply of the AD5410/ AD5420 powers in Application Note AN-1065.An alternative method of coupling the field side of the digital isolators, removing the need to generate the HART signal into the RSET pin (only applicable of the external a digital power supply on the field side of the isolation barrier. RSET is used), is available in Circuit Note CN-0270. Use of The AD5410/AD5420 digital supply out-put supplies up to 5 mA, either configuration results in the AD5700 HART modem output which is more than enough to supply the 2.8 mA requirement of modulating the 4 mA to 20 mA analog current without affecting the ADuM1400 and ADuM1200 operating at a logic signal the dc level of the current. This circuit adheres to the HART frequency of up to 1 MHz. To reduce the number of isolators physical layer specifications as defined by the HART required, nonessential signals such as CLEAR can be connected Communication Foundation. FAULT to GND and , and SDO can be left unconnected, reducing The module is powered from a field supply of 24 V. This supplies the isolation requirements to just three signals. Doing so, AV directly. For transient overvoltage protection, transient DD however, disables the fault alert features of the part. voltage suppressors (TVS) are placed on both the I and field OUT 24V FIELD SUPPLY 10µF SMAJ36CA 36V FIELD 0.1µF GROUND BACKPLANE SUPPLY 0.1µF 0.1µF C3 ADuM1400 10kΩ V V DD1 DD2 MICROCONTROLLER V DV DV CAP1 AV NC CC DD E2 CC V SELECT V IA OA DIGITAL V V IB OB OUTPUTS AD5410/AD5420 V V IC OC V V OD ID CLEAR I OUT GND GND 1 2 18Ω LATCH GND GND I OUT 1 2 SCLK SDIN V V DD2 DD1 24V V V UART DIGITAL OA IA FAULT SMAJ24CA V V INTERFACE INTPUTS OB IB SDO GND GND 2 1 CAP2 GND REFOUT REFIN ADuM1200 C1 C2 0.1µF 2.2nF 22nF 0.1µF AV DD ADuM1402 V CC V V DD1 DD2 V HART_OUT V E2 E1 TXD V V IA OA V V RTS IB OB V V RXD OC IC V V ID OC CD GND GND 1 2 AD5700/AD5700-1 GND GND 2 1 REF 1µF 1.2MΩ 150kΩ ADC_IP AGND DGND 300pF 1.2MΩ 150pF Figure 54. AD5410/AD5420 in an Industrial Analog Output Application Rev. D | Page 27 of 28 BACKPLANE INTERFACE + 07027-048 OUTLINE DIMENSIONS 5.02 7.90 5.00 7.80 4.95 7.70 24 13 4.50 3.25 EXPOSED 4.40 PAD 3.20 (Pins Up) 4.30 3.15 6.40 BSC 1 12 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 1.05 THE EXPOSED PAD, REFER TO 1.20 MAX THE PIN CONFIGURATION AND 1.00 8° FUNCTION DESCRIPTIONS 0.80 SECTION OF THIS DATA SHEET. 0° 0.20 0.15 0.65 0.30 0.75 SEATING 0.09 0.05 BSC PLANE 0.19 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-ADT Figure 55. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters 6.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 31 40 30 1 PIN 1 0.50 INDICATOR TOP 4.25 BSC 5.75 EXPOSED VIEW 4.10 SQ BSC SQ PAD (BOT TOM VIEW) 3.95 0.50 21 10 0.40 11 20 0.30 0.25 MIN 4.50 12° MAX 0.80 MAX REF 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.02 NOM 1.00 THE PIN CONFIGURATION AND 0.30 0.85 FUNCTION DESCRIPTIONS 0.20 REF COPLANARITY SECTION OF THIS DATA SHEET. 0.23 0.80 SEATING 0.08 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 56. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Resolution TUE Package Description Package Option AD5410AREZ −40°C to +85°C 12 Bits 0.3% Max 24-Lead TSSOP_EP RE-24 AD5410AREZ-REEL7 −40°C to +85°C 12 Bits 0.3% Max 24-Lead TSSOP_EP RE-24 AD5410ACPZ-REEL −40°C to +85°C 12 Bits 0.3% Max 40-Lead LFCSP_VQ CP-40-1 AD5410ACPZ-REEL7 −40°C to +85°C 12 Bits 0.3% Max 40-Lead LFCSP_VQ CP-40-1 AD5420AREZ −40°C to +85°C 16 Bits 0.15% Max 24-Lead TSSOP_EP RE-24 AD5420AREZ-REEL7 −40°C to +85°C 16 Bits 0.15% Max 24-Lead TSSOP_EP RE-24 AD5420ACPZ-REEL −40°C to +85°C 16 Bits 0.15% Max 40-Lead LFCSP_VQ CP-40-1 AD5420ACPZ-REEL7 −40°C to +85°C 16 Bits 0.15% Max 40-Lead LFCSP_VQ CP-40-1 EVAL-AD5420EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07027-0-5/12(D) Rev. D | Page 28 of 28 072108-A 061708-A