ANALOG DEVICES AD5398A

120 mA, Current Sinking, 2 10-Bit, I C DAC AD5398A FEATURES Industrial Heater control Current sink: 120 mA 2 Fan control 2-wire, (I C-compatible) 1.8 V serial interface Cooler (Peltier) control 10-bit resolution Solenoid control Integrated current sense resistor Valve control Power supply: 2.7 V to 5.5 V Linear actuator control Guaranteed monotonic over all codes Light control Power down to: 0.5 μA typical Current loop control Internal reference Ultralow noise preamplifier GENERAL DESCRIPTION Power-down function The AD5398A is a single, 10-bit digital-to-analog converter Power-on reset (DAC) with a current sink output capability of 120 mA. This Available in 3 × 3 array WLCSP package device features an internal reference and operates from a APPLICATIONS single 2.7 V to 5.5 V supply. The DAC is controlled via a 2 Consumer 2-wire (1.8 V, I C®-compatible) serial interface that operates Lens autofocus at clock rates up to 400 kHz. Image stabilization The AD5398A incorporates a power-on reset circuit, which Optical zoom ensures the DAC output powers up to 0 V and remains there Shutters until a valid write takes place. It has a power-down feature Iris/exposure that reduces the current consumption of the device to 0.5 μA Neutral density (ND) filters typically. Lens covers Camera phones The AD5398A is designed for autofocus, image stabilization, Digital still cameras and optical zoom applications in camera phones, digital still Camera modules cameras, and camcorders. The AD5398A is also suitable for Digital video cameras/camcorders many industrial applications, such as controlling temperature, Camera-enabled devices light, and movement without derating, over temperatures Security cameras 2 ranging from −30°C to +85°C. The I C address range for the Web/PC cameras AD5398A is 0x18 to 0x1F inclusive. FUNCTIONAL BLOCK DIAGRAM V DD POWER-ON REFERENCE RESET AD5398A V DD D1 SDA 10-BIT 2 I C SERIAL I CURRENT SINK INTERFACE OUTPUT DAC SCL R SENSE R 3.3Ω PD DGND DGND AGND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07795-001 AD5398A TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions ..............................6 Consumer Applications ................................................................... 1 Typical Performance Characteristics ..............................................7 Industrial Applications .................................................................... 1 Terminology .......................................................................................9 General Description ......................................................................... 1 Theory of Operation ...................................................................... 10 Functional Block Diagram .............................................................. 1 Serial Interface ............................................................................ 10 2 Revision History ............................................................................... 2 I C Bus Operation ...................................................................... 10 Specif ica t ions ..................................................................................... 3 Data Format ................................................................................ 11 AC Specifications .......................................................................... 4 Power Supply Bypassing and Grounding ................................ 12 Timing Specifications .................................................................. 4 Applications Information .............................................................. 13 Absolute Maximum Ratings ............................................................ 5 Outline Dimensions ....................................................................... 14 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 14 REVISION HISTORY 10/08—Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD5398A SPECIFICATIONS VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance (RL) = 25 Ω connected to VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 B Version Parameter Min Typ MaxUnitTest Conditions/Comments DC PERFORMANCE VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V with reduced performance Resolution 10 Bits 117 μA/LSB 2 Relative Accuracy ±1.5 ±4 LSB 2, 3 Differential Nonlinearity ±1 LSB Guaranteed monotonic over all codes 2, 4 Zero Code Error 0 0.5 1 mA All 0s loaded to DAC 2 Offset Error @ Code 16 0.5 mA 2 Gain Error ±0.6 % of FSR at 25°C 2, 4, 5 Offset Error Drift 10 μA/°C 2, 5 Gain Error Drift ±0.2 ±0.5 LSB/°C OUTPUT CHARACTERISTICS 4 Minimum Sink Current 3 mA Maximum Sink Current 120 mA V = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V; DD specified maximum sink current may not be achieved 5 Output Current During PD 80 nA PD = 1 5 Output Compliance 0.6 VDD V Output voltage range over which maximum 120 mA sink current is available 5 Output Compliance 0.48 V V Output voltage range over which 90 mA sink current DD is available 5 Power-Up Time 20 μs To 10% of FS, coming out of power-down mode; VDD = 5 V 5 LOGIC INPUT (PD) Input Current ±1 μA Input Low Voltage, VINL 0.54 V VDD = 2.7 V to 5.5 V Input High Voltage, VINH 1.26 V VDD = 2.7 V to 5.5 V Pin Capacitance 3 pF 5 LOGIC INPUTS (SCL, SDA) Input Low Voltage, VINL −0.3 +0.54 V VDD = 2.7 V to 3.6 V Input High Voltage, VINH 1.26 VDD + 0.3 V VDD = 2.7 V to 3.6 V Input Low Voltage, V −0.3 +0.54 V V = 3.6 V to 5.5 V INL DD Input High Voltage, V 1.4 V + 0.3 V V = 3.6 V to 5.5 V INH DD DD Input Leakage Current, I ±1 μA V = 0 V to V IN IN DD Input Hysteresis, VHYST 0.05 VDD V Digital Input Capacitance, CIN 6 pF 6 Glitch Rejection 50 ns Pulse width of spike suppressed POWER REQUIREMENTS VDD 2.7 5.5 V I (Normal Mode) 0.5 1 mA I specification is valid for all DAC codes; DD DD V = V , V = GND, V = 5.5 V IH DD IL DD 7 I (Power-Down Mode) 0.5 μA V = V , V = GND, V = 3 V DD IH DD IL DD 1 Temperature range for the B version is −30°C to +85°C. 2 See the Terminology section. 3 Linearity is tested using a reduced code range: Code 32 to Code 1023. 4 To achieve near zero output current, use the power-down feature. 5 Guaranteed by design and characterization; not production tested. PD is active high. SDA and SCL pull-up resistors are tied to 1.8 V. 6 Input filtering on both the SCL and SDA inputs suppresses noise spikes that are less than 50 ns. 7 PD is active high. When PD is taken high, the AD5389A enters power-down mode. Rev. 0 | Page 3 of 16 AD5398A AC SPECIFICATIONS VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, RL = 25 Ω connected to VDD, unless otherwise noted. Table 2. 1, 2 B Version Parameter Min Typ Max Unit Test Conditions/Comments Output Current Settling Time 250 μs VDD = 5 V, RL = 25 Ω, LL = 680 μH ¼ scale to ¾ scale change (0x100 to 0x300) Slew Rate 0.3 mA/μs Major Code Change Glitch Impulse 0.15 nA-sec 1 LSB change around major carry 3 Digital Feedthrough 0.06 nA-sec 1 Temperature range for the B version is –30°C to +85°C. 2 Guaranteed by design and characterization; not production tested. 3 See the Terminology section. TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 3. B Version 1 Parameter Unit Description Limit at TMIN, TMAX fSCL 400 kHz max SCL clock frequency t1 2.5 μs min SCL cycle time t2 0.6 μs min tHIGH, SCL high time t 1.3 μs min t , SCL low time 3 LOW t 0.6 μs min t , start/repeated start condition hold time 4 HD, STA t 100 ns min t , data setup time 5 SU, DAT 2 t6 0.9 μs max tHD, DAT, data hold time 0 μs min t7 0.6 μs min tSU, STA, setup time for repeated start t 0.6 μs min t , stop condition setup time 8 SU, STO t 1.3 μs min t , bus free time between a stop condition and a start condition 9 BUF t 300 ns max t , rise time of both SCL and SDA when receiving 10 R 0 ns min Can be CMOS driven t11 250 ns max tF, fall time of SDA when receiving 300 ns max t , fall time of both SCL and SDA when transmitting F 3 20 + 0.1 C ns min b C 400 pF max Capacitive load for each bus line b 1 Guaranteed by design and characterization; not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) to bridge the undefined region of the SCL falling edge. 3 Cb is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD. Timing Diagram SDA t t t 3 4 9 t t 10 11 SCL t t t t t t 2 t 7 1 8 4 6 5 START REPEATED STOP CONDITION START CONDITION CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram Rev. 0 | Page 4 of 16 07795-002 AD5398A ABSOLUTE MAXIMUM RATINGS 1 TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any other conditions above those listed in the operational sections Parameter Rating of this specification is not implied. Exposure to absolute V to AGND −0.3 V to +7 V DD maximum rating conditions for extended periods may affect V to DGND −0.3 V to V + 0.3 V DD DD device reliability. Only one absolute maximum rating may be AGND to DGND −0.3 V to +0.3 V applied at any one time. SCL, SDA to DGND −0.3 V to VDD + 0.3 V PD to DGND −0.3 V to VDD + 0.3 V ESD CAUTION I to AGND −0.3 V to V + 0.3 V SINK DD Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C 2 θ Thermal Impedance JA Mounted on 2-Layer Board 84°C/W Mounted on 4-Layer Board 48°C/W Lead Temperature, Soldering 3 Maximum Peak Reflow Temperature 260°C (±5°C) 1 Transient currents of up to 100 mA do not cause SCR latch-up. 2 To achieve the optimum θJA, it is recommended that the AD5398A be soldered onto a 4-layer board. 3 As per Jedec J-STD-020C. Rev. 0 | Page 5 of 16 AD5398A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3 2 1 A B C VIEW FROM BALL SIDE Figure 3. 9-Ball WLCSP Pin Configuration Table 5. 9-Ball WLCSP Pin Function Description Pin Number Mnemonic Description A1 ISINK Output Current Sink. A2 NC No Connection. A3 PD Power-Down. Asynchronous power-down signal. B1 AGND Analog Ground Pin. B2 DGND Digital Ground Pin. 2 B3 SDA I C Interface Signal. C1 DGND Digital Ground Pin. C2 VDD Digital Supply Voltage. 2 C3 SCL I C Interface Signal. 1400µm PD 1 I SINK 8 AGND 7 DGND 2 1690µm SDA V 3 DD 6 SCL DGND 4 5 Figure 4. Metallization Photograph Dimensions shown in μm Contact Factory for Latest Dimensions Rev. 0 | Page 6 of 16 07795-021 07795-023 AD5398A TYPICAL PERFORMANCE CHARACTERISTICS 2.0 VERT = 50µs/DIV INL V = 3.8V DD TEMP = 25°C 1.5 1.0 0.5 3 0 HORIZ = 468µA/DIV –0.5 CH3 M50.0ms CODE Figure 5. Typical INL vs. Code Plot Figure 8. Settling Time for a 4-LSB Step (VDD = 3.6 V) 0.6 DNL V = 3.8V DD VERT = 2µA/DIV 4.8µA p-p TEMP = 25°C 0.5 0.4 0.3 0.2 1 0.1 0 –0.1 –0.2 HORIZ = 2s/DIV –0.3 CH1 M2.0s CODE Figure 9. 0.1 Hz to 10 Hz Noise Plot (V = 3.6 V) Figure 6. Typical DNL vs. Code Plot DD 0.14 92.0 I @ +25°C OUT 91.5 0.12 I @ –40°C OUT 91.0 0.10 90.5 I @ +85°C OUT 0.08 90.0 0.06 89.5 0.04 89.0 0.02 88.5 88.0 0 –6 –6 –6 –6 –6 –6 –6 53.5 100.0 150.0 200.0 250.0 300.0 333.1 TIME CODE Figure 10. Sink Current vs. Code vs. Temperature (V = 3.6 V) Figure 7. ¼ to ¾ Scale Settling Time (VDD = 3.6 V) DD Rev. 0 | Page 7 of 16 OUTPUT CURRENT (mA) DNL (LSB) INL (LSB) 0 0 56 56 112 112 168 168 224 224 280 280 336 336 392 392 448 448 504 504 560 560 616 616 672 672 728 728 784 784 840 840 896 896 952 952 1008 1008 1023 1023 07795-006 07795-005 07795-004 I (A) OUT 0 56 112 168 224 280 336 392 448 504 560 616 672 728 784 840 896 952 1008 07795-008 07795-007 1023 07795-009 AD5398A 2000 0.45 V = 3.6V DD 1800 0.40 1600 0.35 1400 0.30 V = 4.5V DD 1200 V = 3.8V DD 0.25 1000 0.20 800 0.15 600 0.10 400 0.05 200 0 0 –40 –30 –20 –10 0 15 25 35 45 55 65 75 85 10 100 1k 10k 100k FREQUENCY (Hz) TEMPERATURE (°C) Figure 14. Zero Code Error vs. Temperature vs. Supply Voltage Figure 11. AC Power Supply Rejection Ratio (VDD = 3.6 V) 3.5 1.5 V = 4.5V DD 3.0 1.0 POSITIVE INL (V = 3.8V) POSITIVE INL (V = 4.5V) DD DD 2.5 0.5 2.0 V = 3.8V DD 1.5 0 POSITIVE INL (V = 3.6V) DD 1.0 –0.5 0.5 NEGATIVE INL (V = 3.6V) DD –1.0 NEGATIVE INL (V = 3.8V) DD 0 –1.5 –0.5 V = 3.6V DD NEGATIVE INL (V = 4.5V) DD –1.0 –2.0 –40 –30 –20 –10 0 15 25 35 45 55 65 75 85 –40 –30 –20 –10 0 15 25 35 45 55 65 75 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 12. INL vs. Temperature vs. Supply Voltage Figure 15. Full-Scale Error vs. Temperature vs. Supply Voltage 1.0 0.8 0.6 POSITIVE DNL (V = 3.6V) DD 0.4 POSITIVE DNL (V = 4.5V) DD 0.2 0 POSITIVE DNL (V = 3.8V) NEGATIVE DNL (V = 3.8V) DD DD –0.2 –0.4 –0.6 NEGATIVE DNL (V = 4.5V) DD NEGATIVE DNL (V = 3.6V) DD –0.8 –1.0 –40 –30 –20 –10 0 15 25 35 45 55 65 75 85 TEMPERATURE (°C) Figure 13. DNL vs. Temperature vs. Supply Voltage Rev. 0 | Page 8 of 16 DNL (LSB) INL (LSB) ACPSRR (µA/V) 07795-012 07795-011 07795-010 FS ERROR (mA) ZERO CODE ERROR (mA) 07795-096 07795-013 AD5398A TERMINOLOGY Gain Error Drift Relative Accuracy For the DAC, relative accuracy or integral nonlinearity is a This is a measurement of the change in gain error with changes measurement of the maximum deviation, in LSB, from a in temperature. It is expressed in LSB/°C. straight line passing through the endpoints of the DAC transfer Digital-to-Analog Glitch Impulse function. A typical INL vs. code plot is shown in Figure 5. Digital-to-analog glitch impulse is the impulse injected into the Differential Nonlinearity (DNL) analog output when the input code in the DAC register changes Differential nonlinearity is the difference between the measured state. It is normally specified as the area of the glitch in nA-sec change and the ideal 1 LSB change between any two adjacent and is measured when the digital input code is changed by 1 LSB at the major carry transition. codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by Digital Feedthrough design. A typical DNL vs. code plot is shown in Figure 6. Digital feedthrough is a measurement of the impulse injected Zero-Code Error into the analog output of the DAC from the digital inputs of Zero-code error is a measurement of the output error when the DAC, however is measured when the DAC output is not zero code (0x0000) is loaded to the DAC register. Ideally, the updated. It is specified in nA-sec and measured with a full- output is 0 mA. The zero-code error is always positive in the scale code change on the data bus, that is, from all 0s to all 1s and vice versa. AD5398A because the output of the DAC cannot go below 0 mA. This is due to a combination of the offset errors in the Offset Error DAC and output amplifier. Zero-code error is expressed in mA. Offset error is a measurement of the difference between ISINK Gain Error (actual) and IOUT (ideal) in the linear region of the transfer This is a measurement of the span error of the DAC. It is the function, expressed in mA. Offset error is measured on the deviation in slope of the DAC transfer characteristic from the AD5398A with Code 16 loaded into the DAC register. ideal, expressed as a percent of the full-scale range. Offset Error Drift This is a measurement of the change in offset error with a change in temperature. It is expressed in μV/°C. Rev. 0 | Page 9 of 16 AD5398A THEORY OF OPERATION V DD The AD5398A is a fully integrated 10-bit DAC with 120 mA output current sink capability and is intended for driving voice R R P P SDA coil actuators in applications such as lens autofocus, image sta- SCL bilization, and optical zoom. The circuit diagram is shown in Figure 16. A 10-bit current output DAC coupled with Resistor R 2 2 2 I C MASTER I C SLAVE I C SLAVE generates the voltage that drives the noninverting input of the AD5398A DEVICE DEVICE DEVICE operational amplifier. This voltage also appears across the R SENSE 2 Figure 17. Typical I C Bus resistor and generates the sink current required to drive the voice coil. When the bus is idle, SCL and SDA are both high. The master device initiates a serial bus operation by generating a start The R and RSENSE resistors are interleaved and matched. There- condition, which is defined as a high-to-low transition on the fore, the temperature coefficient and any nonlinearities over SDA line while SCL is high. The slave device connected to the temperature are matched and the output drift over temperature bus responds to the start condition and shifts in the next eight is minimized. Diode D1 is an output protection diode. data bits under the control of the serial clock. These eight data V bits consist of a 7-bit address, plus a read/write bit, which is 0 if BAT data is to be written to a device, and 1 if data is to be read from a VOICE COIL 2 V device. Each slave device on an I C bus must have a unique ACTUATOR DD address. The address of the AD5398A is 0001100; however, POWER-ON 0001101, 0001110, and 0001111 address the part because the REFERENCE RESET AD5398A last two bits are unused/don’t care (see Figure 18 and Figure 19). V DD Because the address plus R/W bit always equals eight bits of data, D1 SDA 10-BIT 2 I C SERIAL another way of looking at it is that the write address of the CURRENT INTERFACE I OUTPUT DAC SINK SCL AD5398A is 0001 1000 (0x18) and the read address is 0001 1001 (0x19). Again, Bit 6 and Bit 7 of the address are unused, and, R SENSE therefore, the write addresses can also be 0x1A, 0x1C, and 0x1E, R 3.3Ω PD and the read address can be 0x1B, 0x1D, and 0x1F (see Figure 18 and Figure 19). DGND DGND AGND At the end of the address data, after the R/W bit, the slave Figure 16. Circuit Diagram Showing Connection to Voice Coil device that recognizes its own address responds by generating an acknowledge (ACK) condition. This is defined as the slave SERIAL INTERFACE device pulling SDA low while SCL is low before the ninth clock 2 The AD5398A is controlled using the industry-standard I C pulse, and keeping it low during the ninth clock pulse. Upon 2-wire serial protocol. Data can be written to or read from receiving an ACK, the master device can clock data into the the DAC at data rates up to 400 kHz. After a read operation, AD5398A in a write operation, or it can clock it out in a read the contents of the input register are reset to all zeros. operation. Data must change either during the low period of the clock, because SDA transitions during the high period define a 2 I C BUS OPERATION start condition as described previously, or during a stop condi- 2 An I C bus operates with one or more master devices that tion as described in the Data Format section. generate the serial clock (SCL), and read/write data on the serial 2 I C data is divided into blocks of eight bits, and the slave data line (SDA) to/from slave devices such as the AD5398A. On 2 generates an ACK at the end of each block. The AD5398A all devices on an I C bus, the SCL pin is connected to the SCL 2 requires 10 bits of data; two data-words must be written to it line and the SDA pin is connected to the SDA line. I C devices when a write operation occurs, or read from it when a read can only pull the bus lines low; pulling high is achieved by the operation occurs. At the end of a read or write operation, the pull-up resistors, RP. The value of RP depends on the data rate, 2 AD5398A acknowledges the second data byte. The master bus capacitance, and the maximum load current that the I C generates a stop condition, defined as a low-to-high transition device can sink (3 mA for a standard device). on SDA while SCL is high, to end the transaction. Rev. 0 | Page 10 of 16 07795-015 07795-016 AD5398A DATA FORMAT Data is written to the AD5398A high byte first, MSB first, and is The data format is shown in Table 6. When referring to this table, shifted into the 16-bit input register. After all data is shifted in, note that Bit 14 is unused; Bit 13 to Bit 4 correspond to the DAC data from the input register is transferred to the DAC register. data bits, D9 to D0; and Bit 3 to Bit 0 are unused. Because the DAC requires only 10 bits of data, not all bits of the During a read operation, data is read in the same bit order. input register data are used. The MSB is reserved for an active- high, software-controlled, power-down function. 1191 9 SCL 00 01 1 X X R/W PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X SDA START BY ACK BY ACK BY ACK BY STOP BY MASTER AD5398A AD5398A AD5398A MASTER FRAME 1 FRAME 2 FRAME 3 SERIAL BUS MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE Figure 18. Write Operation 1191 9 SCL 00 01 1 X XR/W PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X SDA START BY ACK BY ACK BY ACK BY STOP BY MASTER AD5398A AD5398A AD5398A MASTER FRAME 1 FRAME 2 FRAME 3 SERIAL BUS MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE Figure 19. Read Operation Table 6. Data Format High Byte Low Byte Serial Data- Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Serial Data Bits SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Input Register R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 1 Function PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 1 PD = soft power-down; X = unused/don’t care; and D7 to D0 = DAC data. Rev. 0 | Page 11 of 16 07795-018 07795-017 AD5398A POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in an application, it is beneficial When the maximum sink current is flowing through the motor, to consider power supply and ground return layout on the PCB. the resistive elements, RT and RG, may have an impact on the The PCB for the AD5398A should have separate analog and voltage headroom of Q1 and may, in turn, limit the maximum digital power supply sections. Where shared AGND and DGND value of R because of voltage compliance. C is necessary, the connection of grounds should be made at only For example, if one point, as close as possible to the AD5398A. V = 3.6 V BAT Pay special attention to the layout of the AGND return path RG = 0.5 Ω and track it between the voice coil motor and ISINK to minimize any series resistance. Figure 20 shows the output current sink RT = 0.5 Ω of the AD5398A and illustrates the importance of reducing the ISINK = 120 mA effective series impedance of AGND, and the track resistance VDROP = 600 mV (the compliance voltage) between the motor and I . The voice coil is modelled as SINK Inductor L and Resistor R . The current through the voice C C then the largest value of resistance of the voice coil, R , is C , coil is effectively a dc current that results in a voltage drop, VC V −[V + (I ×R )+ (I ×R )] BAT DROP SINK T SINK G when the AD5398A is sinking current; the effect of any series R = = C I inductance is minimal. The maximum voltage drop allowed SINK across RSENSE is 400 mV, and the minimum drain to source 3.6 V−[600 mV+ 2×(120 mA× 0.5 Ω)] voltage of Q1 is 200 mV. This means that the AD5398A output = 24 Ω 120 mA has a compliance voltage of 600 mV. If V falls below DROP 600 mV, the output transistor, Q1, can no longer operate For this reason, it is important to minimize any series impedance properly and I might not be maintained as a constant. SINK on both the ground return path and interconnect between the V BAT AD5398A and the motor. VOICE The power supply of the AD5398A should be decoupled with COIL L C ACTUATOR 0.1 μF and 10 μF capacitors. These capacitors should be kept as V C R C physically close as possible, with the 0.1 μF capacitor serving as V DD TRACE a local bypass capacitor, and therefore should be located as close RESISTANCE R D1 T V as possible to the V pin. The 10 μF capacitor should be a T DD I tantalum bead-type; the 0.1 μF capacitor should be a ceramic SINK Q1 type with a low effective series resistance and effective series inductance. The 0.1 μF capacitor provides a low impedance path R SENSE V 3.3Ω DROP to ground for high transient currents. The power supply line should have as large a trace as possible to AGND provide a low impedance path and reduce glitch effects on the GROUND R G RESISTANCE supply line. Clocks and other fast switching digital signals V G GROUND L should be shielded from other parts of the board by digital G INDUCTANCE ground. Avoid crossover of digital and analog signals if possible. Figure 20. Effect of PCB Trace Resistance and Inductance When traces cross on opposite sides of the board, ensure that As the current increases through the voice coil, VC increases they run at right angles to each other to reduce feedthrough and V decreases and eventually approaches the minimum DROP effects through the board. The best board layout technique is to specified compliance voltage of 600 mV. The ground return use a multilayer board with ground and power planes, where path is modelled by the R and L components. The track resis- G G the component side of the board is dedicated to the ground tance between the voice coil and the AD5398A is modelled as plane only and the signal traces are placed on the solder side. RT. The inductive effects of LG influence RSENSE and RC equally, However, this is not always possible with a 2-layer board. and because the current is maintained as a constant, it is not as critical as the purely resistive component of the ground return path. Rev. 0 | Page 12 of 16 07795-019 AD5398 APPLICATIONS INFORMATION The AD5398A is designed to drive both spring preloaded 0.5 and nonspring linear motors used in applications such as lens autofocus, image stabilization, or optical zoom. The operating 0.4 principle of the spring-preloaded motor is that the lens position is controlled by the balancing of a voice coil and a spring. Figure 21 shows the transfer curve of a typical spring preloaded linear 0.3 motor for autofocus. The key points of this transfer function are displacement or stroke, which is the actual distance the lens 0.2 moves in millimeters (mm), and the current through the motor START in milliamps (mA). CURRENT 0.1 A start current is associated with spring-preloaded linear motors, 0 which is effectively a threshold current that must be exceeded for 0 10 20 30 40 50 60 70 80 90 100 110 120 any displacement in the lens to occur. The start current is usually SINK CURRENT (mA) 20 mA or greater; the rated stroke or displacement is usually Figure 21. Spring Preloaded Voice Coil Stroke vs. Sink Current 0.25 mm to 0.4 mm; and the slope of the transfer curve is approxi- mately 10 μm/mA or less. The AD5398A is designed to sink up to 120 mA, which is more than adequate for available commercial linear motors or voice coils. Another factor that makes the AD5398A the ideal solution for these applications is the monotonicity of the device, which ensures that lens positioning is repeatable for the applica- tion of a given digital word. Figure 22 shows a typical application circuit for the AD5398A. V V DD CC + + 0.1µF 10µF 10µF 0.1µF V DD POWER-DOWN VOICE POWER-ON RESET REFERENCE COIL RESET AD5398A ACTUATOR V PD DD V DD R R P P SDA SDA D1 10-BIT 2 I C SERIAL CURRENT INTERFACE SCL SCL I OUTPUT DAC SINK 2 2 2 R I C MASTER I C SLAVE I C SLAVE SENSE R DEVICE DEVICE DEVICE 3.3Ω DGND DGND AGND Figure 22. Typical Application Circuit Rev. 0 | Page 13 of 16 STROKE (mm) 07795-022 07795-020 AD5398A OUTLINE DIMENSIONS 0.65 0.59 1.575 0.53 1.515 SEATING 1.455 3 2 1 PLANE A 0.35 BALL 1 0.32 IDENTIFIER 1.750 0.29 1.690 B 1.630 C 0.50 BSC BALL PITCH TOP VIEW 0.28 BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.24 0.20 Figure 23. 9-Ball Wafer Level Chip Scale Package [WLCSP] (CB-9-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding 1 AD5398ABCBZ-REEL7 −30°C to +85°C 9-Ball Wafer Level Chip Scale (WLCSP) CB-9-1 1Z 1 AD5398ABCBZ-REEL −30°C to +85°C 9-Ball Wafer Level Chip Scale (WLCSP) CB-9-1 1Z AD5398A-WAFER −40°C to +85°C Bare Die Wafer 1 EVAL-AD5398AEBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. 0 | Page 14 of 16 091306-B AD5398A NOTES Rev. 0 | Page 15 of 16 AD5398A NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07795-0-10/08(0) Rev. 0 | Page 16 of 16