ANALOG DEVICES AD5384

40-Channel, 3 V/5 V, Single-Supply, Serial, 14-Bit Voltage Output DAC AD5384 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic Channel monitor INL error: ±4 LSB max Simultaneous output update via LDAC On-chip 1.25 V/2.5 V, 10 ppm/°C reference Clear function to user-programmable code Temperature range: –40°C to +85°C Amplifier boost mode to optimize slew rate Rail-to-rail output amplifier User-programmable offset and gain adjust Power-down Toggle mode enables square wave generation Package type: 100-lead CSPBGA (10 mm × 10 mm) Thermal monitor User Interfaces: APPLICATIONS Serial (SPI-®/QSPI-™/MICROWIRE-™/DSP-compatible, Variable optical attenuators (VOA) featuring data readback) Level setting (ATE) 2 I C-®compatible Optical micro-electro-mechanical systems (MEMS) Control systems Instrumentation FUNCTIONAL BLOCK DIAGRAM DVDD (×3) DGND (×4) AVDD (×5) AGND (×5) DAC GND (×5) REFGND REFOUT/REFIN SIGNAL GND (×5) PD AD5384 1.25V/2.5V SYNC/AD 0 REFERENCE DCEN/AD 1 14 14 14 14 INPUT DAC DAC 0 REG 0 REG 0 VOUT0 14 m REG 0 SDO 14 R c REG 0 STATE R DIN/SDA INTERFACE MACHINE SCLK/SCL CONTROL + 14 14 14 14 INPUT DAC LOGIC CONTROL DAC 1 2 SPI/I C REG 1 REG 1 LOGIC VOUT1 14 VOUT2 m REG 1 14 c REG 1 R VOUT3 R VOUT4 14 14 14 14 INPUT DAC VOUT5 DAC 6 REG 6 REG 6 VOUT6 POWER-ON RESET RESET 14 m REG 6 14 BUSY c REG 6 R R CLR 14 14 14 14 INPUT DAC VOUT0……VOUT38 DAC 7 REG 7 REG 7 VOUT7 14 m REG 7 VOUT8 39-TO-1 14 c REG 7 R MUX R ×5 VOUT38 VOUT39/MON_OUT LDAC Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 04652-0-001 AD5384 TABLE OF CONTENTS General Description ......................................................................... 3 Reset Function ............................................................................ 25 Specifications..................................................................................... 4 Asynchronous Clear Function.................................................. 25 AD5384-5 Specifications ............................................................. 4 BUSY and LDAC Functions...................................................... 25 AC Characteristics........................................................................ 6 Power-On Reset.......................................................................... 25 AD5384-3 Specifications ............................................................. 7 Power-Down ............................................................................... 25 AC Characteristics........................................................................ 9 Interfaces.......................................................................................... 26 Timing Characteristics................................................................... 10 DSP-, SPI-, Microwire-Compatible Serial Interfaces ............ 26 2 Serial Interface ............................................................................ 10 I C Serial Interface ..................................................................... 28 2 I C Serial Interface...................................................................... 12 Microprocessor Interfacing....................................................... 31 Absolute Maximum Ratings.......................................................... 13 Application Information................................................................ 32 Pin Configuration and Function Descriptions........................... 14 Power Supply Decoupling ......................................................... 32 Terminology .................................................................................... 17 Monitor Function....................................................................... 32 Typical Performance Characteristics ........................................... 18 Toggle Mode Function............................................................... 32 Functional Description .................................................................. 21 Thermal Monitor Function....................................................... 33 DAC Architecture—General..................................................... 21 AD5384 in a MEMS-Based Optical Switch ............................ 33 Data Decoding ............................................................................ 21 Optical Attenuators.................................................................... 34 On-Chip Special Function Registers (SFR) ............................ 22 Outline Dimensions ....................................................................... 35 SFR Commands .......................................................................... 22 Ordering Guide .......................................................................... 35 Hardware Functions....................................................................... 25 REVISION HISTORY 10/04—Changed from Rev. 0 to Rev. A Changes to Table 19........................................................................ 24 Changes to Ordering Guide .......................................................... 35 7/04—Revision 0: Initial Version Rev. A | Page 2 of 36 AD5384 GENERAL DESCRIPTION DSP interface standards with interface speeds in excess of The AD5384 is a complete single-supply, 40-channel, 14-bit 2 30 MHz and an I C-compatible interface supporting 400 kHz DAC available in a 100-lead CSPBGA package. All 40 channels data transfer rate. An input register followed by a DAC register have an on-chip output amplifier with rail-to-rail operation. provides double buffering, allowing the DAC outputs to be The AD5384 includes an internal 1.25 V/2.5 V, 10 ppm/°C updated independently or simultaneously. using the LDAC reference, an on-chip channel monitor function that multiplexes input. Each channel has a programmable gain and offset adjust the analog outputs to a common MON_OUT pin for external register letting the user fully calibrate any DAC channel. Power monitoring, and an output amplifier boost mode that allows the consumption is typically 0.25 mA/channel with boost mode off. amplifier slew rate to be optimized. The AD5384 contains a serial interface compatible with SPI, QSPI, MICROWIRE, and Table 1. Complete Family of High Channel Count, Low Voltage, Single-Supply DACs in Portfolio Model Resolution AVDD Range Output Channels Linearity Error (LSB) Package Description Package Option AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100 AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100 AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100 AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100 AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100 AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100 AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100 AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100 AD5383BST-5 12 Bits 4.5 V to 5.5 V 32 ±1 100-Lead LQFP ST-100 AD5383BST-3 12 Bits 2.7 V to 3.6 V 32 ±1 100-Lead LQFP ST-100 AD5390BST-5 14 Bits 4.5 V to 5.5 V 16 ±3 52-Lead LQFP ST-52 AD5390BCP-5 14 Bits 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP CP-64 AD5390BST-3 14 Bits 2.7 V to 3.6 V 16 ±4 52-Lead LQFP ST-52 AD5390BCP-3 14 Bits 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP CP-64 AD5391BST-5 12 Bits 4.5 V to 5.5 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-5 12 Bits 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP CP-64 AD5391BST-3 12 Bits 2.7 V to 3.6 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-3 12 Bits 2.7 V to 3.6 V 16 ±1 64-Lead LFCSP CP-64 AD5392BST-5 14 Bits 4.5 V to 5.5 V 8 ±3 52-Lead LQFP ST-52 AD5392BCP-5 14 Bits 4.5 V to 5.5 V 8 ±3 64-Lead LFCSP CP-64 AD5392BST-3 14 Bits 2.7 V to 3.6 V 8 ±4 52-Lead LQFP ST-52 AD5392BCP-3 14 Bits 2.7 V to 3.6 V 8 ±4 64-Lead LFCSP CP-64 Table 2. 40-Channel, Bipolar Voltage Output DAC Model Resolution Analog Supplies Output Channels Linearity Error (LSB) Package Package Option AD5379ABC 14 Bits ±11.4 V to ±16.5 V 40 ±3 108-Lead CSPBGA BC-108 Rev. A | Page 3 of 36 AD5384 SPECIFICATIONS AD5384-5 SPECIFICATIONS AV = 4.5 V to 5.5 V; DV = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications T to T , unless DD DD MIN MAX otherwise noted. Table 3. 1 Parameter AD5384-5 Unit Test Conditions/Comments ACCURACY Resolution 14 Bits 2 Relative Accuracy (INL) ±4 LSB max ±1 LSB typical Differential Nonlinearity (DNL) –1/+2 LSB max Guaranteed monotonic by design over temperature Zero-Scale Error 4 mV max Offset Error ±4 mV max Measured at code 32 in the linear region Offset Error TC ±5 µV/°C typ Gain Error ±0.024 % FSR max At 25°C ±0.06 % FSR max T to T MIN MAX 3 Gain Temperature Coefficient 2 ppm FSR/°C typ 3 DC Crosstalk 0.5 LSB max REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 2.5 V ±1% for specified performance, AVDD = 2 × REFIN + 50 mV DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±1 µA max Typically ±30 nA Reference Range 1 to V /2 V min/max DD 4 Reference Output Enabled via CR10 in the AD5384 control register, CR12, selects the output voltage. Output Voltage 2.495/2.505 V min/max At ambient; CR12 = 1; optimized for 2.5 V operation 1.22/1.28 V min/max CR12 = 0 Reference TC ±10 ppm/°C max Temperature range: +25°C to +85°C ±15 ppm/°C max Temperature range: −40°C to +85°C 3 OUTPUT CHARACTERISTICS 2 Output Voltage Range 0/AV V min/max DD Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability RL = ∞ 200 pF max R = 5 kΩ 1000 pF max L DC Output Impedance 0.5 Ω max MONITOR PIN Output Impedance 500 Ω typ Three-State Leakage Current 100 nA typ 3 LOGIC INPUTS (EXCEPT SDA/SCL) DV = 2.7 V to 5.5 V DD V , Input High Voltage 2 V min IH V , Input Low Voltage 0.8 V max IL Input Current ±10 µA max Total for all pins. TA = TMIN to TMAX Pin Capacitance 10 pF max LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage 0.7 DVDD V min SMBus-compatible at DVDD < 3.6 V VIL, Input Low Voltage 0.3 DVDD V max SMBus-compatible at DVDD < 3.6 V I , Input Leakage Current ±1 µA max IN V , Input Hysteresis 0.05 DV V min HYST DD C , Input Capacitance 8 pF typ IN Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns Rev. A | Page 4 of 36 AD5384 1 Parameter AD5384-5 Unit Test Conditions/Comments 3 LOGIC OUTPUTS (BUSY, SDO) VOL, Output Low Voltage 0.4 V max DVDD = 5 V ± 10%, sinking 200 µA VOH, Output High Voltage DVDD – 1 V min DVDD = 5 V ± 10%, sourcing 200 µA V , Output Low Voltage 0.4 V max DV = 2.7 V to 3.6 V, sinking 200 µA OL DD V , Output High Voltage DV – 0.5 V min DV = 2.7 V to 3.6 V, sourcing 200 µA OH DD DD High Impedance Leakage Current ±1 µA max SDO only High Impedance Output Capacitance 5 pF typ SDO only 3 LOGIC OUTPUT (SDA) VOL, Output Low Voltage 0.4 V max ISINK = 3 mA 0.6 V max ISINK = 6 mA Three-State Leakage Current ±1 µA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 4.5/5.5 V min/max DV 2.7/5.5 V min/max DD 3 Power Supply Sensitivity ∆Midscale/∆ΑV –85 dB typ DD AIDD 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ 0.475 mA/channel max Outputs unloaded, boost on; 0.32 5mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND AI (Power-Down) 2 µA max Typically 200 nA DD DI (Power-Down) 20 µA max Typically 3 µA DD Power Dissipation 80 mW max Outputs unloaded, boost off, AVDD = DVDD = 5 V 1 AD5384-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. 2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5384-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5384 control register; operating the AD5384-5 with a 1.25 V reference will lead to degraded accuracy specifications. Rev. A | Page 5 of 36 AD5384 1 AC CHARACTERISTICS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V. Table 4. Parameter AD5384-5 Unit Test Conditions/Comments DYNAMIC PERFORMANCE Boost mode off, CR11 = 0 Output Voltage Settling Time 1/4 scale to 3/4 scale change settling to ±1 LSB 8 µs typ 10 µs max 2 Slew Rate 2 V/µs typ Boost mode off, CR11 = 0 3 V/µs typ Boost mode on, CR11 = 1 Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ Channel-to-Channel Isolation 100 dB typ See the Terminology section DAC-to-DAC Crosstalk 1 nV-s typ See the Terminology section Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC 40 µV p-p typ Internal reference, midscale loaded to DAC Output Noise Spectral Density @ 1 kHz 150 nV/√Hz typ @ 10 kHz 100 nV/√Hz typ 1 Guaranteed by design and characterization, not production tested. 2 The slew rate can be programmed via the current boost control bit (CR11) in the AD5384 control register. Rev. A | Page 6 of 36 AD5384 AD5384-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. 1 Parameter AD5384-3 Unit Test Conditions/Comments ACCURACY Resolution 14 Bits 2 Relative Accuracy ±4 LSB max Differential Nonlinearity –1/+2 LSB max Guaranteed monotonic over temperature Zero-Scale Error 4 mV max Offset Error ±4 mV max Measured at Code 64 in the linear region Offset Error TC ±5 µV/°C typ Gain Error ±0.024 % FSR max At 25°C ±0.1 % FSR max T to T MIN MAX 3 Gain Temperature Coefficient 2 ppm FSR/°C typ 3 DC Crosstalk 0.5 LSB max REFERENCE INPUT/OUTPUT 3 Reference Input Reference Input Voltage 1.25 V ±1% for specified performance DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±1 µA max Typically ±30 nA Reference Range 1 to AVDD/2 V min/max 4 Reference Output Output Voltage 1.245/1.255 V min/max At ambient; CR12 = 0; optimized for 1.25 V operation 2.47/2.53 V min/max CR12 = 1 Reference TC ±10 ppm/°C max Temperature range: +25°C to +85°C ±15 ppm/°C max Temperature range: −40°C to +85°C 3 OUTPUT CHARACTERISTICS 2 Output Voltage Range 0/AV V min/max DD Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability RL = ∞ 200 pF max RL = 5 kΩ 1000 pF max DC Output Impedance 0.5 Ω max MONITOR PIN Output Impedance 500 Ω typ Three-State Leakage Current 100 nA typ 3 LOGIC INPUTS (EXCEPT SDA/SCL) DVDD = 2.7 V to 3.6 V VIH, Input High Voltage 2 V min V Input Low Voltage 0.8 V max IL, Input Current ±10 µA max Total for all pins; T = T to T A MIN MAX Pin Capacitance 10 pF max LOGIC INPUTS (SDA, SCL ONLY) V , Input High Voltage 0.7 DV V min SMBus-compatible at DV < 3.6 V IH DD DD VIL, Input Low Voltage 0.3 DVDD V max SMBus-compatible at DVDD < 3.6 V IIN, Input Leakage Current ±1 µA max VHYST, Input Hysteresis 0.05 DVDD V min C , Input Capacitance 8 pF typ IN Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns Rev. A | Page 7 of 36 AD5384 1 Parameter AD5384-3 Unit Test Conditions/Comments 3 LOGIC OUTPUTS (BUSY, SDO) VOL, Output Low Voltage 0.4 V max Sinking 200 µA VOH, Output High Voltage DVDD – 0.5 V min Sourcing 200 µA High Impedance Leakage Current ±1 µA max SDO only High Impedance Output Capacitance 5 pF typ SDO only 3 LOGIC OUTPUT (SDA) V , Output Low Voltage 0.4 V max I = 3 mA OL SINK 0.6 V max I = 6 mA SINK Three-State Leakage Current ±1 µA max Three-State Output Capacitance 8 pF typ POWER REQUIREMENTS AVDD 2.7/3.6 V min/max DVDD 2.7/3.6 V min/max 3 Power Supply Sensitivity ∆Midscale/∆ΑV –85 dB typ DD AI 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ DD 0.475 mA/channel max Outputs unloaded, boost on; 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND AIDD (Power-Down) 2 µA max Typically 200 nA DIDD (Power-Down) 20 µA max Typically 1 µA Power Dissipation 48 mW max Outputs unloaded, boost off, AV = DV = 3 V DD DD 1 AD5384-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C. 2 Accuracy guaranteed from V = 10 mV to AVDD – 50 mV. OUT 3 Guaranteed by characterization, not production tested. 4 Default on the AD5384-3 is 1.25 V. Programmable to 2.5 V via CR12 in the AD5384 control register; operating the AD5384-3 with a 2.5 V reference will lead to degraded accuracy specifications and limited input code range. Rev. A | Page 8 of 36 AD5384 1 AC CHARACTERISTICS AVDD = 2.7 V to 3.6 V and 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. Table 6. Parameter AD5384-3 Unit Test Conditions/Comments DYNAMIC PERFORMANCE Boost mode off, CR11 = 0 Output Voltage Settling Time 1/4 scale to 3/4 scale change settling to ±1 LSB 8 µs typ 10 µs max 2 Slew Rate 2 V/µs typ Boost mode off, CR11 = 0 3 V/µs typ Boost mode on, CR11 = 1 Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ Channel-to-Channel Isolation 100 dB typ See the Terminology section DAC-to-DAC Crosstalk 1 nV-s typ See the Terminology section Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC 40 µV p-p typ Internal reference, midscale loaded to DAC Output Noise Spectral Density @ 1 kHz 150 nV/√Hz typ @ 10 kHz 100 nV/√Hz typ 1 Guaranteed by design and characterization, not production tested. 2 The slew rate can be programmed via the current boost control bit (CR11 ) in the AD5384 control register. Rev. A | Page 9 of 36 AD5384 TIMING CHARACTERISTICS SERIAL INTERFACE DV = 2.7 V to 5.5 V; AV = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T to T , DD DD MIN MAX unless otherwise noted. Table 7. 1, 2, 3 Parameter Limit at T , T Unit Description MIN MAX t1 33 ns min SCLK cycle time t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t4 13 ns min SYNC falling edge to SCLK falling edge setup time 4 th t5 13 ns min 24 SCLK falling edge to SYNC falling edge 4 t6 33 ns min Minimum SYNC low time t 10 ns min Minimum SYNC high time 7 t 50 ns min Minimum SYNC high time in readback mode 7A t 5 ns min Data setup time 8 t9 4.5 ns min Data hold time 4 t10 30 ns max 24th SCLK falling edge to BUSY falling edge t11 670 ns max BUSY pulse width low (single channel update) 4 t 20 ns min 24th SCLK falling edge to LDAC falling edge 12 t 20 ns min LDAC pulse width low 13 t 100 ns max 14 BUSY rising edge to DAC output response time t15 0 ns min BUSY rising edge to LDAC falling edge t16 100 ns min LDAC falling edge to DAC output response time t17 8 µs typ DAC output settling time boost mode off t 20 ns min CLR pulse width low 18 t 12 µs max CLR pulse activation time 19 5 t20 20 ns max SCLK rising edge to SDO valid 5 t21 5 ns min SCLK falling edge to SYNC rising edge 5 t22 8 ns min SYNC rising edge to SCLK rising edge t 20 ns min SYNC rising edge to LDAC falling edge 23 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t = t = 5 ns (10% to 90% of DV ), and are timed from a voltage level of 1.2 V. r f DD 3 See Figure 2, Figure 3, Figure 5, and Figure 6. 4 Standalone mode only. 5 Daisy-chain mode only. 200µA I OL V (MIN) OR OH TO OUTPUT PIN V (MAX) C OL L 50pF 200µA I OH Figure 2. Load Circuit for Digital Output Timing Rev. A | Page 10 of 36 04652-0-003 AD5384 t 1 12 24 24 SCLK t 3 t 2 t t 5 4 t 6 SYNC t 7 t t 8 9 DB0 DIN DB23 t 10 t 11 BUSY t t 12 13 t 1 17 LDAC t 14 1 V OUT t 15 t 13 2 LDAC t 17 t 16 2 V OUT t 18 CLR t 19 V OUT 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t 7A SYNC DB23 DB0 DB23 DB0 DIN INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ DB23 DB0 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 4. Serial Interface Timing Diagram (Data Readback Mode) t 1 SCLK 24 48 t t 22 3 t t 7 2 t 21 t SYNC 4 t t 8 9 DIN DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 t 20 SDO DB23 DB0 t UNDEFINED INPUT WORD FOR DAC N 13 t 23 LDAC Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode) Rev. A | Page 11 of 36 04652-0-004 04652-0-005 03731-0-005 AD5384 2 I C SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 8. 1 Parameter Limit at TMIN, TMAX Unit Description FSCL 400 kHz max SCL clock frequency t1 2.5 µs min SCL cycle time t2 0.6 µs min tHIGH, SCL high time t 1.3 µs min t , SCL low time 3 LOW t 0.6 µs min t , start/repeated start condition hold time 4 HD,STA t5 100 ns min tSU,DAT, data setup time 2 t6 0.9 µs max tHD,DAT, data hold time 0 µs min tHD,DAT, data hold time t 0.6 µs min t , setup time for repeated start 7 SU,STA t 0.6 µs m0in t , stop condition setup time 8 SU,STO t 1.3 µs min t , bus free time between a STOP and a START condition 9 BUF t10 300 ns max tR, rise time of SCL and SDA when receiving 0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible) t11 300 ns max tF, fall time of SDA when transmitting 0 ns min t , fall time of SDA when receiving (CMOS-compatible) F 300 ns max t , fall time of SCL and SDA when receiving F 3 20 + 0.1C ns min t , fall time of SCL and SDA when transmitting b F Cb 400 pF max Capacitive load for each bus line 1 See Figure 6. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 3 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD. SDA t t t t t 9 3 10 11 4 SCL t t t t t t 4 6 2 5 1 8 t 7 START REPEATED STOP CONDITION START CONDITION CONDITION 2 Figure 6. I C-Compatible Serial Interface Timing Diagram Rev. A | Page 12 of 36 04652-0-006 AD5384 ABSOLUTE MAXIMUM RATINGS 1 TA = 25°C, unless otherwise noted. Table 9. Parameter Rating Stresses above those listed under Absolute Maximum Ratings AV to AGND –0.3 V to +7 V DD may cause permanent damage to the device. This is a stress DV to DGND –0.3 V to +7 V DD rating only; functional operation of the device at these or any Digital Inputs to DGND –0.3 V to DVDD + 0.3 V other conditions above those listed in the operational sections SDA/SCL to DGND –0.3 V to + 7 V of this specification is not implied. Exposure to absolute Digital Outputs to DGND –0.3 V to DVDD + 0.3 V maximum rating conditions for extended periods may affect REFIN/REFOUT to AGND –0.3 V to AV + 0.3 V DD device reliability. AGND to DGND –0.3 V to +0.3 V VOUTx to AGND –0.3 V to AV + 0.3 V DD Analog Inputs to AGND –0.3 V to AVDD + 0.3 V Operating Temperature Range Commercial (B Version) –40°C to +85°C Storage Temperature Range –65°C to +150°C JunctionTemperature (T max) 150°C J 100-lead CSPBGA Package θJAThermal Impedance 40°C/W Reflow Soldering Peak Temperature 230°C 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 13 of 36 AD5384 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 123456789 101112 A A B B C C D D E E F F TOP VIEW G G H H J J K K L L M M 123456789 101112 Figure 7. 100-Lead CSPBGA Pin Configuration Table 10. Pin Number and Name CSPBGA Ball CSPBGA Ball CSPBGA Ball CSPBGA Ball CSPBGA Ball Number Name Number Name Number Name Number Name Number Name A1 NC B9 RESET E4 DACGND4 H11 VOUT13 L5 AGND5 A2 VOUT24 B10 VOUT22 E9 DACGND3 H12 VOUT14 L6 VOUT6 A3 CLR B11 NC E11 VOUT17 J1 AVDD1 L7 VOUT32 A4 B12 VOUT23 E12 VOUT19 J2 VOUT30 L8 VOUT34 SYNC A5 SCLK C1 VOUT26 F1 REFGND J4 DACGND5 L9 VOUT36 A6 DVDD1 C2 SIGNAL F2 SIGNAL J5 AGND1 L10 VOUT38 GND4 GND1 A7 DGND C11 NC F4 DACGND1 J6 DACGND2 L11 NC A8 PD C12 VOUT21 F9 SIGNAL J7 DACGND2 L12 VOUT9 GND3 A9 DCEN D1 VOUT27 F11 VOUT16 J8 AGND2 M1 NC A10 LDAC D2 SIGNAL F12 VOUT18 J9 SIGNAL M2 VOUT3 GND4 GND2 A11 BUSY D4 DACGND4 G1 VOUT28 J11 VOUT12 M3 VOUT4 A12 NC D5 AGND4 G2 VOUT29 J12 VOUT11 M4 VOUT5 B1 VOUT25 D6 DVDD2 G4 DACGND1 K1 VOUT0 M5 AVDD5 B2 NC D7 DGND G9 SIGNAL GND3 K2 VOUT1 M6 VOUT7 B3 DGND D8 AGND3 G11 VOUT15 K11 NC M7 VOUT33 B4 DIN D9 DACGND3 G12 AVDD2 K12 VOUT10 M8 VOUT35 B5 SDO D11 VOUT20 H1 REFOUT/REFIN L1 VOUT2 M9 VOUT37 B6 DVDD3 D12 AVDD3 H2 VOUT31 L2 NC M10 VOUT39/ MON_OUT B7 DGND E1 AVDD4 H4 DACGND5 L3 SIGNAL M11 VOUT8 GND5 2 B8 SPI/I C E2 SIGNAL H9 SIGNAL L4 SIGNAL M12 NC GND1 GND2 GND5 Rev. A | Page 14 of 36 04652-0-007 AD5384 Table 11. Pin Function Descriptions Mnemonic Function VOUTx Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. SIGNAL GND(1–5) Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together internally and should be connected to the AGND plane as close as possible to the AD5384. DAC GND(1–5) Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DAC. These pins shound be connected to the AGND plane. AGND(1–5) Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane. AVDD(1–5) Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are shorted internally and should be decoupled with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating range for the AD5384-5 is 4.5 V to 5.5 V; operating range for the AD5384-3 is 2.7 V to 3.6 V. DGND Ground for All Digital Circuitry. DVDD Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled with 0.1 µF ceramic and 10 µF tantalum capacitors to DGND. REF GND Ground Reference Point for the Internal Reference. REFOUT/REFIN The AD5384 contains a common REFOUT/REFIN pin. The default for this pin is a reference input. When the internal reference is selected, this pin is the reference output. If the application requires an external reference, it can be applied to this pin. The internal reference is enabled/disabled via the control register. VOUT39/MON_OUT This pin has a dual function. It acts a a buffered output for Channel 39 in default mode. But when the monitor function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 38 to the MON_OUT pin. The MON_OUT pin output impedance typically is 500 Ω and is intended to drive a high input impedance like that exhibited by SAR ADC inputs. SYNC/AD0 Serial Interface Mode. This is the frame synchronization input signal for the serial clocks before the addressed register is updated. 2 I C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address 2 for the device on the I C bus. DCEN/ AD1 Multifunction Pin. In serial interface mode, this pin acts as a daisy-chain enable in SPI mode and as a hardware 2 address pin in I C mode. Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction 2 with SPI/ I C high to enable the SPI serial interface daisy-chain mode. 2 I C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address 2 for this device on the I C bus. SDO Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of SCLK. Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also goes low during power-on reset, and when the BUSY pin is low. During this time, the interface is disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low. LDAC Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC registers, and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes inactive. However, any events on LDAC during power-on reset or on RESET are ignored. CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated with the data in the CLR code register. BUSY is low for a duration of 35 µs while all channels are being updated with the CLR code. RESET Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power- on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence typically takes 270 µs. The falling edge of RESET initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation and the status of the RESET pin is ignored until the next falling edge is detected. Rev. A | Page 15 of 36 AD5384 Mnemonic Function PD Power Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where AIDD reduces to 2 µA and DIDD to 20 µA. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down. NC No Connect. The user is advised not to connect any signals to these pins. 2 2 This pin acts as serial interface mode select. When this input is high SPI mode is selected. When low, I C is selected. SPI/ I C SCLK/SCL Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. 2 2 2 I C Mode. In I C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in I C mode is compatible with both 100 kHz and 400 kHz operating modes. DIN/SDA Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling edge of SCLK. 2 2 I C Mode. In I C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output. Rev. A | Page 16 of 36 AD5384 TERMINOLOGY Relative Accuracy DC Output Impedance Relative accuracy or endpoint linearity is a measure of the This is the effective output source resistance. It is dominated by maximum deviation from a straight line passing through the package lead resistance. endpoints of the DAC transfer function. It is measured after Output Voltage Settling Time adjusting for zero-scale error and full-scale error, and is expressed in LSB. This is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change, Differential Nonlinearity and is measured from the rising edge. BUSY Differential nonlinearity is the difference between the measured Digital-to-Analog Glitch Energy change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum This is the amount of energy injected into the analog output at ensures monotonicity. the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data Zero-Scale Error between 0x1FFF and 0x2000. Zero-scale error is the error in the DAC output voltage when all DAC-to-DAC Crosstalk 0s are loaded into the DAC register. Ideally, with all 0s loaded to n – 1 the DAC and m = all 1s, c = 2 DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC due to both the digital change and the sub- VOUT = 0 V (Zero-Scale) sequent analog output change at another DAC. The victim Zero-scale error is a measure of the difference between VOUT channel is loaded with midscale. DAC-to-DAC crosstalk is (actual) and VOUT (ideal), expressed in mV. It is mainly due to specified in nV-s. offsets in the output amplifier. Digital Crosstalk Offset Error Digital crosstalk is the glitch impulse transferred to the output Offset error is a measure of the difference between VOUT of one converter due to a change in the DAC register code of (actual) and VOUT (ideal) in the linear region of the transfer another converter. It is specified is specified in nV-s. function, expressed in mV. Offset error is measured on the Digital Feedthrough AD5384-5 with Code 32 loaded into the DAC register, and on the AD5384-3 with Code 64. When the device is not selected, high frequency logic activity on the device’s digital inputs can be capacitively coupled both Gain Error across and through the device to show up as noise on the VOUT Gain Error is specified in the linear region of the output range pins. It can also be coupled along the supply and ground lines. between V = 10 mV and V = AV – 50 mV. It is the OUT OUT DD This noise is digital feedthrough. deviation in slope of the DAC transfer characteristic from the ideal and is expressed in %FSR with the DAC output unloaded. Output Noise Spectral Density DC Crosstalk This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hertz). This is the dc change in the output level of one DAC at midscale It is measured by loading all DACs to midscale and measuring in response to a full-scale code (all 0s to all 1s, and vice versa) noise at the output. It is measured in nV/√Hz in a 1 Hz band- and output change of all other DACs. It is expressed in LSB. width at 10 kHz. Rev. A | Page 17 of 36 AD5384 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 2.0 AV = DV = 5.5V AV = DV = 3V DD DD DD DD V = 2.5V V = 1.25V REF REF 1.5 1.5 T = 25°C T = 25°C A A 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 4096 8192 12288 16384 0 4096 8192 12288 16384 INPUT CODE INPUT CODE Figure 8. Typical AD5384-5 INL Plot Figure 11. Typical AD5384-3 INL Plot 2.539 40 AV = DV = 5V DD DD 2.538 V = 2.5V REF 2.537 T = 25°C 35 A 14ns/SAMPLE NUMBER 2.536 1 LSB CHANGE AROUND MIDSCALE 2.535 30 GLITCH IMPULSE = 10nV-s 2.534 2.533 25 2.532 2.531 20 2.530 2.529 15 2.528 2.527 10 2.526 2.525 5 2.524 2.523 0 0 50 100 150 200 250 300 350 400 450 500 550 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 SAMPLE NUMBER REFERENCE DRIFT (ppm/°C) Figure 9. AD5384-5 Glitch Impulse Figure 12. AD5384-REFOUT Temperature Coefficient AV = DV = 5V DD DD V = 2.5V REF T = 25°C A AV = DV = 5V DD DD V OUT V = 2.5V REF V OUT = 25°C T A Figure 13. Slew Rate with Boost On Figure 10. Slew Rate with Boost Off Rev. A | Page 18 of 36 AMPLITUDE (V) INL ERROR (LSB) 03731-0-012 03731-0-034 03731-0-033 FREQUENCY INL ERROR (LSB) 03731-0-015 03731-0-048 03731-0-035 AD5384 14 AV = 5.5V DD V = 2.5V REF T = 25°C A AV = DV = 5V DD DD 12 V = 2.5V REF T = 25°C A POWER SUPPLY RAMP RATE = 10ms 10 V OUT 8 6 4 AV DD 2 89 10 11 AI (mA) DD Figure 14. Histogram with Boost Off Figure 17. AD5384 Power-Up Transient 14 AV = 5.5V DV = 5.5V DD DD REFIN = 2.5V V = DV IH DD 10 T = 25°C V = DGND IL A 12 T = 25°C A 8 10 8 6 6 4 4 2 2 0 0 0.4 0.5 0.6 0.7 0.8 0.9 –2 –1 0 1 2 INL ERROR DISTRIBUTION (LSB) DI (mA) DD Figure 15. DI Histogram Figure 18. INL Distribution DD PD WR BUSY AV = DV = 5V DD DD V = 2.5V REF T = 25°C A EXITS SOFT PD V OUT AV = DV = 5V TO MIDSCALE DD DD V = 2.5V REF V T = 25°C OUT A EXITS HARDWARE PD TO MIDSCALE Figure 19. Exiting Hardware Power Down Figure 16. Exiting Soft Power Down Rev. A | Page 19 of 36 NUMBER OF UNITS PERCENTAGE OF UNITS (%) 03731-0-045 04598-0-050 04598-0-049 NUMBER OF UNITS 03731-0-011 03731-0-038 04652-0-039 AD5384 6 6 AV = DV = 3V DD DD FULL-SCALE V = 1.25V REF T = 25°C A 5 5 AV = DV = 5V DD DD V = 2.5V 3/4 SCALE REF T = 25°C 4 4 A 3/4 SCALE FULL-SCALE 3 MIDSCALE 3 MIDSCALE 2 2 1/4 SCALE 1 1 ZERO-SCALE 0 0 ZERO-SCALE 1/4 SCALE –1 –1 –40 –20 –10 –5 –2 0 2 5 10 20 40 –40 –20 –10 –5 –2 0 2 5 10 20 –40 CURRENT (mA) CURRENT (mA) Figure 20. AD5384-5 Output Amplifier Source and Sink Capability Figure 23. AD5384-3 Output Amplifier Source and Sink Capability 0.20 2.456 AV = 5V DD AV = DV = 5V DD DD V = 2.5V REF V = 2.5V REF 0.15 T = 25°C A T = 25°C 2.455 A 14ns/SAMPLE NUMBER 0.10 2.454 ERROR AT ZERO SINKING CURRENT 0.05 2.453 0 2.452 –0.05 (V –V ) AT FULL-SCALE SOURCING CURRENT 2.451 DD OUT –0.10 2.450 –0.15 –0.20 2.449 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 50 100 150 200 250 300 350 400 450 500 550 I /I (mA) SAMPLE NUMBER SOURCE SINK Figure 21. Headroom at Rail vs. Source/Sink Current Figure 24. Adjacent Channel DAC to DAC Crosstalk 600 AV = DV = 5V AV = 5V DD DD DD T = 25°C T = 25°C A A DAC LOADED WITH MIDSCALE REFOUT DECOUPLED 500 EXTERNAL REFERENCE WITH 100nF CAPACITOR Y AXIS = 5µV/DIV X AXIS = 100ms/DIV 400 300 REFOUT = 2.5V 200 AV = DV = 5V DD DD V = 2.5V REF T = 25°C A REFOUT = 1.25V EXITS SOFT PD 100 TO MIDSCALE 0 100 1k 10k 100k FREQUENCY (Hz) Figure 22. REFOUT Noise Spectral Density Figure 25. 0.1 Hz to 10 Hz Noise Plot Rev. A | Page 20 of 36 OUTPUT NOISE (nV/ Hz) ERROR VOLTAGE (V) V (V) OUT 04652-0-035 04652-0-040 04652-0-030 AMPLITUDE (V) V (V) OUT 04652-0-034 04652-0-032 04652-0-031 AD5384 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The complete transfer function for these devices can be represented as The AD5384 is a complete single-supply, 40-channel, voltage output DAC offering 14-bit resolution, available in a 100-lead n VOUT = 2 × VREF × x2/2 2 CSPBGA package. It features two serial interfaces, SPI and I C. This family includes an internal1.25/2.5 V, 10 ppm/°C where: reference that can be used to drive the buffered reference x2 is the data-word loaded to the resistor string DAC. inputs. Alternatively, an external reference can be used to drive V is the internal reference voltage or the reference voltage REF these inputs. Reference selection is via a bit in the control externally applied to the DAC REFOUT/REFIN pin. For register. Internal/external reference selection is via the CR10 bit specified performance, an external reference voltage of 2.5 V is in the control register; CR12 selects the reference magnitude if recommended for the AD5384-5, and 1.25 V for the AD5384-3. the internal reference is selected. All channels have an on-chip DATA DECODING output amplifier with rail-to-rail output capable of driving 5 kΩ The AD5384 contains a 14-bit data bus, DB13-DB0. Depending in parallel with a 200 pF load. on the value of REG1 and REG0 outlined in Table 12, this data V (+) AVDD REF is loaded into the addressed DAC input register(s), offset (c) register(s), or gain (m) register(s). The format data, offset (c) ×1 INPUT REG and gain (m) register contents are outlined in Table 13, Table 14, 14-BIT INPUT DATA m REG ×2 and Table 15. DAC V OUT c REG R Table 12. Register Selection REG1 REG0 Register Selected R 1 1 Input Data Register (x1) AGND 1 0 Offset Register (c) 0 1 Gain Register (m) Figure 26. Single-Channel Architecture 0 0 Special Function Registers (SFRs) The architecture of a single DAC channel consists of a14-bit resistor-string DAC followed by an output buffer amplifier operating at a gain of 2. This resistor-string architecture Table 13. DAC Data Format (REG1 = 1, REG0 = 1) guarantees DAC monotonicity. The 14-bitbinary digital code DB13 to DB0 DAC Output (V) loaded to the DAC register determines at which node on the 11 1111 1111 1111 2 V × (16383/16384) REF string the voltage is tapped off before being fed to the output 11 1111 1111 1110 2 VREF × (16382/16384) amplifier. 10 0000 0000 0001 2 VREF × (8193/16384) 10 0000 0000 0000 2 VREF × (8192/16384) Each channel on these devices contains independent offset and 01 1111 1111 1111 2 V × (8191/16384) REF gain control registers allowing the user to digitally trim offset 00 0000 0000 0001 2 V × (1/16384) REF and gain. These registers let the user calibrate out errors in the 00 0000 0000 0000 0 complete signal chain including the DAC using the internal m and c registers which hold the correction factors. All channels are double buffered allowing synchronous updating of all Table 14. Offset Data Format (REG1 = 1, REG0 = 0) channels using the LDAC pin. Figure 26 shows a block diagram DB13 to DB0 Offset (LSB) of a single channel on the AD5384. The digital input transfer 11 1111 1111 1111 +8191 function for each DAC can be represented as 11 1111 1111 1110 +8190 10 0000 0000 0001 +1 n n – 1 x2 = [(m + 2)/ 2 × x1] + (c – 2 ) 10 0000 0000 0000 0 01 1111 1111 1111 –1 where: 00 0000 0000 0001 –8191 x2 is the data-word loaded to the resistor string DAC. 00 0000 0000 0000 –8192 x1 is the 14-bit data-word written to the DAC input register. m is the gain coefficient (default is 0x3FFE on the AD5384). The gain coefficient is written to the 13 most significant bits (DB13 to DB1) and the LSB (DB0) is 0. n is the DAC resolution (n = 14 for AD5384). c is the14-bit offset coefficient (default is 0x2000). Rev. A | Page 21 of 36 04652-0-014 AD5384 Table 15. Gain Data Format (REG1 = 0, REG0 = 1) Soft CLR DB13 to DB0 Gain Factor REG1 = REG0 = 0, A5–A0 = 000010 11 1111 1111 1110 1 DB13–DB0 = Don’t Care 10 1111 1111 1110 0.75 01 1111 1111 1110 0.5 Executing this instruction performs the CLR, which is 00 1111 1111 1110 0.25 functionally the same as that provided by the external pin. CLR 00 0000 0000 0000 0 The DAC outputs are loaded with the data in the CLR code register. It takes 35 µs to fully execute the SOFT CLR, as indicated by the BUSY low time. ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) The AD5384 contains a number of special function registers Soft Power-Down (SFRs), as outlined in Table 16. SFRs are addressed with REG1 = REG0 = 0, A5–A0 = 001000 REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0. DB13–DB0 = Don’t Care Table 16. SFR Register Functions (REG1 = 0, REG0 = 0) Executing this instruction performs a global power-down that R/W A5 A4 A3 A2 A1 A0 Function puts all channels into a low power mode that reduces the analog X 0 0 0 0 0 0 NOP (No Operation) supply current to 2 µA maximum and the digital current to 0 0 0 0 0 0 1 Write CLR Code 20 µA maximum. In power-down mode, the output amplifier 0 0 0 0 0 1 0 Soft CLR can be configured as a high impedance output or can provide a 0 0 0 1 0 0 0 Soft Power-Down 100 kΩ load to ground. The contents of all internal registers are 0 0 0 1 0 0 1 Soft Power-Up retained in power-down mode. No register can be written to 0 0 0 1 1 0 0 Control Register Write while in power-down. 1 0 0 1 1 0 0 Control Register Read Soft Power-Up 0 0 0 1 0 1 0 Monitor Channel 0 0 0 1 1 1 1 Soft Reset REG1 = REG0 = 0, A5–A0 = 001001 DB13–DB0 = Don’t Care SFR COMMANDS This instruction is used to power up the output amplifiers and NOP (No Operation) the internal reference. The time to exit power-down is 8 µs. The hardware power-down and software function are internally REG1 = REG0 = 0, A5–A0 = 000000 combined in a digital OR function. Performs no operation but is useful in serial readback mode to Soft RESET clock out data on DOUT for diagnostic purposes. BUSY pulses REG1 = REG0 = 0, A5–A0 = 001111 low during a NOP operation. DB13–DB0 = Don’t Care Write CLR Code This instruction is used to implement a software reset. All REG1 = REG0 = 0, A5–A0 = 000001 internal registers are reset to their default values, which DB13–DB0 = Contain the CLR data correspond to m at full scale and c at zero. The contents of the DAC registers are cleared, setting all analog outputs to 0 V. The Bringing the CLR line low or exercising the soft clear function soft reset activation time is 135 µs. loads the contents of the DAC registers with the data contained in the user-configurable CLR register, and sets VOUT0 to VOUT39, accordingly. This can be very useful for setting up a specific output voltage in a clear condition. It is also beneficial for calibration purposes; the user can load full scale or zero scale to the clear code register and then issue a hardware or software clear to load this code to all DACs, removing the need for individual writes to each DAC. Default on power-up is all 0s. Rev. A | Page 22 of 36 AD5384 Table 17. Control Register Contents MSB LSB CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Control Register Write/Read REG1 = REG0 = 0, A5–A0 = 001100, R/W status determines if CR8: Thermal Monitor Function. This function is used to monitor the AD5384 internal die temperature, when enabled. the operation is a write (R/W = 0) or a read (R/W = 1). DB13 to The thermal monitor powers down the output amplifiers when DB0 contain the control register data. the temperature exceeds 130°C. This function can be used to Control Register Contents protect the device when power dissipation might be exceeded if a number of output channels are simultaneously short-circuited. CR13: Power-Down Status. This bit is used to configure the A soft power-up re-enables the output amplifiers if the die output amplifier state in power-down. temperature drops below 130°C. CR13 = 1: Amplifier output is high impedance (default on CR8 = 1: Thermal Monitor Enabled. power-up). CR8 = 0: Thermal Monitor Disabled (default on power-up). CR13 = 0: Amplifier output is 100 kΩ to ground. CR7: Don’t Care. CR12: REF Select. This bit selects the operating internal reference for the AD5384. CR12 is programmed as follows: CR6 to CR2: Toggle Function Enable. This function allows the user to toggle the output between two codes loaded to the A CR12 = 1: Internal reference is 2.5 V (AD5384-5 default), the and B register for each DAC. Control register bits CR6 to CR2 recommended operating reference for AD5384-5. are used to enable individual groups of eight channels for operation in toggle mode. A Logic 1 written to any bit enables a CR12 = 0: Internal reference is 1.25 V (AD5384-3 default), group of channels; a Logic 0 disables a group. LDAC is used to the recommended operating reference for AD5384-3. toggle between the two registers. Table 18 shows the decoding CR11: Current Boost Control. This bit is used to boost the for toggle mode operation. For example, CR6 controls group w, current in the output amplifier, thereby altering its slew rate. which contains Channels 32 to 39, CR6 = 1 enables these This bit is configured as follows: channels. CR11 = 1: Boost Mode On. This maximizes the bias current CR1 and CR0: Don’t Care. in the output amplifier, optimizing its slew rate but increasing Table 18. the power dissipation. CR Bit Group Channels CR11 = 0: Boost Mode Off (default on power-up). This CR6 4 32–39 reduces the bias current in the output amplifier and reduces CR5 3 24–31 the overall power consumption. CR4 2 16–23 CR3 1 8–15 CR10: Internal/External Reference. This bit determines if the CR2 0 0–7 DAC uses its internal reference or an externally applied reference. Channel Monitor Function REG1 = REG0 = 0, A5–A0 = 001010 CR10 = 1: Internal Reference Enabled. The reference output depends on data loaded to CR12. DB13–DB8 = Contain data to address the monitored channel. CR10 = 0: External Reference Selected (default on power-up). A channel monitor function is provided on the AD5384. This feature, which consists of a multiplexer addressed via the CR9: Channel Monitor Enable (see Channel Monitor Function). interface, allows any channel output to be routed to the CR9 = 1: Monitor Enabled. This enables the channel monitor MON_OUT pin for monitoring using an external ADC. In channel monitor mode, VOUT39 becomes the MON_OUT pin, function. After a write to the monitor channel in the SFR register, the selected channel output is routed to the to which all monitored pins are routed. The channel monitor MON_OUT pin. VOUT39 operates as the MON_OUT pin. function must be enabled in the control register before any channels are routed to MON_OUT. On the AD5384, DB13 to CR9 = 0: Monitor Disabled (default on power-up). When the DB8 contain the channel address for the monitored channel. monitor is disabled, the MON_OUT pin assumes its normal Selecting Channel Address 63 three-states MON_OUT. DAC output function. Rev. A | Page 23 of 36 AD5384 Table 19. AD5384 Channel Monitor Decoding REG1 REG0 A5 A4 A3 A2 A1 A0 DB13 DB12 DB11 DB10 DB9 DB8 DB7–DB0 MON_OUT 0 0 0 0 1 0 1 0 0 0 0 0 0 0 X VOUT0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 X VOUT1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 X VOUT2 0 0 0 0 1 0 1 0 0 0 0 0 1 1 X VOUT3 0 0 0 0 1 0 1 0 0 0 0 1 0 0 X VOUT4 0 0 0 0 1 0 1 0 0 0 0 1 0 1 X VOUT5 0 0 0 0 1 0 1 0 0 0 0 1 1 0 X VOUT6 0 0 0 0 1 0 1 0 0 0 0 1 1 1 X VOUT7 0 0 0 0 1 0 1 0 0 0 1 0 0 0 X VOUT8 0 0 0 0 1 0 1 0 0 0 1 0 0 1 X VOUT9 0 0 0 0 1 0 1 0 0 0 1 0 1 0 X VOUT10 0 0 0 0 1 0 1 0 0 0 1 0 1 1 X VOUT11 0 0 0 0 1 0 1 0 0 0 1 1 0 0 X VOUT12 0 0 0 0 1 0 1 0 0 0 1 1 0 1 X VOUT13 0 0 0 0 1 0 1 0 0 0 1 1 1 0 X VOUT14 0 0 0 0 1 0 1 0 0 0 1 1 1 1 X VOUT15 0 0 0 0 1 0 1 0 0 1 0 0 0 0 X VOUT16 0 0 0 0 1 0 1 0 0 1 0 0 0 1 X VOUT17 0 0 0 0 1 0 1 0 0 1 0 0 1 0 X VOUT18 0 0 0 0 1 0 1 0 0 1 0 0 1 1 X VOUT19 0 0 0 0 1 0 1 0 0 1 0 1 0 0 X VOUT20 0 0 0 0 1 0 1 0 0 1 0 1 0 1 X VOUT21 0 0 0 0 1 0 1 0 0 1 0 1 1 0 X VOUT22 0 0 0 0 1 0 1 0 0 1 0 1 1 1 X VOUT23 0 0 0 0 1 0 1 0 0 1 1 0 0 0 X VOUT24 0 0 0 0 1 0 1 0 0 1 1 0 0 1 X VOUT25 0 0 0 0 1 0 1 0 0 1 1 0 1 0 X VOUT26 0 0 0 0 1 0 1 0 0 1 1 0 1 1 X VOUT27 0 0 0 0 1 0 1 0 0 1 1 1 0 0 X VOUT28 0 0 0 0 1 0 1 0 0 1 1 1 0 1 X VOUT29 0 0 0 0 1 0 1 0 0 1 1 1 1 0 X VOUT30 0 0 0 0 1 0 1 0 0 1 1 1 1 1 X VOUT31 0 0 0 0 1 0 1 0 1 0 0 0 0 0 X VOUT32 0 0 0 0 1 0 1 0 1 0 0 0 0 1 X VOUT33 0 0 0 0 1 0 1 0 1 0 0 0 1 0 X VOUT34 0 0 0 0 1 0 1 0 1 0 0 0 1 1 X VOUT35 0 0 0 0 1 0 1 0 1 0 0 1 0 0 X VOUT36 0 0 0 0 1 0 1 0 1 0 1 1 0 1 X VOUT37 0 0 0 0 1 0 1 0 1 0 0 1 1 0 X VOUT38 0 0 0 0 1 0 1 0 1 0 0 1 1 1 X VOUT39 0 0 0 0 1 0 1 0 1 0 1 0 0 0 X Undefined • • • • • • • • • • • • • • • • 0 0 0 0 1 0 1 0 1 1 1 1 1 0 X Undefined 0 0 0 0 1 0 1 0 1 1 1 1 1 1 X Three-State REG1 REG0A5 A4 A3 A2 A1 A0 0 000 101 0 VOUT0 VOUT1 AD5384 CHANNEL MONITOR VOUT39/MON_OUT DECODING VOUT37 VOUT38 CHANNEL ADDRESS DB13–DB8 Figure 27. Channel Monitor Decoding Rev. A | Page 24 of 36 04652-0-015 AD5384 HARDWARE FUNCTIONS outputs update immediately after goes high. also BUSY BUSY RESET FUNCTION goes low during power-on reset and when a falling edge is Bringing the line low resets the contents of all internal RESET detected on the pin. During this time, all interfaces are RESET registers to their power-on reset state. Reset is a negative edge- disabled and any events on LDAC are ignored. The AD5384 sensitive input. The default corresponds to m at full scale and to contains an extra feature whereby a DAC register is not updated c at zero. The contents of the DAC registers are cleared, setting unless its x2 register has been written to since the last time VOUT0 to VOUT39 to 0 V. The hardware reset activation time was brought low. Normally, when is brought low, LDAC LDAC takes 270 µs. The falling edge of initiates the reset RESET the DAC registers are filled with the contents of the x2 registers. process; BUSY goes low for the duration, returning high when However, the AD5384 updates the DAC register only if the x2 is complete. While is low, all interfaces are RESET BUSY data has changed, thereby removing unnecessary digital disabled and all LDAC pulses are ignored. When BUSY returns crosstalk. high, the part resumes normal operation and the status of the pin is ignored until the next falling edge is detected. POWER-ON RESET RESET The AD5384 contains a power-on reset generator and state ASYNCHRONOUS CLEAR FUNCTION machine. The power-on reset resets all registers to a predefined Bringing the line low clears the contents of the DAC CLR state and configures the analog outputs as high impedance. The registers to the data contained in the user configurable CLR pin goes low during the power-on reset sequencing, BUSY register and sets VOUT0 to VOUT39 accordingly. This function preventing data writes to the device. can be used in system calibration to load zero scale and full POWER-DOWN scale to all channels. The execution time for a CLR is 35 µs. The AD5384 contains a global power-down feature that puts all BUSY AND LDAC FUNCTIONS channels into a low power mode and reduces the analog power BUSY is a digital CMOS output that indicates the status of the consumption to 2 µA maximum and digital power consumption to 20 µA maximum. In power-down mode, the output amplifier AD5384. The value of x2, the internal data loaded to the DAC can be configured as a high impedance output or it can provide data register, is calculated each time the user writes new data to a 100 kΩ load to ground. The contents of all internal registers the corresponding x1, c ,or m registers. During the calculation are retained in power-down mode. When exiting power-down, of x2, the BUSY output goes low. While BUSY is low, the user the settling time of the amplifier elapses before the outputs can continue writing new data to the x1, m, or c registers, but settles to their correct values. no DAC output updates can take place. The DAC outputs are updated by taking the LDAC input low. If LDAC goes low while BUSY is active, the LDAC event is stored and the DAC outputs update immediately after BUSY goes high. The user can hold the LDAC input permanently low, in which case the DAC Rev. A | Page 25 of 36 AD5384 INTERFACES The AD5384 contains a serial interface that can be A/B. When toggle mode is enabled, this selects whether the 2 programmed either as DSP-, SPI-, MICROWIRE-, or I C- data write is to the A or B register, with Toggle disabled this bit compatible. The SPI/I2C pin is used to select DSP, SPI, should be set to zero to select the A data register. 2 MICROWIRE, or I C interface mode. To minimize both the R/ is the read or write control bit. W power consumption of the device and the on-chip digital noise, the active interface powers up fully only when the device is A5–A0 are used to address the input channels. being written to, i.e., on the falling edge of SYNC. REG1 and REG0 select the register to which data is written, as DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL shown in Table 12. INTERFACES DB13–DB0 contain the input data-word. The serial interface can be operated with a minimum of three wires in standalone mode or five wires in daisy-chain mode. X is a don’t care condition. Daisy chaining allows many devices to be cascaded together to Standalone Mode increase system channel count. The SPI/I2C (Ball B8) should be By connecting DCEN (daisy-chain enable) pin low, standalone tied high to enable the DSP-, SPI-, MICROWIRE-compatible mode is enabled. The serial interface works with both a serial interface. The serial interface control pins are continuous and a noncontinuous serial clock. The first falling , DIN, SCLK—Standard 3-Wire Interface Pins. SYNC edge of SYNC starts the write cycle and resets a counter that DCEN—Selects Standalone Mode or Daisy-Chain Mode. counts the number of serial clocks to ensure that the correct SDO—Data Out Pin for Daisy-Chain Mode. number of bits are shifted into the serial shift register. Any further edges on , except for a falling edge, are ignored SYNC Figure 3 and Figure 5 show the timing diagrams for a serial until 24 bits are clocked in. Once 24 bits are shifted in, the write to the AD5384 in standalone and in daisy-chain modes. SCLK is ignored. For another serial transfer to take place, the The 24-bit data-word format for the serial interface is shown in counter must be reset by the falling edge of . SYNC Table 20. Table 20. 40-Channel, 14-Bit DAC Serial Input Register Configuration MSB LSB A W A5 A4 A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 /B R/ Rev. A | Page 26 of 36 AD5384 Daisy-Chain Mode Readback Mode For systems that contain several devices, the SDO pin can be Readback mode is invoked by setting the R/W bit = 1 in the used to daisy-chain several devices together. This daisy-chain serial input register write. With R/ = 1, Bits A5 to A0, in W mode can be useful in system diagnostics and in reducing the association with Bits REG1 and REG0, select the register to be number of serial interface lines. read. The remaining data bits in the write sequence are don’t cares. During the next SPI write, the data appearing on the SDO By connecting DCEN (daisy-chain enable) pin high, the daisy- output contains the data from the previously addressed register. chain mode is enabled. The first falling edge of SYNC starts the For a read of a single register, the NOP command can be used write cycle. The SCLK is applied continuously to the input shift in clocking out the data from the selected register on SDO. register when is low. If more than 24 clock pulses are SYNC Figure 28 shows the readback sequence. applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of For example, to read back the m register of Channel 0 on the SCLK and is valid on the falling edge. By connecting the SDO AD5384, the following sequence should be followed. First, write of the first device to the DIN input on the next device in the 0x404XXX to the AD5384 input register. This configures the chain, a multidevice interface is constructed. 24 clock pulses are AD5384 for read mode with the m register of Channel 0 required for each device in the system. Therefore, the total selected. Note that Data Bits DB13 to DB0 are don’t cares. number of clock cycles must equal 24N where N is the total Follow this with a second write, a NOP condition, 0x000000. number of AD5384 devices in the chain. During this write, the data from the m register is clocked out on the SDO line, i.e., data clocked out contains the data from the m When the serial transfer to all devices is complete, SYNC is register in Bits DB13 to DB0, and the top 10 bits contain the taken high. This latches the input data in each device in the address information as previously written. In readback mode, daisy-chain and prevents any further data being clocked into the signal must frame the data. Data is clocked out on SYNC the input shift register. the rising edge of SCLK and is valid on the falling edge of the SCLK signal. If the SCLK idles high between the write and read If the SYNC is taken high before 24 clocks are clocked into the operations of a readback operation, the first bit of data is part, this is considered a bad frame and the data is discarded. clocked out on the falling edge of SYNC. The serial clock may be either a continuous or a gated clock. A continuous SCLK source can be used only if it can be arranged that is held low for the correct number of clock cycles. In SYNC gated clock mode a burst clock containing the exact number of clock cycles must be used and taken high after the final SYNC clock to latch the data. SCLK 24 48 SYNC DIN DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION SDO DB23 DB0 UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 28. Serial Readback Operation Rev. A | Page 27 of 36 04652-0-016 AD5384 2 I C SERIAL INTERFACE Slave Addresses 2 The AD5384 features an I C-compatible 2-wire interface A bus master initiates communication with a slave device by consisting of a serial data line (SDA) and a serial clock line issuing a start condition followed by the 7-bit slave address. (SCL). SDA and SCL facilitate communication between the When idle, the AD5384 waits for a start condition followed by AD5384 and the master at rates up to 400 kHz. Figure 6 shows its slave address. The LSB of the address word is the Read/Write the 2-wire interface timing diagrams that incorporate three (R/W) bit. The AD5384 devices are receive-only devices; when different modes of operation. communicating with these, R/W = 0. After receiving the proper 2 Select I C mode by configuring the SPI/I2C pin to a Logic 0. address 1010 1(AD1)(AD0), the AD5384 issues an ACK by The device is connected to this bus as slave devices, i.e., no pulling SDA low for one clock cycle. clock is generated by the AD5384. The AD5384 has a 7-bit slave address 1010 1(AD1)(AD0). The 5 MSBs are hard coded, and The AD5384 has four different user programmable addresses the two LSBs are determined by the state of the AD1 AD0 pins. determined by the AD1 and AD0 bits. The ability to hardware-configure AD1 and AD0 allows four of Write Operation these devices to be configured on the bus. There are three specific modes in which data can be written to 2 I C Data Transfer the AD5384 family of DACs. One data bit is transferred during each SCL clock cycle. The 4-Byte Mode data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control When writing to the AD5384 DACs, the user must begin with signals, which configure start and stop conditions. Both SDA an address byte (R/W = 0), after which the DAC acknowledges and SCL are pulled high by the external pull-up resistors when that it is prepared to receive data by pulling SDA low. The 2 the I C bus is not busy. address byte is followed by the pointer byte; this addresses the specific channel in the DAC to be addressed and also is Start and Stop Conditions acknowledged by the DAC. Two bytes of data are then written A master device initiates communication by issuing a start to the DAC, as shown in Figure 29. A stop condition follows. condition. A start condition is a high-to-low transition on SDA This lets the user update a single channel within the AD5384 at with SCL high. A stop condition is a low-to-high transition on any time and requires four bytes of data to be transferred from SDA while SCL is high. A start condition from the master the master. signals the beginning of a transmission to the AD5384. The stop condition frees the bus. If a repeated start condition (Sr) is 3-Byte Mode generated instead of a stop condition, the bus remains active. In 3-byte mode, the user can update more than one channel in a Repeated START Conditions write sequence without having to write the device address byte A repeated start (Sr) condition may indicate a change of data each time. The device address byte is required only once; sub- direction on the bus. Sr may be used when the bus master is sequent channel updates require the pointer byte and the data 2 writing to several I C devices and wants to maintain control of bytes. In 3-byte mode, the user begins with an address byte the bus. (R/ = 0), after which the DAC acknowledges that it is prepared W to receive data by pulling SDA low. The address byte is followed Acknowledge Bit (ACK) by the pointer byte. This addresses the specific channel in the The acknowledge bit (ACK) is the ninth bit attached to any DAC to be addressed and also is acknowledged by the DAC. 8-bit data-word. ACK is always generated by the receiving This is then followed by the two data bytes, REG1 and REG0, device. The AD5384 devices generate an ACK when receiving which determine the register to be updated. an address or data by pulling SDA low during the ninth clock period. Monitoring ACK allows detection of unsuccessful data If a stop condition does not follow the data bytes, another transfers. An unsuccessful data transfer occurs if a receiving channel can be updated by sending a new pointer byte followed device is busy or if a system fault occurs. In the event of an by the data bytes. This mode requires only three bytes to be sent unsuccessful data transfer, the bus master should re-attempt to update any channel once the device is initially addressed, and communication. reduces the software overhead in updating the AD5384 channels. A stop condition at any time exits this mode. Figure 30 shows a typical configuration. Rev. A | Page 28 of 36 AD5384 SCL SDA 1 0 1 0 1 AD1 AD0 R/W 0 0 A5 A4 A3 A2 A1 A0 START COND ACK BY MSB ACK BY BY MASTER AD538x AD538x ADDRESS BYTE POINTER BYTE SCL REG1 REG0 MSB LSB MSB LSB SDA ACK BY ACK BY STOP AD538x AD538x COND MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE BY MASTER 2 Figure 29. 4-Byte AD5384, I C Write Operation SCL SDA 1 0 1 0 1 AD1 AD0 R/W 0 0 A5 A4 A3 A2 A1 A0 START COND ACK BY MSB ACK BY BY MASTER AD538x AD538x ADDRESS BYTE POINTER BYTE FOR CHANNEL "N" SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY AD538x AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "N" SCL SDA 0 0 A5 A4 A3 A2 A1 A0 MSB ACK BY AD538x POINTER BYTE FOR CHANNEL "NEXT CHANNEL" SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP COND AD538x AD538x BY MASTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DATA FOR CHANNEL "NEXT CHANNEL" 2 Figure 30. 3-Byte AD5384, I C Write Operation Rev. A | Page 29 of 36 04652-0-018 04652-0-017 AD5384 2-Byte Mode Following initialization of 2-byte mode, the user can update The REG0 and REG1 bits in the data byte determine which channels sequentially. The device address byte is required only register is updated. In this mode, following the initialization, once, and the pointer address pointer is configured for auto- only the two data bytes are required to update a channel. The increment or burst mode. channel address automatically increments from Address 0. This mode allows transmission of data to all channels in one block The user must begin with an address byte (R/W = 0), after and reduces the software overhead in configuring all channels. which the DAC acknowledges that it is prepared to receive data A stop condition at any time exits this mode. Toggle mode is by pulling SDA low. The address byte is followed by a specific not supported in 2-byte mode. Figure 31 shows a typical pointer byte (0xFF) that initiates the burst mode of operation. configuration. The address pointer initializes to Channel 0,and, upon receiving the two data bytes for the present address, automatically increments to the next address. SCL SDA 1 0 1 0 1 AD1 AD0 R/W 0 0 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1 START COND ACK BY MSB ACK BY BY MASTER AD538x AD538x ADDRESS BYTE POINTER BYTE SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY AD538x AD538x MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 0 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY AD538x CONVERTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE CHANNEL 1 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY ACK BY STOP AD538x CONVERTER COND MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE BY MASTER CHANNEL N DATA FOLLOWED BY STOP 2 Figure 31. 2-Byte, 1 C Write Operation Rev. A | Page 30 of 36 04652-0-019 AD5384 MICROPROCESSOR INTERFACING AD5384 to MC68HC11 AD5384 to 8051 The serial peripheral interface (SPI) on the MC68HC11 is The AD5384 requires a clock synchronized to the serial data. configured for master mode (MSTR = 1), the Clock Polarity bit The 8051 serial interface must therefore be operated in Mode 0. (CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is In this mode, serial data enters and exits through RxD, and a configured by writing to the SPI control register (SPCR)—see shift clock is output on TxD. Figure 34 shows how the 8051 is the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK connected to the AD5384. Because the AD5384 shifts data out of the AD5384, the MOSI output drives the serial data line (D ) on the rising edge of the shift clock and latches data in on the IN of the AD5384, and the MISO input is driven from D . falling edge, the shift clock must be inverted. The AD5384 OUT requires its data to be MSB first. Since the 8051 outputs the LSB The signal is derived from a port line (PC7). When data SYNC first, the transmit routine must take this into account. is being transmitted to the AD5384, the SYNC line is taken low DVDD 8XC51 AD5384 (PC7). Data appearing on the MOSI output is valid on the 2 SPI/I C falling edge of SCK. Serial data from the 68HC11 is transmitted DVDD RESET in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. RxD SDO DIN DVDD MC68HC11 AD5384 TxD SCLK P1.1 SYNC 2 SPI/I C RESET MISO SDO MOSI DIN SCK SCLK Figure 34. AD5384-to-8051 Interface PC7 SYNC AD5384 to ADSP-2101/ADSP-2103 Figure 35 shows a serial interface between the AD5384 and the Figure 32. AD5384-toMC68HC11 Interface ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in SPORT transmit alternate framing mode. AD5384 to PIC16C6x/7x The ADSP-2101/ADSP-2103 SPORT is programmed through The PIC16C6x/7x synchronous serial port (SSP) is configured the SPORT control register and should be configured as follows: as an SPI master with the Clock Polarity bit = 0. This is done by internal clock operation, active low framing, and 16-bit word writing to the synchronous serial port control register length. Transmission is initiated by writing a word to the Tx (SSPCON). See the PIC16/17 Microcontroller User Manual. In register after the SPORT has been enabled. this example I/O, port RA1 is being used to pulse SYNC and enable the serial port of the AD5384. This microcontroller DVDD ADSP-2101/ AD5384 transfers only eight bits of data during each serial transfer ADSP-2103 2 SPI/I C operation; therefore, three consecutive read/write operations RESET could be needed, depending on the mode. Figure 33 shows the DR SDO connection diagram. DT DIN SCK SCLK TFS SYNC DVDD PIC16C6X/7X AD5384 RFS 2 SPI/I C RESET SDI/RC4 SDO Figure 35. AD5384-to-ADSP-2101/ADSP-2103 Interface SDO/RC5 DIN SCK/RC3 SCLK RA1 SYNC Figure 33. AD5384-to-PIC16C6x/7x Interface Rev. A | Page 31 of 36 04652-0-021 04652-0-020 04652-0-023 04652-0-022 AD5384 APPLICATION INFORMATION POWER SUPPLY DECOUPLING MONITOR FUNCTION In any circuit where accuracy is important, careful considera- The AD5384 contains a channel monitor function that consists tion of the power supply and ground return layout helps to of a multiplexer addressed via the interface, allowing any ensure the rated performance. The printed circuit board on channel output to be routed to this pin for monitoring using an which the AD5384 is mounted should be designed so that the external ADC. In channel monitor mode, VOUT39 becomes analog and digital sections are separated and confined to the MON_OUT pin, to which all monitored signals are routed. certain areas of the board. If the AD5384 is in a system where The channel monitor function must be enabled in the control multiple devices require an AGND-to-DGND connection, the register before any channels are routed to MON_OUT. contains connection should be made at one point only, a star ground the decoding information required to route any channel to point established as close to the device as possible. MON_OUT. Selecting Channel Address 63 three-states MON_OUT. Figure 36 shows a typical monitoring circuit For supplies with multiple pins (AV , AV ), these pins should DD CC implemented using a 12-bit SAR ADC in a 6-lead SOT package. be tied together. The AD5384 should have ample supply bypass- The controller output port selects the channel to be monitored, ing of 10 µF in parallel with 0.1 µF on each supply, located as and the input port reads the converted data from the ADC. close to the package as possible and ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance AVCC (ESR) and effective series inductance (ESI), like the common DIN ceramic types that provide a low impedance path to ground at VOUT0 SYNC OUTPUT PORT high frequencies, to handle transient currents due to internal SCLK AVCC logic switching. AD5384 AD7476 CS The power supply lines of the AD5384 should use as large a VOUT39/MON_OUT V SCLK INPUT PORT IN trace as possible to provide low impedance paths and reduce the SDATA effects of glitches on the power supply line. Fast switching GND signals, such as clocks, should be shielded with digital ground CONTROLLER AGND to avoid radiating noise to other parts of the board, and should VOUT38 DAC_GND SIGNAL_GND never be run near the reference inputs. A ground line routed between the D and SCLK lines helps to reduce crosstalk IN between them (this is not required on a multilayer board Figure 36. Typical Channel Monitoring Circuit because there is a separate ground plane, but separating the lines helps). It is essential to minimize noise on the VIN and TOGGLE MODE FUNCTION REFIN lines. The toggle mode function allows an output signal to be gener- ated using the control signal, which switches between LDAC Avoid crossover of digital and analog signals. Traces on two DAC data registers. This function is configured using the opposite sides of the board should run at right angles to each SFR control register as follows. A write with REG1 = REG0 = 0 other. This reduces the effects of feedthrough through the and A5–A0 = 001100 specifies a control register write. The board. A microstrip technique is by far the best, but is not toggle mode function is enabled in groups of eight channels always possible with a double-sided board. In this technique, using Bits CR6 to CR2 in the control register (see Table 17). the component side of the board is dedicated to the ground Figure 37 shows a block diagram of toggle mode plane while signal traces are placed on the solder side. implementation. DATA REGISTER A DAC V 14-BIT DAC OUT REGISTER DATA INPUT INPUT REGISTER DATA REGISTER B LDAC A/B CONTROL INPUT Figure 37. Toggle Mode Function Rev. A | Page 32 of 36 04652-0-025 04652-0-024 AD5384 Each of the 40 DAC channels on the AD5384 contains an A and THERMAL MONITOR FUNCTION B data register. Note that the B registers can be loaded only The AD5384 contains a temperature shutdown function to when toggle mode is enabled. The sequence of events when protect the chip if multiple outputs are shorted. The short- configuring the AD5384 for toggle mode is circuit current of each output amplifier is typically 40 mA. Operating the AD5384 at 5 V leads to a power dissipation of 1. Enable toggle mode for the required channels via the 200 mW per shorted amplifier. With five channels shorted, this control register. leads to an extra watt of power dissipation. For the 100-lead 2. Load data to A registers. is typically 44°C/W. CSPBGA, the θJA 3. Load data to B registers. The thermal monitor is enabled by the user via CR8 in the control register. The output amplifiers on the AD5384 are 4. Apply . LDAC automatically powered down if the die temperature exceeds approximately 130°C. After a thermal shutdown has occurred, The LDAC is used to switch between the A and B registers in the user can re-enable the part by executing a soft power-up if determining the analog output. The first configures the LDAC the temperature drops below 130°C, or by turning off the output to reflect the data in the A registers. This mode offers thermal monitor function via the control register. significant advantages if the user wants to generate a square wave at the output of all 40 channels, as might be required to AD5384 IN A MEMS-BASED OPTICAL SWITCH drive a liquid crystal-based variable optical attenuator. In this In their feed-forward control paths, MEMS based optical case, the user writes to the control register and enables the switches require high resolution DACs that offer high channel toggle function by setting CR6 to CR2 = 1, thus enabling the density with 14-bit monotonic behavior. The 40-channel, 14-bit five groups of eight for toggle mode operation. The user must AD5384 DAC satisfies these requirements. In the circuit in then load data to all 40 A and B registers. Toggling LDAC sets Figure 38, the 0 V to 5 V outputs of the AD5384 are amplified the output values to reflect the data in the A and B registers. to achieve an output range of 0 V to 200 V, which is used to The frequency of the determines the frequency of the LDAC control actuators that determine the position of MEMS mirrors square wave output. in an optical switch. The exact position of each mirror is measured using sensors. The sensor outputs are multiplexed Toggle mode is disabled via the control register. The first LDAC into a high resolution ADC in determining the mirror position. following the disabling of the toggle mode updates the outputs The control loop is closed and driven by an ADSP-21065L, a with the data contained in the A registers. 32-bit SHARC® DSP with an SPI-compatible SPORT interface. The ADSP-21065L writes data to the DAC, controls the multi- plexer, and reads data from the ADC via the serial interface. 5V OUTPUT RANGE 0V–200V 0.01µF REFOUT REFINA AVDD VOUT1 14-BIT DAC 8-CHANNEL ADC ACTUATORS G = 50 (AD7856) SENSOR FOR MEMS OR AND MIRROR SINGLE-CHANNEL MULTIPLEXER ARRAY ADC (AD7671) 14-BIT DAC G = 50 VOUT40 AD5384 ADSP-21065L Figure 38. AD5384 in a MEMS-Based Optical Switch Rev. A | Page 33 of 36 04652-0-026 AD5384 OPTICAL ATTENUATORS Based on its high channel count, high resolution, monotonic The AD5384 controls the optical attenuator for each behavior, and high level of integration, the AD5384 is ideally wavelength, ensuring that the power is equalized in all targeted at optical attenuation applications used in dynamic wavelengths before being multiplexed onto the fiber. This gain equalizers, variable optical attenuators (VOA), and optical prevents information loss and saturation from occurring at add-drop multiplexers (OADMs). In these applications, each amplification stages further along the fiber. wavelength is individually extracted using an arrayed wave guide; its power is monitored using a photodiode, transimped- ance amplifier, and an ADC in a closed-loop control system. ADD DROP PORTS PORTS OPTICAL SWITCH PHOTODIODES 11 ATTENUATOR 12 DWDM DWDM ATTENUATOR IN OUT FIBRE AWG FIBRE AWG 1n–1 ATTENUATOR 1n ATTENUATOR TIA/LOG AMP (AD8304/AD8305) ADG731 N:1 MULTIPLEXER AD5384, (40:1 MUX) 40-CHANNEL, 14-BIT DAC AD7671 CONTROLLER 16-BIT ADC (0-5V, 1MSPS) Figure 39. OADM Using the AD5384 as Part of an Optical Attenuator Rev. A | Page 34 of 36 04652-0-027 AD5384 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 10.00 BSC SQ 12 11109 8 7 654 32 1 A B C 2.50 SQ BALL A1 D PAD CORNER E 8.80 BSC BOTTOM F TOP VIEW VIEW G H J K L M 0.80 BSC DETAIL A 1.40 1.35 1.11 1.20 DETAILA 0.65 REF 1.01 0.91 0.34 NOM 0.29 MIN 0.12 MAX 0.50* SEATING COPLANARITY 0.45 PLANE 0.40 BALL DIAMETER *COMPLIANT TO JEDEC STANDARDS MO-205AC WITH THE EXCEPTION OF BALL DIAMETER. Figure 40. 100-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-100-2) Dimensions shown in millimeters ORDERING GUIDE AV Output Linearity Package Package DD Model Resolution Temperature Range Range Channels Error (LSB) Description Option AD5384BBC-5 14 Bits –40°C to +85°C 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100-2 AD5384BBC-5REEL7 14 Bits –40°C to +85°C 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100-2 AD5384BBC-3 14 Bits –40°C to +85°C 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100-2 AD5384BBC-3REEL7 14 Bits –40°C to +85°C 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100-2 Rev. A | Page 35 of 36 AD5384 NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04652–0–10/04(A) Rev. A | Page 36 of 36